Method for controlling semiconductor device

Abstract

To provide a semiconductor device that is easy to control.SOLUTION: A semiconductor device includes a first switching device and a second switching device connected in series between a first potential and a second potential lower than the first potential, the first and second switching devices both have a transistor region and a diode region electrically connected in anti-parallel to the transistor region, and the transistor region includes a first gate controlled by a first gate signal, and the diode region includes a diode gate controlled by a diode gate signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device that is easy to control. [Background technology]

[0002] In a reverse conducting IGBT (RC-IGBT), in which an IGBT (Insulated Gate Bipolar Transistor) and a free wheel diode are provided on the same semiconductor substrate, conventionally, as disclosed in Patent Document 1, for example, the control method has been changed depending on the two conduction states, i.e., the forward mode in which current flows through the IGBT and the reverse mode in which current flows through the free wheel diode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6652173 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to change the control method depending on the conduction state as described above, it is necessary to detect or estimate the operating state, which is very difficult to realize.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device that is easy to control. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a first switching device and a second switching device connected in series between a first potential and a second potential lower than the first potential, and each of the first and second switching devices has a transistor region and a diode region electrically connected in antiparallel to the transistor region, and the transistor region has a first gate voltage controlled by a first gate signal. a second gate controlled by a second gate signal; Including, a first gate signal that is a signal based on the first potential of the first main electrode and the second gate signal that is a signal based on the second potential of the second main electrode; a second gate signal that is a signal based on the first potential of the first main electrode; a third gate signal that is a signal based on the second potential of the second main electrode; a second gate signal that is a positive voltage that turns on the second gate of the first switching device at a second timing that is earlier than a first timing at which a negative voltage or zero voltage that turns off the transistor region is applied to the first gate as the first gate signal; the second gate signal is set to a negative voltage or zero voltage so that the second gate is turned off during a third timing when a positive voltage at which the transistor region is turned on is applied as the first gate signal to the first gate of the switching device; a positive voltage at which the diode gate is turned on is applied as the diode gate signal to the diode gate of the diode region of the second switching device at a fourth timing earlier than the third timing at which the transistor region is turned on; and the diode gate signal is set to a negative voltage or zero voltage at a timing equal to or earlier than the third timing so that the diode gate of the diode region of the second switching device is turned off. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, the diode region includes a diode gate controlled by a gate signal, and by controlling the diode gate to be ON when the diode region is preparing for reverse recovery, the amount of holes injected into the diode region is reduced, and the reverse recovery loss during the subsequent reverse recovery of the diode region is reduced. Thus, in the semiconductor device of the present disclosure, by providing the diode region with a diode gate controlled by a diode gate signal, detection or estimation of the operating state is not required to change the control method depending on the conduction state, making control easier. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram showing a configuration of an inverter circuit according to a first embodiment. [Figure 2] 1 is a plan view of an RC-IGBT of an inverter circuit according to a first embodiment, viewed from above. [Figure 3] 2 is a plan view of the RC-IGBT of the inverter circuit of the first embodiment, viewed from the bottom side. FIG. [Figure 4] 1 is a cross-sectional view showing a configuration of an RC-IGBT of an inverter circuit according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing a configuration of an RC-IGBT of an inverter circuit according to a first embodiment. [Figure 6] FIG. 10 is a plan view of an RC-IGBT according to a modification of the first embodiment, viewed from the top side. [Figure 7] FIG. 10 is a cross-sectional view showing a configuration of an RC-IGBT of an inverter circuit according to a modified example of the first embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing a configuration of an RC-IGBT of an inverter circuit according to a modified example of the first embodiment. [Figure 9] 3 is a timing chart used to control the inverter circuit of the first embodiment. [Figure 10] 3 is a diagram illustrating control of the inverter circuit according to the first embodiment. FIG. [Figure 11] 3 is a diagram illustrating control of the inverter circuit according to the first embodiment. FIG. [Figure 12] 3 is a diagram illustrating control of the inverter circuit according to the first embodiment. FIG. [Figure 13] 3 is a diagram illustrating control of the inverter circuit according to the first embodiment. FIG. [Figure 14] 3 is a diagram illustrating control of the inverter circuit according to the first embodiment. FIG. [Figure 15] 3 is a diagram illustrating control of the inverter circuit according to the first embodiment. FIG. [Figure 16] 3 is a diagram illustrating control of the inverter circuit according to the first embodiment. FIG. [Figure 17] 3 is a diagram illustrating control of the inverter circuit according to the first embodiment. FIG. [Figure 18] FIG. 10 is a circuit diagram showing a configuration of an inverter circuit according to a second embodiment. [Figure 19] FIG. 10 is a plan view of the RC-IGBT of the inverter circuit of the second embodiment, viewed from above. [Figure 20] 10 is a plan view of the RC-IGBT of the inverter circuit of the second embodiment, viewed from the bottom side. FIG. [Figure 21] FIG. 10 is a cross-sectional view showing the configuration of an RC-IGBT of an inverter circuit according to a second embodiment. [Figure 22] FIG. 10 is a cross-sectional view showing the configuration of an RC-IGBT of an inverter circuit according to a second embodiment. [Figure 23] FIG. 10 is a circuit diagram showing a configuration of an inverter circuit according to a third embodiment. [Figure 24]FIG. 11 is a plan view of the RC-IGBT of the inverter circuit of the third embodiment, as viewed from above. [Figure 25] 11 is a plan view of the RC-IGBT of the inverter circuit of the third embodiment, viewed from the bottom side. FIG. [Figure 26] FIG. 10 is a cross-sectional view showing the configuration of an RC-IGBT of an inverter circuit according to a third embodiment. [Figure 27] FIG. 10 is a cross-sectional view showing the configuration of an RC-IGBT of an inverter circuit according to a third embodiment. [Figure 28] FIG. 11 is a plan view of an RC-IGBT in an inverter circuit according to a modification of the third embodiment, viewed from the bottom side. [Figure 29] FIG. 11 is a cross-sectional view showing a configuration of an RC-IGBT in an inverter circuit according to a modified example of the third embodiment. [Figure 30] FIG. 11 is a cross-sectional view showing a configuration of an RC-IGBT in an inverter circuit according to a modified example of the third embodiment. [Figure 31] 10 is a timing chart used to control the inverter circuit of the third embodiment. [Figure 32] FIG. 10 is a diagram illustrating control of an inverter circuit according to a third embodiment. [Figure 33] FIG. 10 is a diagram illustrating control of an inverter circuit according to a third embodiment. [Figure 34] FIG. 10 is a diagram illustrating control of an inverter circuit according to a third embodiment. [Figure 35] FIG. 10 is a diagram illustrating control of an inverter circuit according to a third embodiment. [Figure 36] FIG. 10 is a diagram illustrating control of an inverter circuit according to a third embodiment. [Figure 37] FIG. 10 is a diagram illustrating control of an inverter circuit according to a third embodiment. [Figure 38] FIG. 10 is a diagram illustrating control of an inverter circuit according to a third embodiment. [Figure 39] FIG. 10 is a diagram illustrating control of an inverter circuit according to a third embodiment. [Figure 40] 4 is a specific timing chart used to control the inverter circuits according to the first to third embodiments. [Figure 41]FIG. 10 is a diagram summarizing gate control of the RC-IGBT according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - The n type indicates that the impurity concentration is lower than that of the n type. + The p type indicates that the impurity concentration is higher than that of the n type. - The impurity concentration is lower than that of p-type, and p + The type indicates that the impurity concentration is higher than that of the p-type.

[0010] Furthermore, the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0011] In addition, in the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and are not related to the directions in which the embodiments are actually implemented.

[0012] <First Embodiment> <Device configuration> FIG. 1 is a circuit diagram showing a configuration of an inverter circuit IV1 according to a first embodiment of the present disclosure, and shows an inverter circuit for one phase.

[0013] 1 is configured by connecting an RC-IGBT100 (first switching device) constituting a high-side arm and an RC-IGBT200 (second switching device) constituting a low-side arm in series between a power supply potential VCC (first potential) and a reference potential GND (second potential). The connection node between the RC-IGBT100 and the RC-IGBT200 is connected to an inductance load L1.

[0014] The RC-IGBT100 uses the gate signal G I1_H (first gate signal) to the IGBT region T1 controlled by the gate signal G D_H The diode regions D1 controlled by a diode gate signal are connected in antiparallel.

[0015] In addition, the RC-IGBT200 uses the gate signal G I1_L (first gate signal) to the IGBT region T2 controlled by the gate signal G D_L The diode region D2 controlled by the diode gate signal (D1) is connected in inverse parallel.

[0016] Here, the gate signal G I1_H is the IGBT area T 1 The first Trench Gate and the gate signal G I1_L is the IGBT area T 2 The first Trench Gate Also, the gate signal G D_H is applied to the diode trench provided in the diode region D1, and the gate signal G D_L is provided to a diode trench provided in the diode region D2.

[0017] In this way, the gate signal G D_H and gate signal G D_L By using such a control signal, control becomes easier compared to a conventional semiconductor device that uses two gate signals.

[0018] FIG. 2 is a plan view of the RC-IGBT 100 of the inverter circuit IV1 of Embodiment 1 as viewed from the upper surface side, and FIG. 3 is a plan view as viewed from the lower surface side. Hereinafter, for convenience, the IGBT region T1 is referred to as the IGBT region 10 (transistor region), and the diode region D1 is referred to as the diode region 20 (diode region). In the following, in the plan view, illustration of electrodes, insulating films, etc. provided on the semiconductor substrate is omitted for convenience.

[0019] As shown in FIG. 2, the RC-IGBT 100 is provided with the IGBT region 10 and the diode region 20 arranged side by side in a stripe shape, and this can be called a "stripe type". Also, there is a configuration in which a plurality of diode regions 20 are provided in the vertical and horizontal directions, and the IGBT region 10 is provided around the diode region 20, and this can be called an "island type". Hereinafter, the stripe type is taken as an example, but the same effect is obtained when the island type is adopted.

[0020] In FIG. 2, the IGBT region 10 and the diode region 20 extend from one end side to the other end side of the RC-IGBT 100, and are provided alternately in a stripe shape in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. Also, the locations of the IGBT region 10 and the diode region 20 in FIG. 2 can be interchanged, and a configuration in which all the IGBT regions 10 are sandwiched by the diode regions 20 can also be adopted. Also, a configuration in which the IGBT region 10 and the diode region 20 are provided adjacent to each other one by one can also be adopted.

[0021] <Structure of IGBT Region 10> As shown in FIG. 2, in the IGBT region 10, active trench gates 11 (first gates) are provided in a stripe shape. The active trench gates 11 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 is the longitudinal direction of the active trench gates 11.

[0022] The active trench gate 11 is configured by providing a gate trench electrode 11a via a gate trench insulating film 11b in a trench formed in a semiconductor substrate. The gate trench electrode 11a of the active trench gate 11 is electrically connected to a gate pad (not shown).

[0023] n + The source layer 13 is provided on both sides of the active trench gate 11 in the width direction so as to contact the gate trench insulating film 11b. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 n + The p-type source layer 13 is formed along the extension direction of the active trench gate 11. + The metal contact layer 14 is provided alternately.

[0024] p + The contact layer 14 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 is.

[0025] 4 shows a cross-sectional view of the RC-IGBT 100 taken along the dashed line AA in FIG. 2. In FIG. 4, the RC-IGBT 100 is an n-type IGBT made of a semiconductor substrate. - The n-type drift layer 1 is - The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 The semiconductor substrate is + type source layer 13 and p + The n-type contact layer 14 extends to the p-type collector layer 16. + type source layer 13 and p+ The upper end of the p-type contact layer 14 on the paper is called the first main surface (upper surface) of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper is called the second main surface (lower surface) of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the RC-IGBT 100, and the second main surface of the semiconductor substrate is the main surface on the lower side of the RC-IGBT 100. In the RC-IGBT 100, an n-type gate is formed between the first main surface and the second main surface opposite to the first main surface in the IGBT region 10, which is the cell region. - The semiconductor device has a type drift layer 1.

[0026] In the IGBT region 10, n - On the first main surface side of the n-type drift layer 1, - The n-type carrier accumulation layer 2 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 13 / cm 3 ~1.0×10 17 / cm 3 In the RC-IGBT 100, the n-type carrier accumulation layer 2 is not provided, and the n-type carrier accumulation layer 2 is not provided in the region of the n-type carrier accumulation layer 2. - The n-type drift layer 1 can be provided. By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows through the IGBT region 10. - The combined layer and the type drift layer 1 can also be called a drift layer.

[0027] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, there is provided an n-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11. +A p-type source layer 13 is provided in the remaining region. + A contact layer 14 is provided. + type source layer 13 and p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15. + When it is necessary to distinguish between the p-type contact layer 14 and the p-type base layer 15, they can be referred to individually. + The p-type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.

[0028] In addition, the RC-IGBT100 - On the second main surface side of the n-type drift layer 1, - The n-type buffer layer 3 has a higher concentration of n-type impurities than the p-type drift layer 1. The n-type buffer layer 3 is provided to prevent punch-through of a depletion layer extending from the p-type base layer 15 toward the second main surface when the RC-IGBT 100 is in an off state. The n-type buffer layer 3 is doped with, for example, phosphorus (P) or protons (H + ) can be implanted, or it can be formed by implanting both phosphorus and protons. The concentration of n-type impurities in the n-type buffer layer 3 is 1.0×10 12 / cm 3 ~1.0×10 18 / cm 3 is.

[0029] The RC-IGBT 100 does not have the n-type buffer layer 3, and the n-type buffer layer 3 shown in FIG. - The n-type buffer layer 3 and the n-type drift layer 1 may be provided. - The combined layer and the type drift layer 1 can also be called a drift layer.

[0030] In the RC-IGBT 100, a p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. -A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 16 / cm 3 ~1.0×10 20 / cm 3 The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 can be provided so that a part of it protrudes from the IGBT region 10 into the diode region 20.

[0031] The RC-IGBT 100 has an n-type IGBT extending from the first main surface of the semiconductor substrate through the p-type base layer 15. - A trench is formed in the trench, reaching the drift layer 1. A gate trench electrode 11a is provided in the trench via a gate trench insulating film 11b, thereby forming an active trench gate 11.

[0032] The gate trench electrode 11a is connected to the n-type gate electrode 11b via the gate trench insulating film 11b. - The gate trench insulating film 11b of the active trench gate 11 faces the p-type base layer 15 and the n-type drift layer 1. + The active trench gate 11 is in contact with the p-type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0033] An interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. The interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11, and a gate signal G I1 The emitter electrode 6 is insulated for input of the

[0034] A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), and may be, for example, titanium nitride or TiSi, which is an alloy of titanium and silicon (Si). The barrier metal 5 may be n + Mold Source Layer 1 3O Call n + Mold contact layer 17 ohmic contact to n + Mold Source Layer 1 3O Call n + Mold contact layer 17 The emitter electrode 6 is electrically connected to the barrier metal 5. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can be formed of, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or it can be an electrode composed of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating can be, for example, a nickel (Ni) plating film. Furthermore, if there are fine regions, such as between adjacent interlayer insulating films 4, where the emitter electrode 6 cannot be satisfactorily embedded, tungsten, which has better embedding properties than the emitter electrode 6, can be disposed in the fine regions, and the emitter electrode 6 can be provided on the tungsten. Note that, without providing the barrier metal 5, it is also possible to form n + Mold Source Layer 1 3O Call n + Mold contact layer 17 An emitter electrode 6 can also be provided on the n + The barrier metal 5 can be provided only on the n-type semiconductor layer such as the n-type source layer 13. The barrier metal 5 and the emitter electrode 6 can be collectively called an emitter electrode.

[0035] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. Like the emitter electrode 6, the collector electrode 7 can be made of an aluminum alloy or an aluminum alloy and a plating film. The collector electrode 7 can also have a different structure from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0036] The cross section of the RC-IGBT 100 taken along the dashed line BB in FIG. 5 differs from the cross section taken along the dashed line AA in that the n-type IGBT 100 is provided on the first main surface side of the semiconductor substrate in contact with the active trench gate 11. + The difference is that the n-type source layer 13 is not visible in the cross section taken along the dashed line BB. + The p-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. + The p-type contact layer 14 is collectively called the p-type base layer.

[0037] <Structure of diode region 20> 2, the diode trench gate 21 (diode gate) extends from one end side to the opposing other end side of the diode region 20, which is a cell region, along the first main surface of the RC-IGBT 100. The diode trench gate 21 is configured by providing a diode trench electrode 21a in a trench formed in the semiconductor substrate of the diode region 20 via a diode trench insulating film 21b.

[0038] As shown in FIG. 5, the diode trench electrode 21a is connected to the n-type diode trench via the diode trench insulating film 21b. - The n-type drift layer 1 is opposed to the n-type drift layer 1. + type contact layer 17 and p + A contact layer 24 is provided. + The contact layer 17 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3~1.0×10 20 / cm 3 p + The contact layer 24 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 n + Type contact layer 17 and p + The mold contact layers 24 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0039] As shown in FIG. 4, the cross section of the RC-IGBT 100 taken along the dashed line AA shows that the diode region 20 is also made of a semiconductor substrate, just like the IGBT region 10. - The n-type drift layer 1 is formed in the diode region 20. - n-type drift layer 1 and IGBT region 10 - The n-type drift layer 1 is formed integrally and continuously from the same semiconductor substrate. + The upper end of the n-type contact layer 17 in the drawing corresponds to the first main surface of the semiconductor substrate. + The lower end of the cathode layer 26 in the drawing is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are flush with each other, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are flush with each other.

[0040] In the diode region 20, similar to the IGBT region 10, n - An n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, -An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the IGBT region 10. Note that it is not always necessary to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20, and even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, the diode region 20 may not have the n-type carrier accumulation layer 2. Also, like the IGBT region 10, - The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 can be collectively referred to as a drift layer. + A contact layer 17 is provided. + The contact layer 17 is an n-type - The gate electrode is provided between the drift layer 1 and the first main surface.

[0041] The first main surface side of the p-type anode layer 25 is + A contact layer 17 is provided. + The concentration of the n-type impurity in the contact layer 17 is + The concentration of the n-type impurity in the n-type source layer 13 may be the same as or different from the n-type impurity in the n-type source layer 13. + The n-type contact layer 17 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 17 is a region with a higher concentration than the p-type anode layer 25.

[0042] In the diode region 20, an n-type buffer layer 3 is provided on the second main surface side thereof. + A cathode layer 26 is provided. + The cathode layer 26 is an n-type - The n-type drift layer 1 is provided between the n-type drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 16 / cm 3 ~1.0×10 21 / cm 3n + The cathode layer 26 is provided on part or all of the diode region 20. + The cathode layer 26 forms the second main surface of the semiconductor substrate. + The p-type impurity is further selectively implanted into the region where the p-type cathode layer 26 is formed, + A part of the region where the cathode layer 26 is formed can be made into a p-type semiconductor to provide a p-type cathode layer.

[0043] The diode region 20 of the RC-IGBT 100 includes an n-type anode layer 25 extending from the first main surface of the semiconductor substrate. - A trench is formed in the diode region 20, reaching the n-type drift layer 1. A diode trench electrode 21a is provided in the trench of the diode region 20 via a diode trench insulating film 21b, thereby forming a diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - The semiconductor layer 1 faces the semiconductor layer 2 .

[0044] a diode trench electrode 21a, and p + Mold contact layer 24 A barrier metal 5 is provided on the p + Mold contact layer 24 The barrier metal 5 can have the same structure as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. As in the case of the IGBT region 10, the barrier metal 5 can be omitted and the p + The interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, and the gate signal G D The emitter electrode 6 is insulated for input of the

[0045] n + A collector electrode 7 is provided on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is an n-type + ohmic contact with the n-type cathode layer 26, + The cathode layer 26 is electrically connected to the cathode layer 26 .

[0046] 5, the cross section of the RC-IGBT 100 taken along the dashed line BB differs from the cross section taken along the dashed line AA in FIG. 4 in that a p+ type contact layer 24 is provided between the p-type anode layer 25 and the barrier metal 5. The barrier metal 5 is p + The barrier metal 5 is in ohmic contact with and electrically connected to the type contact layer 24. The barrier metal 5 can have the same structure as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. As in the case of the IGBT region 10, the p + It is also possible to make ohmic contact with the mold contact layer 24 .

[0047] In FIG. 3, which is a plan view of the RC-IGBT 100 as seen from the bottom side, i.e., the collector electrode 7 side, the collector electrode 7 is omitted for convenience, and only the p-type collector layer 16 and the n-type collector layer 17 are shown. + 3 shows a state in which the mold cathode layer 26 is exposed. Note that the cross-sectional views taken along dashed lines AA and BB in Fig. 3 are the same as Figs. 4 and 5, respectively.

[0048] <Modification> Next, an RC-IGBT 101 according to a modification of the first embodiment will be described with reference to Fig. 6 to Fig. 8. Fig. 6 is a plan view of the RC-IGBT 101 as viewed from above, Fig. 7 is a cross-sectional view taken along dashed line AA in Fig. 6, and Fig. 8 is a cross-sectional view taken along dashed line BB in Fig. 6.

[0049] <Structure of IGBT Region 10> As shown in FIG. 6, in the IGBT region 10 of the RC-IGBT 101, an active trench gate 11 and a dummy trench gate 12 are provided in a stripe shape. The active trench gate 11 and the dummy trench gate 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 is the same as the longitudinal directions of the active trench gate 11 and the dummy trench gate 12.

[0050] As shown in FIG. 7, the active trench gate 11 is configured such that a gate trench electrode 11a is provided in a trench formed in a semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 is configured such that a dummy trench electrode 12a is provided in a trench formed in the semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to a gate pad (not shown). The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode 6 provided on the first main surface of the RC-IGBT 101.

[0051] n + type source layers 13 are provided on both sides in the width direction of the active trench gate 11 in contact with the gate trench insulating film 11b. n + type source layer 13 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 is. n + type source layer 13 is provided alternately with a p + type contact layer 14 along the extending direction of the active trench gate 11. p + type contact layer 14 is also provided between two adjacent dummy trench gates 12. p + type contact layer 14 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 15 / cm3 ~1.0×10 20 / cm 3 is.

[0052] The number of dummy trench gates 12 included in the IGBT region 10 can be one or more, but the number of dummy trench gates 12 can also be zero. In other words, all of the trenches provided in the IGBT region 10 can be active trench gates 11. In that case, the result is an RC-IGBT 100 shown in FIG. 2.

[0053] The gate trench electrode 11a is connected to the n-type gate electrode 11b via the gate trench insulating film 11b. - The dummy trench electrode 12a faces the n-type drift layer 1. The dummy trench electrode 12a is connected to the n-type drift layer 1 via the dummy trench insulating film 12b. - 7, which is a cross-sectional view taken along dashed line AA, and FIG. 8, which is a cross-sectional view taken along dashed line BB, the n-type drift layer 1 in the region where the dummy trench gate 12 is provided is + Type source layer 13 and p + The contact layer 14 is insulated from the emitter electrode 6 by an interlayer insulating film 4. The configuration of the diode region 20 is the same as that of the RC-IGBT 100.

[0054] By providing the dummy trench gate 12, the carrier accumulation effect is enhanced, and the effect of reducing conduction loss due to the lower resistance is obtained.

[0055] <Operation> Next, gate control in the RC-IGBT 100 will be described with reference to Figures 9 to 17. Figure 9 shows, on the left, a timing chart of gate control of the RC-IGBT 100 that constitutes the high-side arm of the inverter circuit IV1 shown in Figure 1, and, on the right, a timing chart of gate control of the RC-IGBT 200 that constitutes the low-side arm.

[0056] In the left diagram of FIG. 9, the upper part shows the gate signal G given to the active trench gate 11 in the IGBT region. I1The middle part shows the timing chart of the gate signal G given to the diode trench gate 21 in the diode region. D 10 shows a timing chart of the output of the inverter circuit IV1, and the lower part shows a timing chart of the output of the inverter circuit IV1.

[0057] In the right diagram of FIG. 9, the upper part shows the gate signal G given to the active trench gate 11 in the IGBT region. I1 The middle part shows the timing chart of the gate signal G given to the diode trench gate 21 in the diode region. D 10 shows a timing chart of the output of the inverter circuit IV1, and the lower part shows a timing chart of the output of the inverter circuit IV1.

[0058] As shown in FIG. 9, the RC-IGBT 100 and the RC-IGBT 200 are controlled by PWM (Pulse Width Modulation). In response to the PWM signal, a pulse signal inverted between the high side and the low side is input to the active trench gate 11 in the IGBT region, and a gate signal G given to the active trench gate 11 is input to the diode trench gate 21 in the diode region. I1 A pulse signal generated based on the reference is input.

[0059] Since the RC-IGBT100 and the RC-IGBT200 have the same configuration, the following description will be given using the RC-IGBT100 as an example. In each of Figures 10 to 17, the left diagram shows a timing chart for the RC-IGBT100, and the right diagram shows a cross-sectional view of the RC-IGBT100 corresponding to Figure 4. In Figures 10 to 17, the size of the arrows schematically represents the amount of hole injection.

[0060] 10 shows the carrier state in the RC-IGBT 100 at time t1 on the timing chart in the left diagram. At time t1, the IGBT region 10 is in forward conduction, and only the active trench gate 11 on the emitter electrode 6 side of the IGBT region 10 is turned on. Holes are injected from the collector electrode 7 and conduct forward through the channel layer CH formed on the side of the active trench gate 11.

[0061] 11 shows the carrier state in the RC-IGBT 100 at time t2a on the timing chart on the left. At time t2a, the IGBT region 10 is being prepared to turn off, and the diode trench gate 21 in the diode region 20 is also turned on, forming a channel layer CH on the side surface. However, since the regions are different, this does not significantly affect the injection of holes from the bottom surface.

[0062] 12 shows the carrier state in the RC-IGBT 100 at time t2b on the timing chart on the left. At time t2b, the IGBT region 10 is turned off, and both the active trench gate 11 and the diode trench gate 21 are turned off. However, hole injection continues unchanged until the diode region of the reverse arm becomes conductive, and forward conduction continues.

[0063] The right diagram in Figure 13 shows the carrier state in the RC-IGBT 100 at time t3 on the timing chart on the left. At time t3, the IGBT region 10 is non-conductive, and since all gates are OFF, hole injection stops and there is no conduction. Up to this point, we have been explaining the IGBT mode, and the operation is the same as that of a conventional RC-IGBT.

[0064] 14 shows the carrier state in the RC-IGBT 100 at time t4 on the timing chart on the left. At time t4, the diode region 20 is in reverse conduction, and the active trench gate 11 of the IGBT region 10 is turned on. However, since there is a distance between the active trench gate 11 and the diode region 20, holes are injected from the emitter electrode 6, causing reverse conduction in the diode region 20.

[0065] 15 shows the carrier state in the RC-IGBT 100 at time t5a on the timing chart on the left. At time t5a, the diode region 20 is preparing for reverse recovery, and the diode trench gate 21 is turned on, reducing the amount of holes injected into the diode region 20.

[0066] The right diagram in Figure 16 shows the carrier state in the RC-IGBT 100 at time t5b on the timing chart on the left. Time t5b is the time of reverse recovery of the diode region 20, and reverse recovery occurs when the IGBT region of the reverse arm turns on. In this case, the amount of injected holes decreases, and the number of internal carriers decreases, resulting in a decrease in reverse recovery loss.

[0067] 17 shows the carrier state in the RC-IGBT 100 at time t6 on the timing chart on the left. At time t6, the diode region 20 is non-conductive, and the diode is not conductive because a voltage is applied in the direction that blocks current.

[0068] In the diode mode described above, reverse recovery loss is significantly reduced compared to conventional RC-IGBTs.

[0069] <Embodiment 2> <Device configuration> FIG. 18 is a circuit diagram showing a configuration of an inverter circuit IV2 according to the second embodiment of the present disclosure, and shows an inverter circuit for one phase.

[0070] The inverter circuit IV2 shown in Fig. 18 is configured by connecting in series between a power supply potential VCC and a reference potential GND an RC-IGBT100A (first switching device) constituting a high-side arm and an RC-IGBT200A (second switching device) constituting a low-side arm. The connection node between the RC-IGBT100A and the RC-IGBT200A is connected to an inductance load L1. The RC-IGBT100A is connected to an inductance load L1 in response to a gate signal G I1_H (first gate signal) and gate signal GI2_H The diode region D10 is connected in anti-parallel to the IGBT region T10 controlled by the (second gate signal).

[0071] In addition, the RC-IGBT200A uses the gate signal G I1_L (first gate signal) and gate signal G I2_L The diode region D20 is connected in antiparallel to the IGBT region T20 controlled by the (second gate signal).

[0072] Here, the gate signal G I2_H is supplied to a second gate trench provided in the IGBT region T10, and a gate signal G I2_L is provided to a second gate trench provided in the IGBT region T20.

[0073] In this way, the gate signal G I2_H and gate signal G I2_L By using control signals such as these, control becomes easier and power loss can be significantly reduced compared to when each arm is controlled by a single gate signal.

[0074] Fig. 19 is a plan view of the RC-IGBT 100A of the inverter circuit IV2 of the second embodiment as seen from the top side, and Fig. 20 is a plan view of the RC-IGBT 100A as seen from the bottom side. Note that, for the sake of convenience, the IGBT region T10 will be referred to as the IGBT region 10 and the diode region D10 as the diode region 20 below.

[0075] As shown in FIG. 19, the RC-IGBT 100A has an IGBT region 10 and a diode region 20 arranged in a stripe pattern. The IGBT region 10 is the same as the RC-IGBT 100 shown in FIG. 2, but in the diode region 20, there is a P + Only the mold contact layer 24 is provided.

[0076] 20, active trench gates 18 (second gates) are provided in a stripe pattern on the underside of the IGBT region 10. The active trench gates 18 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 is the same as the longitudinal direction of the active trench gates 18.

[0077] The active trench gate 18 is configured by providing a gate trench electrode 18a in a trench formed in a semiconductor substrate via a gate trench insulating film 18b. The gate trench electrode 18a of the active trench gate 18 is electrically connected to a gate pad (second gate pad) not shown.

[0078] P-type collector layers 16 are provided on both sides of the active trench gate 18 in the width direction, in contact with the gate trench insulating films 18b. The p-type collector layers 16 are semiconductor layers containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p-type collector layer 16 is arranged along the extension direction of the active trench gate 18 as follows: n + The mold collector layers 19 are alternately provided.

[0079] n + The mold collector layer 19 is n For example, as a type impurity arsenic or Phosphorus The semiconductor layer has a p-type impurity concentration of 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 is.

[0080] 20, diode trench gates 22 are provided in a stripe pattern on the underside of the diode region 20. The diode trench gates 22 extend in the longitudinal direction of the diode region 20, and the longitudinal direction of the diode region 20 coincides with the longitudinal direction of the diode trench gates 22.

[0081] The diode trench gate 22 is configured by providing a diode trench electrode 22a in a trench formed in a semiconductor substrate via a diode trench insulating film 22b. + A mold cathode layer 26 is provided.

[0082] Figure 19 and Figure 20 A cross-sectional view of the RC-IGBT 100A shown in Fig. 21 taken along dashed line CC is shown, and a cross-sectional view of the RC-IGBT 100A taken along dashed line DD is shown in Fig. 22. Note that the same components as those in the cross section of the RC-IGBT 100 shown in Figs. 4 and 5 are denoted by the same reference numerals, and redundant explanations will be omitted.

[0083] In FIG. 21, the lower surface of the IGBT region 10 is n + The p-type collector layer 19, the p-type collector layer 16, and the n-type buffer layer 3 are provided in this order from the second main surface of the semiconductor substrate, and these impurity layers are in contact with the gate trench insulating film 18b on both sides in the width direction of the active trench gate 18. The bottom of the active trench gate 18 is an n-type - The electrode extends into the drift layer 1.

[0084] An interlayer insulating film 4 is provided on the gate trench electrode 18a of the active trench gate 18. The interlayer insulating film 4 is formed on the gate trench electrode 18a of the active trench gate 18, and the gate signal G I2 The collector electrode 7 is insulated for input.

[0085] A barrier metal 5 is formed on the interlayer insulating film 4 and on the region of the second main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided.

[0086] In FIG. 21, the upper surface of the diode region 20 is + The p-type contact layer 24, the p-type anode layer 25, and the n-type carrier accumulation layer 2 are provided in this order from the first main surface of the semiconductor substrate, and these impurity layers are in contact with the diode trench insulating film 21b on both sides in the width direction of the diode trench gate 21. The bottom of the diode trench gate 21 is an n-type - The electrode extends into the drift layer 1.

[0087] An interlayer insulating film 4 is provided on the diode trench electrode 21a of the diode trench gate 21. The interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, and the diode trench electrode 21a is electrically connected to the emitter electrode 6.

[0088] A barrier metal 5 is formed on the interlayer insulating film 4 and on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided.

[0089] In FIG. 21, the bottom surface of the diode region 20 is + Mold cathode layer 26 and n-type buffer layer 3 are provided in this order from the second main surface of the semiconductor substrate, and these impurity layers are in contact with diode trench insulating film 22b on both sides in the width direction of diode trench gate 22. In addition, the bottom of diode trench gate 22 is n - The electrode extends into the drift layer 1.

[0090] An interlayer insulating film 4 is provided on the diode trench electrode 22a of the diode trench gate 22. The interlayer insulating film 4 is formed on the diode trench electrode 22a of the diode trench gate 22, and the diode trench electrode 22a is electrically connected to the collector electrode 7.

[0091] In FIG. 22, the upper surface of the IGBT region 10 is +The p-type contact layer 14, the p-type base layer 15, and the n-type carrier accumulation layer 2 are provided in this order from the first main surface of the semiconductor substrate, and these impurity layers are in contact with the gate trench insulating film 11b on both sides in the width direction of the active trench gate 11. The bottom of the active trench gate 11 is an n-type - The electrode extends into the drift layer 1.

[0092] 22, a p-type collector layer 16 and an n-type buffer layer 3 are provided in this order from the second main surface of the semiconductor substrate on the underside of the IGBT region 10, and these impurity layers are in contact with the gate trench insulating film 18b on both sides in the width direction of the active trench gate 18. The bottom of the active trench gate 18 is an n-type impurity layer. - The electrode extends into the drift layer 1.

[0093] In the inverter circuit IV2 of the second embodiment described above, the turn-off loss in the IGBT region can be significantly reduced by a relatively simple control method that controls only the active trench gates 11 and 18. The mechanism behind this will be described later.

[0094] Additionally, a diode trench gate 21 is provided on the upper side of the diode region 20, and a diode trench gate 22 is provided on the lower side. The diode trench electrode 21a and diode trench electrode 22a are fixed to the potentials of the emitter electrode 6 and collector electrode 7, respectively. Therefore, although the diode trench gates 21 and 22 do not function actively, their provision makes the trench arrangement uniform, preventing the generation of localized high electric fields due to uneven structures and facilitating high breakdown voltage. Note that the active trench gate 11 on the upper side of the IGBT region 10 and the active trench gate 18 on the lower side do not need to face each other, and the number of them does not need to be the same. Similarly, the diode trench gate 21 on the upper side of the diode region 20 and the diode trench gate 22 on the lower side do not need to face each other, and the number of them does not need to be the same.

[0095] <Third Embodiment> <Device configuration> FIG. 23 is a circuit diagram showing a configuration of an inverter circuit IV3 according to the third embodiment of the present disclosure, and shows an inverter circuit for one phase.

[0096] The inverter circuit IV3 shown in Fig. 23 is configured by connecting in series between a power supply potential VCC and a reference potential GND an RC-IGBT100B (first switching device) constituting a high-side arm and an RC-IGBT200B (second switching device) constituting a low-side arm. The connection node between the RC-IGBT100B and the RC-IGBT200B is connected to an inductance load L1. The RC-IGBT100B is connected to an inductance load L1 in response to a gate signal G I1_H (first gate signal) and gate signal G I2_H (second gate signal) to the IGBT region T10 controlled by the gate signal G D_H The diode regions D1 controlled by a diode gate signal are connected in antiparallel.

[0097] In addition, the RC-IGBT200B uses the gate signal G I1_L (first gate signal) and gate signal G I2_L (second gate signal) to the IGBT region T20 controlled by the gate signal G D_L The diode region D2 controlled by the diode gate signal (D1) is connected in inverse parallel.

[0098] Here, the gate signal G I2_H is supplied to a second gate trench provided in the IGBT region T10, and a gate signal G I2_L is applied to a second gate trench provided in the IGBT region T20. D_H is applied to the diode trench provided in the diode region D1, and the gate signal G D_L is provided to a diode trench provided in the diode region D2.

[0099] In this way, the gate signal G I2_H, gate signal G I2_L , gate signal G D_H and gate signal G D_L By using control signals such as these, control becomes easier and power loss can be significantly reduced compared to when each arm is controlled by a single gate signal.

[0100] Fig. 24 is a plan view of the RC-IGBT 100B of the inverter circuit IV3 of the third embodiment as seen from the top side, and Fig. 25 is a plan view of the RC-IGBT 100B as seen from the bottom side. Note that, for the sake of convenience, the IGBT region T10 will be referred to as the IGBT region 10 and the diode region D1 will be referred to as the diode region 20 below.

[0101] As shown in Fig. 24, the top surface configuration of the RC-IGBT 100B is the same as the top surface configuration of the RC-IGBT 100 according to the first embodiment shown in Fig. 2. Furthermore, the bottom surface configuration of the RC-IGBT 100B is the same as the bottom surface configuration of the RC-IGBT 100A according to the second embodiment shown in Fig. 20.

[0102] Figure 24 and Figure 25 A cross-sectional view of the RC-IGBT 100B shown in FIG. 26 is taken along the dashed line CC, and a cross-sectional view of the RC-IGBT 100B shown in FIG. 27 is taken along the dashed line DD. The cross-sectional structure shown in FIG. 26 is basically the same as the cross-sectional structure of the RC-IGBT 100A of the second embodiment shown in FIG. 21, but in the diode region 20 of FIG. 26, on the upper surface side, + The p-type contact layer 17, the p-type anode layer 25, and the n-type carrier accumulation layer 2 are provided in this order from the first main surface of the semiconductor substrate, and these impurity layers are in contact with the diode trench insulating film 21b on both sides in the width direction of the diode trench gate 21. The bottom of the diode trench gate 21 is an n-type - The diode trench electrode 21a is connected to the gate signal G Dis input. The active trench gates 11 on the upper side of the IGBT region 10 and the active trench gates 18 on the lower side do not need to face each other, and the numbers of them do not need to be the same. Similarly, the diode trench gates 21 on the upper side of the diode region 20 and the diode trench gates 22 on the lower side do not need to face each other, and the numbers of them do not need to be the same.

[0103] The cross-sectional structure shown in FIG. 27 is basically the same as the cross-sectional structure of the RC-IGBT 100A of the second embodiment shown in FIG. 22, but the diode trench electrode 21a is provided with a gate signal G D is input.

[0104] In the inverter circuit IV3 of the third embodiment described above, the active trench gate 11 is provided on the upper surface side of the IGBT region 10, the active trench gate 18 is provided on the lower surface side, the diode trench gate 21 is provided on the upper surface side of the diode region 20, and the diode trench gate 22 is provided on the lower surface side. The diode trench gate 21 is connected to the gate signal G D This is used to control the RC-IGBT 100B. This configuration makes it possible to significantly reduce the turn-off loss in the IGBT region and the reverse recovery loss in the diode region with a relatively simple control method. The mechanism behind this will be explained later.

[0105] <Modification> Next, an RC-IGBT 100B1 according to a modification of the third embodiment will be described with reference to Fig. 28 to Fig. 30. Fig. 28 is a plan view of the RC-IGBT 100B1 as viewed from the bottom, Fig. 29 is a cross-sectional view taken along dashed line CC in Fig. 28, and Fig. 30 is a cross-sectional view taken along dashed line DD in Fig. 28. The top surface configuration of the RC-IGBT 100B1 is the same as that in Fig. 24.

[0106] In FIG. 28, a plurality of stripe-shaped p-type collector layers 16 are provided on the lower surface side of the IGBT region 10, and a plurality of p-type collector layers 16 are arranged so as to be surrounded by the p-type collector layers 16. n +The region sandwiched between the p-type collector layers 16 is an n-type buffer layer 3.

[0107] In FIG. 28, the bottom surface of the diode region 20 is + A mold cathode layer 26 is provided over one surface.

[0108] In the cross-sectional configuration shown in FIG. 29, the upper surface side is the same as that in FIG. 26, but a planar gate 181 is provided on the lower surface side of the IGBT region 10 instead of the active trench gate 18. The planar gate 181 is n + The gate electrode 181a is covered with the interlayer insulating film 4 and is connected to the gate electrode 181b. I2 For input, it is insulated from the collector electrode 7. The active trench gate 11 on the upper surface side can also be configured as a planar gate.

[0109] In addition, the bottom surface of the diode region 20 is + A cathode layer 26 is provided. + A barrier metal 5 is provided on the mold cathode layer 26, the interlayer insulating film 4, and the region where the interlayer insulating film 4 is not provided. collector electrode 7 will be established.

[0110] The cross-sectional structure shown in FIG. 30 is basically the same as that shown in FIG. 29, and the p-type collector layer 16 has a p-type + The mold collector layer 19 is not provided.

[0111] In the RC-IGBT 100B1 described above, a planar gate 181 is provided instead of the active trench gate 18, but even in this configuration, the turn-off loss in the IGBT region and the reverse recovery loss in the diode region are significantly reduced.

[0112] <Operation> Next, gate control in the RC-IGBT 100B will be described with reference to Figs. 31 to 39. Fig. 31 shows, on the left, a timing chart of gate control of the RC-IGBT 100B that constitutes the high-side arm of the inverter circuit IV3 shown in Fig. 23, and, on the right, a timing chart of gate control of the RC-IGBT 200B that constitutes the low-side arm. 32 In FIG. 39, the size of the arrows schematically represents the amount of injected holes.

[0113] In the left diagram of FIG. 31, the top row shows a timing chart of a gate signal given to the RC-IGBT that constitutes the high-side arm of a conventional inverter circuit, and the second row from the top shows a timing chart of a gate signal G given to the active trench gate 11 in the IGBT region. I1 The third row from the top shows the timing chart of the gate signal G given to the active trench gate 18 in the IGBT region. I2 The fourth row from the top shows the timing chart of the gate signal G given to the diode trench gate 21 in the diode region. D 10 shows a timing chart of the output of the inverter circuit IV3, and the bottom shows a timing chart of the output of the inverter circuit IV4.

[0114] In the right diagram of FIG. 31, the top row shows a timing chart of a gate signal given to the RC-IGBT that constitutes the low-side arm of a conventional inverter circuit, and the second row from the top shows a timing chart of a gate signal G given to the active trench gate 11 in the IGBT region. I1 The third row from the top shows the timing chart of the gate signal G given to the active trench gate 18 in the IGBT region. I2 The fourth row from the top shows the timing chart of the gate signal G given to the diode trench gate 21 in the diode region. D 10 shows a timing chart of the output of the inverter circuit IV3, and the bottom shows a timing chart of the output of the inverter circuit IV4.

[0115] As shown in FIG. 31, the RC-IGBT 100B and the RC-IGBT 200B are PWM controlled, and in response to the PWM signal, pulse signals inverted on the high side and low side are input to the active trench gate 11 and the active trench gate 18 in the IGBT region, and the gate signal G given to the active trench gate 11 is input to the diode trench gate 21 in the diode region. I1 A pulse signal generated based on the reference is input.

[0116] Since the RC-IGBT 100B and the RC-IGBT 200B have the same configuration, the following description will be given taking the RC-IGBT 100B as an example. In each of Figures 32 to 39, the left diagram shows a timing chart for the RC-IGBT 100B, and the right diagram shows a cross-sectional view of the RC-IGBT 100B corresponding to Figure 26.

[0117] 32 shows the carrier state in the RC-IGBT 100B at time t1 on the timing chart on the left. At time t1, the IGBT region 10 is in forward conduction, and only the active trench gate 11 on the emitter electrode 6 side of the IGBT region 10 is turned on. Holes are injected from the collector electrode 7 and conduct forward through the channel layer CH formed on the side of the active trench gate 11.

[0118] The right diagram in Figure 33 shows the carrier state in the RC-IGBT 100B at time t2a on the timing chart on the left diagram. At time t2a, the IGBT region 10 is preparing to turn off, and the diode trench gate 21 in the diode region 20 is turned ON, and the active trench gate 18 is also turned ON, reducing hole injection from the bottom surface.

[0119] The right diagram in Figure 34 shows the carrier state in the RC-IGBT 100B at time t2b on the timing chart in the left diagram. Time t2b is when the IGBT region 10 is turned off, and both the active trench gate 11 and the diode trench gate 21 are turned off. However, hole injection continues until the diode region of the reverse arm becomes conductive, and forward conduction continues. However, because the active trench gate 18 is turned on, hole injection decreases, resulting in a reduction in turn-off loss.

[0120] The right diagram of FIG. 35 shows the carrier state in the RC-IGBT 100B at time t3 on the timing chart of the left diagram. At time t3, the IGBT region 10 is non-conductive, and hole injection stops and no conduction occurs because gates other than the active trench gate 18 are turned off. In the above IGBT mode, turn-off loss is significantly reduced compared to a conventional RC-IGBT. This mechanism for significantly reducing turn-off loss is also the same in the configuration of the inverter circuit IV2 of the second embodiment.

[0121] 36 shows the carrier state in the RC-IGBT 100B at time t4 on the timing chart on the left. At time t4, the diode region 20 is in reverse conduction, and the active trench gate 11 of the IGBT region 10 is turned on. However, since there is a distance between the active trench gate 11 and the diode region 20, holes are injected from the emitter electrode 6, causing reverse conduction in the diode region 20.

[0122] 37 shows the carrier state in the RC-IGBT 100B at time t5a on the timing chart on the left. At time t5a, the diode region 20 is preparing for reverse recovery, and the diode trench gate 21 is turned on, reducing the amount of holes injected into the diode region 20.

[0123] The right diagram in Figure 38 shows the carrier state in the RC-IGBT 100B at time t5b on the timing chart in the left diagram. Time t5b is the time of reverse recovery of the diode region 20, and reverse recovery occurs when the IGBT region of the reverse arm turns on. In this case, the amount of hole injection decreases, and the internal carry decreases, resulting in a decrease in reverse recovery loss.

[0124] The right diagram in Figure 39 shows the carrier state in the RC-IGBT 100B at time t6 on the timing chart on the left. At time t6, the diode region 20 is non-conductive, and the diode is not conductive because a voltage is applied in the direction that blocks current.

[0125] In the diode mode described above, reverse recovery loss is significantly reduced compared to conventional RC-IGBTs.

[0126] In this way, in the inverter circuit IV3 of the third embodiment, the RC-IGBT 100B is controlled in the IGBT mode and the diode mode, so that the turn-off loss and the reverse recovery loss are significantly reduced.

[0127] <Example of timing chart> Next, a specific example of a timing chart for controlling the RC-IGBTs of the first to third embodiments is shown in Fig. 40. Note that the RC-IGBT 100 of the first embodiment does not have the active trench gate 18, so that the gate signal G I2_H and gate signal G I2_L The timing chart excluding the above is applied, and the RC-IGBT 100 of the second embodiment A So , Ge Port signal G D_H and gate signal G D_L The timing chart except for the above applies.

[0128] In FIG. 40, the gate signal G I1_H , G I2_H , G D_H , G I1_L , G I2_L , G D_LIn FIG. 40, the gate signal G I1_H For example, as shown in the period Δtb, the active trench gate 18 is turned off during the off period (Wn_off) of the active trench gate 11, which is the main gate, and as shown in the period Δta, the gate signal G is generated so as to turn on the active trench gate 18 before the active trench gate 11 is turned off. I2_H Generate.

[0129] Here, the definition of each period in Fig. 40 will be explained. The period Δta is the period from the time when the active trench gate 18 is turned on, based on the potential of the collector electrode 7, which is the second main electrode of the IGBT region, to the time when the active trench gate 11 is turned off, based on the potential of the emitter electrode 6, which is the first main electrode of the IGBT region.

[0130] The period Δtb is the period from the time when the active trench gate 18 is turned off based on the potential of the collector electrode 7 of the IGBT region to the time when the active trench gate 11 is turned on based on the potential of the emitter electrode 6 of the IGBT region.

[0131] The period Δtc is from the time when the diode trench gate 21, which is based on the potential of the emitter electrode 6 acting as the anode electrode of the diode region, is turned on to the time when the active trench gate 11, which is based on the potential of the emitter electrode 6 of the IGBT region of the other arm, is turned on. off This is the time from the time when the diode trench gate 21 is turned off to the time when the potential of the emitter electrode 6 in the diode region is used as a reference. If the dead time within the period Δtc is short, a sufficient low-loss effect can be expected even if the dead time is synchronized with the timing when the IGBT in the same arm is turned off.

[0132] If the periods Δta and Δtc are too long, the conduction loss increases, so in order to keep the conduction loss in the IGBT region and the diode region within an allowable range, it is desirable that they be within 20 μsec, that is, a maximum of 20 μsec.

[0133] Based on this, the magnitude relationships among the periods are 20 μsec≧Δta≧0, Wn_off≧Δtb≧0, and 20 μsec≧Δtc≧0.

[0134] While the leakage current is small during the period when the active trench gate 11, which is the main gate, is off, if the period when the active trench gate 18, which is the sub-gate, is on and the period when the active trench gate 11 is on overlap, the turn-on loss increases, so this is adjusted by the period Δtb.

[0135] <Summary of gate control> Fig. 41 is a table showing gate control of the RC-IGBT 100B according to the third embodiment. Fig. 41 shows the modes at each time shown in Figs. 32 to 38 and the voltage of the gate signal in each mode. Note that voltage V in Fig. 41 is an arbitrary voltage, voltage Vc is the collector voltage, and voltage Ve is the emitter voltage.

[0136] According to the present disclosure, low-loss operation of an RC-IGBT having multiple gates is possible with the same control regardless of the direction of current, as shown in FIG.

[0137] As described above in detail, the effects described in this specification are achieved regardless of whether the IGBT region 10 or the diode region 20 is a stripe or an island, whether the gate is a trench or a planar, or whether a dummy gate is present.

[0138] <Other application examples> The semiconductor device of the present disclosure can be expected to have the effect of reducing loss in the RC-IGBT, regardless of the size of the separation region between the IGBT region 10 and the diode region 20, or even if there is no separation region. Furthermore, in the first to fourth embodiments, the active trench gate 18 penetrates through the n-type buffer layer 3 and reaches the inside of the n-type drift layer 1, but this is not limitative, and the effect of reducing loss in the RC-IGBT remains the same even if the tip of the active trench gate 18 stops within the n-type buffer layer 3.

[0139] In the above-described first to fourth embodiments, the semiconductor device of the present disclosure has been described using an RC-IGBT in which the IGBT region and the diode region are provided on the same semiconductor substrate as an example. In the case of an RC-IGBT, in addition to the above-described low loss, heat dissipation and module productivity are improved.

[0140] On the other hand, the present disclosure can also be applied to a configuration in which the IGBT region 10 and the diode region 20 are formed on separate semiconductor substrates, configured as an IGBT chip and a diode chip, respectively, and the diode chip is connected in anti-parallel to the IGBT chip, achieving the same effects as when applied to an RC-IGBT. Furthermore, by using separate chips, the IGBT chip and the diode chip do not interact with each other when reducing loss, making control easier. Also, MOSFET chips can be used instead of IGBT chips.

[0141] It should be noted that, within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

[0142] The present disclosure described above will be summarized as an appendix.

[0143] (Appendix 1) a first switching device and a second switching device connected in series between a first potential and a second potential lower than the first potential; The first and second switching devices together a transistor region and a diode region electrically connected in antiparallel to the transistor region, the transistor region includes a first gate controlled by a first gate signal; The semiconductor device, wherein the diode region includes a diode gate controlled by a diode gate signal.

[0144] (Appendix 2) a first switching device and a second switching device connected in series between a first potential and a second potential lower than the first potential; The first and second switching devices together a transistor region and a diode region electrically connected in antiparallel to the transistor region, The transistor region includes a first gate controlled by a first gate signal and a second gate controlled by a second gate signal.

[0145] (Appendix 3) a first switching device and a second switching device connected in series between a first potential and a second potential lower than the first potential; The first and second switching devices together a transistor region and a diode region electrically connected in antiparallel to the transistor region, the transistor region includes a first gate controlled by a first gate signal and a second gate controlled by a second gate signal; The semiconductor device, wherein the diode region includes a diode gate controlled by a diode gate signal.

[0146] (Appendix 4) 4. The semiconductor device according to claim 1, wherein the transistor region and the diode region are formed on the same semiconductor substrate.

[0147] (Appendix 5) 4. The semiconductor device according to claim 1, wherein the transistor region and the diode region are formed on separate semiconductor substrates.

[0148] (Appendix 6) A method for controlling a semiconductor device according to claim 1, comprising: applying a positive voltage to turn on the diode gate as the diode gate signal to the diode gate of the diode region of the second switching device at a second timing earlier than a first timing at which a positive voltage to turn on the transistor region is applied as the first gate signal to the first gate of the first switching device; A method for controlling a semiconductor device, which sets the diode gate signal to a negative voltage or zero voltage at a timing that is the same as or earlier than the first timing so that the diode gate of the diode region of the second switching device is turned off.

[0149] (Appendix 7) A method for controlling a semiconductor device according to claim 2, comprising: The transistor region is provided between an electrically isolated first main electrode and a second main electrode, the first gate signal is a signal based on the first potential of the first main electrode; the second gate signal is a signal based on the second potential of the second main electrode, applying a positive voltage to turn on the second gate as the second gate signal to the second gate at a second timing that is earlier than a first timing at which a negative voltage or zero voltage to turn off the transistor region is applied to the first gate as the first gate signal; A method for controlling a semiconductor device, comprising: setting the second gate signal to a negative voltage or zero voltage so that the second gate is turned off during a third timing from the first timing when a positive voltage is applied to the first gate of the first switching device as the first gate signal to turn on the transistor region.

[0150] (Appendix 8) 4. A method for controlling a semiconductor device according to claim 3, comprising: The transistor region is provided between an electrically isolated first main electrode and a second main electrode, the first gate signal is a signal based on the first potential of the first main electrode; the second gate signal is a signal based on the second potential of the second main electrode, of the first switching device A positive voltage that turns on the second gate is applied as the second gate signal to the second gate at a second timing that is earlier than a first timing at which a negative voltage or zero voltage that turns off the transistor region is applied as the first gate signal to the first gate. setting the second gate signal to a negative voltage or zero voltage so that the second gate is turned off during a third timing at which a positive voltage is applied as the first gate signal to the first gate of the first switching device so that the transistor region is turned on from the first timing; applying a positive voltage to the diode gate of the diode region of the second switching device as the diode gate signal at a fourth timing that is earlier than the third timing at which the transistor region is turned on, so that the diode gate is turned on; A method for controlling a semiconductor device, wherein the diode gate signal is set to a negative voltage or zero voltage at a timing that is the same as or earlier than the third timing so that the diode gate of the diode region of the second switching device is turned off.

[0151] (Appendix 9) 9. The method for controlling a semiconductor device according to claim 6, wherein the second timing is a timing that is up to 20 μsec earlier than the first timing.

[0152] (Appendix 10) 9. The method for controlling a semiconductor device according to claim 8, wherein the fourth timing is a timing that is up to 20 μsec earlier than the third timing. [Explanation of symbols]

[0153] 100,100A,100B,200,200A,200B RC-IGBT, D1 diode region, T1 transistor region, VCC first potential, GND second potential, G I1 ,G I2 ,G D Gate signal, 11,18 active trench gate, 21 diode trench gate.

Claims

1. a first switching device and a second switching device connected in series between a first potential and a second potential lower than the first potential; The first and second switching devices together a transistor region and a diode region electrically connected in antiparallel to the transistor region, the transistor region includes a first gate controlled by a first gate signal and a second gate controlled by a second gate signal; a diode gate control signal for controlling a semiconductor device, the diode region including a diode gate controlled by the diode gate signal; The transistor region is provided between a first main electrode and a second main electrode that are electrically isolated from each other; the first gate signal is a signal based on the first potential of the first main electrode, the second gate signal is a signal based on the second potential of the second main electrode, of the first switching device applying a positive voltage to the second gate as the second gate signal at a second timing that is earlier than a first timing at which a negative voltage or zero voltage to turn off the transistor region is applied to the first gate as the first gate signal; setting the second gate signal to a negative voltage or zero voltage so that the second gate is turned off during a third timing from the first timing when a positive voltage is applied as the first gate signal to the first gate of the first switching device so that the transistor region is turned on; applying a positive voltage to the diode gate of the diode region of the second switching device as the diode gate signal at a fourth timing that is earlier than the third timing at which the transistor region is turned on, so that the diode gate is turned on; a control method for a semiconductor device, the method including setting the diode gate signal to a negative voltage or zero voltage at a timing that is the same as or earlier than the third timing so that the diode gate of the diode region of the second switching device is turned off.

2. 2. The method for controlling a semiconductor device according to claim 1, wherein said second timing is a timing that is a maximum of 20 .mu.sec earlier than said first timing.

3. 2. The method for controlling a semiconductor device according to claim 1, wherein said fourth timing is a timing that is a maximum of 20 [mu]sec earlier than said third timing.

Images