Semiconductor Devices

Abstract

To provide a technology for stabilizing an operation of a semiconductor device.SOLUTION: A semiconductor device of the disclosure includes an area provided with a plurality of circuit blocks each having an avalanche photo diode. Some parts of the plurality of circuit blocks are pixel circuits further including a first control circuits which control the avalanche photo diodes to bring them in stand-by states capable of performing avalanche multiplication, or recharge states for returning the avalanche photo diodes to states capable of performing avalanche multiplication again after performing the avalanche multiplication according to a first control signal. Other parts of the plurality of circuit blocks are signal generation circuits which generate signals according to the waveform of the first control signal. The signal generation circuits are configured not to output a signal according to the output of the avalanche photo diode.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices that output a digital signal corresponding to the count value of photons incident on a photoelectric conversion element such as an avalanche photodiode are known. Patent Document 1 discloses a semiconductor device having a pixel region in which a plurality of pixels are two-dimensionally arranged, each outputting a digital signal corresponding to the frequency of receiving photons. Each of the plurality of pixels disclosed in Patent Document 1 includes an avalanche photodiode and a control circuit that controls the avalanche photodiode between a standby state in which avalanche multiplication is possible and a recharge state in which avalanche multiplication is again possible. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-123847 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the semiconductor device described in Patent Document 1, as the number of pixels increases and the load of the control signals increases, variations in the elements of each pixel and differences in their placement can cause changes in the frequency and phase of the control signals, potentially making it impossible to obtain the desired pixel output. Furthermore, when there are multiple control signals, it is preferable to use a test circuit to determine which control signal is affecting pixel operation and correct or change the control signal as necessary. However, arranging the test circuit within the pixel circuit area requires increasing the pixel size, which raises concerns that it may be impossible to increase the number of pixels arranged. An object of the present invention is to provide a technique for stabilizing the operation of a semiconductor device. [Means for solving the problem]

[0005] According to one disclosure of the present specification, there is provided an area in which a plurality of circuit blocks each having an avalanche photodiode are provided, and some of the plurality of circuit blocks include: a transistor for controlling the supply of a voltage that enables avalanche multiplication in the avalanche photodiode; In response to a first control signal, the avalanche photodiode The transistor is turned off and the voltage is not supplied. The state and The transistor is turned on and the voltage is supplied and a first control circuit for controlling the state of the avalanche photodiode, and another part of the plurality of circuit blocks is a signal generation circuit for generating a signal corresponding to a waveform of the first control signal, and the signal generation circuit is configured not to output a signal corresponding to the output of the avalanche photodiode.

[0006] According to another disclosure of this specification, there is provided an area in which a plurality of circuit blocks each having an avalanche photodiode are provided, and some of the plurality of circuit blocks include: a transistor for controlling the supply of a voltage that enables avalanche multiplication in the avalanche photodiode; In response to a first control signal, the avalanche photodiode The transistor is turned off and the voltage is not supplied. The state and The transistor is turned on and the voltage is supplied and a second control circuit that counts the number of periods in which the avalanche multiplication occurs in the avalanche photodiode among periods defined by the intervals between pulses superimposed on the first control signal, and another part of the plurality of circuit blocks is a signal generation circuit that further includes a selection circuit that selects and outputs one of the first control signal and a signal different from the first control signal in response to a third control signal. [Effects of the Invention]

[0007] According to the present invention, it is possible to stabilize the operation of a semiconductor device without increasing the pixel size. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram (part 1) showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram (part 2) showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention. [Figure 3] 1 is a diagram showing an example of the configuration of a pixel and a signal generating circuit in a semiconductor device according to a first embodiment of the present invention. [Figure 4] 1 is a perspective view showing a configuration example of a semiconductor device according to a first embodiment of the present invention. [Figure 5] FIG. 3 is a timing chart showing the operation of the semiconductor device according to the first embodiment of the present invention. [Figure 6] FIG. 10 is a diagram showing an example of the configuration of a pixel circuit and a signal generating circuit in a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a timing chart showing the operation of the semiconductor device according to the second embodiment of the present invention. [Figure 8] FIG. 10 is a diagram showing an example of the configuration of a pixel circuit and a signal generating circuit in a semiconductor device according to a third embodiment of the present invention. [Figure 9] FIG. 10 is a timing chart showing the operation of the semiconductor device according to the third embodiment of the present invention. [Figure 10] FIG. 10 is a diagram showing an example of the configuration of a pixel circuit and a signal generating circuit in a semiconductor device according to a fourth embodiment of the present invention. [Figure 11] FIG. 10 is a block diagram showing a schematic configuration of a light detection system according to a fifth embodiment of the present invention. [Figure 12] FIG. 10 is a block diagram showing a schematic configuration of a range image sensor according to a sixth embodiment of the present invention. [Figure 13] FIG. 13 is a schematic diagram showing an example of the configuration of an endoscopic surgery system according to a seventh embodiment of the present invention. [Figure 14] FIG. 13 is a schematic diagram showing an example of the configuration of a moving body according to an eighth embodiment of the present invention. [Figure 15] FIG. 13 is a block diagram showing a schematic configuration of a light detection system according to an eighth embodiment of the present invention. [Figure 16] FIG. 13 is a flowchart showing the operation of the light detection system according to the eighth embodiment of the present invention. [Figure 17]FIG. 13 is a schematic diagram showing a schematic configuration of a light detection system according to a ninth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same or corresponding elements in multiple drawings are designated by common reference numerals, and their description may be omitted or simplified.

[0010] In the first to fourth embodiments described below, an imaging device will be mainly described as an example of a semiconductor device. However, the semiconductor device to which the configuration of each embodiment can be applied is not limited to an imaging device, and can also be applied to other examples of semiconductor devices. Examples of semiconductor devices to which the present invention can be applied include memory devices typified by DRAM (Dynamic Random Access Memory) and NVM (Non-Volatile Memory), photoelectric conversion devices, etc. Examples of photoelectric conversion devices include the imaging device, distance measurement devices (devices for distance measurement using focus detection or TOF (Time Of Flight)), and photometric devices (devices for measuring the amount of incident light), which will be described below.

[0011] [First embodiment] A semiconductor device according to a first embodiment of the present invention will be described with reference to Figs. 1 to 5. Figs. 1 and 2 are block diagrams showing a schematic configuration of the semiconductor device according to this embodiment. Fig. 3 is a diagram showing an example configuration of a pixel circuit and a signal generating circuit in the semiconductor device according to this embodiment. Fig. 4 is a perspective view showing an example configuration of the semiconductor device according to this embodiment. Fig. 5 is a timing chart explaining the operation of the semiconductor device according to this embodiment.

[0012] First, the structure of the semiconductor device according to the present embodiment will be described with reference to Figures 1 to 4. As shown in Figure 1, the semiconductor device 100 according to the present embodiment includes a pixel region 10, a vertical selection circuit 30, a signal processing circuit 40, a horizontal selection circuit 50, an output section 60, and a control section 70.

[0013] The pixel region 10 includes a plurality of circuit blocks arranged two-dimensionally across a plurality of rows and a plurality of columns. FIG. 1 illustrates an example in which the pixel region 10 includes (m+1)×(n+1) circuit blocks arranged in (m+1) rows from the 0th row to the mth row and (n+1) columns from the 0th column to the nth column. Some of the plurality of circuit blocks are pixel circuits P, and other of the plurality of circuit blocks are signal generation circuits T. In FIG. 1, the pixel circuits P and the signal generation circuits T are indicated with reference numerals indicating the row and column numbers. For example, the pixel circuit P arranged in the 1st row and the 1st column is designated by the reference numeral "P11." Furthermore, the signal generation circuit T arranged in the 0th row and the 1st column is designated by the reference numeral "T01."

[0014] The pixel region 10 includes a first pixel region 10a in which pixel circuits P are arranged and a second pixel region 10b in which signal generation circuits T are arranged. The pixel circuits P may be arranged two-dimensionally across multiple rows and multiple columns. The signal generation circuit T may be arranged in at least one row and / or one column of the multiple rows and multiple columns constituting the pixel region 10. In the configuration example of FIG. 1, the first pixel region 10a is configured with (m×n) pixel circuits P arranged in m rows from the first row to the mth row and n columns from the first column to the nth column. In addition, in the configuration example of FIG. 1, the second pixel region 10b is configured with (m+n+1) signal generation circuits T arranged in the 0th row and the 0th column to the nth column and the 1st row to the mth row of the 0th column. Note that the number of rows and columns of the pixel circuits P constituting the first pixel region 10a and the number of rows and columns of the signal generation circuits T constituting the second pixel region 10b are not particularly limited.

[0015] As described above, in the semiconductor device 100 of this embodiment, each of the multiple rows and multiple columns constituting the pixel region 10 includes at least one signal generation circuit T. At least one row and one column of the multiple rows and multiple columns constituting the pixel region 10 may be composed only of the signal generation circuit T. The second pixel region 10b is preferably arranged along two sides of the periphery of the first pixel region 10a, as shown in FIG. 1, for example.

[0016] In a typical photoelectric conversion device, optical black pixels (OB pixels) that generate a reference signal and dummy pixels for maintaining structural periodicity may be arranged around pixels (effective pixels) that output signals used as image signals. In such cases, the signal generation circuit T may utilize some of the OB pixels or dummy pixels. Like the OB pixels, the signal generation circuit T may be configured to be optically shielded by a light-shielding layer or the like.

[0017] In each row of the pixel region 10, a control line 14 is arranged extending in a first direction (the horizontal direction in FIG. 1). The control line 14 is connected to each of the pixel circuits P and / or the signal generation circuits T arranged in the first direction and serves as a common signal line for these. The first direction in which the control lines 14 extend may be referred to as the row direction or the horizontal direction. Note that FIG. 1 shows a control signal pVSEL, which is one of the control signals supplied via the control line 14 of each row, along with a symbol indicating the row number. For example, the control signal pVSEL supplied to the control line 14 of the first row is labeled "pVSEL[1]." Each of the control lines 14 may include multiple signal lines for supplying multiple types of control signals to the pixel circuits P and the signal generation circuits T.

[0018] In each column of the pixel region 10, an output line 16 is arranged, extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. The output line 16 is connected to each of the pixel circuits P and signal generation circuits T arranged in the second direction and serves as a common signal line for these. The second direction in which the output lines 16 extend may be referred to as the column direction or vertical direction. Note that FIG. 1 shows the signal POUT output to the output line 16 of each column together with a symbol indicating the column number. For example, the signal POUT output to the output line 16 of the first column is labeled "POUT[1]." If the signal POUT output from the pixel circuit P and the signal generation circuit T is a k-bit signal, each of the output lines 16 has k signal lines for outputting a k-bit digital signal.

[0019] The control lines 14 of each row are connected to a vertical selection circuit 30. The vertical selection circuit 30 is a circuit section that receives control signals output from the control section 70, generates control signals pVSEL for driving the pixel circuits P and the signal generation circuits T, and supplies the control signals to the pixel circuits P and the signal generation circuits T via the control lines 14. The vertical selection circuit 30 may include logic circuits such as a shift register or an address decoder. The vertical selection circuit 30 sequentially scans the pixel circuits P and the signal generation circuits T in the pixel region 10 row by row, and outputs signals from the pixel circuits P and the signal generation circuits T to the output lines 16 of each column.

[0020] The signal processing circuit 40 has a plurality of processing circuits 42 corresponding to each column. The output line 16 of each column is connected to the processing circuit 42 of the corresponding column. The processing circuit 42 of each column has a function of holding a signal POUT output from the pixel circuit P and / or signal generation circuit T of the corresponding column via the output line 16. For example, if the signal POUT output from the pixel circuit P and the signal generation circuit T is a k-bit digital signal, each of the processing circuits 42 has at least k holding units.

[0021] The horizontal selection circuit 50 receives a control signal output from the control unit 70, generates a control signal pHSEL for reading out a signal from the signal processing circuit 40, and supplies the control signal to the signal processing circuit 40. The horizontal selection circuit 50 may include logic circuits such as a shift register and an address decoder. The horizontal selection circuit 50 sequentially scans the processing circuits 42 of each column by supplying the control signal pHSEL to the processing circuits 42 of each column via the control lines 18, and sequentially outputs the signals held in each holding unit to the horizontal output line HSIG. Note that FIG. 1 shows the control signal pHSEL supplied from the control line 18 along with a symbol indicating the column number. For example, the control signal pHSEL supplied from the control line 18 for the nth column is labeled "pHSEL[n]." The horizontal output line HSIG has at least k signal lines to output a k-bit digital signal.

[0022] The output unit 60 has an external interface circuit and is a circuit unit for outputting a signal supplied via the horizontal output line HSIG as an output signal SOUT to the outside of the semiconductor device 100. The external interface circuit included in the output unit 60 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit such as an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit can be used as the external interface circuit.

[0023] The control unit 70 is a circuit unit for supplying control signals that control the operations and timings of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output unit 60. Note that at least some of the control signals that control the operations and timings of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output unit 60 may be supplied from outside the semiconductor device 100.

[0024] The connection of each functional block of the semiconductor device 100 is not limited to the example configuration shown in FIG. 1, and may be configured as shown in FIG. 2, for example.

[0025] In the configuration example of FIG. 2, an output line 16 extending in a first direction is arranged in each row of the pixel region 10. The output line 16 is connected to each of the pixel circuits P and / or signal generation circuits T arranged in the first direction, and forms a signal line common to these pixel circuits P and / or signal generation circuits T. Furthermore, a control line 18 extending in a second direction is arranged in each column of the pixel region 10. The control line 18 is connected to each of the pixel circuits P and / or signal generation circuits T arranged in the second direction, and forms a signal line common to these pixel circuits P and / or signal generation circuits T.

[0026] The control line 18 of each column is connected to a horizontal selection circuit 50. The horizontal selection circuit 50 receives a control signal output from the control unit 70, generates a control signal pHSEL for reading out pixel signals from the pixel circuits P and the signal generation circuits T, and supplies the control signal to the pixel circuits P and / or the signal generation circuits T via the control line 18. Specifically, the horizontal selection circuit 50 sequentially scans the pixel circuits P and the signal generation circuits T in the pixel area 10 column by column, and outputs signals from the pixel circuits P and / or the signal generation circuits T of each row belonging to the selected column to an output line 16.

[0027] The output line 16 of each row is connected to a signal processing circuit 40. The signal processing circuit 40 includes a plurality of processing circuits 42 provided corresponding to each row of the pixel region 10. Each of the processing circuits 42 has a function of holding in a holding unit a signal from the pixel circuit P or signal generation circuit T of each row that is output column by column from the pixel region 10 via the output line 16 of the corresponding row.

[0028] The signal processing circuit 40 receives a control signal output from the control unit 70, and outputs the signals held in the holding units of the processing circuits 42 of each row to the output unit 60 in sequence. Other configurations in the configuration example of FIG. 2 may be similar to the configuration example of FIG.

[0029] FIG. 3A is a diagram illustrating an example of the configuration of a pixel circuit P in the semiconductor device of this embodiment. The pixel circuit P is a circuit block that outputs a signal corresponding to incident light. As shown in FIG. 3A, each pixel circuit P includes a photodiode PD, a logic circuit NOT2, a first control circuit 20, and a second control circuit 22. The first control circuit 20 includes a PMOS transistor MP. The second control circuit 22 includes a logic circuit NOT1, a counter 24, and an output circuit 26. The logic circuits NOT1 and NOT2 may be configured using NOT circuits (inverter circuits). Note that the logic circuit NOT2 does not necessarily have to be included in each pixel circuit P and may be part of, for example, the vertical selection circuit 30 or the control unit 70. In this case, the output signal of the logic circuit NOT2 is supplied to the first control circuit 20 via a control line 14.

[0030] The cathode of the photodiode PD is connected to one of the source and drain of the PMOS transistor MP and the input node of the logic circuit NOT1. The gate of the PMOS transistor MP is connected to the output node of the logic circuit NOT2. The output node of the logic circuit NOT1 is connected to the input node of the counter 24. The output node of the counter 24 is connected to the input node of the output circuit 26. The output node of the output circuit 26 is connected to the output line 16. A voltage VPDL is applied to the anode of the photodiode PD. A first control signal pCLK generated by a pulse generating circuit (not shown) provided outside the pixel circuit P is input to the input node of the logic circuit NOT2 via the control line 14. That is, an inverted signal of the first control signal pCLK is input to the gate of the PMOS transistor MP. A voltage SVDD is applied to the other of the source and drain of the PMOS transistor MP. In this embodiment, the voltage SVDD is approximately 3.3 V, and the voltage VPDL is approximately −20 V. The first control signal pCLK is a signal (clock signal) including pulses with a predetermined period.

[0031] The first control circuit 20 has a function of controlling the operation of the photodiode PD. More specifically, the first control circuit 20 has a function of controlling the photodiode PD between a standby state in which avalanche multiplication is possible and a recharge state in which avalanche multiplication is possible again after avalanche multiplication has occurred, in response to the first control signal pCLK. When the PMOS transistor MP is turned on in response to the level of the first control signal pCLK, a reverse bias voltage equal to the potential difference between the voltages SVDD and VPDL is applied to the photodiode PD. By setting this reverse bias voltage to a voltage greater than the breakdown voltage of the photodiode PD, the photodiode PD operates as a Geiger-mode avalanche photodiode.

[0032] The logic circuit NOT1 has the function of converting the output signal of the photodiode PD into a pulse signal suitable for the digital circuit in the subsequent stage. The logic circuit NOT1 is composed of an inverter circuit, and outputs a signal PDOut, which is an inverted version of the signal VC of the cathode section, which corresponds to the output of the photodiode PD, to the counter 24.

[0033] The counter 24 has a function of counting the number of times the output (signal PDOut) of the logic circuit NAND1 transitions from a low level to a high level, thereby generating a k-bit count signal having a count value corresponding to the incidence of photons on the photodiode PD.

[0034] The output circuit 26 has a function of receiving the k-bit count signal output from the counter 24 and outputting the count signal (signal POUT) to the output line 16. The output circuit 26 may rearrange the signals as appropriate. The signal output by the output circuit 26 may also be a differential signal.

[0035] FIG. 3B is a diagram illustrating an example of the configuration of a signal generation circuit T in the semiconductor device of this embodiment. The signal generation circuit T is a circuit block that outputs a signal corresponding to the waveform of a control signal. The signal generation circuit T is configured with the same circuit elements as those constituting the pixel circuit P. That is, as shown in FIG. 3B, each signal generation circuit T includes a photodiode PD, a logic circuit NOT2, a first control circuit 20, and a second control circuit 22. The first control circuit 20 includes a PMOS transistor MP. The second control circuit 22 includes a logic circuit NOT1, a counter 24, and an output circuit 26. The logic circuits NOT1 and NOT2 may be configured with NOT circuits (inverter circuits). Note that the logic circuit NOT2 does not necessarily have to be included in each signal generation circuit T and may be part of, for example, the vertical selection circuit 30 or the control unit 70. In this case, the output signal of the logic circuit NOT2 is supplied to the first control circuit 20 via a control line 14 or the like. The signal generation circuit T differs from the pixel circuit P in that the input node of the counter 24 is disconnected from the output node of the logic circuit NOT1, and instead a first control signal pCLK is input to the input node of the counter 24. That is, the photodiode PD of the signal generation circuit T is electrically disconnected from the second control circuit 22, and a signal corresponding to the output of the photodiode PD is not output. Note that here, the wiring between the logic circuit NOT1 and the counter 24 is disconnected to prevent an electrical connection, but the wiring between the counter 24 and the output circuit 26 may also be disconnected to prevent an electrical connection. Also, the wiring between the output circuit 26 and the output line 16 may also be disconnected to prevent an electrical connection. Furthermore, the wiring between the logic circuit NOT1 and the cathode of the photodiode PD may also be disconnected to prevent an electrical connection. In addition, instead of disconnecting the wiring, a switch may also be provided to prevent an electrical connection.

[0036] By configuring the signal generating circuit T in this way, the signal generating circuit T can count the number of times the first control signal pCLK transitions from a low level to a high level using the counter 24 and output the number to the output line 16.

[0037] The semiconductor device 100 according to this embodiment may be formed on a single substrate, or may be configured as a stacked semiconductor device in which multiple substrates are stacked. In the latter case, for example, as shown in FIG. 4, a stacked semiconductor device can be configured in which a sensor substrate 110 and a circuit substrate 120 are stacked and electrically connected. At least a photodiode PD, which is one of the components of the pixel circuit P and the signal generation circuit T, can be arranged on the sensor substrate 110. Furthermore, a first control circuit 20 and a second control circuit 22, which are one of the components of the pixel circuit P and the signal generation circuit T, can be arranged on the circuit substrate 120. The photodiode PD can be electrically connected to the first control circuit 20 and the second control circuit 22 via connection wiring provided for each pixel circuit P and each signal generation circuit T. Furthermore, a vertical selection circuit 30, a signal processing circuit 40, a horizontal selection circuit 50, an output unit 60, a control unit 70, etc. can be further arranged on the circuit substrate 120.

[0038] The photodiodes PD of the pixel circuits P and the signal generation circuits T, the first control circuit 20, and the second control circuit 22 are provided on the sensor substrate 110 and the circuit substrate 120 so as to overlap in a plan view. The vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, the output section 60, and the control section 70 can be arranged around the pixel region 10.

[0039] In this specification, the term "planar view" refers to a view from a direction perpendicular to the light incident surface of the sensor substrate 110. Furthermore, the term "cross section" refers to a cross section of the sensor substrate 110 in a direction perpendicular to the light incident surface.

[0040] It is possible to increase the integration density of elements and achieve higher performance by configuring the stacked semiconductor device 100. In particular, by arranging the photodiodes PD and the first and second control circuits 20 and 22 on separate substrates, it is possible to arrange the photodiodes PD at high density without sacrificing the light receiving area of ​​the photodiodes PD, thereby improving the photon detection efficiency.

[0041] The number of substrates constituting the semiconductor device 100 is not limited to two, and the semiconductor device 100 may be constructed by stacking three or more substrates.

[0042] 4, the sensor substrate 110 and the circuit substrate 120 are assumed to be diced chips, but the sensor substrate 110 and the circuit substrate 120 are not limited to chips. For example, the sensor substrate 110 and the circuit substrate 120 may each be a wafer. The sensor substrate 110 and the circuit substrate 120 may be stacked in the wafer state and then diced, or may be formed into chips and then stacked and bonded.

[0043] Next, the operation of the semiconductor device 100 according to this embodiment will be described with reference to FIG. 5. FIG. 5 is a timing diagram showing the operation of the pixel circuit P and the signal generation circuit T shown in FIGS. 3(a) and 3(b). In FIG. 5, "Pmn Count" indicates the count value of the counter 24 of the pixel circuit Pmn, and "Tm0 Count" indicates the count value of the counter 24 of the signal generation circuit Tm0. The other signals shown in FIG. 5 correspond to the signals shown in each part in FIG. 3. Furthermore, FIG. 5 indicates the timing at which photons are incident on the photodiode PD with an arrow above the signal waveform.

[0044] First, the operation of the pixel circuit P will be described below using the pixel circuit Pmn in the mth row and nth column as an example.

[0045] It is assumed that immediately before time t1, the signal VC is at a high level, and the signal PDOut and the first control signal pCLK are at a low level. Also, it is assumed that immediately before time t1, the count value of the counter 24 is N. The signal levels of the signals VC and PDOut during the period before time t1, when the first control signal pCLK becomes high, vary depending on the light incidence situation up to that point. FIG. 5 shows an output assuming that no light is incident before time t1. When the signal VC is at a high level corresponding to the voltage SVDD, this indicates that recharging of the photodiode PD is complete. The period during which the signal VC is at a high level and the PMOS transistor MP is off (the first control signal pCLK is at a low level) is the period during which the photodiode PD is controlled to a standby state in which avalanche multiplication is possible.

[0046] At time t1, the first control signal pCLK transitions from low to high, turning on the PMOS transistor MP and performing a recharge operation to return the cathode (signal VC) of the photodiode PD to the voltage SVDD.

[0047] At the next time t2, a photon is incident on the photodiode PD. This causes avalanche multiplication in the photodiode PD, causing the signal VC to transition from a high level to a low level corresponding to the voltage VPDL. Then, the signal PDOut, which is the output of the logic circuit NOT1, transitions from a low level to a high level. As a result, the count value of the counter 24 increases by 1 LSB from N to N+1.

[0048] After time t1, photons are assumed to be incident on the photodiode PD at times t3 and t4, which are before time t5 when the first control signal pCLK next transitions from low to high. At times t3 and t4, avalanche multiplication has already occurred in the photodiode PD, and the photodiode PD is in a state before recharging. Therefore, the photons incident at times t3 and t4 do not cause a transition in the signal level of each node, and the photons incident at times t3 and t4 are not counted by the counter 24. Such uncounted photons are indicated by dashed arrows above the waveform of the signal VC.

[0049] At the next time t5, the first control signal pCLK transitions from low to high. This turns on the PMOS transistor MP, causing a recharge operation to return the cathode of the photodiode PD (signal VC) to voltage SVDD, and the signal VC transitions from low to high. Then, the signal PDOut, which is the output of the logic circuit NOT1, transitions from high to low.

[0050] At the next time t6, the first control signal pCLK transitions from low to high. If no photons are incident on the photodiode PD during the period from time t5 to time t6, the signal levels of the signals VC and PDOut do not change during this period.

[0051] Similarly, after time t7, if a photon is incident during the period from when the first control signal pCLK transitions from low to high until the next transition of the first control signal pCLK from low to high, the count value of the counter 24 increases by 1 LSB. For example, during the period from time t6 to time t8, the count value of the counter 24 increases by 1 LSB from N+1 to N+2 in response to the incident photon at time t7. Furthermore, during the period from time t8 to time t10, the count value of the counter 24 increases by 1 LSB from N+2 to N+3 in response to the incident photon at time t9. On the other hand, if a photon is not incident during the period from when the first control signal pCLK transitions from low to high until the next transition of the first control signal pCLK from low to high, the signal levels of the signals VC and PDOut do not change. That is, photon counting is not performed.

[0052] That is, the second control circuit 22 of the pixel circuit P operates to count the number of periods in which avalanche multiplication occurs in the photodiode PD within a period defined by the interval between pulses superimposed on the first control signal pCLK.

[0053] Next, the operation of the signal generating circuit T will be described below, taking as an example the signal generating circuit Tm0 in the mth row and 0th column, which is arranged in the same row as the pixel circuit Pmn.

[0054] The circuitry of the signal generation circuit T is basically the same as the circuitry of the pixel circuit P, except that the connection between the logic circuit NOT1 and the counter 24 is cut off. In other words, the transitions of the signals VC and PDOut in the signal generation circuit T are the same as the transitions of the signals VC and PDOut in the pixel circuit P.

[0055] 3(b), the first control signal pCLK is directly input to the counter 24 of the signal generation circuit T. That is, the counter 24 of the signal generation circuit T increments its count value by 1 LSB each time the first control signal pCLK transitions from a low level to a high level. Specifically, the count value of the counter 24 of the signal generation circuit T increments by 1 LSB at each of times t1, t5, t6, t8, and t10 when the first control signal pCLK transitions from a low level to a high level.

[0056] That is, the second control circuit 22 of the signal generation circuit T, unlike the second control circuit 22 of the pixel circuit P, operates to count the number of periods defined by the intervals between pulses superimposed on the first control signal pCLK.

[0057] To increase the operating speed of the semiconductor device 100, it may be necessary to increase the frequency of the first control signal pCLK or shorten its high-level period. In such cases, depending on the load of the driven element, the desired output result corresponding to the first control signal pCLK may not be obtained. In this regard, in the semiconductor device 100 according to this embodiment, the signal generation circuit T counts and outputs the number of pulses of the first control signal pCLK input during a predetermined period. Therefore, by deliberately changing the waveform of the first control signal pCLK, it is possible to accurately confirm the range in which the desired output result is obtained and adjust the waveform of the first control signal pCLK as needed. Furthermore, because the signal generation circuits T in the same row as the pixel circuits P operate at the same operating timing, it is possible to accurately confirm the state of the first control signal pCLK input to the pixel circuits P. Furthermore, by checking the output of the row in which only the signal generation circuits T are arranged (signal generation circuits T00 to T0n in FIGS. 1 and 2), it is possible to accurately confirm the state of signal changes depending on the column position.

[0058] As described above, according to the semiconductor device of this embodiment, it is possible to accurately check the state of the first control signal pCLK and stabilize the operation of the semiconductor device.

[0059] [Second embodiment] A semiconductor device according to a second embodiment of the present invention will be described with reference to Figures 6 and 7. Figure 6 is a diagram showing an example of the configuration of a pixel circuit and a signal generating circuit in the semiconductor device according to this embodiment. Figure 7 is a timing chart explaining the operation of the semiconductor device according to this embodiment. Components similar to those in the semiconductor device according to the first embodiment are given the same reference numerals, and their description will be omitted or simplified.

[0060] The semiconductor device according to this embodiment differs from the semiconductor device according to the first embodiment in the circuit configurations of the pixel circuit P and the signal generation circuit T that constitute the pixel region 10. The pixel circuit P and the signal generation circuit T in the semiconductor device of this embodiment will be described below, focusing on the differences from the first embodiment.

[0061] FIG. 6A is a diagram illustrating an example of the configuration of a pixel circuit P in the semiconductor device of this embodiment. As shown in FIG. 6A, the pixel circuit P includes a photodiode PD, logic circuits NOT2 and OR1, a first control circuit 20, and a second control circuit 22. The first control circuit 20 includes a PMOS transistor MP. The second control circuit 22 includes a logic circuit NOR1, a counter 24, and an output circuit 26. The logic circuit NOT2 can be configured using a NOT circuit (inverter circuit), the logic circuit OR1 can be configured using a two-input OR circuit, and the logic circuit NOR1 can be configured using a two-input NOR circuit. Note that the logic circuits NOT2 and OR1 do not necessarily need to be included in each pixel circuit P and may be part of, for example, the vertical selection circuit 30 or the control unit 70. In this case, the output signal of the logic circuit NOT2 is supplied to the first control circuit 20 via a control line 14, and the output signal of the logic circuit OR1 is supplied to the second control circuit 22 via the control line 14.

[0062] The cathode of the photodiode PD is connected to one of the source and drain of the PMOS transistor MP and a first input node of the logic circuit NOR1. The gate of the PMOS transistor MP is connected to the output node of the logic circuit NOT2. The second input node of the logic circuit NOR1 is connected to the output node of the logic circuit OR1. The output node of the logic circuit NOR1 is connected to the input node of the counter 24. A first control signal pCLK is input to the first input node of the logic circuit OR1 via a control line 14. A second control signal pCNTEN_B generated by a pulse generating circuit (not shown) provided outside the pixel circuit P is input to the second input node of the logic circuit OR1 via the control line 14. The output signal of the logic circuit OR1 is the signal CNTEN_B input to the second input node of the logic circuit NOR1. In this embodiment, the output signal of the logic circuit NOR1 is the signal PDOut. Other points are the same as those of the pixel circuit P of the first embodiment.

[0063] As described above, in this embodiment, the second control signal pCNTEN_B is added, and the signal CNTEN_B, which is the result of the OR logic of the first control signal pCLK and the second control signal pCNTEN_B, is input to the second control circuit 22. The second control signal pCNTEN_B is a signal for defining the exposure period of the photodiode PD. In addition, the logic circuit of the second control circuit 22 is changed from an inverter circuit (logic circuit NOT1) to a NOR circuit (logic circuit NOR1), and the output signal of the logic circuit NOR1, which receives the signal VC and the signal CNTEN_B as inputs, is set as the signal PDOut.

[0064] By configuring the pixel circuit P in this manner, it is possible to control the operation of the counter 24 asynchronously with the first control signal pCLK. For example, in an environment where a large number of incident photons are present, i.e., a high-brightness environment, it is possible to appropriately recharge the photodiode PD with the first control signal pCLK, while controlling the exposure period of the photodiode PD with the second control signal pCNTEN_B.

[0065] FIG. 6B is a diagram illustrating an example of the configuration of the signal generation circuit T in the semiconductor device of this embodiment. Similar to the pixel circuit P, the signal generation circuit T includes a photodiode PD, logic circuits NOT2 and OR1, a first control circuit 20, and a second control circuit 22, as shown in FIG. 6B. The first control circuit 20 includes a PMOS transistor MP. The second control circuit 22 includes a logic circuit NOR1, a counter 24, and an output circuit 26. The logic circuit NOT2 can be configured with a NOT circuit (inverter circuit), the logic circuit OR1 can be configured with a two-input OR circuit, and the logic circuit NOR1 can be configured with a two-input NOR circuit. The logic circuits NOT2 and OR1 do not necessarily need to be included in each signal generation circuit T and may be part of, for example, the vertical selection circuit 30 or the control unit 70. In this case, the output signal of the logic circuit NOT2 is supplied to the first control circuit 20 via the control line 14, etc., and the output signal of the logic circuit OR1 is supplied to the second control circuit 22 via the control line 14, etc. The signal generation circuit T differs from the pixel circuit P in that the input node of the counter 24 is separated from the output node of the logic circuit NOR1, and instead a signal CNTEN_B is input to the input node of the counter 24. A reference voltage GND is applied to a second input node of the logic circuit NOR1 instead of the signal CNTEN_B being input.

[0066] By configuring the signal generation circuit T in this manner, the signal generation circuit T can measure the number of times the first control signal pCLK transitions from a low level to a high level while the second control signal pCNTEN_B is at a low level using the counter 24. Then, the signal POUT, which is the measurement result by the counter 24, can be output from the output line 16.

[0067] Next, the operation of the semiconductor device 100 according to this embodiment will be described with reference to FIG. 7. FIG. 7 is a timing diagram showing the operation of the pixel circuit P and the signal generation circuit T shown in FIGS. 6(a) and 6(b). In FIG. 7, "Pmn Count" indicates the count value of the counter 24 of the pixel circuit Pmn, and "Tm0 Count" indicates the count value of the counter 24 of the signal generation circuit Tm0. The other signals shown in FIG. 7 correspond to the signals shown in various parts in FIG. 6. FIG. 7 also shows the timing at which photons are incident on the photodiode PD with arrows above the signal waveforms. Here, it is assumed that photons are incident at the same timing as in the timing diagram of FIG. 5.

[0068] First, the operation of the pixel circuit P will be described below using the pixel circuit Pmn in the mth row and nth column as an example.

[0069] Immediately before time t1, the second control signal pCNTEN_B and the signal VC are at a high level, and the first control signal pCLK and the signal PDOut are at a low level. Also, immediately before time t1, the count value of the counter 24 is N.

[0070] At time t1, the first control signal pCLK transitions from low to high, turning on the PMOS transistor MP and performing a recharge operation to return the cathode (signal VC) of the photodiode PD to the voltage SVDD.

[0071] At time te0 after the first control signal pCLK returns from high to low, the second control signal pCNTEN_B transitions from high to low. This causes the signal CNTEN_B to transition from high to low. At this time, since the logic circuit NOR1 is NOR logic, the signal PDOut becomes an inverted signal of the signal VC. In other words, the counter 24 is now in a state where it can detect changes in the output of the photodiode PD. The subsequent operations from time t2 to time t9 are the same as those in FIG.

[0072] At the next time tel, the second control signal pCNTEN_B transitions from low to high. This transition causes the signal CNTEN_B to transition from low to high. At this time, since the logic circuit NOR1 is NOR logic, the signal PDOut remains low regardless of the state of the signal VC. In other words, the count value of the counter 24 no longer increases.

[0073] For example, even if avalanche multiplication occurs in the photodiode PD due to an incident photon at subsequent time t11 and the signal VC transitions from high to low, the signal PDOut remains low and the count value of the counter 24 does not change. In other words, the second control signal pCNTEN_B can control the operation of the counter 24 asynchronously with the first control signal pCLK. In this way, the count period in the second control circuit of the pixel circuit P is defined by the first control signal pCLK and the second control signal pCNTEN_B.

[0074] Next, the operation of the signal generating circuit T will be described below, taking as an example the signal generating circuit Tm0 in the mth row and 0th column, which is arranged in the same row as the pixel circuit Pmn.

[0075] The circuitry of the signal generation circuit T is basically the same as the circuitry of the pixel circuit P, except that the connection between the logic circuit NOR1 and the counter 24 is cut off. In other words, the transitions of the signals VC and PDOut in the signal generation circuit T are the same as the transitions of the signals VC and PDOut in the pixel circuit P.

[0076] 6(b), the counter 24 of the signal generation circuit T receives a signal CNTEN_B corresponding to the logical sum of the first control signal pCLK and the second control signal pCNTEN_B. That is, the counter 24 of the signal generation circuit T increases its count value by 1 LSB at the timing when at least one of the first control signal pCLK and the second control signal pCNTEN_B becomes high level. Specifically, the count value of the counter 24 of the signal generation circuit T increases by 1 LSB at each of times t5, t6, t8, and te1. The count period in the second control circuit 22 of the signal generation circuit T is determined by the first control signal pCLK and the second control signal pCNTEN_B, similar to the count period in the second control circuit 22 of the pixel circuit P.

[0077] As the number of pixel circuits P constituting the pixel region 10 increases, the phase relationship between the first control signal pCLK and the second control signal pCNTEN_B may be reversed due to the influence of loads and wiring, making it impossible to obtain the desired output result. In this regard, in the semiconductor device 100 of this embodiment, the signal generation circuit T can count and output the number of pulses of the first control signal pCLK input during a period when the second control signal pCNTEN_B is at a low level. Therefore, by deliberately changing the transition timing of the second control signal pCNTEN_B, it is possible to accurately confirm the range in which the desired output result is obtained, and to adjust the waveforms of the first control signal pCLK and the second control signal pCNTEN_B as necessary. Furthermore, because the pixel circuits P and the signal generation circuit T in the same row operate at the same operating timing, it is possible to accurately confirm the phase relationship between the first control signal pCLK and the second control signal pCNTEN_B input to the pixel circuits P and their respective states. Furthermore, by checking the output of the row in which only the signal generation circuit T is arranged (signal generation circuit T00 to signal generation circuit T0n in FIGS. 1 and 2), it is possible to accurately check the change state of the signal that depends on the column position.

[0078] In this way, according to the semiconductor device of this embodiment, it is possible to accurately confirm the phase relationship between the first control signal pCLK and the second control signal pCNTEN_B and the state of the first control signal pCLK, thereby stabilizing the operation of the semiconductor device.

[0079] [Third embodiment] A semiconductor device according to a third embodiment of the present invention will be described with reference to Figs. 8 and 9. Fig. 8 is a diagram showing an example of the configuration of a pixel circuit and a signal generating circuit in the semiconductor device according to this embodiment. Fig. 9 is a timing chart explaining the operation of the semiconductor device according to this embodiment. Components similar to those in the semiconductor devices according to the first and second embodiments are given the same reference numerals, and their description will be omitted or simplified.

[0080] The semiconductor device according to the present embodiment differs from the semiconductor device according to the first and second embodiments in the circuit configurations of the pixel circuit P and the signal generation circuit T that constitute the pixel region 10. The pixel circuit P and the signal generation circuit T in the semiconductor device of the present embodiment will be described below, focusing on the differences from the first and second embodiments.

[0081] FIG. 8A is a diagram illustrating an example of the configuration of a pixel circuit P in the semiconductor device of this embodiment. As shown in FIG. 8A, the pixel circuit P includes a photodiode PD, logic circuits NOR2 and OR1, a first control circuit 20, and a second control circuit 22. The first control circuit 20 includes a PMOS transistor MP. The second control circuit 22 includes a logic circuit NOR1, a counter 24, and an output circuit 26. The logic circuits NOR1 and NOR2 may be configured as two-input NOR circuits, and the logic circuit OR1 may be configured as a two-input OR circuit. Note that the logic circuits NOR2 and OR1 do not necessarily need to be included in each pixel circuit P and may be part of, for example, the vertical selection circuit 30 or the control unit 70. In this case, the output signal of the logic circuit NOR2 is supplied to the first control circuit 20 via a control line 14, and the output signal of the logic circuit OR1 is supplied to the second control circuit 22 via the control line 14.

[0082] The gate of the PMOS transistor MP is connected to the output node of the logic circuit NOR2. A first control signal pCLK is input to a first input node of the logic circuit NOR2. A reset signal pRES generated by a pulse generating circuit (not shown) provided outside the pixel circuit P is supplied to a second input node of the logic circuit NOR2 via a control line 14. The reset signal pRES is a control signal used to reset the count value of the counter 24. Other points are the same as those of the pixel circuit P of the second embodiment.

[0083] In this way, in this embodiment, the reset signal pRES is added, which makes it possible to reset the count value of the counter 24. In addition, the signal input to the gate of the PMOS transistor MP is changed from an inverted signal of the first control signal pCLK to an output signal of NOR logic of the first control signal pCLK and the reset signal pRES.

[0084] By configuring the pixel circuit P in this manner, it is possible to control the reset of the counter 24 and the recharge operation of the photodiode PD asynchronously with the first control signal pCLK and the second control signal pCNTEN_B. This makes it possible, for example, to arbitrarily control the accumulation time and to control the photodiode PD so that avalanche multiplication does not occur. In other words, it is possible to reduce power consumption due to avalanche multiplication and recharge operations. Furthermore, by fixing the signal PDOut output from the logic circuit NOR1 to a low level, it is possible to avoid erroneous detection after the reset of the counter 24 is released, which may occur if the signal PDOut is indefinite.

[0085] FIG. 8B is a diagram illustrating an example of the configuration of the signal generation circuit T in the semiconductor device of this embodiment. As shown in FIG. 8B, the signal generation circuit T includes a photodiode PD, logic circuits NOR2 and OR1, a first control circuit 20, and a second control circuit 22. The first control circuit 20 includes a PMOS transistor MP. The second control circuit 22 includes a logic circuit NOR1, a counter 24, and an output circuit 26. The logic circuits NOR1 and NOR2 may be configured as two-input NOR circuits, and the logic circuit OR1 may be configured as a two-input OR circuit. The logic circuits NOR2 and OR1 do not necessarily need to be included in each pixel circuit P and may be part of, for example, the vertical selection circuit 30 or the control unit 70. In this case, the output signal of the logic circuit NOR2 is supplied to the first control circuit 20 via a control line 14, and the output signal of the logic circuit OR1 is supplied to the second control circuit 22 via the control line 14. The signal generating circuit T differs from the pixel circuit P in that the input node of the counter 24 is separated from the output node of the logic circuit NOR1, and instead the signal CNTEN_B is input to the input node of the counter 24.

[0086] By configuring the signal generation circuit T in this manner, the signal generation circuit T can measure the number of times the first control signal pCLK transitions from a low level to a high level while the reset signal pRES and the second control signal pCNTEN_B are at a low level using the counter 24. Then, the signal POUT, which is the measurement result by the counter 24, can be output to the output line 16.

[0087] Next, the operation of the semiconductor device 100 according to this embodiment will be described with reference to FIG. 9. FIG. 9 is a timing diagram showing the operation of the pixel circuit P and the signal generation circuit T shown in FIGS. 8(a) and 8(b). In FIG. 9, "Pmn Count" indicates the count value of the counter 24 of the pixel circuit Pmn, and "Tm0 Count" indicates the count value of the counter 24 of the signal generation circuit Tm0. The other signals shown in FIG. 9 correspond to the signals shown in each part of FIG. 8. FIG. 9 also shows the timing at which photons are incident on the photodiode PD with an arrow above the signal waveform. Here, it is assumed that photons are incident at the same timing as in the timing diagrams of FIGS. 5 and 7.

[0088] First, the operation of the pixel circuit P will be described below using the pixel circuit Pmn in the mth row and nth column as an example.

[0089] During a period before time tr0, the reset signal pRES, the second control signal pCNTEN_B, and the signal VC are at a high level, and the first control signal pCLK and the signal PDOut are at a low level. Here, time tr0 is a time before time t1 in FIGS. 5 and 7. During this period, the reset signal pRES is at a high level, so the counter 24 is in a reset state, and the count value of the counter 24 is 0. Furthermore, since the PMOS transistor MP of the first control circuit 20 is maintained in an on state, the photodiode PD is maintained in a recharged state.

[0090] At time tr0, the reset signal pRES transitions from high to low. This allows the counter 24 to detect changes in the output of the photodiode PD. The PMOS transistor MP of the first control circuit 20 is turned off, and the photodiode PD is placed in a standby state where avalanche multiplication is possible.

[0091] The subsequent operations from time t1 to time t10 are the same as those in FIG. At the next time tr1, the reset signal pRES transitions from low to high. This resets the counter 24, and the count value of the counter 24 returns to 0. Furthermore, the PMOS transistor MP of the first control circuit 20 turns on, and the photodiode PD enters a recharge state. In other words, the reset signal pRES can control the operations of the counter 24 and the photodiode PD asynchronously with the first control signal pCLK and the second control signal pCNTEN_B.

[0092] Next, the operation of the signal generating circuit T will be described below, taking as an example the signal generating circuit Tm0 in the mth row and 0th column, which is arranged in the same row as the pixel circuit Pmn.

[0093] The circuitry of the signal generation circuit T is basically the same as the circuitry of the pixel circuit P, except that the connection between the logic circuit NOR1 and the counter 24 is cut off. In other words, the transitions of the signals VC and PDOut in the signal generation circuit T are the same as the transitions of the signals VC and PDOut in the pixel circuit P.

[0094] On the other hand, in the period up to time tr0, a High-level reset signal pRES is input to the counter 24 of the signal generation circuit T, and therefore the count value of the counter 24 is 0. After time tr0, as in Fig. 7, the signal CNTEN_B transitions from Low to High at each of times t5, t6, t8, and te1, and the count value of the counter 24 increases by 1 LSB. At the following time tr1, like the counter 24 of the pixel circuit P, the counter 24 is reset, and the count value of the counter 24 returns to 0.

[0095] As the number of pixel circuits P constituting the pixel region 10 increases, the phase relationship between the first control signal pCLK and the second control signal pCNTEN_B or the reset signal pRES may be reversed due to the influence of loads and wiring, making it impossible to obtain a desired output result. In this regard, in the semiconductor device 100 of this embodiment, the signal generation circuit T can count and output the number of pulses of the first control signal pCLK input during a period when the reset signal pRES and the second control signal pCNTEN_B are at a low level. Therefore, by deliberately changing the transition timing of the second control signal pCNTEN_B and the reset signal pRES, it is possible to accurately confirm the range in which a desired output result can be obtained. Furthermore, the waveforms of the first control signal pCLK, the second control signal pCNTEN_B, and the reset signal pRES can be adjusted as necessary. Furthermore, because the pixel circuits P and the signal generation circuit T in the same row operate at the same operating timing, it is possible to accurately confirm the phase relationship between the first control signal pCLK, the second control signal pCNTEN_B, and the reset signal pRES input to the pixel circuits P and their respective states. Furthermore, by checking the output of the row in which only the signal generation circuit T is arranged (signal generation circuit T00 to signal generation circuit T0n in FIGS. 1 and 2), it is possible to accurately check the change state of the signal that depends on the column position.

[0096] Thus, according to the semiconductor device of this embodiment, it is possible to accurately confirm the phase relationship between the first control signal pCLK and the second control signal pCNTEN_B and the reset signal pRES, as well as the state of the first control signal pCLK, thereby stabilizing the operation of the semiconductor device.

[0097] [Fourth embodiment] A semiconductor device according to a fourth embodiment of the present invention will be described with reference to Fig. 10. Fig. 10 is a diagram showing an example of the configuration of a pixel circuit and a signal generating circuit in the semiconductor device according to this embodiment. Components similar to those in the semiconductor devices according to the first to third embodiments are given the same reference numerals, and their description will be omitted or simplified.

[0098] The semiconductor device according to the present embodiment differs from the semiconductor device according to the third embodiment in the circuit configuration of the signal generation circuit T that constitutes the pixel region 10. The signal generation circuit T in the semiconductor device of the present embodiment will be described below, focusing on the differences from the third embodiment.

[0099] Fig. 10(a) is a diagram showing the configuration of a pixel circuit P in the semiconductor device of this embodiment, and Fig. 10(b) is a diagram showing the configuration of a signal generation circuit T in the semiconductor device of this embodiment. As shown in Figs. 10(a) and 10(b), the semiconductor device of this embodiment has the same configuration of the pixel circuit P as in the third embodiment, but the configuration of the signal generation circuit T is different from that of the third embodiment.

[0100] As shown in FIG. 10(b), the signal generation circuit T includes a photodiode PD, logic circuits NOR2, OR1, and NOR1, a first control circuit 20, a selection circuit SEL, and an output amplifier 28. That is, the signal generation circuit T of this embodiment differs from the signal generation circuit T of the third embodiment in that the counter 24 and the output circuit 26 are replaced with a selection circuit SEL and an output amplifier 28. The selection circuit SEL includes multiple input nodes, one output node, and a control node. A first control signal pCLK, a second control signal pCNTEN_B, a reset signal pRES, and a signal PDOut, which is the output of the logic circuit NOR1, are supplied to the multiple input nodes of the selection circuit SEL. A test output selection signal TESTSEL (third control signal) is supplied to the control node of the selection circuit SEL. The output node of the selection circuit SEL is connected to the input node of the output amplifier 28. The output node of the output amplifier 28 is connected to the output line 16.

[0101] The selection circuit SEL has a function of selecting either the first control signal pCLK or a signal different from the first control signal pCLK from among the signals input to the selection circuit SEL, depending on the setting value of the test output selection signal TESTSEL, and outputting the selected signal to the output amplifier 28. The signals input to the selection circuit SEL are not necessarily limited to the first control signal pCLK, the second control signal pCNTEN_B, the reset signal pRES, and the signal PDOut, but may be other signals. For example, the signal CNTEN_B, the signal VC, a signal of another node, etc. may be selected as the signal input to the selection circuit SEL. Furthermore, the number of bits of the signal TESTSEL may be changed as appropriate depending on the number of input signals.

[0102] The output amplifier 28 appropriately amplifies the analog signal output from the selection circuit SEL and outputs it as a signal POUT to the output line 16. Note that, although FIG. 10(b) assumes that the output of the output amplifier 28 is a single-wire output, the output of the output amplifier 28 may also be a differential output.

[0103] By configuring the signal generation circuit T in this manner, it is possible to directly check the waveform of each signal. This makes it possible to accurately check whether the desired signal is being input to each pixel circuit P and to make adjustments as necessary. Furthermore, because the pixel circuits P and signal generation circuits T in the same row operate at the same operating timing, it is possible to accurately check the phase relationship and each state of the first control signal pCLK, second control signal pCNTEN_B, and reset signal pRES input to the pixel circuits P. Furthermore, by checking the output of a row in which only the signal generation circuit T is arranged (signal generation circuits T00 to T0n in FIGS. 1 and 2), it is possible to accurately check the change state of signals that depend on the column position.

[0104] As described above, according to the semiconductor device of this embodiment, it is possible to accurately check the states of the first control signal pCLK, the second control signal pCNTEN_B, the reset signal pRES, etc., and to stabilize the operation of the semiconductor device.

[0105] [Fifth embodiment] A light detection system according to a fifth embodiment of the present invention will be described with reference to Fig. 11. Fig. 11 is a block diagram showing a schematic configuration of the light detection system according to this embodiment. In this embodiment, a light detection sensor to which the semiconductor device 100 described in any of the first to fourth embodiments is applied will be described.

[0106] The semiconductor device 100 described in the first to fourth embodiments can be applied to various photodetection systems. Examples of applicable photodetection systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photodetection system. Figure 11 illustrates a block diagram of a digital still camera as an example of such systems.

[0107] 11 includes a photoelectric conversion device 201, a lens 202 that forms an optical image of a subject on the photoelectric conversion device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the photoelectric conversion device 201. The photoelectric conversion device 201 is the semiconductor device 100 described in any one of the first to fourth embodiments, and converts the optical image formed by the lens 202 into image data.

[0108] The photodetection system 200 also includes a signal processing unit 208 that processes an output signal output from the photoelectric conversion device 201. The signal processing unit 208 generates image data from the digital signal output from the photoelectric conversion device 201. The signal processing unit 208 also performs various corrections and compressions as necessary and outputs the image data. The photoelectric conversion device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit, which is part of the signal processing unit 208, may be formed on the same semiconductor substrate on which the photoelectric conversion device 201 is provided, or may be formed on a different semiconductor substrate from the photoelectric conversion device 201. The photoelectric conversion device 201 and the signal processing unit 208 may also be formed on the same semiconductor substrate.

[0109] The light detection system 200 further includes a buffer memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The light detection system 200 also includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out imaging data from the recording medium 214. The recording medium 214 may be built into the light detection system 200 or may be removable. Communication between the recording medium control I / F unit 216 and the recording medium 214 and communication from the external I / F unit 212 may be performed wirelessly.

[0110] The photodetection system 200 further includes an overall control and calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the photoelectric conversion device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from outside, and the photodetection system 200 only needs to include at least the photoelectric conversion device 201 and the signal processing unit 208 that processes the output signal output from the photoelectric conversion device 201. The timing generation unit 220 may be mounted on the photoelectric conversion device 201. The overall control and calculation unit 218 and the timing generation unit 220 may be configured to perform some or all of the control functions of the photoelectric conversion device 201.

[0111] The photoelectric conversion device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the photoelectric conversion device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal. The signal processing unit 208 may be configured to perform distance measurement calculations on the signal output from the photoelectric conversion device 201.

[0112] As described above, according to this embodiment, by configuring a light detection system using the semiconductor device 100 according to the first to fourth embodiments, it is possible to realize a light detection system capable of acquiring higher quality images.

[0113] [Sixth embodiment] A range image sensor according to a sixth embodiment of the present invention will be described with reference to Fig. 12. Fig. 12 is a block diagram showing a schematic configuration of the range image sensor according to this embodiment. In this embodiment, the range image sensor will be described as an example of a light detection system to which the semiconductor device 100 described in any of the first to fourth embodiments is applied.

[0114] 12, the range image sensor 300 according to this embodiment may include an optical system 302, a photoelectric conversion device 304, an image processing circuit 306, a monitor 308, and a memory 310. This range image sensor 300 receives light (modulated light or pulsed light) that is irradiated from a light source device 320 toward a subject 330 and reflected by the surface of the subject 330, and obtains a range image according to the distance to the subject 330.

[0115] The optical system 302 is composed of one or more lenses, and serves to focus image light (incident light) from the subject 330 onto the light receiving surface (sensor section) of the photoelectric conversion device 304.

[0116] The photoelectric conversion device 304 is a semiconductor device 100 described in any one of the first to fourth embodiments, and has the function of generating a distance signal indicating the distance to the subject 330 based on image light from the subject 330, and supplying the generated distance signal to the image processing circuit 306.

[0117] The image processing circuit 306 has a function of performing image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 304 .

[0118] The monitor 308 has a function of displaying the distance image (image data) obtained by the image processing in the image processing circuit 306. The memory 310 has a function of storing (recording) the distance image (image data) obtained by the image processing in the image processing circuit 306.

[0119] Thus, according to this embodiment, by constructing a distance image sensor using the semiconductor devices of the first to fourth embodiments, it is possible to realize a distance image sensor that can acquire distance images containing more accurate distance information, in combination with improved characteristics of the pixel circuit P.

[0120] [Seventh embodiment] An endoscopic surgery system according to a seventh embodiment of the present invention will be described with reference to Fig. 13. Fig. 13 is a schematic diagram showing an example of the configuration of the endoscopic surgery system according to this embodiment. In this embodiment, the endoscopic surgery system will be described as an example of a light detection system to which the semiconductor device 100 described in any of the first to fourth embodiments is applied.

[0121] FIG. 13 shows a state in which an operator (doctor) 460 is performing surgery on a patient 472 on a patient bed 470 using an endoscopic surgery system 400.

[0122] 13, an endoscopic surgery system 400 of this embodiment may include an endoscope 410, a surgical tool 420, and a cart 430 on which various devices for endoscopic surgery are mounted. The cart 430 may be mounted with a CCU (camera control unit) 432, a light source device 434, an input device 436, a treatment tool control device 438, a display device 440, and the like.

[0123] The endoscope 410 includes a lens barrel 412, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 472, and a camera head 414 connected to the base end of the lens barrel 412. Although Fig. 16 illustrates the endoscope 410 configured as a so-called rigid lens barrel having a rigid lens barrel 412, the endoscope 410 may also be configured as a so-called flexible lens barrel having a flexible lens barrel. The endoscope 410 is held in a movable state by an arm 416.

[0124] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 412. A light source device 434 is connected to the endoscope 410, and light generated by the light source device 434 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 412, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 472. The endoscope 410 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0125] An optical system and a photoelectric conversion device (not shown) are provided inside the camera head 414, and light reflected from an observation object (observation light) is collected by the optical system onto the photoelectric conversion device. The photoelectric conversion device photoelectrically converts the observation light to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to an observation image. The semiconductor device 100 described in any of the first to fourth embodiments can be used as the photoelectric conversion device. The image signal is transmitted to the CCU 432 as RAW data.

[0126] The CCU 432 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 410 and the display device 440. Furthermore, the CCU 432 receives an image signal from the camera head 414, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0127] The display device 440 , under the control of the CCU 432 , displays an image based on the image signal that has been subjected to image processing by the CCU 432 .

[0128] The light source device 434 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 410 with irradiation light when photographing an operation site or the like.

[0129] The input device 436 is an input interface for the endoscopic surgery system 400. A user can input various information and instructions to the endoscopic surgery system 400 via the input device 436.

[0130] The treatment tool control device 438 controls the driving of an energy treatment tool 450 for cauterizing tissue, incising, sealing blood vessels, or the like.

[0131] The light source device 434, which supplies illumination light to the endoscope 410 when photographing the surgical site, can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 434. In this case, it is also possible to capture images corresponding to each RGB color in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 414 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0132] Furthermore, the light source device 434 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 414 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0133] The light source device 434 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation utilizes, for example, the wavelength dependency of light absorption in body tissue. Specifically, by irradiating light with a narrower band than the light (i.e., white light) used in normal observation, a predetermined tissue, such as blood vessels on the surface of the mucosa, can be photographed with high contrast. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto a body tissue and observing the fluorescence from the body tissue, or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 434 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0134] As described above, according to this embodiment, by configuring an endoscopic surgery system using the semiconductor devices of the first to fourth embodiments, it is possible to realize an endoscopic surgery system capable of acquiring higher quality images.

[0135] [Eighth embodiment] An optical detection system and a moving body according to an eighth embodiment of the present invention will be described with reference to Figs. 14 to 16. Fig. 14 is a schematic diagram showing a configuration example of a moving body according to this embodiment. Fig. 15 is a block diagram showing a schematic configuration of an optical detection system according to this embodiment. Fig. 16 is a flow diagram showing the operation of the optical detection system according to this embodiment. In this embodiment, an example of application of an optical detection system to an in-vehicle camera using the semiconductor device 100 described in any of the first to fourth embodiments will be shown.

[0136] FIG. 14 is a schematic diagram showing a configuration example of a moving body (vehicle system) according to this embodiment. FIG. 14 shows the configuration of a vehicle 500 (automobile) as an example of a vehicle system incorporating a photodetection system to which the semiconductor device according to any one of the first to fourth embodiments is applied. FIG. 14(a) is a schematic front view of the vehicle 500, FIG. 14(b) is a schematic plan view of the vehicle 500, and FIG. 14(c) is a schematic rear view of the vehicle 500. The vehicle 500 is provided with a pair of photoelectric conversion devices 502 on the front side. Here, the photoelectric conversion devices 502 are the semiconductor device 100 described in any one of the first to fourth embodiments. The vehicle 500 also includes an integrated circuit 503, an alarm device 512, and a main control unit 513.

[0137] FIG. 15 is a block diagram showing an example configuration of a photodetection system 501 mounted on a vehicle 500. The photodetection system 501 includes a photoelectric conversion device 502, an image preprocessing unit 515, an integrated circuit 503, and an optical system 514. The photoelectric conversion device 502 is the semiconductor device 100 described in any one of the first to fourth embodiments. The optical system 514 forms an optical image of a subject on the photoelectric conversion device 502. The photoelectric conversion device 502 converts the optical image of the subject formed by the optical system 514 into an electrical signal. The image preprocessing unit 515 performs predetermined signal processing on the signal output from the photoelectric conversion device 502. The function of the image preprocessing unit 515 may be incorporated into the photoelectric conversion device 502. The photodetection system 501 includes at least two sets of the optical system 514, the photoelectric conversion device 502, and the image preprocessing unit 515, and the output from each set of the image preprocessing unit 515 is input to the integrated circuit 503.

[0138] The integrated circuit 503 is an integrated circuit for use in an imaging system, and includes an image processing unit 504, an optical distance measuring unit 506, a parallax calculation unit 507, an object recognition unit 508, and an abnormality detection unit 509. The image processing unit 504 processes an image signal output from an image pre-processing unit 515. For example, the image processing unit 504 performs image processing such as development processing and defect correction on the output signal of the image pre-processing unit 515. The image processing unit 504 includes a memory 505 that temporarily stores the image signal. For example, the positions of known defective pixels in the photoelectric conversion device 502 can be stored in the memory 505.

[0139] The optical distance measurement unit 506 performs focusing and distance measurement of the subject. The parallax calculation unit 507 calculates distance information (distance information) from multiple image data (parallax images) acquired by the multiple photoelectric conversion devices 502. Each of the photoelectric conversion devices 502 may be configured to be able to acquire various information such as distance information. The object recognition unit 508 recognizes subjects such as cars, roads, signs, and people. When the abnormality detection unit 509 detects an abnormality in the photoelectric conversion device 502, it notifies the main control unit 513 of the abnormality.

[0140] The integrated circuit 503 may be realized by dedicated hardware, a software module, or a combination thereof. It may also be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or a combination thereof.

[0141] The main control unit 513 supervises and controls the operations of the light detection system 501, the vehicle sensor 510, the control unit 520, etc. Note that the vehicle 500 does not necessarily have to include the main control unit 513. In this case, the photoelectric conversion device 502, the vehicle sensor 510, and the control unit 520 transmit and receive control signals via a communication network. For example, the CAN standard may be applied to the transmission and reception of these control signals.

[0142] The integrated circuit 503 has a function of receiving a control signal from the main control unit 513 or transmitting a control signal or a set value to the photoelectric conversion device 502 by its own control unit.

[0143] The optical detection system 501 is connected to a vehicle sensor 510 and can detect the vehicle's driving conditions, such as vehicle speed, yaw rate, and steering angle, as well as the conditions of the environment outside the vehicle and other vehicles and obstacles. The vehicle sensor 510 also serves as a distance information acquisition means for acquiring distance information to an object. The optical detection system 501 is also connected to a driving assistance control unit 511 that performs various driving assistance functions, such as automatic steering, automatic cruising, and collision prevention functions. In particular, the collision determination function determines whether or not a collision with another vehicle or obstacle has occurred based on the detection results of the optical detection system 501 and the vehicle sensor 510. This allows for avoidance control when a collision is estimated, and activation of safety devices in the event of a collision.

[0144] The optical detection system 501 is also connected to an alarm device 512 that issues an alarm to the driver based on the determination result of the collision determination unit. For example, if the collision determination unit determines that there is a high possibility of a collision, the main control unit 513 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 512 warns the user by sounding an alarm or the like, displaying alarm information on a display screen of a car navigation system or meter panel, vibrating the seat belt or steering wheel, etc.

[0145] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are photographed by the light detection system 501. Fig. 14(b) shows an example of the arrangement of the light detection system 501 when the light detection system 501 photographs the area in front of the vehicle.

[0146] As described above, the photoelectric conversion device 502 is disposed in front of the vehicle 500. Specifically, if the center line of the vehicle 500's heading or outer shape (for example, vehicle width) is regarded as an axis of symmetry, and the two photoelectric conversion devices 502 are disposed symmetrically about the axis of symmetry, this is preferable for obtaining distance information between the vehicle 500 and an object to be photographed and determining the possibility of a collision. Furthermore, the photoelectric conversion device 502 is preferably disposed so as not to obstruct the driver's field of vision when the driver visually checks the situation outside the vehicle 500 from the driver's seat. The warning device 512 is preferably disposed so as to be easily within the driver's field of vision.

[0147] Next, a fault detection operation of the photoelectric conversion device 502 in the light detection system 501 will be described with reference to Fig. 16. The fault detection operation of the photoelectric conversion device 502 can be performed according to steps S110 to S180 shown in Fig. 16.

[0148] Step S110 is a step for performing startup settings for the photoelectric conversion device 502. That is, settings for the operation of the photoelectric conversion device 502 are transmitted from outside the photodetection system 501 (for example, from the main control unit 513) or from inside the photodetection system 501, and the image capturing operation and fault detection operation of the photoelectric conversion device 502 are started.

[0149] Next, in step S120, pixel signals are acquired from the valid pixels. Furthermore, in step S130, output values ​​are acquired from the failure detection pixels provided for failure detection. These failure detection pixels have photoelectric conversion elements, just like the valid pixels. A predetermined voltage is written to these photoelectric conversion elements. The failure detection pixels output signals corresponding to the voltage written to these photoelectric conversion elements. Note that steps S120 and S130 may be reversed.

[0150] Next, in step S140, a correspondence between the expected output value of the fault detection pixel and the actual output value from the fault detection pixel is determined. If the result of the correspondence determination in step S140 indicates that the expected output value and the actual output value match, the process proceeds to step S150, where it is determined that the imaging operation is normal, and the process proceeds to step S160. In step S160, the pixel signals of the scanning row are sent to memory 505 and temporarily stored. Thereafter, the process returns to step S120, where the fault detection operation continues. On the other hand, if the result of the correspondence determination in step S140 indicates that the expected output value and the actual output value do not match, the process proceeds to step S170. In step S170, it is determined that an abnormality exists in the imaging operation, and an alarm is issued to the main control unit 513 or the alarm device 512. The alarm device 512 displays the detection of the abnormality on the display unit. Thereafter, in step S180, the photoelectric conversion device 502 is stopped, and the operation of the light detection system 501 is terminated.

[0151] In this embodiment, the flowchart is looped for each line, but the flowchart may be looped for each set of lines, or the fault detection operation may be performed for each frame. The issuance of the alarm in step S170 may be notified to the outside of the vehicle via a wireless network.

[0152] Furthermore, although the present embodiment has been described as a control for preventing collisions with other vehicles, the present invention is also applicable to control for automatic driving by following other vehicles, control for automatic driving so as not to deviate from a lane, and the like. Furthermore, the light detection system 501 is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention is not limited to moving bodies, but can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0153] [Ninth embodiment] A light detection system according to a ninth embodiment of the present invention will be described with reference to Fig. 17. Fig. 17 is a schematic diagram showing a configuration example of the light detection system according to this embodiment. In this embodiment, an example of application of the semiconductor device 100 according to any one of the first to fourth embodiments to eyeglasses (smart glasses) will be described.

[0154] 17(a) shows glasses 600 (smart glasses) according to one application example. The glasses 600 include lenses 601, a photoelectric conversion device 602, and a control device 603.

[0155] The photoelectric conversion device 602 is the semiconductor device 100 described in any one of the first to fourth embodiments, and is provided on the lens 601. The number of photoelectric conversion devices 602 may be one or more. When a plurality of photoelectric conversion devices 602 are used, a combination of different types of photoelectric conversion devices 602 may be used. The arrangement position of the photoelectric conversion device 602 is not limited to that shown in FIG. 17( a). A display device (not shown) including a light-emitting device such as an OLED or LED may be provided on the back side of the lens 601.

[0156] The control device 603 functions as a power source that supplies power to the photoelectric conversion device 602 and the display device. The control device 603 also has a function of controlling the operations of the photoelectric conversion device 602 and the display device. The lens 601 is provided with an optical system for condensing light onto the photoelectric conversion device 602.

[0157] 17(b) shows glasses 610 (smart glasses) according to another application example. The glasses 610 include lenses 611 and a control device 612. The control device 612 may be equipped with a photoelectric conversion device (not shown) corresponding to the photoelectric conversion device 602 and a display device.

[0158] The lens 611 is provided with a photoelectric conversion device in the control device 612 and an optical system for projecting light from the display device, and an image is projected. The control device 612 functions as a power source that supplies power to the photoelectric conversion device and the display device, and also has a function of controlling the operations of the photoelectric conversion device and the display device.

[0159] The control device 612 may further include a gaze detection unit that detects the gaze of the wearer. In this case, an infrared light emitting unit may be provided in the control device 612, and the infrared light emitted from the infrared light emitting unit may be used to detect the gaze. Specifically, the infrared light emitting unit emits infrared light toward the eyeball of the user gazing at the displayed image. An imaging unit having a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. By providing a reduction unit that reduces the light from the infrared light emitting unit to the display unit in a planar view, it is possible to reduce degradation of image quality.

[0160] The user's line of sight with respect to the displayed image can be detected from an image of the eyeball obtained by capturing infrared light. Any known method can be applied to gaze detection using an image of the eyeball. As an example, a gaze detection method based on a Purkinje image formed by reflection of irradiated light on the cornea can be used. More specifically, a gaze detection process based on the pupil-corneal reflex method is performed. Using the pupil-corneal reflex method, a gaze vector representing the direction (rotation angle) of the eyeball is calculated based on the image of the pupil and the Purkinje image included in the image of the eyeball, thereby detecting the user's gaze.

[0161] The display device of this embodiment may include a photoelectric conversion device having a light receiving element, and may be configured to control a display image based on user line-of-sight information from the photoelectric conversion device. Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device or by an external control device. If determined by an external control device, they are communicated to the display device via communication. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than the resolution of the first field of view area.

[0162] The display area may also be configured to have a first display area and a second display area different from the first display area, and to determine a high-priority area from the first display area and the second display area based on line-of-sight information. The first display area and the second display area may be determined by a control device of the display device or by an external control device. If determined by an external control device, the determination is communicated to the display device via communication. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0163] Note that AI may be used to determine the first field of view area and areas with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from an image of the eyeball, using as training data an image of the eyeball and the actual direction in which the eyeball in the image was looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0164] When display control is performed based on visual recognition detection, the present invention is preferably applied to smart glasses that further include a photoelectric conversion device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0165] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible. For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0166] Furthermore, the configurations of the pixel circuits P and the signal generating circuits T and their operation timings described in the first to fourth embodiments are not limited to those described in the embodiments. For example, the configurations of the logic circuits and the first control circuit 20 may be different, and the operation timings can also be changed as appropriate.

[0167] Furthermore, the first control signal pCLK and the second control signal pCNTEN_B supplied to the pixel circuit P and the signal generation circuit T may be inverted signals of the signals described in the above embodiment. In this case, the logic circuits constituting the pixel circuit P and the signal generation circuit T may be appropriately changed according to the waveforms of these control signals.

[0168] Furthermore, the photodetection systems shown in the fifth to ninth embodiments are examples of photodetection systems to which the semiconductor device of the present invention can be applied, and photodetection systems to which the semiconductor device of the present invention can be applied are not limited to the configurations shown in Figures 11 to 17.

[0169] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0170] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0171] MP...PMOS transistor NOR1, NOR2, NOT1, NOT2, OR1...Logic circuits P...Pixel circuit T…Signal generation circuit 10...Pixel area 14...Control line 16...Output line 20...First control circuit 22...Second control circuit 24...Counter 26...Output circuit 100...Semiconductor device

Claims

1. a region in which a plurality of circuit blocks each having an avalanche photodiode are provided; a pixel circuit further including a first control circuit, some of the plurality of circuit blocks having a transistor that controls supply of a voltage that enables avalanche multiplication in the avalanche photodiode, and that controls the avalanche photodiode between a state in which the transistor is turned off and the voltage is not supplied, and a state in which the transistor is turned on and the voltage is supplied, in response to a first control signal; another part of the plurality of circuit blocks is a signal generating circuit that generates a signal corresponding to a waveform of the first control signal; The signal generating circuit is configured not to output a signal corresponding to the output of the avalanche photodiode. A semiconductor device characterized by:

2. a first signal line connected to the pixel circuit and the signal generating circuit and supplying the first control signal common to the pixel circuit and the signal generating circuit; 2. The semiconductor device according to claim 1.

3. the plurality of circuit blocks include a plurality of signal generating circuits; The semiconductor device further includes a first signal line connected to the plurality of signal generating circuits and supplying the first control signal common to the plurality of signal generating circuits.

2. The semiconductor device according to claim 1.

4. The signal generating circuit generates a signal corresponding to a waveform of the first control signal and a waveform of a second control signal corresponding to an exposure period of the avalanche photodiode.

4. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor substrate.

5. a second signal line connected to the pixel circuit and the signal generating circuit and supplying the second control signal common to the pixel circuit and the signal generating circuit; 5. The semiconductor device according to claim 4.

6. the plurality of circuit blocks include a plurality of signal generating circuits; The semiconductor device further includes a second signal line connected to the plurality of signal generating circuits and supplying the second control signal common to the plurality of signal generating circuits.

5. The semiconductor device according to claim 4.

7. the pixel circuit further includes a second control circuit that counts the number of periods during which the avalanche multiplication occurs in the avalanche photodiode, within a period defined by an interval between pulses superimposed on the first control signal; The signal generating circuit has a third control circuit that counts the number of periods defined by the intervals between pulses superimposed on the first control signal.

4. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor substrate.

8. The counting periods in the second control circuit and the third control circuit are determined by the first control signal and a second control signal corresponding to an exposure period of the avalanche photodiode.

8. The semiconductor device according to claim 7.

9. The counting period in the second control circuit and the third control circuit is determined by the first control signal, the second control signal, and a reset signal that resets the count values ​​in the second control circuit and the third control circuit.

9. The semiconductor device according to claim 8.

10. The avalanche photodiode of the signal generating circuit is electrically disconnected from the third control circuit.

10. The semiconductor device according to claim 7, wherein the first insulating film is a semiconductor material.

11. a region in which a plurality of circuit blocks each having an avalanche photodiode are provided; Some of the plurality of circuit blocks include a first control circuit having a transistor for controlling the supply of a voltage that enables avalanche multiplication in the avalanche photodiode, and controlling the avalanche photodiode between a state in which the transistor is turned off and the voltage is not supplied, and a state in which the transistor is turned on and the voltage is supplied, in response to a first control signal; a second control circuit that counts the number of periods in which the avalanche multiplication occurs in the avalanche photodiode, among periods defined by intervals between pulses superimposed on the first control signal; Another part of the plurality of circuit blocks is a signal generating circuit further including a selection circuit that selects and outputs one of the first control signal and a signal different from the first control signal in response to a third control signal. A semiconductor device characterized by:

12. The signal different from the first control signal is at least one of a signal corresponding to an output from the avalanche photodiode, a second control signal corresponding to an exposure period of the avalanche photodiode, and a reset signal that resets a count value in the second control circuit of the pixel circuit.

12. The semiconductor device according to claim 11.

13. the plurality of circuit blocks are arranged across a plurality of rows and a plurality of columns, The pixel circuits and the signal generating circuits are arranged in the same row.

13. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

14. the plurality of circuit blocks are arranged across a plurality of rows and a plurality of columns, The plurality of signal generating circuits are arranged in the same row.

7. The semiconductor device according to claim 3 or 6.

15. The signal generating circuit includes the same circuit elements as the circuit elements that configure the pixel circuit.

15. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

16. The first control signal is a clock signal including pulses of a predetermined period.

16. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

17. A semiconductor device according to any one of claims 1 to 16, a signal processing device that processes a signal output from the semiconductor device; An optical detection system comprising:

18. The signal processing device generates a distance image representing distance information to an object based on the signal.

18. The optical detection system of claim 17.

19. A mobile object, A semiconductor device according to any one of claims 1 to 16, a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal output from the semiconductor device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

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