Semiconductor light emitting element, light source device and distance measuring device

Abstract

To provide a light source device that can achieve both flattening of a FFP and a reduction in the chip area due to an increase in emission diameter.SOLUTION: A light source device has a plurality of semiconductor light emitting elements arranged on a semiconductor substrate, the semiconductor light emitting elements each having a first reflecting mirror, a resonator part including an active layer, and a second reflecting mirror laminated in this order. The semiconductor light emitting elements are each provided with an electrical contact area for supplying carrier to the active layer on a surface of the second reflecting mirror on the opposite side of the active layer. The plurality of semiconductor light emitting element include a first semiconductor light emitting element provided with the contact area in a first shape, and a second semiconductor light emitting element provided with the contact area in a second shape different from the first shape.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light emitting element, a light source device, and a distance measuring device. [Background technology]

[0002] Patent Document 1 describes an example in which two types of VCSELs (Vertical Cavity Surface Emitting Lasers) that emit beams with different far-field patterns (FFPs) are configured on the same substrate. In order to differentiate the FFPs, a metal member is placed on the optical path from which the beam is emitted in one of the VCSELs, causing loss in the higher-order mode and thereby controlling the transverse mode of oscillation.

[0003] Another known method of imparting loss to higher-order modes is to control the reflectivity within the plane of the reflector by processing the top surface of the VCSEL's upper reflector or patterning the dielectric layer above it, thereby selectively imparting loss to higher-order modes.

[0004] By placing VCSELs that emit different FFPs on the same substrate and overlapping the light emitted from them, it becomes possible to flatten the FFPs emitted from the VCSEL array, in other words, to achieve more uniform light irradiation, as described in Patent Document 1.

[0005] Uniform light illumination is useful when using VCSELs as a light source for illumination. For example, VCSELs are used as light sources for ToF (Time of Flight) LiDAR (Light Detection and Ranging). When irradiating light, uniform irradiation can prevent areas with low light intensity, which has the advantage of preventing non-detection when a small object is present in that area.

[0006] When using VCSELs as lighting, for example as a light source for ToF, the pulse width is short, but the optical output may require a peak output of 0.1 W or more, or even up to 100 W depending on the application. In such cases, the required light intensity is achieved by arranging a large number of VCSELs in a two-dimensional array.

[0007] When multiple VCSELs are used in an array, increasing the light-emitting diameter of each VCSEL makes it possible to increase the ratio of the area used for actual light emission to the chip area of ​​the VCSEL array. In other words, increasing the light-emitting diameter of each VCSEL reduces the chip area required for the VCSEL array, which provides advantages in terms of coupling with an optical system and cost.

[0008] However, if the VCSEL's emission diameter is large (typically 10 μm or more), it becomes impossible to control the transverse mode by selectively inflicting loss on higher-order modes. Therefore, when adopting a method such as that described in Patent Document 1, it is necessary to keep the emission diameter to 10 μm or less in order to control the FFP, which poses the problem of not being able to simultaneously reduce the chip area by increasing the emission diameter and control (uniformize) the FFP. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-278572 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of the present invention is to provide a light source device that can achieve both flattening of the FFP and reduction of the chip area by enlarging the light-emitting diameter. [Means for solving the problem]

[0011] One aspect of the present invention is a light source device including a plurality of semiconductor light emitting elements arranged on a semiconductor substrate, each of which has a first reflecting mirror, a resonator portion including an active layer, and a second reflecting mirror stacked in this order, Multiple each of the semiconductor light-emitting elements has an electrical contact region on a surface of the second reflector opposite to the active layer, the electrical contact region being for supplying carriers to the active layer; The aforementioned multiple half of The semiconductor light emitting device includes a first semiconductor light emitting element in which the shape of the contact region is a first shape, and a second semiconductor light emitting element in which the shape of the contact region is a second shape different from the first shape, The aforementioned Multiple Each of the semiconductor light emitting elements has a current confinement portion having an annular low conductivity region and a high conductivity region inside the annular low conductivity region, in at least one of the first reflecting mirror, the resonator portion, and the second reflecting mirror; In a plan view, the contact region of the first semiconductor light emitting element overlaps with the center of gravity of the light emitting region defined by the current confinement portion. The light source device is characterized by the above. [Effects of the Invention]

[0012] According to the present invention, it is possible to achieve both flattening of the FFP and reduction of the chip area by enlarging the light emitting diameter. [Brief explanation of the drawings]

[0013] [Figure 1A] 1 is a top view of the VCSEL array 10 according to the first embodiment. [Figure 1B] Cross-sectional view of the VCSEL 100 of Example 1 [Figure 1C] Cross-sectional view of the VCSEL 200 of Example 1 [Figure 2A] FIG. 1 is a diagram illustrating a current density distribution in Example 1. [Figure 2B] FIG. 1 is a diagram illustrating a current density distribution in Example 1. [Figure 2C] FIG. 1 is a diagram illustrating the beam intensity distribution in the far field region in Example 1. [Figure 2D] FIG. 1 is a diagram illustrating the beam intensity distribution in the far field region in Example 1. [Figure 3A] 1 is a top view of a VCSEL array 20 according to a second embodiment of the present invention; [Figure 3B] Cross-sectional view of a VCSEL 300 according to a second embodiment [Figure 3C] Cross-sectional view of a VCSEL 400 according to a second embodiment [Figure 3D] FIG. 10 is a diagram illustrating the current density distribution in Example 2. [Figure 3E] FIG. 10 is a diagram illustrating the current density distribution in Example 2. [Figure 3F] FIG. 10 is a diagram illustrating the beam intensity distribution in the far field region in Example 2. [Figure 3G] FIG. 10 is a diagram illustrating the beam intensity distribution in the far field region in Example 2. [Figure 4A] 1 is a top view of a VCSEL array 30 according to a third embodiment of the present invention; [Figure 4B] Cross-sectional view of VCSEL 500 according to Example 3 [Figure 4C] Top view of VCSEL 500 of Example 3 [Figure 4D] Top view of VCSEL 500 (modification) of Example 3 [Figure 5A] 1 is a top view of a VCSEL array 40 according to a fourth embodiment of the present invention; [Figure 5B] Cross-sectional view of VCSEL 600 according to Example 4 [Figure 5C] Cross-sectional view of a VCSEL 700 according to a fourth embodiment [Figure 6] 10 is a schematic diagram of a distance measuring device according to a sixth embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0014] [First Example] A VCSEL array (light source device) 10 according to the first embodiment of the present invention is configured by arranging a plurality of VCSELs (semiconductor light emitting elements).

[0015] 1A is a diagram illustrating the arrangement of VCSELs in a VCSEL array 10. The VCSEL array 10 of this embodiment includes two types of VCSELs: a VCSEL 100 and a VCSEL 200. L. The VCSEL 100 emits laser light with a single-peaked FFP, and the VCSEL 200 emits laser light with a bi-peaked FFP (see FIG. 2C).

[0016] As will be described later, VCSEL100 and VCSEL200 differ in the shape of the electrical contact region (shown by the dotted line in FIG. 1A) provided on the surface side of the upper DBR to supply carriers to the resonator portion, which results in different FFP profiles. Details will be described later.

[0017] The VCSEL array 10 of this embodiment is composed of 20 VCSELs 100 and one VCSEL 200. The number of VCSELs 100 is greater than the number of VCSELs 200 because the VCSELs 100 have a smaller light-emitting area and therefore have a smaller optical output per VCSEL. The ratio of the number of VCSELs is determined so that the intensity is flattened when the beams emitted from these are superimposed in the far-field region.

[0018] The configuration of each VCSEL will be explained below.

[0019] 1B is a cross-sectional schematic diagram of VCSEL 100. VCSEL 100 is constructed by stacking a lower DBR (first reflector) 102, a semiconductor resonator section 103, and an upper DBR (second reflector) 104 in this order on a GaAs substrate (semiconductor substrate) 101. Although these components are shown in direct contact in FIG. 3, other components may be provided between them. Furthermore, the above description is merely an explanation of the structure and does not limit the order in which the components are manufactured.

[0020] Three quantum well layers 140 are arranged in the cavity section 103. The upper DBR 104 is partially covered with Al 0.98 The insulating oxidized confinement layer 106 is formed by oxidizing GaAs using steam oxidation. In this embodiment, the current confinement portion formed by the oxidized confinement layer 106 is formed in the upper DBR 104, but the current confinement portion may also be formed in the lower DBR 102 or the resonator portion 103.

[0021] The resonator portion 103 and the upper DBR 104 are processed into a cylindrical mesa shape, and are covered from above with an insulating film 161. On the insulating film 161, an ITO (Indium Tin Oxide) layer is formed.

[0022] As shown in FIG. 1B , an insulating film 161 with a partially removed central portion is provided on the upper surface of the mesa-shaped upper DBR 104, and an ITO layer 162 contacts the upper surface of the upper DBR 104 in the removed portion. In this disclosure, the portion from which the insulating film 161 is removed is referred to as an insulating opening. It can be said that the ITO layer 162 contacts the upper surface of the upper DBR 104 at the insulating opening portion. In this embodiment, the insulating opening in the insulating film 161 is circular. Furthermore, a ring electrode 150 is in electrical contact with a portion of the ITO layer 162. The common electrode 151 is in ohmic contact with the rear surface of the GaAs substrate 101.

[0023] Carriers supplied from ring electrode 150 are supplied to resonator portion 103 through the insulating opening portion. That is, a contact region on the surface of upper DBR 104 (the surface opposite to the surface in contact with the active layer) is formed by insulating film 161, a portion of which has been removed in a circular shape, and ITO layer 162, which is in contact with upper DBR 104 at the insulating opening portion where insulating film 161 has been removed. The shape (first shape) of the contact region in VCSEL 100 is circular.

[0024] The lower DBR (Distributed Bragg Reflector) 102 is made of Al with an optical thickness of λc / 4. 0.1 GaAs layer and Al 0.9 The GaAs layer is counted as one pair, and 35 pairs are stacked to form the structure. λc is the center wavelength of the high reflection band of the lower DBR 102, which is 940 nm in this embodiment.

[0025] The quantum well layer 140 is an 8 nm thick In 0.1 The GaAs layer is covered with 10 nm of Al 0.1 GaAs In this embodiment, three quantum well layers are arranged in the resonator section 103.

[0026] The upper DBR 104 is an Al 0.1 GaAs layer and Al 0.9 The structure is composed of 20 pairs of GaAs layers stacked together. 0.1 G A part of the aAs layer has a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3 GaAs contact The Al layer closest to the quantum well layer 140 of the upper DBR is replaced with a conductive layer, improving the electrical contact with the transparent conductive layer (ITO layer) 162. 0.1 A part of the GaAs layer is thick 30nm thick Al 0.98 The Al layer is replaced by a GaAs layer. 0.98 After the mesa of the VCSEL 100 is formed, the GaAs layer is oxidized by steam oxidation from the mesa sidewall to a predetermined length from the mesa edge, thereby forming an insulating oxidized constriction layer 106 .

[0027] The diameter d1 of the insulating opening portion where the insulating film 161 has been removed is 10 μm. The diameter d2 of the semiconductor portion inside 6 (i.e., the portion with high conductivity through which current can flow, hereinafter referred to as the non-oxidized portion) is 30 μm. In addition, in a plan view, the centers of the insulating opening portion and the non-oxidized portion are approximately aligned, and the insulating opening portion is included in the non-oxidized portion. Because the non-oxidized portion is the portion in the resonator portion 103 through which current can flow, the diameter of the non-oxidized portion becomes the light-emitting diameter of the VCSEL. This is the same in this embodiment and in the following embodiments.

[0028] The number of pairs in the lower DBR 102 is designed to have a higher reflectance than the upper DBR 104. Furthermore, the insulating film 161 and ITO layer 162 provided on the upper DBR 104 are also transparent at the emission wavelength and transmit light, so that the VCSEL 100 of this embodiment can extract light from the upper DBR 104 side.

[0029] 1C shows a schematic cross-sectional view of VCSEL 200. VCSEL 200 is configured by stacking a lower DBR (first reflector) 202, a semiconductor resonator section 203, and an upper DBR (second reflector) 204 in this order on a GaAs substrate (semiconductor substrate) 201.

[0030] Three quantum well layers 240 are arranged in the cavity section 203. The upper DBR is partially covered with Al 0.98 An oxidized constriction layer 206 having insulating properties is formed by oxidizing GaAs using steam oxidation.

[0031] The resonator section 203 and the upper DBR 204 are processed into a cylindrical mesa shape, and are covered from above with an insulating film 261. On the insulating film 261, an ITO (Indium Tin Oxide) layer is formed.

[0032] As shown in FIG. 1C, an insulating film 261 with a circular ring-shaped central portion removed is provided on the upper surface of the mesa-shaped upper DBR 204, and an ITO layer 262 contacts the upper surface of the upper DBR 204 in the removed portion (insulating opening). The insulating opening in the VCSEL 200 is circular (ring) shaped. A ring electrode 250 is in electrical contact with a portion of the ITO 262. A common electrode 251 is in ohmic contact with the rear surface of the GaAs substrate 201.

[0033] Carriers supplied from the ring electrode 250 are supplied to the resonator portion 203 through the insulating opening portion. That is, a contact region on the surface of the upper DBR 204 (the surface opposite to the surface in contact with the active layer) is formed by the insulating film 261, a portion of which has been removed in an annular shape, and the ITO layer 262, which is in contact with the upper DBR 204 at the insulating opening portion where the insulating film 261 has been removed. VC The shape (second shape) of the contact region in the SEL 200 is annular.

[0034] The inner diameter d3 of the annular insulating opening portion where insulating film 261 has been removed is 35 μm, and the outer diameter d4 is 45 μm. The diameter d2 of the semiconductor portion inside oxidized constriction layer 206 (i.e., the portion that is highly conductive and allows current to flow; hereinafter referred to as the non-oxidized portion) is 70 μm. In plan view, the centers of the insulating opening portion and the non-oxidized portion are approximately aligned, and the insulating opening portion is included in the non-oxidized portion.

[0035] The layer structure of the VCSEL in Figure 1C is the same as that of the VCSEL in Figure 1B because they are monolithically formed simultaneously on the same substrate using the same crystal growth layers, and therefore a detailed description of the layer structure in Figure 1C will be omitted.

[0036] The arrangement of the VCSELs 100 and 200 in the VCSEL array 10 will be further described with reference to FIG. 1A.

[0037] The ring electrodes 150 on the VCSEL 100 are electrically connected to each other via wiring electrodes 172. They are also electrically connected to wire bonding pads 170 for supplying current from the outside. The ring electrode 250 on the VCSEL 200 is electrically connected to wire bonding pads 270 for supplying current from the outside.

[0038] The reason why VCSEL200 is arranged at the edge of the array as shown in Figure 1A, rather than being surrounded entirely by VCSEL100, is to enable the wiring electrodes from VCSEL200 to be connected to pad 270 without crossing other wiring electrodes. In this case, there is no need to make the wiring multilayer, which is advantageous in terms of the processing process and electrical crosstalk via parasitic capacitance.

[0039] In d-ToF applications, it is desirable to change the current in nanoseconds or less. Also, the current value is large compared to the current values in other applications such as general communication, and can be 1 A or more. Therefore, when the wirings are connected by parasitic capacitance, it is a condition where unintended current easily flows through the parasitic capacitance, and there may be a problem that the controllability of FFP by controlling the current value due to the unintended current decreases.

[0040] In FIG. 1A, the VCSELs 100 are arranged in a square pattern, but other arrangement methods such as a triangular pattern may be used. Also, the position, number, and shape of the wiring electrodes 172 that connect the wire bonding pads and the ring electrodes 150 of the VCSELs on each mesa have the same effect even if they are different from the configuration shown in FIG. 1 as long as the electrical connection is equivalent.

[0041] FIG. 2A shows the calculation result of the current density distribution injected into the active layer in the configuration of the VCSEL 100.

[0042] FIG. 2A shows the distribution of the current density flowing into the quantum well layer 140 when the diameter d1 of the active layer insulating opening changes from 5 μm to 25 μm with the oxidation constriction diameter d2 being 30 μm. The horizontal axis in FIG. 2A is the radial position when the mesa center (that is, also the center of the non-oxidized portion) is set as position 0. From this, it can be seen that if the diameter d1 of the insulating opening portion is up to 20 μm, a convex current density distribution can be created in the center. Thus, by setting d1 < d2, the shape of the current density distribution flowing into the current quantum well layer can be formed into a convex shape in the center, and the far-field image can be controlled. In this embodiment, d1 is 20 μm.

[0043] FIG. 2B shows the calculation of the current density distribution injected into the active layer in the configuration of the VCSEL 200 results. In this embodiment, the inner diameter of the annular insulating opening portion from which the insulating layer is removed is 35 μm, and the outer diameter is 45 μm. For comparison, the calculation results when the width of the insulating opening is changed to 10 μm from an inner diameter of 20 μm to 50 μm are shown. Also, the diameter d2 of the non-oxidized portion of the oxidation constriction layer is 70 μm.

[0044] As shown in Figure 2B, when the inner diameter is 35 μm and the outer diameter is 45 μm, the current density distribution injected into the active layer has a peak at 20 μm on the horizontal axis, and the current density at the minimum values ​​near positions 0 and 33 μm is similar to that under other conditions. In this way, a bimodal current density distribution can be achieved by using a circular current injection distribution.

[0045] Figure 2C shows the intensity distribution in the far-field region of light emitted from VCSEL100 and VCSEL200. This is a far-field pattern obtained by roughly estimating the intensity distributions of the zeroth and first-order transverse modes from the half-widths of the current density distributions shown in Figures 2A and 2B. Figure 2D shows the intensity distributions superimposed at the intensity ratio based on the number of VCSELs shown in Figure 1A.

[0046] This shows that by comparing the beams from VCSEL100 and VCSEL200 and superimposing them at the designed intensity ratio, flattening can be achieved mainly in the divergence angle range of -0.5 to +0.5°.

[0047] The intensity ratio between VCSEL100 and VCSEL200 is designed to be approximately 20:1, with VCSEL100 being the main component. The light-emitting diameter per unit area is small, and the amount of light that can be emitted is also small. For this reason, in the VCSEL array 10 of this embodiment, more VCSELs 100 are arranged. When the beams from all the VCSELs that make up the VCSEL array 10 are superimposed, the intensity is designed to be flattened in the center of the divergence angle, which in this embodiment is within a range of ±0.5°.

[0048] Next, a comparison of the array size between the VCSEL array 10 of this embodiment and a conventional VCSEL will be described. As shown in FIG. 1A, the VCSEL array 10 of this embodiment is composed of VCSELs 100 with an emission diameter of 30 μm and VCSELs 200 with an emission diameter of 70 μm. The VCSELs 100 are arranged at a pitch of 64 μm, based on the emission diameter and the size required around it. Since six VCSELs are arranged horizontally and four vertically, the size of the VCSEL array 10 is 384 μm horizontally and 256 μm vertically.

[0049] On the other hand, in the configuration of the conventional example, the light-emitting diameter must be 10 μm or less to control the beam shape as described above. Therefore, consider a case where the light-emitting diameter is 10 μm and the pitch is narrower than that of this embodiment by the difference in the light-emitting diameter of 20 μm, specifically, a pitch of 44 μm. To obtain the same optical output at the same drive current density as this embodiment, the total light-emitting area, calculated by adding up the light-emitting areas, should be the same as the VCSEL array 10 of this embodiment. Calculations show that the number of VCSELs required to obtain the same optical output as this embodiment with the configuration of the conventional example is approximately 225. When these are arranged in an array of 15 elements vertically and horizontally, the length of the array is 660 μm.

[0050] As described above, the VCSEL array 10 of this embodiment can achieve the same optical output with a smaller area than an array using a conventional VCSEL. This is because the VCSEL array is configured with a larger light-emitting diameter than the conventional example. The reason why a VCSEL array with a larger light-emitting diameter can be configured is because the FFP can be flattened with a larger light-emitting diameter than the conventional example. This is also true for this embodiment and Example 2 and subsequent examples.

[0051] [Second Example] 3A shows a VCSEL array 20 using VCSEL 300 and VCSEL 400 in this embodiment. In this embodiment, the VCSEL 300 that emits laser light with a single peak FFP and the VCSEL 400 that emits laser light with a bipeak FFP are approximately the same size, and both have an emission diameter of approximately 70 μm. In other words, the emission diameter of the VCSEL that emits laser light with a single peak FFP is larger than in Example 1.

[0052] The ring electrodes 350 on the VCSEL 300 are electrically connected to each other via wiring electrodes 372, and are also electrically connected to wire bonding pads 370 for supplying current from the outside. The ring electrodes 450 on the VCSEL 400 are electrically connected to each other via wiring electrodes 472, and are also electrically connected to wire bonding pads 470 for supplying current from the outside.

[0053] The reason why VCSEL 300 is not arranged so that it is completely surrounded by VCSEL 400, but is arranged at the edge of the array as shown in Figure 3A, is to enable the wiring electrode from VCSEL 300 to be connected to pad 370 without crossing other wiring electrodes. In this case, there is no need to make the wiring multilayer, which is advantageous in terms of the processing process and electrical crosstalk via parasitic capacitance.

[0054] 3B shows a schematic cross-sectional view of VCSEL 300. VCSEL 300 is configured by stacking a lower DBR 302, a semiconductor resonator section 303, an upper DBR 304, and a tunnel junction layer 342 on a GaAs substrate 301 in this order.

[0055] Three quantum well layers 340 are arranged in the cavity section 303. The upper DBR is partially covered with Al 0.98 An insulating oxidized constriction layer 306 is formed by oxidizing GaAs using steam oxidation.

[0056] The resonator section 303, the upper DBR 304, and the tunnel junction layer 342 are processed into a cylindrical mesa shape, and are covered with an insulating film 361. On the insulating film 361, an ITO (Indium Tin Oxide) layer is formed.

[0057] As shown in Figure 3B, an insulating film 361 with a partially removed central portion is provided on the top surface of the mesa-shaped upper DBR 304, and an ITO layer 362 contacts the top surface of the upper DBR 304 through this insulating opening. In this embodiment, the insulating opening in the insulating film 361 is circular. A ring electrode 350 is in electrical contact with part of the ITO 362. The common electrode 351 is in ohmic contact with the back surface of the GaAs substrate 301.

[0058] The lower DBR302 is an Al substrate with an optical thickness of λc / 4. 0.1 GaAs layer and Al 0.9 The GaAs layer is counted as one pair, and 35 pairs are stacked to form the structure. λc is the center wavelength of the high reflection band of the lower DBR 302, which is 940 nm in this embodiment.

[0059] The quantum well layer 340 is an 8 nm thick In 0.1 The GaAs layer is covered with 10 nm of Al 0.1 GaAs In this embodiment, three quantum well layers are arranged in the resonator section 303.

[0060] The upper DBR304 is an Al 0.1 GaAs layer and Al 0.9 The Al layer closest to the quantum well layer 340 of the upper DBR is 0.1 A part of the GaAs layer is covered with a 30 nm thick Al 0.98 GaAs layer This Al has been replaced. 0.98 After the mesa of the VCSEL 300 is formed, the GaAs layer is oxidized by steam oxidation from the mesa sidewalls to a predetermined length from the mesa edge, thereby forming an insulating oxidized constriction layer 306 .

[0061] The tunnel junction layer 342 has a carrier concentration of 5×10 19 cm -3 Over-doped p-type GaAs layer (p-type semiconductor layer) with a carrier concentration of 1×10 19 cm -3 The tunnel junction layer is composed of an n-type GaAs layer (n-type semiconductor layer) doped with a carrier concentration of 1×10 or more. 18 cm -3 Since the p-type layer and n-type layer are in direct contact with each other, the tunnel effect allows current to flow in the reverse direction through a thin depletion layer that is generated at the pn interface.

[0062] The number of pairs is designed so that the lower DBR 302 has a higher reflectance than the upper DBR 304. Furthermore, the insulating film 361 and ITO layer 362 provided on the upper DBR 304 are also transparent at the emission wavelength and transmit light, so that the VCSEL 300 of this embodiment can extract light from the upper DBR 306 side.

[0063] The VCSEL 300 has the same configuration as in Example 1, with an opening in a portion of the insulating film above the mesa, but in this example, a tunnel junction layer 342 is present. The contact region in the VCSEL 300 is formed by an insulating film 361 with an insulating opening provided on the n-type GaAs layer of the tunnel junction layer, and an ITO layer (transparent conductive film) 362 that contacts the upper DBR 304 at the insulating opening portion where the insulating film 361 has been removed. In this example, due to the presence of the tunnel junction layer 342, the preferred diameter d6 of the insulating opening and the diameter d5 of the non-oxidized portion differ from those in Example 1. The effect of this will be explained below.

[0064] The diameter d6 of the insulating opening portion where the insulating film 361 has been removed is 20 μm, and the diameter d5 of the non-oxidized portion inside the oxidized constriction layer 506 is 70 μm. The effect of this will be explained based on the calculation results in FIG. 3D. In FIG. 3D, the current density distribution is calculated when d5 is fixed at 70 μm and d6 is changed. From FIG. 3D, it can be seen that the current density distribution maintains a convex shape at the center until d6 is 20 μm. It can also be seen that current can be injected up to the boundary between the oxidized and non-oxidized portions, that is, up to position 35 μm in FIG. 3D. When d6 is 30 μm or more, the point where the current density is maximum is no longer the center of the non-oxidized portion, that is, position 0 in FIG. 3D. In other words, the convex shape at the center is no longer present. Thus, in this embodiment, compared to Example 1, the top of the mesa By providing the tunnel junction layer 342, a current density distribution that is convex in the center can be achieved even in a larger area.

[0065] FIG. 3C shows a cross-sectional schematic diagram of the VCSEL 400. The layers from the back electrode 451 to the tunnel junction layer 442 are the same as those of the VCSEL 300. As shown in FIG. 3C, the tunnel junction layer 442 is processed into an annular shape. Specifically, the surface of the upper DBR 404 of the VCSEL 400 has an area with a tunnel junction layer and an area without a tunnel junction layer. The annular tunnel junction layer 442 has an inner diameter d3 of 35 μm and an outer diameter d4 of 45 μm. An ITO layer 462 is provided on the upper surface of the tunnel junction layer 442 and on (at least a portion of) the upper surface of the upper DBR 404 where the tunnel junction layer 442 is not provided. A ring electrode 450 is disposed on the ITO layer 462. An insulating film 461 is provided on the mesa sidewall.

[0066] In this embodiment, the tunnel junction layer 342 of the VCSEL 300 is not removed except for the portion in contact with the ITO layer 362, and is disposed over the entire upper surface of the upper DBR 304. On the other hand, in the VCSEL 400, the tunnel junction layer 442 is processed to have an annular shape. Therefore, in the VCSEL 400, the tunnel junction layer 442 does not have the function of spreading the current laterally, and the shape of the unremoved portion of the tunnel junction layer 442 determines the distribution of the current injected into the DBR 404. The current distribution injected into the active layer 440 is determined by the diffusion of the current within the upper DBR 404. In other words, it is the same as the VCSEL 200 of the first embodiment. Therefore, the size of the annular shape of the tunnel junction layer 442 is the same as in the first embodiment, and the shape of the tunnel junction layer 442 does not have the function of spreading the current laterally. The current density distribution injected into layer 440 is also the same.

[0067] The difference between removing and not removing the tunnel junction layer is due to the difference in the degree of lateral current diffusion required to form a desirable current distribution in the same 70 μm diameter non-oxidized portion. VCSEL300 utilizes the high conductivity of the n-type layer that forms tunnel junction layer 342 to achieve the lateral current diffusion effect. On the other hand, VCSEL400 obtains a desirable current injection distribution by not utilizing the conductivity of the n-type layer of tunnel junction layer 462, so the unnecessary portion of tunnel junction layer 442 is processed to form a ring shape.

[0068] The above current diffusion effect can also be achieved by providing the tunnel junction layer 342 of the VCSEL 300 only in a partial region including the insulating opening portion, instead of providing it over the entire top surface of the upper DBR 304. For example, the tunnel junction layer 342 may be formed so that it includes the mesa center and has a diameter larger than d5, and so as to include the entire non-oxidized portion of the oxidized constriction layer 306 in plan view.

[0069] Figure 3E shows the calculated current injection distribution into the active layer when current is injected from a circular region with an inner diameter of 30 μm and an outer diameter of 40 μm. The results show that the ratio of the maximum value near 17 μm in the lateral direction to the minimum value near 31 μm in the lateral direction is 1.65 when the tunnel junction layer 442 is not removed, whereas the ratio is approximately 7.04 times when the circular region is removed. This indicates that a current distribution closer to the oscillation mode with a bimodal lateral intensity distribution is obtained when the circular region is removed, and that the configuration shown in Figure 3C is preferable.

[0070] Figure 3F shows the intensity distribution in the far-field region of light emitted from VCSEL300 and VCSEL400. This is a far-field pattern obtained by roughly estimating the intensity distributions of the zeroth and first-order transverse modes from the half-widths of the current density distributions shown in Figures 3D and 3E. Figure 3G shows intensity distributions superimposed at an intensity ratio based on the number of VCSELs shown in Figure 3A. The intensity ratio between VCSEL300 and VCSEL400 is designed to be 1:3, with the VCSEL400 component being the dominant component. Therefore, in the VCSEL array 20 of this embodiment, more VCSEL400s are arranged.

[0071] 3G shows that by superimposing the beams from VCSEL300 and VCSEL400 at the designed intensity ratio, flattening is achieved mainly in the divergence angle range of -0.5 to +0.5°. Furthermore, comparing the tail portions of the beam shape after superposition shown in FIG. 2D of Example 1, which shows a tail of about ±2° in Example 1 (FIG. 2D), this is reduced to about ±1.5° in this Example (FIG. 3G). Because the flattened width is in the range of ±0.5° in both cases, it can be seen that the shape of this Example is closer to a rectangle.

[0072] Furthermore, in Examples 1 and 2, the range exceeding ±0.5° may be blocked using an optical diaphragm or the like, and only the flattened portion may be extracted and used. In this case, the smaller the width of the skirt in the range exceeding ±0.5° outside the flattened region, the less light is lost due to the shading. In other words, when an optical diaphragm is used, this Example is preferable because it loses less light than Example 1.

[0073] [Third Example] 4A shows the VCSEL array 30 of this embodiment. In this embodiment, a VCSEL 500 is arranged in addition to the VCSEL 300 and VCSEL 400 used in embodiment 2. Since the VCSEL 300 and VCSEL 400 have been explained in embodiment 2, details thereof will be omitted.

[0074] A cross-sectional schematic diagram of VCSEL500 is shown in FIG. 4B. The same components of VCSEL500 as those of VCSEL400 are designated by the same part numbers, and their description will be omitted. The difference from VCSEL400 is that, in addition to the annular tunnel junction layer 442, a tunnel junction layer 542 is disposed on the upper DBR and connected to electrically independent ITO layers 562 and 563. That is, two contact regions, each connected to a different power supply, are disposed on the upper DBR of VCSEL500. The tunnel junction layer 542 is circular and disposed within the inner diameter of the annular tunnel junction layer 442.

[0075] 4C shows a top view of the VCSEL 500. This view focuses on the shape of the tunnel junction layer, and for convenience of explanation, the ITO layer 562 and the top electrode 450 are omitted.

[0076] 4B and 4C show that the tunnel junction layer 442 and the tunnel junction layer 542 are electrically independent. The tunnel junction layer 442 has a circular shape with a cutout, and injecting current through it produces a bimodal current density distribution similar to that of the VCSEL 400. Meanwhile, the tunnel junction layer 542 has a circular shape similar to that of the VCSEL 100, producing a unimodal current density distribution. Therefore, controlling the ratio of currents from these two tunnel junction layers makes it possible to control the FFP. The center of the tunnel junction layer 542 (circular) coincides with the center of the non-oxidized portion of the oxidized constriction layer 406 (a portion with high conductivity through which current can flow). The contact region of the tunnel junction layer 542 includes the center of the non-oxidized portion in a planar view and is included within the entire non-oxidized portion. The center of the tunnel junction layer 442 (circular) also coincides with the center of the non-oxidized portion and is included within the entire non-oxidized portion in a planar view. Furthermore, the tunnel junction layer 442 and the tunnel junction layer 542 are spaced apart from each other, the tunnel junction layer 542 is included inside (inner diameter portion of) the annular tunnel junction layer 442 , and the tunnel junction layer 442 surrounds the tunnel junction layer 542 .

[0077] The arrangement of each VCSEL in the VCSEL array 30 will be further described with reference to FIG. 4A.

[0078] The ring electrodes 350 on the VCSEL 300 are electrically connected to each other via wiring electrodes 372, and are also electrically connected to wire bonding pads 370 for supplying current from the outside. The ring electrodes 450 on the VCSEL 400 are electrically connected to each other via wiring electrodes 472, and are also electrically connected to wire bonding pads 470 for supplying current from the outside. The two ring electrodes 450 and electrode 563 of the VCSEL 500 are connected to each other via wiring electrodes 572 and 573, respectively, and are also connected to pads 580 and 581.

[0079] In this embodiment, the configuration shown in FIG. 4A is employed in order to reduce electrical crosstalk without using multiple layers of wiring, but configurations other than the above may also be employed.

[0080] In this embodiment, the advantageous effects of including the VCSEL 500 will be described. In this embodiment, when the balance of the optical outputs from the VCSEL 300 and the VCSEL 400 is lost due to driving conditions including the ambient temperature, changes over time, or the like, the FPP from the VCSEL 500 can be controlled to correct the FPP shape of the entire array to a desirable shape. To control the FPP of the VCSEL 500, it is sufficient to control the current injected into the two tunnel junction layers 442 and 542 of the CSEL 500, as described above.

[0081] According to this embodiment, the FFP can be corrected by the VCSEL 500, which contributes to improving the reliability of the ToF system, for example, when the amount of light emitted by either the VCSEL 300 or the VCSEL 400 is reduced due to a malfunction.

[0082] If either VCSEL300 or VCSEL400 fails, reducing the optical output from the array and degrading the flatness of the FFP, the FPP shape can be corrected as described above. Specifically, by controlling the current injected through ITO layers 562 and 563 connected to VCSEL500, the FFP and optical output can be restored to within the specified range for the ToF system. Therefore, the number of VCSELs is designed to create an array configuration that can obtain the optical output required for the ToF system without driving VCSEL500 at its maximum rated current. Then, in the event of a failure, increasing the current injected into VCSEL500 restores both the flatness of the FFP and the optical output, allowing the ToF system to maintain the same characteristics as before the failure.

[0083] Regarding the flatness of the FFP, in the ToF system, based on the image captured on the imaging side, it is possible to detect abnormalities in the FFP on the light source side from the commonly contained shading information from the shading of images captured of multiple different shooting targets.In addition, when checking during inspections rather than in actual use, corrections can be made using images captured by illuminating a flat surface with a constant reflectance.

[0084] In this embodiment, VCSEL300, VCSEL400, and VCSEL500 are arranged in a single array, and the beams from VCSEL300 and VCSEL400 are used as a base for correction by VCSEL500. On the other hand, as a modified example, even an array consisting of only VCSEL500 can achieve the effect of favorable FFP control. This configuration requires a larger number of wiring electrodes than the present embodiment shown in FIG. 4A, making the configuration more complex. Depending on the arrangement of the VCSEL500 within the array, multi-layer wiring may be required. However, an advantage of using only VCSEL500 is that the illumination light distribution can be made symmetrical even in areas closer to the far-field region. Specifically, in this embodiment, different types of VCSELs are arranged in a concentrated region within the array. Therefore, when irradiating an object closer than the far-field region with light, the illumination light distribution reflecting the VCSEL arrangement within the array becomes asymmetric in intensity. This phenomenon becomes more pronounced as the distance from the far-field region approaches the near-field region. On the other hand, when only VCSEL500 is used, the array arrangement is uniform, so although the intensity distribution of the illumination light changes as it approaches the near-field region from the far-field region, there is an advantage in that symmetry is maintained.

[0085] The far-field and near-field regions mentioned above include not only the region defined by the beam emitted from the VCSEL, but also the near-field region of the beam after it has been transformed by an optical system such as a lens in a ToF system, etc. The length of the near-field region after transformation by the optical system is often longer than the length of the near-field region defined by the beam characteristics immediately after it is emitted from the VCSEL, and depending on the design of the optical system, symmetry in this near-field region may be important.

[0086] Furthermore, in the above embodiment, the ITO layer (transparent conductive film) 563 is used for the tunnel junction layer 542 of the VCSEL 500, but instead of the transparent conductive film, wiring made of a metal material may be used.

[0087] 4D shows a top view of the VCSEL 500 according to this modification. As described above, the metal wiring 564 is used for connection to the tunnel junction layer 542. However, an ITO layer (transparent conductive film) 566 is provided on the upper surface of the tunnel junction layer 542, and the metal wiring 564 and the ITO layer 566 are electrically connected.

[0088] In this modification, since the light extraction efficiency is reduced due to light blocking by the metal wiring 564, an insulating film 565 is provided below the metal wiring 564. The optical film thickness of the insulating film 565 is λc / 4. This reduces the reflectance below the metal wiring 564, preventing laser oscillation and reducing the reduction in light extraction efficiency due to light blocking by the metal wiring 564.

[0089] [Fourth Example] FIG. 5A shows a VCSEL array 40 using VCSELs 600 and 700 according to this embodiment. Wiring electrodes and contact region shapes are omitted from FIG. 5A. In this embodiment, the VCSEL 600, which emits single-peak FFP laser light, and the VCSEL 700, which emits bi-peak FFP laser light, are approximately the same size, with each having an emission diameter of approximately 70 μm. The emission diameter and the arrangement of the VCSELs within the VCSEL array are similar to those in Example 2, but the VCSELs of this embodiment differ from Example 2 in that they emit light from the back surface of the GaAs substrate, as will be described in the explanations of FIGS. 5B and 5C below.

[0090] 5B shows a schematic cross-sectional view of the VCSEL 600. The VCSEL 600 is configured by stacking a lower DBR 602, a semiconductor resonator section 603, an upper DBR 604, and a tunnel junction layer 642 on a GaAs substrate 601.

[0091] Three quantum well layers 640 are arranged in the cavity section 603. The upper DBR is partially covered with Al 0.98 An oxidized constriction layer 606 having insulating properties is formed by oxidizing GaAs by steam oxidation.

[0092] The resonator portion 603, upper DBR 604, and tunnel junction layer 642 are processed into a cylindrical mesa shape, and are covered from above with an insulating film 661. As shown in FIG. 5B, the insulating film 661 has a central portion partially removed to provide an insulating opening. An upper electrode 650 is formed on the insulating film 661, covering the mesa-shaped semiconductor resonator portion 603, upper DBR 604, insulating film 661, and the insulating opening. The upper electrode 650 is made of a metal material. The insulating opening is circular, and the upper electrode 650 is in electrical contact with the tunnel junction layer 642. The common electrode 651 is in ohmic contact with the back surface of the GaAs substrate 601, and the light-emitting portion has a circular opening removed.

[0093] The lower DBR602 is an Al substrate with an optical thickness of λc / 4. 0.1 GaAs layer and Al 0.9 The quantum well layer 640 is made up of 24 pairs of GaAs layers stacked together. λc is the center wavelength of the high reflection band of the lower DBR 602, which is 940 nm in this embodiment. 0.1 The GaAs layer is covered with 10 nm of Al 0.1 The structure is sandwiched between GaAs barrier layers. In this embodiment, three quantum well layers are arranged in the resonator section 603.

[0094] The upper DBR604 is an Al with an optical thickness of λc / 4. 0.1 GaAs layer and Al 0.9 The structure is composed of 40 pairs of GaAs layers stacked together. 0.1 G A part of the aAs layer has a thickness of 50 nm and a carrier concentration of 1×10 19 cm -3 GaAs contact The Al layer closest to the quantum well layer (active layer) 640 of the upper DBR is replaced with a new Al layer, improving electrical contact with the upper electrode 650. 0.1 A part of the GaAs layer is 3 0nm Al 0.98 The Al layer is replaced by a GaAs layer. 0.98 After forming the mesa of the VCSEL 600, the GaAs layer is oxidized by steam oxidation from the mesa sidewall to a predetermined length from the mesa edge, forming an insulating oxidized confinement layer 606. The tunnel junction layer 642 has a carrier concentration of 5×10 19 cm -3 A heavily doped p-type GaAs layer and a carrier A concentration 1 x 10 19 cm -3 It consists of a heavily doped n-type GaAs layer.

[0095] The number of pairs in the upper DBR 604 is designed so that the reflectivity is higher than that of the lower DBR 602, and the VCSEL 600 of this embodiment can extract light from the rear surface side of the substrate.

[0096] The effect of the tunnel junction layer 642 in this embodiment and the relationship between the preferred insulating aperture diameter and the diameter of the non-oxidized portion are similar to those of the VCSEL 300 in the second embodiment, and therefore a description thereof will be omitted.

[0097] FIG. 5C shows a schematic cross-sectional view of the VCSEL 700. The layers from the back electrode 751 to the tunnel junction layer 742 are the same as those of the VCSEL 600. As shown in FIG. 5C, the tunnel junction layer 742 is annularly processed on the outermost surface of the upper DBR 704. An insulating film 761 is provided on the mesa sidewall. The inner diameter d3 of the annular tunnel junction layer 742 is 35 μm, and the outer diameter d4 is 45 μm. A surface electrode 750 covers the upper DBR 704, the insulating film 761, and the tunnel junction layer 742. The surface electrode 750 is in direct contact with the DBR 704, but current mainly flows through the annularly processed tunnel junction layer 742. This is because the surface electrode 750 is made of an electrode material that can make ohmic contact with the n-type GaAs layer and forms a Schottky contact with the DBR 704.

[0098] The number of pairs in the upper DBR 704 is designed so that the reflectivity is higher than that of the lower DBR 702, and the VCSEL 700 of this embodiment can extract light from the rear surface side of the substrate.

[0099] In the VCSEL 700, the effect of current spreading via the tunnel junction layer 742 is the same as in the VCSEL 400 of the second embodiment, and therefore a description thereof will be omitted here.

[0100] [Fifth Example] FIG. 6 shows a laser image detection and ranging (LiDAR) device that uses the VCSEL array (surface-emitting laser array) 20 described in the second embodiment as a light source.

[0101] As shown in FIG. 6, the distance measuring device 1000 is composed of an overall control unit 1010, a VCSEL array driver 1020, a VCSEL array 20, an emission-side optical system 1040, a reception-side optical system 1060, a light-receiving image sensor 1070, and a distance data processing unit 1080.

[0102] In this embodiment, the VCSEL array described in the second embodiment is used, but the present invention is not limited to this, and the VCSEL arrays described in the other embodiments may also be used.

[0103] In FIG. 6, the light-emitting optical system 1040 and the light-receiving optical system 1060 are each a single convex lens-shaped member. However, it is not composed of only one convex lens system, but of multiple lenses. The light-receiving image sensor 1070 is an image sensor in which optical sensors capable of detecting the timing of light reception are arranged in a two-dimensional array.

[0104] The operation of the distance measuring device 1000 is outlined below. First, a drive signal is output from the overall control unit 1010 to the surface-emitting laser array driver 1020. In response to the drive signal, the surface-emitting laser array driver 1020 injects a predetermined current value into the surface-emitting laser array 1030, causing the surface-emitting laser array 1030 to oscillate. Laser light generated by the surface-emitting laser array 1030 passes through the light-emitting side optical system 1040 and strikes the measurement object 1200, and the light reflected by the measurement object 1200 passes through the light-receiving side optical system 1060 and enters the light-receiving image sensor 1070. The distance data processing unit 1080 only needs to be electrically connected to the light-receiving image sensor 1070. Therefore, the distance data processing unit 1080 may be disposed in the same package as the light-receiving image sensor 1070, or may be mounted in a separate package and electrically connected via a circuit board or the like.

[0105] The electrical signal pulses output from each pixel of the light-receiving image sensor 1070 are input to a distance data processing unit 1080. The distance data processing unit 1080 calculates distance information in the light propagation direction from the time (detection timing) of the electrical signal pulses output from each pixel of the light-receiving image sensor 1070 and the light emission timing of the surface-emitting laser array driver 1020, and generates and outputs three-dimensional information.

[0106] In this way, the distance measuring device 1000 can output three-dimensional information.

[0107] The distance measuring device 1000 can be applied to the automotive field, such as control to prevent collisions with other vehicles and automatic driving control to follow other vehicles. Furthermore, it can be used in moving objects (moving devices) such as ships, aircraft, and industrial robots, and in moving object detection systems. Furthermore, it can be widely applied to devices that use three-dimensional recognition of objects, including distance information.

[0108] The uses of 3D information are not limited to those mentioned above. For example, distance information may be used in image processing. When acquiring an image of real space and superimposing a virtual object on it, using 3D information of the real space allows the virtual object to be displayed seamlessly on the real world. In addition, by acquiring 3D information when acquiring an image, it is possible to correct the blurring effect based on the 3D information after shooting. [Explanation of symbols]

[0109] 100,200:VCSEL 101, 201: GaAs substrate (semiconductor substrate) 102, 202: Lower DBR (first reflector) 103, 203: Semiconductor resonator section 104.204: Upper DBR (secondary reflector)

Claims

1. A light source device comprising a plurality of semiconductor light emitting elements, each of which has a first reflecting mirror, a resonator portion including an active layer, and a second reflecting mirror stacked in this order on a semiconductor substrate, each of the plurality of semiconductor light-emitting elements has an electrical contact region on a surface of the second reflector opposite to the active layer, the electrical contact region being for supplying carriers to the active layer; the plurality of semiconductor light emitting elements include a first semiconductor light emitting element in which the shape of the contact region is a first shape, and a second semiconductor light emitting element in which the shape of the contact region is a second shape different from the first shape; each of the plurality of semiconductor light-emitting elements has a current confinement portion having an annular low-conductivity region and a high-conductivity region inside the annular low-conductivity region, in at least one of the first reflecting mirror, the resonator portion, and the second reflecting mirror; In a plan view, the contact region of the first semiconductor light emitting element overlaps with the center of gravity of the light emitting region defined by the current confinement portion. A light source device characterized by:

2. the first shape is circular; the second shape is annular; The light source device according to claim 1 .

3. the contact region is included in a highly conductive region of the current confinement portion in plan view.

3. The light source device according to claim 1.

4. a center of the first shape and a center of the second shape coincide with a center of a highly conductive region of the current confinement portion in a plan view; The light source device according to claim 1 .

5. In at least one of the plurality of semiconductor light emitting elements, The contact region is composed of an insulating film provided on the second reflecting mirror, a portion of which has been removed, and a conductive film that is in contact with the second reflecting mirror at the portion where the insulating film has been removed. It is being The light source device according to claim 1 .

6. In at least one of the plurality of semiconductor light emitting elements, a tunnel junction layer including an n-type semiconductor layer is provided on a surface of the second reflector opposite to a surface in contact with the active layer, the contact region is composed of an insulating film provided on the n-type semiconductor layer, a portion of which has been removed, and a conductive film in contact with the n-type semiconductor layer at the portion where the insulating film has been removed. The light source device according to claim 1 .

7. The tunnel junction layer has a carrier concentration of 1×10 １９ cm -３ The above p-type layer and n-type layer are directly Consists of contact, The light source device according to claim 6 .

8. In at least one of the plurality of semiconductor light emitting elements, the surface of the second reflector has a region where an n-type semiconductor layer and a tunnel junction layer are provided and a region where they are not provided; a conductive film is provided in the region where the tunnel junction layer is provided and in at least a part of the region where the tunnel junction layer is not provided; The light source device according to claim 1 .

9. the plurality of semiconductor light emitting elements include a third semiconductor light emitting element having a first contact region and a second contact region on the surface of the second reflector, the first contact region and the second contact region being connected to different power sources; The light source device according to claim 1 .

10. the first contact region is a region including the center of the second reflector, the second contact region is a region spaced apart from the first contact region and surrounding the first contact region; The light source device according to claim 9 .

11. Each of the plurality of semiconductor light emitting elements is the reflectance of the first reflecting mirror is higher than the reflectance of the second reflecting mirror; a transparent conductive film is provided on the front surface side of the second reflecting mirror, The light is emitted from the front surface side of the second reflecting mirror. The light source device according to claim 1 .

12. Each of the plurality of semiconductor light emitting elements is the reflectance of the first reflector is lower than the reflectance of the second reflector; emitting light through the semiconductor substrate; The light source device according to claim 1 .

13. The light source device according to any one of claims 1 to 12; a sensor for detecting reflected light of light emitted from the light source device; a processing unit that acquires distance information based on the detection timing of the reflected light; A distance measuring device comprising:

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