Photoelectric conversion device, photoelectric conversion system, and mobile body

Abstract

To provide a laminated photoelectric conversion apparatus that prevents an excess charge from being mixed in an OB region and detects black level reference signals more accurately.SOLUTION: Included are a first substrate having a first semiconductor device layer including a plurality of photoelectric conversion units and a well in which the plurality of photoelectric conversion units is disposed; and a second substrate having a second semiconductor device layer including a circuit configured to process signals obtained by the plurality of photoelectric conversion units. The first and second substrates are laminated together. The first semiconductor device layer includes an effective pixel region, an OB pixel region provided between the effective pixel region and an end of the first semiconductor device layer, and an outer periphery region disposed between the OB pixel region and the end of the first semiconductor device layer. In a planar view, a light-blocking region formed by a light-blocking layer overlaps the OB pixel region, and the light-blocking region does not overlap the outer periphery region. The outer periphery region has a charge draining region including a semiconductor region of the same conductivity type as a signal charge. A fixed potential is supplied to the charge draining region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, a photoelectric conversion system, and a mobile object. [Background technology]

[0002] A photoelectric conversion device is known that has an effective pixel area including a plurality of pixels and a light-shielded optical black (OB) area arranged around the effective pixel area. Patent Document 1 discloses a back-illuminated photoelectric conversion device in which light is irradiated from the surface of a semiconductor substrate opposite to the surface on which a wiring layer is arranged. Patent Document 1 discloses a charge-discharging pixel that discharges signal charges leaking from the effective pixel area between the effective pixel area and the OB area, or between the effective pixel area and the OB area. The signal charges leaking from the effective pixel area are then forcibly discharged. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-97418 Summary of the Invention [Problem to be solved by the invention]

[0004] Although Patent Document 1 considers excess charge that mixes into the OB region from the effective pixel region, it does not consider excess charge that mixes into the OB region from the periphery of the OB region. In other words, when OB pixels are arranged at the edge of the substrate as in Patent Document 1, if signal charge generated around the OB region mixes into the OB region, the black level reference signal fluctuates, so it is necessary to suppress the mixing of excess charge into the OB region. In particular, in the case of a stacked-type photoelectric conversion device, there is no need to arrange a signal processing circuit that processes signals output from the pixels around the OB region, which makes the effect of the present invention more pronounced.

[0005] An object of the present invention is to provide a stacked photoelectric conversion device that can suppress the intrusion of excess charge into the OB region and more accurately detect the black level reference signal. [Means for solving the problem]

[0006] A photoelectric conversion device comprising: a first substrate having a first semiconductor element layer including a plurality of photoelectric conversion units and wells in which the plurality of photoelectric conversion units are arranged; and a second substrate having a second semiconductor element layer including a circuit for processing signals obtained by the plurality of photoelectric conversion units, wherein the first substrate and the second substrate are stacked, and the first semiconductor element layer includes an effective pixel area having a portion of the plurality of photoelectric conversion units, an optical black pixel area provided between the effective pixel area and an end of the first semiconductor element layer and having a portion of the plurality of photoelectric conversion units, and and a peripheral region disposed between the optical black pixel region and an end of the first semiconductor element layer, wherein, in a planar view, the optical black pixel region is overlapped by a light-shielding region formed of a light-shielding layer, and in the peripheral region, a pad portion that conducts electricity between the photoelectric conversion device and the outside is disposed with a gap between it and the light-shielding region in a planar view, and a charge discharge region is disposed in the peripheral region between the pad portion and the well, and the charge discharge region includes a semiconductor region of the same conductivity type as the signal charge, and a fixed potential is supplied to the charge discharge region. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a stacked photoelectric conversion device that can suppress the intrusion of excess charge into the OB region and more accurately detect the reference signal for the black level. [Brief explanation of the drawings]

[0008] [Figure 1] 2A to 2C are schematic diagrams illustrating semiconductor substrates of the photoelectric conversion device according to the first embodiment. [Figure 2] 1 is a schematic top view of a semiconductor substrate according to a first embodiment. [Figure 3]Schematic cross-sectional view taken along the line X-X' in FIG. 2. [Figure 4] FIG. 10 is a schematic top view of a semiconductor substrate according to a second embodiment. [Figure 5] Schematic cross-sectional view taken along line X-X' in FIG. 4. [Figure 6] FIG. 11 is a schematic top view of a semiconductor substrate according to a third embodiment. [Figure 7] 7 is a schematic cross-sectional view taken along the line X-X' in FIG. 6. [Figure 8] FIG. 10 is a schematic cross-sectional view of a photoelectric conversion device according to a fourth embodiment. [Figure 9] FIG. 10 is a schematic cross-sectional view of a photoelectric conversion device according to a fifth embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view of a photoelectric conversion device according to a sixth embodiment. [Figure 11] FIG. 13 is a schematic plan view of a light-shielding layer of a photoelectric conversion device according to a sixth embodiment. [Figure 12] FIG. 13 is a schematic plan view of another example of the light-shielding layer of the photoelectric conversion device according to the sixth embodiment. [Figure 13] FIG. 13 is a block diagram of a photoelectric conversion system according to a seventh embodiment. [Figure 14] FIG. 13 is a block diagram of a photoelectric conversion system according to an eighth embodiment. [Figure 15] 13 is a flowchart of a photoelectric conversion system according to the eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0010] In the following description, a semiconductor region of a first conductivity type in which carriers of the same conductivity type as the signal charge are the majority carriers is an N-type semiconductor region, and a semiconductor region of a second conductivity type is a P-type semiconductor region. Note that the present invention also applies when the signal charge is a hole. In this case, a semiconductor region of a first conductivity type in which carriers of the same conductivity type as the signal charge are the majority carriers is a P-type semiconductor region, and a semiconductor region of a second conductivity type is an N-type semiconductor region.

[0011] In this specification and claims, when the term "impurity concentration" is used simply, it means the net impurity concentration compensated by impurities of the opposite conductivity type. In other words, "impurity concentration" refers to the NET doping concentration. A region where the P-type doping concentration is higher than the N-type doping concentration is a P-type semiconductor region. Conversely, a region where the N-type doping concentration is higher than the P-type doping concentration is an N-type semiconductor region.

[0012] In this specification, "planar view" refers to a view from a direction perpendicular to the light incident surface of a semiconductor substrate, which will be described later. Furthermore, a cross section refers to a surface in a direction perpendicular to the light incident surface of the semiconductor substrate. Note that, when the light incident surface of the semiconductor substrate is rough when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor substrate when viewed macroscopically.

[0013] In this specification, the depth direction is the direction from the light incident surface (first surface) of the semiconductor substrate toward the surface (second surface) on which the transistor is disposed.

[0014] (Embodiment 1) 1 shows a photoelectric conversion device 500 according to a first embodiment. The photoelectric conversion device is a semiconductor device IC. The photoelectric conversion device 500 according to this embodiment can be used as, for example, an image sensor, a photometric sensor, or a distance measuring sensor.

[0015] The photoelectric conversion device 500 is a stacked photoelectric conversion device in which all or part of the substrate 1 and the substrate 2 are stacked and bonded. The substrates 1 and 2 may be in the form of chips obtained by dicing a wafer after stacking, or may be in the form of a wafer. The photoelectric conversion device 500 is a stacked back-illuminated photoelectric conversion device.

[0016] The substrate 1 has a semiconductor element layer 11 (first semiconductor element layer) including pixel circuits included in the pixels 10, and a wiring structure 12 (first wiring structure). In this specification, the "semiconductor element layer" does not only refer to a semiconductor layer, but also includes a semiconductor layer and a gate of a transistor formed in the semiconductor layer. The wiring layer of the wiring structure is not included in the "semiconductor element layer". The substrate 2 has a wiring structure 24 (second wiring structure) and a semiconductor element layer 23 (second semiconductor element layer) including an electric circuit. As will be described later, the wiring structure 12 of the substrate 1 and the wiring structure 24 of the substrate 2 are joined by a metal junction formed by joining the wiring layers included in each wiring structure. The metal junction is a structure in which metals constituting the wiring layer and metals constituting the wiring layer are directly joined.

[0017] As will be described in detail later, elements constituting the pixel 10 are arranged in the semiconductor element layer 11. Note that a portion of the configuration of the pixel 10 may be arranged in the semiconductor element layer 11, and another portion may be arranged in the semiconductor element layer. In this case, the pixel circuit configuration arranged in the semiconductor element layer 11 of the pixel 10 may include a photoelectric conversion element such as a photodiode. The pixel circuits including the photoelectric conversion elements are arranged in a two-dimensional array in a planar view in the semiconductor element layer 11. The semiconductor element layer 11 has a pixel region in which a plurality of pixel circuits are arranged in a two-dimensional array. In FIG. 1, a plurality of photoelectric conversion elements constituting a plurality of pixel circuits are arranged in a two-dimensional array in the row and column directions in the semiconductor element layer 11.

[0018] The wiring structure 12 includes M (M is an integer of 1 or more) wiring layers and interlayer insulating materials. The wiring structure 24 includes N (N is an integer of 1 or more) wiring layers and interlayer insulating materials.

[0019] The semiconductor element layer 23 includes an electric circuit that processes signals obtained by a photoelectric conversion unit disposed in the semiconductor element layer 11. For convenience of explanation, the configuration illustrated on the upper surface of the substrate 2 in FIG. 1 is the configuration disposed in the semiconductor element layer 23. The electric circuit is, for example, any one of transistors that constitute the row scanning circuit 20, the column scanning circuit 21, the signal processing circuit 22, etc. shown in FIG. 1. The signal processing circuit 22 is, for example, at least one of a part of the configuration of the pixel 10, such as an amplification transistor, a selection transistor, or a reset transistor, an amplification circuit, a selection circuit, a logic operation circuit, an AD conversion circuit, a memory, or a circuit that performs compression processing, synthesis processing, etc.

[0020] A pixel 10 may refer to the smallest unit of a circuit that is repeatedly arranged to form an image. The pixel circuit included in the pixel 10 and disposed in the semiconductor element layer 11 may include at least a photoelectric conversion element. The pixel circuit may also include components other than the photoelectric conversion element. For example, the pixel circuit may further include at least one of a transfer transistor, a FD, a reset transistor, an amplification transistor, a capacitance-addition transistor, and a selection transistor. Typically, a pixel 10 is configured by a selection transistor and a group of elements connected to a signal line via the selection transistor. In other words, the selection transistor may be the outer edge of the pixel circuit. Alternatively, a pixel 10 may be configured by a combination of a photoelectric conversion element and a transfer transistor. Alternatively, a pixel 10 may be configured by a combination of one or more photoelectric conversion elements and one amplification circuit or one AD conversion circuit.

[0021] FIG. 2 is a schematic top view of an end portion of the semiconductor element layer 11 in the first embodiment. The pixel region of the semiconductor element layer 11 includes an effective pixel region 100, which includes effective pixels that use incident signal charges as signals, and an optical black pixel region 101, which includes optical black pixels (OB pixels) that detect a reference value for the black level. The OB pixel region 101 is disposed around the effective pixel region 100 in a planar view and includes a light-shielding layer 13 that blocks light from entering the photoelectric conversion units in the OB pixel region 101. In other words, a light-shielding region formed by a light-shielding layer overlaps the OB pixel region in a planar view. The "surrounding" does not necessarily mean the entire periphery; it may be at least one of the top, bottom, left, and right sides of the effective pixel region 100. Hereinafter, the term "surrounding" also includes regions that do not completely block the periphery, unless otherwise specified. Furthermore, "light-shielding" is not limited to blocking 100% of light. For example, it refers to blocking 50% or more of light.

[0022] A well region 14 and a peripheral region 15 located around the well region 14 are arranged inside the semiconductor element layer 11. In a plan view, the peripheral region 15 does not overlap with the light-shielding region formed by the light-shielding layer 13. In this embodiment, the peripheral region 15 and the light-shielding region do not completely overlap in a plan view, but they may partially overlap as in embodiments described later. At least a portion of the pixel 10 is formed in the well region 14. A pad portion 16 is provided in the peripheral region 15.

[0023] The pad portion 16 is disposed between the edge of the semiconductor element layer 11 and the well region 14. In a plan view, the shortest distance L1 between the semiconductor element layer 11 and the light-shielding layer 13 is, for example, 100 μm or more and 250 μm or less, and preferably 100 μm or more and 150 μm or less. Furthermore, in a plan view, the shortest distance L2 between the center of the pad portion 16 and the light-shielding layer 13 is, for example, 30 μm or more and 200 μm or less, and preferably 50 μm or more and 100 μm or less. A distance of at least a predetermined distance is required to avoid defects due to manufacturing errors during pad formation. On the other hand, a distance of at most a predetermined distance is preferable to increase the area of ​​the effective pixel region 100 without increasing the area of ​​the semiconductor element layer 11. The center of the pad portion 16 refers to the center of the pad trench. As will be described in detail later, the closer the distance between the center of the pad portion 16 and the OB pixel region 101, the more pronounced the effect of this embodiment becomes. The shortest distance L3 between the center of the pad portion 16 and the pixel 10 of the OB pixel region 101 is, for example, 100 μm or more and 500 μm or less, and preferably 250 μm or more and 350 μm or less.

[0024] 3 shows a schematic cross-sectional view of the X-X' cross section in FIG. 2. Substrate 1 and substrate 2 are laminated by being bonded together at bonding surface 3. Wiring structure 12 of substrate 1 and wiring structure 24 of substrate 2 are located between semiconductor element layer 11 of substrate 1 and semiconductor element layer 23 of substrate 2. In FIG. 3, wiring structure 12 has three wiring layers, 121, 122, and 123, and wiring structure 24 has three wiring layers, 241, 242, and 243.

[0025] The wiring structure 12 has three wiring layers: wiring layers 121, 122, and 123. The wiring layers 121, 122, and 123 may be, for example, Cu wiring layers. In FIG. 3, the wiring layer 123 constitutes the metal portion 31 of the metal junction 30. The metal junction 30 is embedded in a recess formed in an interlayer insulating film and has a damascene structure.

[0026] The wiring structure 24 has three wiring layers: wiring layers 241, 242, and 243. The wiring layers 241, 242, and 243 can be Cu wiring layers. In FIG. 3, the wiring layer 243 forms the metal portion 32 of the metal junction 30. The metal portion 32 is embedded in a recess formed in an interlayer insulating film and has a damascene structure.

[0027] An interlayer insulating film having a recess in which metal portion 31 is buried, an interlayer insulating film having a recess in which metal portion 32 is buried, and metal portions 31 and 32 are bonded (contacted) to each other. Metal portion 31 and metal portion 32 are bonded to each other to form metal junction 30.

[0028] Here, via plugs 124 formed in the interlayer insulating film of wiring layer 123 provide electrical conductivity between metal portion 31 and wiring layer 122. Via plugs 244 formed in the interlayer insulating film of wiring layer 243 provide electrical conductivity between metal portion 32 and wiring layer 242. Electrical connection is made between semiconductor element layer 11 and semiconductor element layer 23 at metal junctions 30 where via plugs 124 and 244 are connected.

[0029] For example, wiring layer 123 includes wiring pattern 123a connected to the wiring pattern of the wiring layer above it, and wiring pattern 123b not connected to the wiring pattern of the upper layer. Also, wiring layer 243 includes wiring pattern 243a connected to the wiring pattern of the lower layer, and wiring pattern 243b not connected to the wiring pattern of the lower layer. For example, in FIG. 3, wiring pattern 123a is connected to the wiring pattern of the upper layer through via plug 124. Also, wiring pattern 243a is connected to the wiring pattern of the lower layer through via plug 244. Note that via plugs are not required, and the wiring patterns may be connected by directly contacting the wiring patterns of the upper or lower layers.

[0030] 3, the wiring patterns 123a, 243a electrically connect the semiconductor element layer 11 and the semiconductor element layer 23. Note that it is not necessary for all of the wiring patterns 123a, 243a to connect the semiconductor element layer 11 and the semiconductor element layer 23, and some of the wiring patterns 123a, 243a may be connected to the semiconductor element layer 11 or the semiconductor element layer 23. Also, some of the wiring patterns 123a, 243a may be connected to either of the wiring layers and may not be connected to either the semiconductor element layer 11 or the semiconductor element layer 23.

[0031] 3, the semiconductor element layer 11 has a well region 14 in which a well 19 is arranged, and a peripheral region 15 located between the edge of the semiconductor element layer 11 and the well region 14. The well 19 is, for example, a region into which P-type impurities are ion-implanted, and the peripheral region 15 is a region in which the well 19 is not arranged. The peripheral region 15 is an N-type semiconductor region or a region having a lower P-type impurity concentration than the well 19.

[0032] In the well 19, a plurality of photoelectric conversion units in the effective pixel region 100 and a plurality of photoelectric conversion units in the OB pixel region 101 are arranged. The effective pixel region 100 and the OB pixel region 101 are arranged in the well region 14. In the OB pixel region 101, a light-shielding layer 13 is arranged on the light incident surface side of the semiconductor element layer 11. The light-shielding layer is arranged on the light incident surface of the semiconductor element layer 11, for example, via an insulating material. A microlens is arranged on the light incident surface side of the semiconductor element layer 11, via an insulating material. In addition, in FIG. 5, a color filter is arranged between the microlens and the insulating material. The arrangement of the color filter can be selected appropriately. For example, a Bayer array may be used. Furthermore, multiple photoelectric conversion units may be arranged per microlens. In FIG. 3, a microlens is also arranged in the OB pixel region 101, but the microlens is not essential. A configuration in which a microlens is not arranged at a position overlapping the light-shielding layer 13 in a planar view may be adopted. 3, the light-shielding layer 13 may be disposed between a pixel 10 and an adjacent pixel 10 in a plan view in the effective pixel region 100. This makes it possible to reduce crosstalk between pixels in the effective pixel region 100.

[0033] Pad sections 16 are arranged in the peripheral region 15. As shown in Fig. 2, a plurality of pad sections 16 are arranged in the peripheral region 15. The plurality of pad sections 16 conduct electricity between the photoelectric conversion device 500 and a signal processing device or the like arranged outside the photoelectric conversion device. The plurality of pad sections 16 include a pad section that outputs a signal from the photoelectric conversion device 500 to the outside and a pad section that inputs a power supply voltage or the like to the photoelectric conversion device 500.

[0034] 3, a trench that becomes a pad portion 16 is formed at an end of the semiconductor element layer 11. The trench is formed in the depth direction from the light incident surface of the semiconductor element layer 11 to a depth that reaches the wiring pattern of the wiring layer 242 of the substrate 2. The pad portion 16 is electrically connected to the wiring layer 242 formed on the substrate 2 by wire bonding.

[0035] The wiring layer 242 can be an Al wiring layer. Note that the entire wiring layer 242 does not need to be made of Al, and only the wiring to which the pad portion 16 is connected may be made of Al wiring, with the other wiring being made of Cu wiring. Here, an example of wire bonding is shown, but a through-silicon via (TSV) in which a trench is filled with metal may also be used.

[0036] The trench of the pad portion 16 may be formed to a depth that reaches the wiring layer of the substrate 1.

[0037] As described above, the pad portion 16 requires the formation of a trench, making it impossible to provide the light-shielding layer 13 too close. In a back-illuminated photoelectric conversion device, the thickness (length in the depth direction) of the semiconductor element layer 11 tends to be smaller than that of a front-illuminated photoelectric conversion device. For example, the thickness of the semiconductor element layer 11 is 11 μm or less. Therefore, there is a high possibility that long-wavelength light, such as infrared light, incident from the light incident surface of the semiconductor element layer 11 is reflected by the surface on which the transistors are formed, resulting in the generation of excess charge. In particular, in a stacked back-illuminated photoelectric conversion device configuration in which peripheral circuits such as scanning circuits and signal processing circuits are not mounted on the substrate 1, as shown in FIG. 3, the distance between the edge of the substrate and the OB pixel region 101 is short. In other words, in a stacked back-illuminated photoelectric conversion device configuration, no circuit elements are disposed between the pad portion 16 and the well 19. Therefore, when light is incident on a non-light-shielded region, such as a part of the well region 14 or the peripheral region 15, photoelectric conversion may occur, generating charge. If excess charge generated in the non-shaded region is mixed into the OB pixel region 101 via the well region 14, the detection of the black level reference value becomes inaccurate, and the pixel values ​​of the effective pixel region cannot be corrected correctly.

[0038] In this embodiment, a drain section 17 that discharges excess charge is provided in the peripheral region 15. The drain section 17 functions as a charge discharge region that discharges excess charge. A semiconductor region 171 of the same conductivity type as the peripheral region 15 is disposed in the drain section 17. The semiconductor region 171 can be formed by ion implantation of impurities of the same conductivity type as the peripheral region 15. The semiconductor region 171 has a higher impurity concentration than the peripheral region 15. A contact plug 172 is formed in the semiconductor region 171. A fixed potential is applied to the drain section 17 via the wiring layer 121 and the contact plug 172. For example, if the peripheral region 15 is N-type and the well region 14 is P-type, a positive power supply voltage is applied. Furthermore, if the peripheral region 15 is P-type and the well region 14 is N-type, a negative power supply voltage is applied. For example, if the peripheral region 15 is P-type, a ground potential is applied. Therefore, the drain section 17 can discharge excess charge, and by creating a potential difference between it and the well region 14, it is possible to prevent charge from being mixed into the OB pixel region 101. Similarly, charge generated as dark current at the edge of the substrate can also be prevented from being mixed into the OB pixel region 101. This makes it possible to accurately detect the reference value of the black level.

[0039] It is preferable to arrange the semiconductor region 171 and the well 19 as close as possible. For example, the distance between the semiconductor region 171 and the well 19 is preferably 0 μm or more and 100 μm or less. This makes it easier to prevent excess charges, such as charges photoelectrically converted near the well 19 in the peripheral region 15 and noise charges (dark current), from passing through the well 19 and entering the OB pixel region 101.

[0040] The wiring pattern of the wiring layer 121 connected to the drain section 17 may be the same as the wiring pattern supplied to the drain of the pixel transistor. For example, the wiring pattern to which the VDD power supply of the reset transistor is supplied and the wiring pattern to which the VDD power supply supplied to the drain section 17 is supplied may be the same.

[0041] In FIG. 2 , the pad portions 16 are arranged between the upper end of the semiconductor element layer 11 and the well region 14, and between the left end of the semiconductor element layer 11 and the well region 14, in a planar view. The pad portions 16 may also be arranged between the lower end of the semiconductor element layer 11 and the well region 14, and between the right end of the semiconductor element layer 11 and the well region 14, in a planar view. That is, the peripheral region 15 in which the pad portions 16 are arranged may be arranged so as to surround the entire periphery of the well region 14 of the semiconductor element layer 11, in a planar view. In such a case, the area where the light-shielding layer 13 is not arranged between the OB pixel region 101 and the peripheral region 15 tends to become large, which significantly improves the accuracy of detecting the reference value for the black level. It is not essential that the pad portions 16 be arranged so as to surround the entire periphery of the well region 14 of the semiconductor element layer 11, in a planar view. Even when the pad portion 16 is not arranged in this way, the effect of the present invention can be obtained as long as the pad portion 16 is arranged in at least a portion between the end of the semiconductor element layer 11 and the well region 14 in a planar view. For example, a configuration may be possible in which the pad portion 16 is arranged between the upper end of the semiconductor element layer 11 and the well region 14 in a planar view, and the pad portion 16 is not arranged between the left end of the semiconductor element layer 11 and the well region 14. Even in this case, it is possible to obtain the effect of being able to detect the reference value of the black level more accurately.

[0042] (Embodiment 2) Fig. 4 shows a schematic top view of an end portion of the semiconductor element layer 11 in embodiment 2. Fig. 5 shows a schematic cross-sectional view of the X-X' cross section in Fig. 4. This embodiment differs from embodiment 1 in that the light-shielding layer 13 is arranged so as to cover the well region 14. Other than this point and points described below, the present embodiment is substantially the same as embodiment 1, and therefore description thereof will be omitted.

[0043] 5, in this embodiment, the light-shielding layer 13 is arranged so as to partially overlap the outer peripheral region 15 in a plan view. In other words, in a cross-sectional view, the light-shielding layer 13 protrudes from the end of the well region 14 toward the pad portion 16.

[0044] In the first embodiment, because a portion of the well region 14 is not light-shielded, excess charge photoelectrically converted in the well region 14 may be mixed into the adjacent OB pixel region 101. In contrast, in the second embodiment, because the well region 14 is light-shielded, photoelectric conversion does not occur in the well region 14. In other words, the well 19 is not exposed from the light-shielded region in a planar view. That is, in a planar view, the edge of the well 19 and the edge of the light-shielding layer 13 are at the same position, or the edge of the light-shielding layer 13 protrudes further toward the semiconductor element layer 11 than the edge of the well 19. In such a case, excess charge is generated at the edge of the semiconductor element layer 11 only in the peripheral region 15 of the non-light-shielded region. Since the drain portion 17 is provided in the peripheral region 15, excess charge is discharged, which further suppresses charge mixing into the OB pixel region 101 compared to the first embodiment. This allows for more accurate detection of the black level reference value.

[0045] (Embodiment 3) Fig. 6 shows a schematic top view of an end portion of the semiconductor element layer 11 in embodiment 3. Fig. 7 shows a schematic cross-sectional view of the X-X' cross section in Fig. 6. This embodiment differs from embodiment 2 in that an isolation region 18 is disposed around the pad portion 16 of the semiconductor element layer 11. Other than this point and matters described below, the present embodiment is substantially the same as embodiment 2, and therefore description thereof will be omitted.

[0046] In plan view, the isolation region 18 is arranged to surround the entire periphery of the pad portion 16. The isolation region 18 is an element isolation region in which an insulating film such as a silicon oxide film or a silicon nitride film is buried in a trench formed in the semiconductor element layer 11.

[0047] In the case of the second embodiment, if a wire bond comes into contact with the side surface of the trench of the pad portion 16 of the semiconductor element layer 11 in which the pad portion 16 is formed, a short circuit occurs with the peripheral region 15 to which a voltage is applied. On the other hand, in the case of the third embodiment, the isolation region 18 separates the peripheral region 15 into a region near the trench of the pad portion 16 and a region near the well 19. That is, the side surface of the trench of the semiconductor element layer 11 in which the pad portion 16 is formed is insulated by the isolation region 18 from the peripheral region 15 to which a voltage is applied and in which the drain portion 17 is disposed. Therefore, similar to the second embodiment, it is possible to more accurately detect the reference value of the black level while avoiding a short circuit between the wire bond and the peripheral region 15.

[0048] (Embodiment 4) 8 is a cross-sectional schematic diagram of a stacked back-illuminated photoelectric conversion device according to the fourth embodiment. This embodiment differs from the third embodiment in that the semiconductor element layer 11 includes an avalanche photodiode (hereinafter, APD). The fourth embodiment also differs from the third embodiment in that the distance L4 between the second conductivity type semiconductor region 161 to which the APD drive voltage is applied and the semiconductor region 171 that discharges excess charge is greater than the distance between the well 19 and the semiconductor region 171 in the third embodiment. Other than these points and those described below, the fourth embodiment is substantially the same as the third embodiment, and therefore further description will be omitted.

[0049] The APD disposed on the substrate 1 is composed of a first conductivity type semiconductor region 151 and a second conductivity type semiconductor region 152. The avalanche-multiplied charge is sent to the substrate 2 via the metal junction 30. A quench circuit, a counter circuit, etc. are disposed on the substrate 2, and a signal is sent to the counter circuit, etc. of the substrate 2 via the metal junction 30. Therefore, a metal junction 30 that connects the semiconductor element layer 11 and the semiconductor element layer 23 is disposed for each APD.

[0050] To drive the APD, a high voltage needs to be applied to the second conductivity type semiconductor region 152. The difference between the voltage applied to the semiconductor region 151 and the voltage applied to the semiconductor region 152 is, for example, 20 V or more. An example of the voltage applied to the semiconductor region 152 is a negative voltage with an absolute value greater than −20 V. The voltage applied to the semiconductor region 152 is supplied from the second conductivity type semiconductor region 161 via the second conductivity type semiconductor region 153. Therefore, the above-mentioned high voltage is applied to the second conductivity type semiconductor region 161.

[0051] On the other hand, because the semiconductor region 171 for discharging excess charge is formed of the first conductivity type, if it is close to the semiconductor region 161 of the second conductivity type, an avalanche multiplication region is formed between the semiconductor region 161 and the semiconductor region 171. In other words, an avalanche multiplication region is formed in a region other than the pixel region, and excess charge may be avalanche-multiplied and enter the OB pixel region 101.

[0052] Therefore, when the photoelectric conversion unit to be placed on the substrate 1 is an APD, the distance L4 between the second conductivity type semiconductor region 161 surrounding the pixel region and the first conductivity type semiconductor region 171 must be set to a distance that does not cause avalanche multiplication.

[0053] According to this embodiment, since the distance L4 is set, the formation of an avalanche multiplication region between the semiconductor region 161 and the semiconductor region 171 can be suppressed, and the reference value of the black level can be accurately detected.

[0054] The distance L4 can be set to, for example, 1 μm or more and 10 μm or less, and is preferably set to 3 μm or more and 6 μm or less.

[0055] As shown in FIG. 8, the semiconductor region 171 and the light-shielding layer 13 may overlap each other in plan view.

[0056] (Embodiment 5) 9 shows a cross-sectional schematic diagram of a stacked back-illuminated photoelectric conversion device according to embodiment 5. This embodiment differs from embodiment 4 in that the drain section 17 is connected to the pad section 16 within the same substrate. Other than this point and the points described below, the present embodiment is essentially the same as embodiment 4, and therefore further description will be omitted.

[0057] In this embodiment, the trench of the pad portion 16 is formed deep enough to reach the wiring pattern of the wiring layer 122 of the substrate 1, and the wiring pattern of the wiring layer 122 is connected to a bonding wire. The wiring pattern to which the bonding wire is connected and the drain portion 17 are connected via the contact plug 172 and the wiring pattern of the wiring layer 121.

[0058] As explained in the fourth embodiment, when the photoelectric conversion unit disposed on the substrate 1 is an APD, a high voltage is required to drive the APD. However, since the substrate 2 is generally formed by a micro-process, applying such a high voltage for driving the APD to the semiconductor element layer 23 of the substrate 2 is not preferable from the viewpoint of withstand voltage. Therefore, it is preferable that the high voltage for driving the APD is supplied from a pad disposed on the substrate 1. In this case, excess charge discharged from the drain portion 17 of the substrate 1 is discharged to the outside of the photoelectric conversion device via the pad portion 16 disposed on the substrate 1.

[0059] Furthermore, if the depth of the trench in the pad portion 16 that supplies the driving voltage for the element arranged on the substrate 2 is different from the depth of the trench in the pad portion 16 that supplies the driving voltage for the APD arranged on the substrate 1, the process may become more complicated and the difficulty of the process may increase.

[0060] Therefore, in this embodiment, it is preferable that the voltage for driving the elements placed on the substrate 2 is also applied to the pads formed on the substrate 1 and then supplied to the semiconductor element layer 23 of the substrate 2 via the metal junction 40.

[0061] According to this embodiment, similarly to the fourth embodiment, it is possible to accurately detect the reference value of the black level while suppressing the formation of an avalanche multiplication region between the semiconductor region 161 and the semiconductor region 171. Furthermore, since a high voltage is not applied to the semiconductor element layer 23 of the substrate 2, it is easier to ensure the reliability of the photoelectric conversion device when an APD is used.

[0062] (Embodiment 6) FIG. 10 shows a cross-sectional schematic diagram of a stacked back-illuminated photoelectric conversion device according to the sixth embodiment, and FIG. 11 shows a schematic plan view of the light-shielding layer of the photoelectric conversion device according to the sixth embodiment, viewed from the light-incident surface side. In FIG. 11, the positions of the via plugs are also shown to make the positions of the via plugs easier to understand in a plan view. This embodiment differs in that the second conductivity type semiconductor region 161 and the light-shielding layer 13 are connected via via plugs 191a, 191b, and 191c. Another difference is that color filters of different colors are disposed. Other than these points, the present embodiment is essentially the same as the fifth embodiment, and therefore a description thereof will be omitted.

[0063] 10, the light-shielding layer 13 and the second-conductivity-type semiconductor region 161 are electrically connected via via plugs 191a, 191b, and 191c. As described in the fourth embodiment, a high voltage, which is a negative voltage having an absolute value greater than −20 V, is applied to the second-conductivity-type semiconductor region 161. This voltage is also applied to the light-shielding layer 13 through the via plugs 191a, 191b, and 191c. In other words, the light-shielding layer 13 and the semiconductor region 161 are at the same potential. If the potential difference between the semiconductor region 161 and the light-shielding layer 13 is large, dielectric breakdown may occur in the insulating film disposed between the light-shielding layer 13 and the semiconductor region 161. However, according to this embodiment, dielectric breakdown in the insulating film can be suppressed.

[0064] In FIG. 10, the light-shielding layer 13 and the semiconductor region 161 are connected by three via plugs, but they may be connected by one or two via plugs, or by four or more via plugs.

[0065] 10, the semiconductor region 161 is preferably arranged so that it is wider than the pixel region including the OB pixel region 101. In other words, it is preferable that the semiconductor region 161 is arranged so that it is wider than the pixel region in a cross-sectional view. This makes it easier to connect the light-shielding layer 13 and the semiconductor region 161 through a via plug. Although only one cross-section is shown in FIG. 10, it is preferable that the semiconductor region 161 is arranged so that it is wider than the pixel region 100 even in a cross-section in a direction intersecting the cross-section of FIG.

[0066] The second conductivity type semiconductor region 152 forming the avalanche multiplication region of the APD may be disposed over the entire pixel region in plan view. In this case, the end of the second conductivity type semiconductor region 152 may be included in the second conductivity type semiconductor region 161 or may be in contact with the outer periphery of the second conductivity type semiconductor region 161.

[0067] 11, the light-shielding layer 13 is disposed so as to partially surround the opening of the pad portion 16 in a plan view. For example, if the opening is rectangular, the light-shielding layer 13 is disposed so as to surround three of the four sides constituting the rectangle in a plan view. In this way, it is preferable that the light-shielding layer 13 is disposed as far as possible to the edge of the semiconductor element layer 11.

[0068] 11, via plugs 191a, 191b, and 191c are arranged so as to surround the effective pixel region 100 and the OB pixel region 101 in a plan view. The via plugs 191a and 191b are also connected to the semiconductor region 161 in a cross section intersecting the cross section of FIG. 10. In this way, by arranging the via plugs so as to surround the entire periphery of the effective pixel region 100 and the OB pixel region 101, it is possible to more easily suppress dielectric breakdown of the insulating film between the light-shielding layer 13 and the semiconductor region 161, regardless of the position of the light-shielding layer 13.

[0069] 12, the light-shielding layer 13 may be disposed so as to surround the entire periphery of the pad portion 16 in a plan view. This makes it possible to reduce the amount of light entering the semiconductor element layer 11 more than in the example shown in FIG.

[0070] 12 does not show the via plugs 191a, 191b, and 191c shown in Fig. 11, but the via plugs 191a, 191b, and 191c may be provided. Also, the OB pixel region 101 shown in Fig. 11 may be provided.

[0071] According to this embodiment, similar to the fifth embodiment, it is possible to accurately detect the reference value of the black level while suppressing the formation of an avalanche multiplication region between the semiconductor region 161 and the semiconductor region 171. Furthermore, since a high voltage is not applied to the semiconductor element layer 23 of the substrate 2, it is easier to ensure the reliability of the photoelectric conversion device when an APD is used. Furthermore, it is possible to suppress dielectric breakdown of the insulating film disposed between the light-shielding layer 13 and the semiconductor region 161.

[0072] (Embodiment 7) FIG. 13 is a block diagram showing the configuration of a photoelectric conversion system 1200 according to this embodiment. The photoelectric conversion system 1200 of this embodiment includes a photoelectric conversion device 1204. Here, any of the photoelectric conversion devices described in the above embodiments can be applied to the photoelectric conversion device 1204. The photoelectric conversion system 1200 can be used, for example, as an imaging system. Specific examples of imaging systems include a digital still camera, a digital camcorder, and a surveillance camera. FIG. 13 shows an example of a digital still camera as the photoelectric conversion system 1200.

[0073] 13 includes a photoelectric conversion device 1204, a lens 1202 that forms an optical image of a subject on the photoelectric conversion device 1204, an aperture 1203 that adjusts the amount of light that passes through the lens 1202, and a barrier 1201 that protects the lens 1202. The lens 1202 and the aperture 1203 form an optical system that focuses light on the photoelectric conversion device 1204.

[0074] The photoelectric conversion system 1200 includes a signal processing unit 1205 that processes an output signal output from a photoelectric conversion device 1204. The signal processing unit 1205 performs signal processing operations, performing various corrections and compression on an input signal as necessary and outputting the signal. The photoelectric conversion system 1200 also includes a buffer memory unit 1206 for temporarily storing image data and an external interface unit (external I / F unit) 1209 for communicating with an external computer or the like. The photoelectric conversion system 1200 also includes a recording medium 1211 such as a semiconductor memory for recording or reading image data, and a recording medium control interface unit (recording medium control I / F unit) 1210 for recording or reading data from the recording medium 1211. The recording medium 1211 may be built into the photoelectric conversion system 1200 or may be removable. Communication between the recording medium control I / F unit 1210 and the recording medium 1211 and communication from the external I / F unit 1209 may be performed wirelessly.

[0075] The photoelectric conversion system 1200 further includes an overall control and calculation unit 1208 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1207 that outputs various timing signals to the photoelectric conversion device 1204 and the signal processing unit 1205. Here, timing signals and the like may be input from an external source, and the photoelectric conversion system 1200 only needs to include at least the photoelectric conversion device 1204 and the signal processing unit 1205 that processes the output signal output from the photoelectric conversion device 1204. As explained in the fourth embodiment, the timing generation unit 1207 may be mounted on the photoelectric conversion device. The overall control and calculation unit 1208 and the timing generation unit 1207 may be configured to perform some or all of the control functions of the photoelectric conversion device 1204.

[0076] The photoelectric conversion device 1204 outputs an image signal to the signal processing unit 1205. The signal processing unit 1205 performs predetermined signal processing on the image signal output from the photoelectric conversion device 1204 and outputs image data. The signal processing unit 1205 generates an image using the image signal. The signal processing unit 1205 may also perform distance measurement calculations on the signal output from the photoelectric conversion device 1204. The signal processing unit 1205 and the timing generating unit 1207 may be mounted on the photoelectric conversion device. That is, the signal processing unit 1205 and the timing generating unit 1207 may be provided on the substrate on which the pixels are arranged, or may be provided on a separate substrate. By configuring an imaging system using the photoelectric conversion device of each of the above-described embodiments, an imaging system capable of acquiring higher quality images can be realized.

[0077] (Embodiment 8) The photoelectric conversion system and mobile body of this embodiment will be described with reference to Fig. 14 and Fig. 15. Fig. 14 is a schematic diagram showing an example of the configuration of the photoelectric conversion system and mobile body according to this embodiment. Fig. 15 is a flow diagram showing the operation of the photoelectric conversion system according to this embodiment. In this embodiment, an example of an in-vehicle camera is shown as the photoelectric conversion system.

[0078] FIG. 14 shows an example of a vehicle system and a photoelectric conversion system mounted thereon that performs imaging. The photoelectric conversion system 1301 includes a photoelectric conversion device 1302, an image preprocessing unit 1315, an integrated circuit 1303, and an optical system 1314. The optical system 1314 forms an optical image of a subject on the photoelectric conversion device 1302. The photoelectric conversion device 1302 converts the optical image of the subject formed by the optical system 1314 into an electrical signal. The photoelectric conversion device 1302 is any of the photoelectric conversion devices described in the above-mentioned embodiments. The image preprocessing unit 1315 performs predetermined signal processing on the signal output from the photoelectric conversion device 1302. The function of the image preprocessing unit 1315 may be incorporated into the photoelectric conversion device 1302. The photoelectric conversion system 1301 is provided with at least two sets of an optical system 1314, a photoelectric conversion device 1302, and an image pre-processing unit 1315, and the output from each set of image pre-processing unit 1315 is input to the integrated circuit 1303.

[0079] The integrated circuit 1303 is an integrated circuit for use in an imaging system, and includes an image processing unit 1304 including a memory 1305, an optical distance measurement unit 1306, a distance measurement calculation unit 1307, an object recognition unit 1308, and an abnormality detection unit 1309. The image processing unit 1304 performs image processing such as development and defect correction on the output signal of the image pre-processing unit 1315. The memory 1305 temporarily stores captured images and stores the positions of defects in the captured pixels. The optical distance measurement unit 1306 focuses on the subject and measures the distance. The distance measurement calculation unit 1307 calculates distance information from multiple image data acquired by multiple photoelectric conversion devices 1302. The object recognition unit 1308 recognizes subjects such as cars, roads, signs, and people. If the abnormality detection unit 1309 detects an abnormality in the photoelectric conversion device 1302, it notifies the main control unit 1313 of the abnormality.

[0080] The integrated circuit 1303 may be realized by dedicated hardware, a software module, or a combination thereof. It may also be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or a combination thereof.

[0081] The main control unit 1313 supervises and controls the operations of the photoelectric conversion system 1301, the vehicle sensor 1310, the control unit 1320, etc. It is also possible to adopt a method in which the main control unit 1313 is not provided, and the photoelectric conversion system 1301, the vehicle sensor 1310, and the control unit 1320 each have their own communication interface and send and receive control signals via a communication network (for example, CAN standard).

[0082] The integrated circuit 1303 has a function of receiving a control signal from the main control unit 1313 or transmitting a control signal or a set value to the photoelectric conversion device 1302 by its own control unit.

[0083] The photoelectric conversion system 1301 is connected to a vehicle sensor 1310 and can detect the vehicle's driving conditions, such as vehicle speed, yaw rate, and steering angle, as well as the conditions of the environment outside the vehicle and other vehicles and obstacles. The vehicle sensor 1310 also serves as a distance information acquisition means for acquiring distance information to an object. The photoelectric conversion system 1301 is also connected to a driving assistance control unit 1311 that performs various driving assistance functions, such as automatic steering, automatic cruising, and collision prevention functions. In particular, the collision determination function determines whether or not a collision with another vehicle or obstacle has occurred based on the detection results of the photoelectric conversion system 1301 and the vehicle sensor 1310. This allows for avoidance control when a collision is predicted, and activation of safety devices in the event of a collision.

[0084] The photoelectric conversion system 1301 is also connected to an alarm device 1312 that issues an alarm to the driver based on the determination result of the collision determination unit. For example, if the collision determination unit determines that there is a high possibility of a collision, the main control unit 1313 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 1312 warns the user by sounding an alarm or the like, displaying alarm information on a display screen of a car navigation system or meter panel, vibrating the seat belt or steering wheel, etc.

[0085] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are photographed by the photoelectric conversion system 1301. Fig. 14(b) shows an example of the arrangement of the photoelectric conversion system 1301 when the photoelectric conversion system 1301 photographs the area in front of the vehicle.

[0086] The two photoelectric conversion devices 1302 are arranged in front of the vehicle 1300. Specifically, if the center line of the vehicle 1300's heading or outer shape (for example, vehicle width) is regarded as an axis of symmetry, and the two photoelectric conversion devices 1302 are arranged symmetrically about the axis of symmetry, this is preferable for obtaining distance information between the vehicle 1300 and an object to be photographed and determining the possibility of a collision. Furthermore, the photoelectric conversion devices 1302 are preferably arranged so as not to obstruct the driver's field of vision when the driver visually checks the situation outside the vehicle 1300 from the driver's seat. The warning device 1312 is preferably arranged so as to be easily within the driver's field of vision.

[0087] Next, a fault detection operation of the photoelectric conversion device 1302 in the photoelectric conversion system 1301 will be described with reference to Fig. 15. The fault detection operation of the photoelectric conversion device 1302 is performed in accordance with steps S1410 to S1480 shown in Fig. 15.

[0088] Step S1410 is a step for performing startup settings for the photoelectric conversion device 1302. That is, settings for the operation of the photoelectric conversion device 1302 are transmitted from outside the photoelectric conversion system 1301 (for example, from the main control unit 1313) or from inside the photoelectric conversion system 1301, and the image capturing operation and fault detection operation of the photoelectric conversion device 1302 are started.

[0089] Next, in step S1420, pixel signals are acquired from the valid pixels. Furthermore, in step S1430, output values ​​are acquired from the failure detection pixels provided for failure detection. These failure detection pixels, like the valid pixels, have photoelectric conversion units. A predetermined voltage is written to these photoelectric conversion units. The failure detection pixels output signals corresponding to the voltage written to these photoelectric conversion units. Note that steps S1420 and S1430 may be reversed.

[0090] Next, in step S1440, a determination is made as to whether the expected output value of the fault detection pixel matches the actual output value from the fault detection pixel. If the result of the determination in step S1440 indicates that the expected output value and the actual output value match, the process proceeds to step S1450, where it is determined that the imaging operation is normal, and the process proceeds to step S1460. In step S1460, the pixel signals of the scanning row are sent to the memory 1305 and temporarily stored. Thereafter, the process returns to step S1420, where the fault detection operation continues. On the other hand, if the result of the determination in step S1440 indicates that the expected output value and the actual output value do not match, the process proceeds to step S1470. In step S1470, it is determined that an abnormality exists in the imaging operation, and an alarm is issued to the main control unit 1313 or the alarm device 1312. The alarm device 1312 displays on the display unit that an abnormality has been detected. Thereafter, in step S1480, the photoelectric conversion device 1302 is stopped, and the operation of the photoelectric conversion system 1301 is terminated.

[0091] In this embodiment, the flowchart is looped for each line, but the flowchart may be looped for each set of lines, or the fault detection operation may be performed for each frame. The issuance of the alarm in step S1470 may be notified to the outside of the vehicle via a wireless network.

[0092] In addition, although the present embodiment has been described as a control for preventing collisions with other vehicles, the present invention can also be applied to control for automatic driving by following other vehicles, control for automatic driving so as not to deviate from a lane, etc. Furthermore, the photoelectric conversion system 1301 is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0093] The photoelectric conversion device of the present invention may further be configured to be capable of acquiring various types of information such as distance information. [Explanation of symbols]

[0094] 1 First board 2 Second board 3 Joint surface 13 Light blocking layer 14 well area 15 Outer area 16 Pad section 17 Drain section 30 Metallic joint

Claims

1. a first substrate having a first semiconductor element layer including a plurality of photoelectric conversion units and a well in which the plurality of photoelectric conversion units are disposed; a second substrate having a second semiconductor element layer including a circuit for processing signals obtained by the plurality of photoelectric conversion units, the first substrate and the second substrate are stacked, the first semiconductor element layer has an effective pixel region having some of the plurality of photoelectric conversion units, an optical black pixel region provided between the effective pixel region and an end of the first semiconductor element layer and having some of the plurality of photoelectric conversion units, and a peripheral region disposed between the optical black pixel region and the end of the first semiconductor element layer, a light-shielding region formed of a light-shielding layer overlaps the optical black pixel region in a plan view; a pad portion for conducting electricity between the photoelectric conversion device and the outside is disposed in the outer peripheral region with a gap interposed between the pad portion and the light-shielding region in a plan view; a charge discharge region is disposed between the pad portion and the well in the peripheral region, the charge discharge region including a semiconductor region of the same conductivity type as the signal charge; A photoelectric conversion device, wherein a fixed potential is supplied to the charge discharging region.

2. The photoelectric conversion device according to claim 1 , wherein the gap overlaps with the charge discharging region in a plan view.

3. A photoelectric conversion device as described in claim 1, characterized in that, in a planar view, the light-shielding region overlaps with the charge discharge region.

4. 4. The photoelectric conversion device according to claim 1, wherein an element isolation is arranged between the charge discharging region and the pad portion so as to penetrate the first semiconductor element layer.

5. 5. The photoelectric conversion device according to claim 1, wherein the conductivity type of the peripheral region is N-type, and a positive potential is applied to the charge discharging region.

6. 5. The photoelectric conversion device according to claim 1, wherein the conductivity type of the peripheral region is P-type, and a ground potential is applied to the charge discharging region.

7. 7. The photoelectric conversion device according to claim 1, wherein the light-shielding region overlaps with a part of the well and the outer peripheral region in a plan view.

8. The photoelectric conversion device according to claim 7 , wherein the well is not exposed from the light-shielding region in a plan view.

9. 5. The photoelectric conversion device according to claim 4, wherein the element isolation has a region filled with an insulating material.

10. 10. The photoelectric conversion device according to claim 1, wherein the distance between the center of the pad portion and the light-shielding layer is 30 [mu]m or more and 200 [mu]m or less.

11. the photoelectric conversion unit is an avalanche photodiode, 11. The photoelectric conversion device according to claim 1, wherein the distance between the well and the charge discharging region is 1 [mu]m or more and 10 [mu]m or less.

12. the photoelectric conversion unit is an avalanche photodiode, 11. The photoelectric conversion device according to claim 1, wherein the well and the charge discharging region are spaced apart from each other by a distance that does not cause avalanche multiplication.

13. 13. The photoelectric conversion device according to claim 1, wherein the pad portion is connected to a wiring layer disposed on the first substrate.

14. 14. The photoelectric conversion device according to claim 1, wherein in the first semiconductor element layer, no circuit element is disposed between the pad portion and the well.

15. The photoelectric conversion device according to any one of claims 1 to 14, a signal processing unit that processes a signal output from the photoelectric conversion device.

16. The photoelectric conversion device according to any one of claims 1 to 14, a distance information acquisition means for acquiring distance information to an object based on a signal from the photoelectric conversion device; and a control means for controlling the moving body based on the distance information.

Images