semiconductor integrated circuit device

Abstract

This semiconductor integrated circuit device comprises a plurality of cells each having a fin FET. A plurality of fins (21A, 21B, 22A, 22B) constituting the fin FET extend in the X direction, and are arranged on virtual grid lines (GL) equispaced in the Y direction. The cells include buried power rails (11A, 11B, 12A, 12B). The cells having large sizes in the Y direction include buried power rails (11B, 12B) having a wide width. The center positions of the buried power rails (11A, 11B, 12A, 12B) in the Y direction are on respectively corresponding virtual grid lines (GL), or at the center positions between respectively adjoining virtual grid lines (GL).

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit device including standard cells. [Background technology]

[0002] The standard cell method is known as a method for forming semiconductor integrated circuits on a semiconductor substrate. In this method, basic units with specific logic functions (such as inverters, latches, flip-flops, and full adders) are prepared in advance as standard cells, and multiple standard cells are placed on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, in order to increase the integration density of semiconductor integrated circuit devices, it has been proposed to use buried power rails (BPRs), which are power supply wiring provided in a buried interconnect layer, for standard cells, rather than power supply wiring provided in a metal wiring layer formed above transistors as in the past.

[0004] Patent Document 1 discloses a configuration in which, in a block made up of standard cells, power supply wiring is configured as buried power supply wiring, the source of a transistor is connected to this buried power supply wiring, and it is further connected to power supply wiring provided in an upper wiring layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2019 / 0080969 (FIG. 1E) Summary of the Invention [Problem to be solved by the invention]

[0006] Because buried power wiring is formed by being buried in the substrate, it cannot be formed in the areas where the transistor source, drain, and channel exist. On the other hand, buried power wiring must have sufficient current supply capacity to the transistor. In addition, transistors such as finFETs (field effect transistors) and nanosheet FETs used in microfabrication processes may be subject to restrictions on their size and placement location in order to suppress manufacturing variations.

[0007] An object of the present disclosure is to enable the placement of embedded power supply wiring having a sufficient wiring width without interfering with the regular placement of FinFETs in a semiconductor integrated circuit device that uses embedded power supply wiring. [Means for solving the problem]

[0008] An aspect of the present disclosure is a semiconductor integrated circuit device including a plurality of standard cells each having a FinFET (Field Effect Transistor), wherein a plurality of fins constituting the FinFET each extend in a first direction and are arranged on equally spaced virtual grid lines in a second direction perpendicular to the first direction, the plurality of standard cells including a first standard cell and a second standard cell that is larger in size in the second direction than the first standard cell, the first standard cell including a first buried power wiring that extends in the first direction, the second standard cell including a second buried power wiring that extends in the first direction and is larger in size in the second direction than the first buried power wiring, and the center positions of the first and second buried power wirings in the second direction are on the virtual grid line or at the center positions between adjacent virtual grid lines.

[0009] According to this aspect, in the semiconductor integrated circuit device, the multiple fins constituting the FinFET extend in a first direction and are arranged on equally spaced virtual grid lines in a second direction. The first and second standard cells include buried power wiring, and the second standard cell that is larger in size in the second direction includes buried power wiring that is larger in size in the second direction. This makes it possible to obtain sufficient current supply capability for the FinFET. The buried power wirings included in the first and second standard cells have centers in the second direction on the virtual grid lines or in the center position between adjacent virtual grid lines. This makes it possible to arrange buried power wiring with a sufficient wiring width without interfering with the regular arrangement of the FinFETs. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to arrange embedded power supply wiring having a sufficient wiring width in a semiconductor integrated circuit device without interfering with the regular arrangement of FinFETs. [Brief explanation of the drawings]

[0011] [Figure 1] 1A and 1B are plan views showing the layout structure of an inverter cell that constitutes a semiconductor integrated circuit device according to an embodiment; [Figure 2] (a) and (b) are cross-sectional structures of the inverter cell shown in Figure 1. [Figure 3] 1A and 1B are plan views showing the layout structure of a two-input NAND cell that constitutes a semiconductor integrated circuit device according to an embodiment; [Figure 4] (a) is the circuit diagram of an inverter cell, and (b) is the circuit diagram of a two-input NAND cell. [Figure 5] Configuration example of circuit block of semiconductor integrated circuit device according to embodiment [Figure 6] Enlarged view of part of Figure 5 [Figure 7] FIG. 10 is a plan view showing another layout structure of the inverter cell constituting the semiconductor integrated circuit device according to the embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (hereinafter, simply referred to as cells as appropriate), at least some of which include FinFETs (Field Effect Transistors).

[0013] In this disclosure, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction.

[0014] (First embodiment) Fig. 1 is a plan view showing an example of the layout structure of a standard cell constituting a semiconductor integrated circuit device according to this embodiment. Both Fig. 1(a) and Fig. 1(b) show inverter cells. Fig. 2 is a diagram showing the cross-sectional structure of the cell shown in Fig. 1, with Fig. 2(a) being a cross-sectional view taken along line A-A' in Fig. 1(a) and Fig. 2(b) being a cross-sectional view taken along line BB' in Fig. 1(a).

[0015] 3A and 3B are plan views showing examples of layout structures of other standard cells constituting the semiconductor integrated circuit device according to this embodiment, both of which show two-input NAND cells.

[0016] 4A and 4B show circuit diagrams of the cells, where FIG. 4A is a circuit diagram of the inverter cell shown in FIG. 1, and FIG. 4B is a circuit diagram of the two-input NAND cell shown in FIG.

[0017] The inverter cell shown in Fig. 1 and the two-input NAND cell shown in Fig. 3 have FinFETs, and the multiple fins that make up the FinFETs each extend in the X direction. The multiple fins have the same width, i.e., size in the Y direction (denoted as Wf), and are arranged on virtual grid lines GL (shown by thin dashed lines) that are equally spaced in the Y direction. The pitch of the virtual grid lines GL is Pg. That is, the multiple fins are arranged at a pitch Pg.

[0018] The inverter cell shown in Figure 1(a) and the two-input NAND cell shown in Figure 3(a) have two fins that make up the FinFET, and the cell height is Pg × 8. The inverter cell shown in Figure 1(b) and the two-input NAND cell shown in Figure 3(b) have three fins that make up the FinFET, and the cell height is Pg × 11. The drive capability of a FinFET changes depending on the number of fins that make it up.

[0019] The layout structure of the inverter cell shown in FIGS. 1 and 2 will be described.

[0020] In the inverter cell shown in FIG. 1(a), power supply wirings 11A and 12A extending in the X direction are provided at both ends in the Y direction. Both power supply wirings 11A and 12A are buried power supply wirings (BPR) formed in a buried wiring layer. The power supply wiring 11A supplies a power supply voltage VDD, and the power supply wiring 12A supplies a power supply voltage VSS. The centers of the power supply wirings 11A and 12A in the Y direction coincide with the center between the virtual grid lines GL. The width of the power supply wirings 11A and 12A, i.e., the size in the Y direction, is Wb1.

[0021] Two fins 21A extending in the X direction are provided in a P-type transistor region on an N-well. Two fins 22A extending in the X direction are provided in an N-type transistor region on a P-type substrate. A gate wiring 31A extends in the Y direction from the P-type transistor region to the N-type transistor region. As shown in FIG. 2(b), the gate wiring 31A is formed so as to surround the fins 21A and 22A from three directions. The two fins 21A and the gate wiring 31A form a fin FET P1. The two fins 22A and the gate wiring 31A form a fin FET N1. Note that, for manufacturing purposes, a distance Sb must be maintained between the embedded power wiring and the fin closest to it.

[0022] A local wiring 41A extending in the Y direction is provided at the left end of the fin 21A in the drawing. The left end of the fin 21A in the drawing is connected to the power supply wiring 11A via the local wiring 41A and a via 51A. A local wiring 42A extending in the Y direction is provided at the left end of the fin 22A in the drawing. The left end of the fin 22A in the drawing is connected to the power supply wiring 12A via the local wiring 42A and a via 52A. A local wiring 43A extending in the Y direction is provided at the right ends of the fins 21A and 22A in the drawing. One end of the right side of the fins 21A and 22A in the drawing is connected to each other by the local wiring 43A.

[0023] The metal wiring 61A to which the input A is applied is connected to the gate wiring 31A through a via. The metal wiring 62A from which the output Y is output is connected to the local wiring 43A through a via.

[0024] The inverter cell shown in Fig. 1(b) has a finFET consisting of three fins, but otherwise has the same layout structure as the inverter cell in Fig. 1(a).

[0025] In the inverter cell shown in FIG. 1(b), power supply wirings 11B and 12B extending in the X direction are provided at both ends in the Y direction. Both power supply wirings 11B and 12B are buried power supply wirings (BPR) formed in a buried wiring layer. The power supply wiring 11B supplies a power supply voltage VDD, and the power supply wiring 12B supplies a power supply voltage VSS. The centers of the power supply wirings 11B and 12B in the Y direction coincide with the virtual grid line GL. The width of the power supply wirings 11B and 12B, i.e., the size in the Y direction, is Wb2. Note that Wb2>Wb1.

[0026] Three fins 21B extending in the X direction are provided in a P-type transistor region on an N-well. Three fins 22B extending in the X direction are provided in an N-type transistor region on a P-type substrate. A gate wiring 31B extends in the Y direction from the P-type transistor region to the N-type transistor region. The gate wiring 31B is formed so as to surround the fins 21B and 22B from three directions. The three fins 21B and the gate wiring 31B form a fin FET P1. The three fins 22B and the gate wiring 31B form a fin FET N1.

[0027] A local wiring 41B extending in the Y direction is provided at the left end of the fin 21B in the drawing. The left end of the fin 21B in the drawing is connected to the power supply wiring 11B via the local wiring 41B and a via 51B. A local wiring 42B extending in the Y direction is provided at the left end of the fin 22B in the drawing. The left end of the fin 22B in the drawing is connected to the power supply wiring 12B via the local wiring 42B and a via 52B. A local wiring 43B extending in the Y direction is provided at the right ends of the fins 21B and 22B in the drawing. The right ends of the fins 21B and 22B in the drawing are connected to each other by the local wiring 43B.

[0028] The metal wiring 61B to which the input A is applied is connected to the gate wiring 31B through a via. The metal wiring 62B to which the output Y is output is connected to the local wiring 43B through a via.

[0029] The layout structure of the two-input NAND cell shown in Fig. 3 will be described below. Note that the description of the configuration that can be inferred from the layout structure of the inverter cell shown in Fig. 1 and Fig. 2 may be omitted.

[0030] In the two-input NAND cell shown in FIG. 3(a), power supply wiring 13A and 14A extending in the X direction are provided at both ends in the Y direction. Both power supply wiring 13A and 14A are buried power supply wiring (BPR) formed in a buried wiring layer. The power supply wiring 13A supplies a power supply voltage VDD, and the power supply wiring 14A supplies a power supply voltage VSS. The centers of the power supply wirings 13A and 14A in the Y direction coincide with the center between the virtual grid lines GL. The width, i.e., the size in the Y direction, of the power supply wirings 13A and 14A is Wb1.

[0031] Two fins 23A extending in the X direction are provided in a P-type transistor region on the N-well. Two fins 24A extending in the X direction are provided in an N-type transistor region on a P-type substrate. Gate wirings 32A and 33A extend in the Y direction from the P-type transistor region to the N-type transistor region. The two fins 23A and the gate wirings 32A and 33A form finFETs P11 and P12, respectively. The two fins 24A and the gate wirings 32A and 33A form finFETs N11 and N12, respectively.

[0032] The two-input NAND cell shown in Fig. 3(b) has a FinFET consisting of three fins, but otherwise has the same layout structure as the two-input NAND cell shown in Fig. 3(a).

[0033] In the two-input NAND cell shown in FIG. 3(b), power supply wirings 13B and 14B extending in the X direction are provided at both ends in the Y direction. Both power supply wirings 13B and 14B are buried power supply wirings (BPR) formed in a buried wiring layer. The power supply wiring 13B supplies a power supply voltage VDD, and the power supply wiring 14B supplies a power supply voltage VSS. The centers of the power supply wirings 13B and 14B in the Y direction coincide with the virtual grid line GL. The width of the power supply wirings 13B and 14B, i.e., the size in the Y direction, is Wb2. Note that Wb2>Wb1.

[0034] Three fins 23B extending in the X direction are provided in a P-type transistor region on the N-well. Three fins 24B extending in the X direction are provided in an N-type transistor region on the P-type substrate. Gate wirings 32B and 33B extend in the Y direction from the P-type transistor region to the N-type transistor region. The three fins 23B and the gate wirings 32B and 33B form finFETs P11 and P12, respectively. The three fins 24B and the gate wirings 32B and 33B form finFETs N11 and N12, respectively.

[0035] Here, the inverter cell of FIG. 1(a) and the two-input NAND cell of FIG. 3(a) together with other cells having the same cell height (=Pg×8) form a single circuit block. In this circuit block, cells are arranged in the X direction to form cell rows, and power supply wiring 11A, 13A, etc. that supplies power supply voltage VDD are connected to these rows, and power supply wiring 12A, 14A, etc. that supplies power supply voltage VSS are connected to these rows. The cell rows are then arranged in the Y direction. Every other cell row is arranged in a reversed position in the Y direction. As a result, cell rows adjacent in the Y direction share power supply wiring.

[0036] Similarly, the inverter cell of FIG. 1(b) and the two-input NAND cell of FIG. 3(b) together with other cells having the same cell height (=Pg×11) form a single circuit block. In this circuit block, cells are arranged in the X direction to form cell rows, and power supply wiring 11B, 13B, etc. that supply power supply voltage VDD are connected to these rows, and power supply wiring 12B, 14B, etc. that supply power supply voltage VSS are connected to these rows. The cell rows are then arranged in the Y direction. Every other cell row is arranged in a reversed position in the Y direction. As a result, cell rows adjacent in the Y direction share power supply wiring.

[0037] 5 shows an example of the configuration of a circuit block of a semiconductor integrated circuit device according to this embodiment. The configuration of layers above the fins and gate wiring is omitted in FIG. 5. In FIG. 5, block A is composed of cells with a cell height of Pg×8, and block B is composed of cells with a cell height of Pg×11. Both blocks A and B consist of three rows of cells, and the virtual grid lines GL are common to blocks A and B.

[0038] In block A, cell C1A is the inverter cell of FIG. 1(a), and cell C2A is the two-input NAND cell of FIG. 3(a). From the top of the figure, cells C2A, C2A, and C1A are arranged in the first column from the left, cells C1A, C1A, C1A, and C1A are arranged in the second column from the left, and cells C2A, C1A, and C2A are arranged in the third column from the left. Power supply wiring 1A supplies power supply voltage VDD and is connected to power supply wiring 11A of cell C1A and power supply wiring 13A of cell C2A. Power supply wiring 2A supplies power supply voltage VSS and is connected to power supply wiring 12A of cell C1A and power supply wiring 14A of cell C2A.

[0039] In block B, cell C1B is the inverter cell of FIG. 1(b), and cell C2B is the two-input NAND cell of FIG. 3(b). From the top of the figure, cells C2B, C2B, and C1B are arranged in the first column from the left, cells C1B, C1B, C1B, and C1B are arranged in the second column from the left, and cells C2B, C1B, and C2B are arranged in the third column from the left. Power supply line 1B supplies power supply voltage VDD and is connected to power supply line 11B of cell C1B and power supply line 13B of cell C2B. Power supply line 2B supplies power supply voltage VSS and is connected to power supply line 12B of cell C1B and power supply line 14B of cell C2B.

[0040] In block A, the distance between the centers of the closest fins between cells adjacent in the Y direction is 3×Pg. The center positions of the power supply wiring 1A, 2A are in the middle between the virtual grid lines GL. This allows the width Wb1 of the power supply wiring 1A, 2A to be maximized. The width Wb1 of the power supply wiring 1A, 2A is Wb1=3×Pg-2×Sb-Wf This becomes:

[0041] In block B, the distance between the centers of the closest fins between cells adjacent in the Y direction is 4×Pg. The centers of the power supply wiring 1B and 2B are located on the virtual grid line GL. This allows the width Wb2 of the power supply wiring 1B and 2B to be maximized. The width Wb2 of the power supply wiring 1B and 2B is Wb2=4×Pg-2×Sb-Wf That is, the width Wb2 of the power supply wirings 1B and 2B is larger than the width Wb1 of the power supply wirings 1A and 2A by Pg.

[0042] The cells that make up block B have a larger number of fins that make up the FinFET than the cells that make up block A. As a result, the cells that make up block B operate faster but consume more power than the cells that make up block A. In contrast, as described above, the power supply wiring 1B, 2B is wider than the power supply wiring 1A, 2A, so it is possible to supply sufficient current to the cells that make up block B.

[0043] Furthermore, for example, the vias 51B and 52B for the power supply wiring 11B and 12B in the inverter cell of FIG. 1(b) are larger in size and have lower resistance than the vias 51A and 52A for the power supply wiring 11A and 12A in the inverter cell of FIG. 1(a). Therefore, the inverter cell of FIG. 1(b) can achieve a higher current supply capacity. Note that instead of increasing the via size, the number of vias may be increased. For example, in the inverter cell of FIG. 1(b), two vias may be provided for each of the power supply wiring 11B and 12B.

[0044] 5, the virtual grid lines GL for arranging the fins are shared by blocks A and B, and the cells are arranged so that the fins included in blocks A and B are arranged on the virtual grid lines GL. This allows the fins to be arranged regularly throughout the layout. This improves the ease of manufacturing the semiconductor integrated circuit device, suppresses manufacturing variations, and improves yield.

[0045] As described above, according to this embodiment, in the semiconductor integrated circuit device, the multiple fins constituting the FinFETs extend in the X direction and are arranged on virtual grid lines GL that are equally spaced in the Y direction. The standard cells include buried power supply wiring, and standard cells that are larger in size in the Y direction include buried power supply wiring that is larger in size in the Y direction. This makes it possible to obtain sufficient current supply capability for the FinFETs. The buried power supply wiring of the standard cells has its center position in the Y direction on the virtual grid line GL or in the center position between adjacent virtual grid lines GL. This makes it possible to arrange buried power supply wiring with a sufficient wiring width without interfering with the regular arrangement of the FinFETs.

[0046] Fig. 6 is a partially enlarged view of cell C1A at the right end of the top two rows in block A in Fig. 5. Fig. 6 shows a layout structure in which the inverter cells of Fig. 1(a) are arranged adjacent to each other in the Y direction. In Fig. 6, a via 53 larger than via 52A is arranged at the location (indicated by the dashed line) where via 52A of the inverter cell of Fig. 1(a) is arranged adjacent to via 52A.

[0047] (Variation) Figure 7 shows another layout structure of the inverter cell. The inverter cell shown in Figure 7 has four fins that make up the FinFET, and the cell height is Pg × 14. Other than this, it has the same layout structure as the inverter cell in Figure 1.

[0048] In the inverter cell shown in FIG. 7, power supply wirings 11C and 12C extending in the X direction are provided at both ends in the Y direction. Both power supply wirings 11C and 12C are buried power supply wirings (BPR) formed in a buried wiring layer. The power supply wiring 11C supplies a power supply voltage VDD, and the power supply wiring 12C supplies a power supply voltage VSS. The centers of the power supply wirings 11C and 12C in the Y direction coincide with the center between the virtual grid lines GL. The width of the power supply wirings 11C and 12C, i.e., the size in the Y direction, is Wb3. Note that Wb3>Wb2.

[0049] Four fins 21C extending in the X direction are provided in a P-type transistor region on an N-well. Four fins 22C extending in the X direction are provided in an N-type transistor region on a P-type substrate. A gate wiring 31C extends in the Y direction from the P-type transistor region to the N-type transistor region. The gate wiring 31C is formed so as to surround the fins 21C, 22C from three directions. The four fins 21C and the gate wiring 31C form a fin FET P1. The four fins 22C and the gate wiring 31C form a fin FET N1.

[0050] A local wiring 41C extending in the Y direction is provided at the left end of the fin 21C in the drawing. The left end of the fin 21C in the drawing is connected to the power supply wiring 11C via the local wiring 41C and a via 51C. A local wiring 42C extending in the Y direction is provided at the left end of the fin 22C in the drawing. The left end of the fin 22C in the drawing is connected to the power supply wiring 12C via the local wiring 42C and a via 52C. A local wiring 43C extending in the Y direction is provided at the right ends of the fins 21C and 22C in the drawing. The right ends of the fins 21C and 22C in the drawing are connected to each other by the local wiring 43C.

[0051] The metal wiring 61C to which the input A is applied is connected to the gate wiring 31C through a via. The metal wiring 62C from which the output Y is output is connected to the local wiring 43C through a via.

[0052] The inverter cell in Fig. 7 and other cells having the same cell height (=Pg × 14) form a single circuit block. This circuit block may be placed along the common virtual grid line GL together with blocks A and B shown in Fig. 5, for example.

[0053] Furthermore, the width Wb3 of the power supply wirings 11C and 12C is as follows.

[0054] Wb3=5×Pg-2×Sb-Wf That is, Wb3 is larger than Wb2 by Pg.

[0055] Furthermore, the vias 51C and 52B for the power supply wirings 11C and 12C are larger in size than the vias 51B and 52B for the power supply wirings 11B and 12B in the inverter cell of FIG. 1(b). Therefore, a larger current supply capacity can be achieved in the inverter cell of FIG. 7. Note that instead of increasing the via size, the number of vias may be increased. For example, if two vias are provided for each of the power supply wirings 11B and 12B in the inverter cell of FIG. 1(b), three vias may be provided for each of the power supply wirings 11C and 12C in the inverter cell of FIG. 7.

[0056] In the above description, the semiconductor integrated circuit device has been described as including standard cells having FinFETs, but the transistors included in the standard cells are not limited to FinFETs. For example, the present disclosure can also be applied to a semiconductor integrated circuit device including standard cells having nanosheet FETs. [Industrial Applicability]

[0057] In the present disclosure, for a semiconductor integrated circuit device that uses embedded power wiring, embedded power wiring having a sufficient wiring width is arranged without interfering with the regular arrangement of FinFETs, which is useful, for example, for improving the integration density and performance of a system LSI. [Explanation of symbols]

[0058] 1A, 1B, 2A, 2B embedded power wiring 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 14A, 14B Embedded power wiring 21A, 21B, 21C, 22A, 22B, 22C, 23A, 23B, 24A, 24B Fins 41A, 41B, 41C, 42A, 42B, 42C Local wiring 51A, 51B, 51C, 52A, 52B, 52C vias C1A, C1B, C2A, C2B standard cells P1, P11, P12, N1, N11, N12 FinFETs GL Virtual Grid Lines

Claims

1. A semiconductor integrated circuit device including a plurality of standard cells each having a FinFET (Field Effect Transistor), the plurality of fins constituting the FinFET each extend in a first direction and are arranged on equally spaced virtual grid lines in a second direction perpendicular to the first direction; the plurality of standard cells include a first standard cell and a second standard cell that is larger in size in the second direction than the first standard cell; The first standard cell is a first embedded power supply wiring extending in the first direction; The second standard cell is a second embedded power supply wiring extending in the first direction and having a size in the second direction larger than that of the first embedded power supply wiring; The first and second buried power supply wirings have central positions in the second direction on the virtual grid lines or at the central positions between adjacent virtual grid lines. A semiconductor integrated circuit device characterized by:

2. 2. The semiconductor integrated circuit device according to claim 1, The first standard cell is a first FinFET including N fins (N is an integer of 1 or more); The second standard cell is a second FinFET including M fins (M is an integer greater than N); A semiconductor integrated circuit device characterized by:

3. 2. The semiconductor integrated circuit device according to claim 1, The first standard cell is a first local wiring extending in the second direction and connected to the first buried power wiring through a first via; The second standard cell is a second local wiring extending in the second direction and connected to the second buried power wiring through a second via; The second vias are larger in size or are more numerous than the first vias. A semiconductor integrated circuit device characterized by:

4. 2. The semiconductor integrated circuit device according to claim 1, The first and second standard cells realize the same circuit function. A semiconductor integrated circuit device characterized by:

5. 2. The semiconductor integrated circuit device according to claim 1, the plurality of standard cells include a third standard cell that is larger in size in the second direction than the second standard cell; The third standard cell is a third embedded power supply wiring extending in the first direction and having a size in the second direction larger than that of the second embedded power supply wiring; A semiconductor integrated circuit device characterized by:

6. 6. The semiconductor integrated circuit device according to claim 5, The first standard cell is a first FinFET including N fins (N is an integer of 1 or more); The second standard cell is a second FinFET including M fins (M is an integer greater than N); The third standard cell is a third FinFET including L fins (L is an integer greater than M); A semiconductor integrated circuit device characterized by:

7. 6. The semiconductor integrated circuit device according to claim 5, The first standard cell is a first local wiring extending in the second direction and connected to the first buried power wiring through a first via; The second standard cell is a second local wiring extending in the second direction and connected to the second buried power wiring through a second via; The third standard cell is a third local wiring extending in the second direction and connected to the third buried power wiring through a third via; The second vias are larger in size or more in number than the first vias. The third vias are larger in size or are more numerous than the second vias. A semiconductor integrated circuit device characterized by:

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