Photoelectric conversion device and photoelectric conversion system

Abstract

To provide a photoelectric conversion device and a photoelectric conversion system that reduce the influence of light incident on a peripheral area.SOLUTION: A photoelectric conversion device includes a pixel array area 12E and a peripheral area 13 on the periphery of the pixel array area. Each pixel 101 in the pixel array area includes a first semiconductor area 311 of a first conductivity type arranged on the side of a first surface S1, and a second semiconductor area 315 of a second conductivity type arranged on the side of a second surface S2. Predetermined voltage that causes an avalanche doubling operation is supplied between the first semiconductor area and the second semiconductor area. The peripheral area includes a third semiconductor area 1311 of the first conductivity type arranged on the first surface side, a fourth semiconductor area 1315 of the second conductivity type arranged separate from the third semiconductor area, and a fifth semiconductor area 1313 of the first conductivity type. The concentration of impurities of the first conductivity type in the fifth semiconductor area is lower than the concentration of impurities of the first conductivity type in the third semiconductor area, and voltage is supplied between the third semiconductor area and the fourth semiconductor area.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system. [Background technology]

[0002] Patent Document 1 describes an APD (avalanche photodiode) that aims to reduce crosstalk from pixels and suppress DCR (dark count rate). The APD includes a high-field region, an isolation region for isolating adjacent pixels, and a hole accumulation region for trapping electrons on the sidewall of the isolation region, with the hole accumulation region electrically connected to an anode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-201005 Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor substrate of the photoelectric conversion device may have a pixel array region and a peripheral region disposed around the pixel array region. When light is unintentionally incident on the peripheral region, photoelectric conversion generates charges (electrons and holes), which may enter pixels of the pixel array. Alternatively, the charges generated by photoelectric conversion may recombine to generate light, which may be detected by pixels of the pixel array, such as light-shielded pixels (OB pixels).

[0005] An object of the present invention is to provide an advantageous technique for reducing the influence of light incident on the peripheral region of a photoelectric conversion device. [Means for solving the problem]

[0006] One aspect of the present invention relates to a photoelectric conversion device having a semiconductor layer including a pixel array region having a plurality of pixels and a peripheral region arranged around the pixel array region, the semiconductor layer having a first surface and a second surface, each pixel in the pixel array region including a first semiconductor region of a first conductivity type arranged on the side of the first surface and a second semiconductor region of a second conductivity type arranged on the side of the second surface, and an avalanche current is generated between the first semiconductor region and the second semiconductor region. Multiplication A predetermined voltage capable of causing operation is supplied, the peripheral region includes a third semiconductor region of the first conductivity type arranged on the side of the first surface, a fourth semiconductor region of the second conductivity type arranged at a distance from the third semiconductor region, and a fifth semiconductor region of the first conductivity type arranged between the third semiconductor region and the fourth semiconductor region and close to the third semiconductor region, the impurity concentration of the first conductivity type in the fifth semiconductor region is lower than the impurity concentration of the first conductivity type in the third semiconductor region, and a voltage is supplied between the third semiconductor region and the fourth semiconductor region. [Effects of the Invention]

[0007] According to the present invention, an advantageous technique for reducing the influence of light incident on the peripheral region of a photoelectric conversion device is provided. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a basic configuration of a photoelectric conversion device according to an embodiment. [Figure 2] FIG. 2 is a diagram showing a configuration example of a sensor substrate. [Figure 3] FIG. 2 is a diagram showing an example of the configuration of a circuit board. [Figure 4] FIG. 2 is an equivalent circuit diagram of one pixel and its signal processing unit. [Figure 5] 3A to 3C are diagrams illustrating the operation of a pixel. [Figure 6] FIG. 2 is a diagram showing a first configuration example of a pixel. [Figure 7A] FIG. 2 is a diagram showing a first configuration example of a pixel. [Figure 7B] FIG. 2 is a diagram showing a first configuration example of a pixel. [Figure 8]FIG. 10 is a diagram showing a second configuration example of a pixel. [Figure 9A] FIG. 10 is a diagram showing a second configuration example of a pixel. [Figure 9B] FIG. 10 is a diagram showing a second configuration example of a pixel. [Figure 10] FIG. 1 is a plan view showing the configuration of a photoelectric conversion device according to a first embodiment. [Figure 11] FIG. 1 is a cross-sectional view showing the configuration of a photoelectric conversion device according to a first embodiment. [Figure 12] FIG. 10 is a plan view showing the configuration of a photoelectric conversion device according to a second embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing the configuration of a photoelectric conversion device according to a second embodiment. [Figure 14] FIG. 10 is a plan view showing the configuration of a photoelectric conversion device according to a third embodiment. [Figure 15A] FIG. 10 is a cross-sectional view showing the configuration of a photoelectric conversion device according to a third embodiment. [Figure 15B] FIG. 10 is a cross-sectional view showing the configuration of a photoelectric conversion device according to a third embodiment. [Figure 16A] FIG. 10 is a cross-sectional view showing the configuration of a photoelectric conversion device according to a fourth embodiment. [Figure 16B] FIG. 10 is a cross-sectional view showing the configuration of a photoelectric conversion device according to a fourth embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing the configuration of a photoelectric conversion device according to a fifth embodiment. [Figure 18] FIG. 1 is a diagram showing the configuration of a photoelectric conversion system. [Figure 19] FIG. 1 is a diagram showing the configuration of a photoelectric conversion system. [Figure 20] FIG. 1 is a diagram showing the configuration of a photoelectric conversion system. [Figure 21] FIG. 1 is a diagram showing the configuration of a photoelectric conversion system. [Figure 22] FIG. 1 is a diagram showing the configuration of a photoelectric conversion system. [Figure 23] FIG. 1 is a diagram showing the configuration of a photoelectric conversion system. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0011] In this specification, a planar view refers to a view from a direction perpendicular to the light incident surface of the semiconductor layer. A cross-sectional view refers to a surface perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0012] In the following description, the anode of the avalanche photodiode (APD) is set to a fixed potential, and a signal is extracted from the cathode side. Therefore, the first conductivity type semiconductor region having majority carriers of charges of the same polarity as the signal charge is an N-type semiconductor region, and the second conductivity type semiconductor region having majority carriers of charges of a polarity opposite to that of the signal charge is a P-type semiconductor region. The present invention also applies when the cathode of the APD is set to a fixed potential and a signal is extracted from the anode side. In this case, the first conductivity type semiconductor region having majority carriers of charges of the same polarity as the signal charge is a P-type semiconductor region, and the second conductivity type semiconductor region having majority carriers of charges of a polarity opposite to that of the signal charge is an N-type semiconductor region. While the following description focuses on a case where one node of the APD is set to a fixed potential, the potentials of both nodes may fluctuate.

[0013] In this specification, when the term "impurity concentration" is used simply, it means the net impurity concentration minus the amount compensated for by impurities of the opposite conductivity type. In other words, "impurity concentration" refers to the NET doping concentration. A region where the P-type doped impurity concentration is higher than the N-type doped impurity concentration is a P-type semiconductor region. Conversely, a region where the N-type doped impurity concentration is higher than the P-type doped impurity concentration is an N-type semiconductor region.

[0014] First, a basic configuration and driving method common to photoelectric conversion devices and driving methods thereof according to a plurality of embodiments to be described later will be described with reference to FIGS. 1, 2, 3, 4, and 5. FIG.

[0015] FIG. 1 illustrates a basic configuration of a photoelectric conversion device 100 according to an embodiment. Here, an example in which the photoelectric conversion device 100 is configured as a stacked-type photoelectric conversion device is described. However, the present invention is also applicable to photoelectric conversion devices other than stacked-type photoelectric conversion devices. The photoelectric conversion device 100 may be configured by stacking multiple substrates, including a sensor substrate 301 and a circuit substrate 401, and electrically connecting the multiple substrates. The sensor substrate 301 may have a first semiconductor layer having a photoelectric conversion element 102 (described later) and a first wiring structure. The circuit substrate 401 may have a second semiconductor layer having circuits such as a signal processing unit 103 (described later) and a second wiring structure. The photoelectric conversion device 100 may be configured by stacking the second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer in this order, for example. The photoelectric conversion device described as the following embodiment may be, for example, a back-illuminated photoelectric conversion device. However, the photoelectric conversion device according to the present invention may also be configured as a front-illuminated photoelectric conversion device.

[0016] The sensor substrate 301 and the circuit substrate 401 may each be a chip diced from a wafer, but these substrates are not limited to chips. For example, each substrate may be a wafer. Furthermore, multiple substrates may be stacked in the wafer state and then diced, or multiple chips may be stacked or joined after being diced.

[0017] The sensor substrate 301 may include a semiconductor layer including a pixel array region 12 having a plurality of pixels and a peripheral region 13 arranged around the pixel array region 12. The region between the outer edge of the pixel array region 12 and the outer edge of the sensor substrate 301 may be the peripheral region 13. Circuit elements such as active elements may or may not be arranged in the peripheral region 13. The circuit substrate 401 may include a semiconductor layer including a circuit region 22 that processes signals detected by pixels in the pixel array region 12.

[0018] 2 is a diagram showing an example of the configuration of the sensor substrate 301. In the pixel array region 12, a plurality of pixels 101 can be arranged in a two-dimensional array to form a plurality of rows and a plurality of columns. Each pixel 101 can include a photoelectric conversion element 102 including an avalanche photodiode (hereinafter, referred to as APD).

[0019] The pixels 101 arranged in the pixel array region 12 may be pixels for forming an image. However, when the sensor substrate 11 or the photoelectric conversion device 100 is applied to TOF (Time of Flight), each pixel 101 does not necessarily have to be a pixel for forming an image. In other words, the pixel 101 may be a pixel for measuring the time and amount of light that arrives.

[0020] 3 is a diagram showing the configuration of a circuit board 401. The circuit board 401 may include, for example, a signal processing unit 103 that processes charges generated by photoelectric conversion in the photoelectric conversion element 102, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, signal lines 113, and a vertical scanning circuit unit 110. One signal processing unit 103 may be provided for one pixel 101. The photoelectric conversion element 102 in FIG. 2 and the signal processing unit 103 in FIG. 3 may be electrically connected via connection wiring provided for each pixel 101.

[0021] The vertical scanning circuit unit 110 may be configured, for example, to receive a first control pulse supplied from the control pulse generation unit 115, generate a second control pulse, and supply the second control pulse to each pixel 101. The vertical scanning circuit unit 110 may include, for example, logic circuits such as a shift register and an address decoder. A signal output from the photoelectric conversion element 102 of each pixel 101 may be processed by a signal processing unit 103 provided corresponding to that pixel 101. The signal processing unit 103 may include a counter, a memory, etc., and the memory may hold digital values.

[0022] The horizontal scanning circuit unit 111 can be configured to supply the signal processing unit 103 with a third control pulse that sequentially selects each column in order to read out the signal from the memory of each pixel 101 that holds the digital signal. The circuit board 401 can have a plurality of signal lines 113. Signals are output to the plurality of signal lines 113 from the signal processing unit 103 assigned to the pixels 101 in the row selected by the vertical scanning circuit unit 110. The signals output to the plurality of signal lines 113 can be output to a recording unit or a signal processing unit outside the photoelectric conversion device 100 via an output circuit 114.

[0023] 2, the photoelectric conversion elements 102 or pixels 101 may be arranged one-dimensionally in the pixel array region 12. Each signal processing unit 103 may be assigned to at least two photoelectric conversion elements 102 or pixels 101.

[0024] 2 and 3, a plurality of signal processing units 103 may be arranged in a region overlapping the pixel array region 12 in a planar view. Then, a vertical scanning circuit unit 110, a horizontal scanning circuit unit 111, a readout circuit 112, an output circuit 114, and a control pulse generation unit 115 may be arranged so as to overlap a region between the outer edge of the sensor substrate 11 and the outer edge of the pixel array region 12 in a planar view. In other words, the vertical scanning circuit unit 110, the horizontal scanning circuit unit 111, the readout circuit 112, the output circuit 114, and the control pulse generation unit 115 may be arranged in a region overlapping the peripheral region 13 of the sensor substrate 11 in a planar view.

[0025] FIG. 4 illustrates an equivalent circuit of one pixel 101 in FIG. 2 and one signal processing unit 103 in FIG. 3. The APD 201 generates charge pairs in response to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201. A voltage VH (second voltage) higher than the voltage VL supplied to the anode may be supplied to the cathode of the APD 201. A reverse bias voltage (predetermined voltage) that can cause the APD 201 to perform avalanche multiplication may be supplied between the anode and cathode. With such a reverse bias voltage supplied between the anode and cathode, charges generated by incident light may cause avalanche multiplication, generating an avalanche current.

[0026] A mode in which an APD is operated with a voltage between the anode and cathode greater than the breakdown voltage is called Geiger mode. A mode in which an APD is operated with a voltage between the anode and cathode close to or less than the breakdown voltage is called linear mode. An APD operated in Geiger mode is called a SPAD. For example, the voltage VL (first voltage) is −30 V and the voltage VH (second voltage) is 1 V. The APD 201 may be operated in either linear mode or Geiger mode.

[0027] The quench element 202 can be arranged to connect a power supply that supplies voltage VH to the APD 201. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has the function of suppressing avalanche multiplication by suppressing the voltage supplied to the APD 201 (quench operation). The quench element 202 also has the function of returning the voltage supplied to the APD 201 to voltage VH by flowing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0028] The signal processing unit 103 may include a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. The signal processing unit 103 may be a circuit including at least one of the waveform shaping unit 210, the counter circuit 211, and the selection circuit 212. The waveform shaping unit 210 may shape the potential change of the cathode of the APD 201 obtained upon photon detection and output a pulse signal. For example, an inverter circuit may be used as the waveform shaping unit 210. In FIG. 4, the waveform shaping unit 210 is configured with one inverter, but the waveform shaping unit 210 may include a series connection of multiple inverters or may include another circuit that has a waveform shaping effect.

[0029] The counter circuit 211 can count the pulse signals output from the waveform shaping unit 210 and hold the count value. The counter circuit 211 can also be configured to reset the signal held in the counter circuit 211 by receiving a control pulse pRES via a drive line 213. The selection circuit 212 can receive a control pulse pSEL from the vertical scanning circuit unit 110 in FIG. 3 via a drive line 214 in FIG. 4 (not shown in FIG. 3), and can switch between electrical connection and disconnection between the counter circuit 211 and the signal line 113. The selection circuit 212 can include, for example, a buffer circuit for outputting a signal.

[0030] A switch such as a transistor may be disposed between the quench element 202 and the APD 201 and / or between the photoelectric conversion element 102 and the signal processing unit 103 to control the electrical connection. Similarly, the supply of the voltage VH and / or the voltage VL to the photoelectric conversion element 102 may be controlled by a switch such as a transistor.

[0031] The photoelectric conversion device 100 may be configured to acquire pulse detection timing using a time-to-digital converter (hereinafter referred to as TDC) and a memory instead of the counter circuit 211. The generation timing of the pulse signal output from the waveform shaping unit 210 may be converted into a digital signal by the TDC. To measure the timing of the pulse signal, a control pulse pREF (reference signal) may be supplied to the TDC from the vertical scanning circuit unit 110 in FIG. 1 via a drive line. The TDC may acquire, as a digital signal, a signal obtained by converting the input timing of the signal output from each pixel via the waveform shaping unit 210 into a relative time based on the control pulse pREF.

[0032] 5 is a diagram schematically illustrating the relationship between the operation of the APD 201 and the output signal. FIG. 5(a) is a diagram illustrating the APD 201, the quench element 202, and the waveform shaping unit 210 excerpted from FIG. 4. Here, the input side of the waveform shaping unit 210 is referred to as node A, and the output side is referred to as node B. FIG. 5(b) shows the waveform change at node A in FIG. 5(a), and FIG. 5(c) shows the waveform change at node B in FIG. 5(a).

[0033] Between time t0 and time t1, a potential difference of VH-VL is applied to the APD 201 in FIG. 5(a). When a photon is incident on the APD 201 at time t1, avalanche multiplication occurs in the APD 201, an avalanche multiplication current flows through the quench element 202, and the voltage at node A drops. As the voltage drop increases and the potential difference applied to the APD 201 decreases, the avalanche multiplication operation of the APD 201 stops, as shown at time t2, and the voltage level at node A no longer drops below a certain value. After that, between time t2 and time t3, a current flows through node A from voltage VL to compensate for the voltage drop, and at time t3, node A returns to its original potential level. At this time, the portion of the output waveform at node A that exceeds a certain threshold is shaped by the waveform shaping unit 210 and output as a signal at node B.

[0034] The arrangement of the signal lines 113, the readout circuits 112, and the output circuits 114 is not limited to that shown in Fig. 3. For example, the signal lines 113 may be arranged to extend in the row direction, and the readout circuits 112 may be arranged at the ends of the signal lines 113.

[0035] Here, a first configuration example of the pixel 101 will be described with reference to FIGS. 6, 7A, and 7B. For convenience, FIGS. 7A and 7B show an example in which the pixel array region is configured with four pixels arranged in two rows and two columns. An opening OP is provided around the periphery of the pixel array region, and a pad electrode PE is disposed in the opening OP. FIG. 6(a) schematically shows a plan view of the cathodes of two pixels 101 and their periphery, and FIG. 6(b) schematically shows a plan view of the anodes of two pixels 101 and their periphery. FIG. 7A schematically shows a cross-sectional view of the two pixels 101 in FIGS. 6(a) and 6(b) in the opposite side direction, and FIG. 7B schematically shows a cross-sectional view of the two pixels 101 in FIGS. 6(a) and 6(b) in the diagonal direction. The opposite side direction is, for example, a direction connecting one side of a pixel with another side opposite to that side. The diagonal direction is, for example, a direction connecting one corner of a pixel with another corner opposite to that corner.

[0036] The sensor substrate 301 may include a first semiconductor layer 302 having a first surface S1 and a second surface S2, and a first wiring structure 303. The circuit substrate 401 may include a second semiconductor layer 402 and a second wiring structure 403. The first wiring structure 303 may be disposed between the first surface S1 of the first semiconductor layer 302 and the circuit substrate 401. The second wiring structure 403 may be disposed between the sensor substrate 301 and the second semiconductor layer 402.

[0037] Each pixel 101 may include a first semiconductor region 311 of a first conductivity type serving as a cathode of the APD 201 and a second semiconductor region 315 of a second conductivity type serving as an anode of the APD 201. The first semiconductor region 311 of the first conductivity type may be disposed on a first surface S1 side of the first semiconductor layer 302, and the second semiconductor region 315 of the second conductivity type may be disposed on a second surface S2 side of the first semiconductor layer 302. A predetermined voltage capable of causing avalanche doubling may be supplied between the first semiconductor region 311 and the second semiconductor region 315. Each pixel 101 may include a semiconductor region 313 of the first conductivity type disposed between the first semiconductor region 311 serving as a cathode and the second semiconductor region 315 serving as an anode, in close proximity to the first semiconductor region 311. The impurity concentration of the first conductivity type in the semiconductor region 313 is lower than the impurity concentration of the first conductivity type in the first semiconductor region 311 of the first conductivity type serving as a cathode.

[0038] Each pixel 101 may include a semiconductor region 312 of a second conductivity type between a first semiconductor region 311 of a first conductivity type serving as a cathode and a second semiconductor region 315 of a second conductivity type serving as an anode. For example, if the semiconductor region 312 is the same node as the second semiconductor region 315 serving as an anode, the semiconductor region 312 may also function as an anode. The region between the first semiconductor region 311 and the semiconductor region 312 may serve as an avalanche multiplication region. A semiconductor region 316 of a first conductivity type or a second conductivity type may be disposed between the first surface S1 and the semiconductor region 312 of the second conductivity type so as to surround the first semiconductor region 311 of the first conductivity type serving as a cathode. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 is lower than the impurity concentration of the first conductivity type in the semiconductor region 313 serving as a cathode. When the semiconductor region 316 has the second conductivity type, the concentration of the impurities of the second conductivity type in the semiconductor region 316 is lower than the concentration of the impurities of the second conductivity type in the semiconductor region 312 of the second conductivity type.

[0039] A semiconductor region 316 of the first conductivity type or the second conductivity type may be disposed between the semiconductor region 312 of the second conductivity type and the second semiconductor region 315 of the second conductivity type serving as an anode. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the first conductivity type in the semiconductor region 313. When the semiconductor region 316 has the second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the second conductivity type in the semiconductor region 312 of the second conductivity type.

[0040] A semiconductor region 317 of the first conductivity type may be disposed between the second semiconductor region 315 of the second conductivity type serving as an anode and the semiconductor region 312 of the second conductivity type. The semiconductor region 316 may include a portion disposed between the second semiconductor region 315 of the second conductivity type serving as an anode and the semiconductor region 317 of the first conductivity type, and a portion surrounding the side surface of the semiconductor region 317 of the first conductivity type.

[0041] A second conductivity type isolation region 314 may be arranged between adjacent pixels 101 among the plurality of pixels 101. A second conductivity type contact region 318 may be arranged between the second conductivity type isolation region 314 and the first surface S1 so as to be electrically connected to the second conductivity type isolation region 314. The second conductivity type contact region 318 has a higher impurity concentration of the second conductivity type than the impurity concentration of the second conductivity type in the second conductivity type isolation region 314. The second conductivity type isolation region 314 may be arranged so as to be electrically connected to a second conductivity type second semiconductor region 315 serving as an anode. An anode voltage (anode potential) may be supplied to the second conductivity type contact region 318 via a conductive path arranged in the first wiring structure 303, thereby supplying the anode voltage (anode potential) to the second conductivity type second semiconductor region 315 serving as an anode. 6, four contact regions 318 are provided for one pixel 101, but any number of contact regions 318 may be provided for one pixel 101. Alternatively, two or more pixels 101 may be grouped together, and one or more contact regions 318 may be provided for each group.

[0042] An insulating isolation portion 324 may be disposed in the second conductivity type isolation region 314. The insulating isolation portion 324 may include a groove provided in the isolation region 314 and an insulator disposed so as to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. The insulating isolation portion 324 may be referred to as DTI (Deep Trench Isolation). The insulating isolation portion 324 or the groove may be disposed so as to penetrate the first semiconductor layer 302, or may be disposed so as not to penetrate the first semiconductor layer 302. The insulating isolation portion 324 or the groove may electrically separate the second conductivity type isolation region 314 into an isolation region on one pixel 101 side and an isolation region on the adjacent pixel 101 side. The insulating isolation portion 324 may be configured to include a groove, an insulator disposed so as to cover the inner surface of the groove, and a metal or a light-shielding material disposed inside the insulator. Furthermore, the insulating separation portion 324 does not have to penetrate the semiconductor layer.

[0043] A pinning layer 331 (shown by a thick line) may be disposed on the second surface S2 side of the second semiconductor region 315 of the second conductivity type serving as an anode. The pinning layer 331 may also be called a fixed charge film. The pinning layer 331 is disposed so as to be in contact with the second surface S2 and may be formed by, for example, ALD (Atomic Layer Deposition). The pinning layer 331 may be made of a material selected from, for example, hafnium oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, and ruthenium oxide. The pinning layer 331 may be composed of multiple layers. The aforementioned film covering the surface (inner surface) of the groove provided in the separation region 314 may be the pinning layer 331.

[0044] The pinning layer 331 and the second surface S2 may be covered with an insulating film 321. The insulating film 321 may be, for example, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film. The insulating film 321 may be composed of multiple films. The second semiconductor region 315 of the second conductivity type serving as an anode may be provided with a concave-convex structure 325. The surface of the concave-convex structure 325 may be covered with the pinning layer 331. The concave-convex structure 325 functions to diffract incident light and lengthen the optical path within the semiconductor layer 302. This is advantageous for improving near-infrared sensitivity. The concave-convex structure 325 may be composed of grooves provided in the semiconductor layer 302, and the pinning layer 331 and an insulator disposed in the grooves. The pinning layer 331 may be disposed so as to cover the exposed surface of the semiconductor layer 302. In other words, the pinning layer 331 is disposed along the grooves of the concave-convex structure and the second surface S2. The insulator disposed in the groove may be made of an insulating film 321 .

[0045] The insulating film 321 may be covered with a planarization layer 322. A microlens 323 may be disposed on the planarization layer 322. The example shown in FIGS. 7A and 7B is a back-illuminated type in which light is incident from the outside onto the second surface S of the semiconductor layer 302 through the microlens 323, but the photoelectric conversion device 100 may also be configured as a front-illuminated type. Note that, although not shown, in addition to the planarization layer 322, a filter layer such as a color filter or an infrared light cut filter may be provided on the second surface S2 side of the semiconductor layer 302.

[0046] A second configuration example of the pixel 101 will be described below with reference to FIGS. 8, 9A, and 9B. For convenience, FIGS. 9A and 9B show an example in which the pixel array region is configured with four pixels arranged in two rows and two columns. An opening OP is provided around the periphery of the pixel array region, and a pad electrode PE is disposed in the opening OP. FIG. 8(a) schematically shows a plan view of the cathodes of two pixels 101 and their peripheries, and FIG. 8(b) schematically shows a plan view of the anodes of two pixels 101 and their peripheries. FIG. 9A schematically shows a cross-sectional view of the two pixels 101 in FIGS. 8(a) and 8(b) in the direction opposite to each other, and FIG. 9B schematically shows a cross-sectional view of the two pixels 101 in FIGS. 8(a) and 8(b) in the diagonal direction.

[0047] The sensor substrate 301 may include a first semiconductor layer 302 having a first surface S1 and a second surface S2, and a first wiring structure 303. The circuit substrate 401 may include a second semiconductor layer 402 and a second wiring structure 403. The first wiring structure 303 may be disposed between the first surface S1 of the first semiconductor layer 302 and the circuit substrate 401. The second wiring structure 403 may be disposed between the sensor substrate 301 and the second semiconductor layer 402.

[0048] Each pixel 101 may include a first semiconductor region 311 of a first conductivity type serving as a cathode of the APD 201 and a second semiconductor region 315 of a second conductivity type serving as an anode of the APD 201. The first semiconductor region 311 of the first conductivity type may be disposed on a first surface S1 side of the first semiconductor layer 302, and the second semiconductor region 315 of the second conductivity type may be disposed on a second surface S2 side of the first semiconductor layer 302. A predetermined voltage capable of causing avalanche doubling may be supplied between the first semiconductor region 311 and the second semiconductor region 315. Each pixel 101 may include a ring-shaped semiconductor region 313 of the first conductivity type disposed adjacent to a peripheral portion of the first semiconductor region 311 between the first semiconductor region 311 serving as a cathode and the second semiconductor region 315 serving as an anode. The impurity concentration of the first conductivity type in the semiconductor region 313 is lower than the impurity concentration of the first conductivity type in the first semiconductor region 311 of the first conductivity type serving as a cathode.

[0049] Each pixel 101 may include a semiconductor region 312 of a second conductivity type adjacent to a central portion of the first semiconductor region 311 between a first semiconductor region 311 of a first conductivity type serving as a cathode and a second semiconductor region 315 of a second conductivity type serving as an anode. For example, if the semiconductor region 312 is the same node as the second semiconductor region 315 serving as an anode, the semiconductor region 312 may also function as an anode. The region between the first semiconductor region 311 and the semiconductor region 312 may be an avalanche multiplication region. A semiconductor region 316 of the first conductivity type or the second conductivity type may be disposed between the semiconductor region 312 of the second conductivity type and the second semiconductor region 315 of the second conductivity type serving as an anode. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the first conductivity type in the semiconductor region 313. When the semiconductor region 316 has the second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the second conductivity type in the second conductivity type semiconductor region 312. The semiconductor region 316 may be arranged to surround the periphery of the first conductivity type semiconductor region 313. Furthermore, the semiconductor region 316 may include a portion arranged between the first conductivity type semiconductor region 313 and the second conductivity type second semiconductor region 315 serving as an anode.

[0050] A second conductivity type isolation region 314 may be arranged between adjacent pixels 101 among the plurality of pixels 101. A second conductivity type contact region 318 may be arranged between the second conductivity type isolation region 314 and the first surface S1 so as to be electrically connected to the second conductivity type isolation region 314. The second conductivity type contact region 318 has a higher impurity concentration of the second conductivity type than the impurity concentration of the second conductivity type in the second conductivity type isolation region 314. The second conductivity type isolation region 314 may be arranged so as to be electrically connected to a second conductivity type second semiconductor region 315 serving as an anode. An anode voltage (anode potential) may be supplied to the second conductivity type contact region 318 via a conductive path arranged in the first wiring structure 303, thereby supplying the anode voltage (anode potential) to the second conductivity type second semiconductor region 315 serving as an anode. 8, four contact regions 318 are provided for one pixel 101, but any number of contact regions 318 may be provided for one pixel 101. Alternatively, two or more pixels 101 may be grouped together, and one or more contact regions 318 may be provided for each group.

[0051] An insulating isolation portion 324 may be disposed in the second conductivity type isolation region 314. The insulating isolation portion 324 may include a groove provided in the isolation region 314 and an insulator disposed so as to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. The insulating isolation portion 324 may be referred to as DTI (Deep Trench Isolation). The insulating isolation portion 324 or the groove may be disposed so as to penetrate the first semiconductor layer 302, or may be disposed so as not to penetrate the first semiconductor layer 302. The insulating isolation portion 324 or the groove may electrically separate the second conductivity type isolation region 314 into an isolation region on one pixel 101 side and an isolation region on the adjacent pixel 101 side.

[0052] A pinning layer 331 (shown by a thick line) may be disposed on the second surface S2 side of the second semiconductor region 315 of the second conductivity type serving as an anode. The pinning layer 331 may also be referred to as a fixed charge film. The pinning layer 331 is disposed so as to be in contact with the second surface S2 and may be formed by, for example, atomic layer deposition (ALD). The pinning layer 331 may be formed of, for example, polycrystalline silicon, a hafnium oxide film, or an aluminum oxide film. The pinning layer 331 and the second surface S2 may be covered with an insulating film 321. The insulating film 321 may be, for example, a SiO film, a SiN film, or a SiON film. The second semiconductor region 315 of the second conductivity type serving as an anode may be provided with a concave-convex structure 325. The surface of the concave-convex structure 325 may be covered with the pinning layer 331. The concave-convex structure 325 functions to diffract incident light and lengthen the optical path within the semiconductor layer 302. This is advantageous for improving near-infrared sensitivity.

[0053] The insulating film 321 may be covered with a planarization layer 322. A microlens 323 may be disposed on the planarization layer 322. The example shown in Figures 9A and 9B is a back-illuminated type in which light is incident from the outside onto the second surface S of the semiconductor layer 302 through the microlens 323, but the photoelectric conversion device 100 may also be configured as a front-illuminated type.

[0054] The configuration of the photoelectric conversion device 100 of the first embodiment will be described below with reference to Figures 10 and 11. The photoelectric conversion device 100 of the first embodiment provides an example in which a charge drain section 1350 is applied to the photoelectric conversion device 100 having the configuration according to the first configuration example described with reference to Figures 6, 7A, and 7B. Explanation of matters that overlap with those already described will be omitted. In detail, the photoelectric conversion device of the first embodiment differs from the first configuration example in that it does not include, for example, an insulating isolation section or a concave-convex structure.

[0055] The photoelectric conversion device 100 of the first embodiment has a semiconductor layer 302 (or, from another perspective, a sensor substrate 301) including a pixel array region 12 having a plurality of pixels 101 and a peripheral region 13 arranged around the pixel array region 12. The pixel array region 12 may include an effective pixel region 12E in which pixels (effective pixels) 102 that output signals in response to incident light are arranged, and an OB pixel region 12OB in which light-shielded pixels (OB pixels, or light-shielded pixels) 102 are arranged. The OB pixel region 12OB may be arranged along at least a portion of the periphery of the effective pixel region 12E. The OB pixel region 12OB may typically be arranged to surround the effective pixel region 12E. At least one, and typically multiple, pad electrodes PE may be arranged in the peripheral region 13. In the OB pixel 101, an APD 201 including an anode and a cathode is shielded from light by a light-shielding film LSM. The pixels 101 in the OB pixel region 12OB can have the same configuration as the pixels 101 in the effective pixel region 12E, except that the APDs 201 are shielded from light by a light-shielding film LSM.

[0056] One or more charge draining units 1350 may be arranged in the peripheral region 13. In FIG. 10( a), one charge draining unit 1350 is indicated by a black circle. FIG. 10( b) is a schematic plan view of one charge draining unit 1350. Preferably, the multiple charge draining units 1350 are arranged at a predetermined pitch along each of the four sides of the pixel array region 12. Preferably, the predetermined pitch is larger than the arrangement pitch of the multiple pixels 101 in the pixel array region 12. The multiple charge draining units 1350 may be arranged to form multiple columns along each of the four sides of the pixel array region 12. The multiple charge draining units 1350 may also be arranged in a staggered pattern along each of the four sides of the pixel array region 12.

[0057] As illustrated in Fig. 11, the semiconductor layer 302 has a first surface S1 and a second surface S2. Each pixel 101 arranged in the pixel array region 12 (effective pixel region 12E, OB pixel region 12OB) may have a structure similar to the first configuration example described with reference to Figs. 6, 7A, and 7B. Hereinafter, the description will be made with mutual reference to Figs. 11, 6, 7A, and 7B.

[0058] Each pixel 101 may include a first semiconductor region 311 of a first conductivity type serving as a cathode of the APD 201 and a second semiconductor region 315 of a second conductivity type serving as an anode of the APD 201. The first semiconductor region 311 of the first conductivity type may be disposed on a first surface S1 side of the first semiconductor layer 302, and the second semiconductor region 315 of the second conductivity type may be disposed on a second surface S2 side of the first semiconductor layer 302. A predetermined voltage capable of causing avalanche doubling may be supplied between the first semiconductor region 311 and the second semiconductor region 315. Each pixel 101 may include a semiconductor region 313 of the first conductivity type disposed between the first semiconductor region 311 serving as a cathode and the second semiconductor region 315 serving as an anode, in close proximity to the first semiconductor region 311. The impurity concentration of the first conductivity type in the semiconductor region 313 is lower than the impurity concentration of the first conductivity type in the first semiconductor region 311 of the first conductivity type serving as a cathode.

[0059] Each pixel 101 may include a semiconductor region 312 of a second conductivity type between a first semiconductor region 311 of a first conductivity type serving as a cathode and a second semiconductor region 315 of a second conductivity type serving as an anode. A semiconductor region 316 of a first conductivity type or a second conductivity type may be disposed between the first surface S1 and the semiconductor region 312 of the second conductivity type so as to surround the first semiconductor region 311 of the first conductivity type serving as the cathode. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 is lower than the impurity concentration of the first conductivity type in the semiconductor region 313 serving as the cathode. When the semiconductor region 316 has the second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 is lower than the impurity concentration of the second conductivity type in the semiconductor region 312 of the second conductivity type.

[0060] A semiconductor region 316 of the first conductivity type or the second conductivity type may be disposed between the semiconductor region 312 of the second conductivity type and the second semiconductor region 315 of the second conductivity type serving as an anode. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the first conductivity type in the semiconductor region 313. When the semiconductor region 316 has the second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 may be lower than the impurity concentration of the second conductivity type in the semiconductor region 312 of the second conductivity type.

[0061] A semiconductor region 317 of the first conductivity type may be disposed between the second semiconductor region 315 of the second conductivity type serving as an anode and the semiconductor region 312 of the second conductivity type. The semiconductor region 316 may include a portion disposed between the second semiconductor region 315 of the second conductivity type serving as an anode and the semiconductor region 317 of the first conductivity type, and a portion surrounding the side surface of the semiconductor region 317 of the first conductivity type.

[0062] A second conductivity type isolation region 314 may be arranged between adjacent pixels 101 among the plurality of pixels 101. A second conductivity type contact region 318 may be arranged between the second conductivity type isolation region 314 and the first surface S1 so as to be electrically connected to the second conductivity type isolation region 314. The second conductivity type contact region 318 has a higher impurity concentration of the second conductivity type than the impurity concentration of the second conductivity type in the second conductivity type isolation region 314. The second conductivity type isolation region 314 may be arranged so as to be electrically connected to a second conductivity type second semiconductor region 315 serving as an anode. An anode voltage (anode potential) may be supplied to the second conductivity type contact region 318 via a conductive path arranged in the first wiring structure 303, thereby supplying the anode voltage (anode potential) to the second conductivity type second semiconductor region 315 serving as an anode.

[0063] An insulating isolation portion 324 may be disposed in the second conductivity type isolation region 314. The insulating isolation portion 324 may include a groove provided in the isolation region 314 and an insulator disposed so as to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. The insulating isolation portion 324 may be referred to as DTI (Deep Trench Isolation). The insulating isolation portion 324 or the groove may be disposed so as to penetrate the first semiconductor layer 302, or may be disposed so as not to penetrate the first semiconductor layer 302. The insulating isolation portion 324 or the groove may electrically separate the second conductivity type isolation region 314 into an isolation region on one pixel 101 side and an isolation region on an adjacent pixel 101 side.

[0064] A pinning layer 331 (shown by a thick line) may be disposed on the second surface S2 side of the second semiconductor region 315 of the second conductivity type serving as an anode. The pinning layer 331 may also be referred to as a fixed charge film. The pinning layer 331 is disposed so as to be in contact with the second surface S2 and may be formed by, for example, ALD (Atomic Layer Deposition). The pinning layer 331 may be formed of, for example, polycrystalline silicon, hafnium oxide, or aluminum oxide. The pinning layer 331 and the second surface S2 may be covered with an insulating film 321.

[0065] The peripheral region 13 may include a third semiconductor region 1311 of a first conductivity type disposed on the first surface S1 side and a fourth semiconductor region 1315 of a second conductivity type disposed apart from the third semiconductor region 1311. The fourth semiconductor region 1315 may include an extension portion EP extending parallel to the second surface S2. A predetermined voltage may be supplied between the third semiconductor region 1311 and the fourth semiconductor region 1315. The voltage supplied between the third semiconductor region 1311 and the fourth semiconductor region 1315 may be the same as the voltage supplied between the first semiconductor region 311 serving as an anode and the second semiconductor region 315 serving as a cathode. A pn ​​junction is formed between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type, and is reverse biased by the voltage supplied between the third semiconductor region 1311 and the fourth semiconductor region 1315, thereby functioning as a photodiode.

[0066] The peripheral region 13 may also include a fifth semiconductor region 1313 of the first conductivity type, which has a lower concentration of first conductivity type impurities than the third semiconductor region 1311, between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type. The fifth semiconductor region 1313 may be arranged close to the third semiconductor region 1311. The fifth semiconductor region 1313 of the first conductivity type is arranged to surround a side surface of the third semiconductor region 1311. The fifth semiconductor region 1313 of the first conductivity type may include a portion between the third semiconductor region 1311 and the fourth semiconductor region 1315 that is arranged to be in contact with the third semiconductor region 1311. The third semiconductor region 1311 of the first conductivity type, the fourth semiconductor region 1315 of the second conductivity type, and the fifth semiconductor region 1313 of the first conductivity type may configure a charge drain unit 1350. The fifth semiconductor region 1313 of the first conductivity type can function to reduce the electric field in the vicinity of the third semiconductor region 1311 of the first conductivity type.

[0067] The third semiconductor region 1311 of the first conductivity type may be formed in a region at the same depth (for example, the depth from the first surface S1) as the first semiconductor region 311 of the first conductivity type serving as a cathode of the pixel 101 in the pixel array region 12. Furthermore, the first semiconductor region 311 and the third semiconductor region 1311 may be disposed between the first surface S1 and the first depth. The impurity concentration of the first conductivity type in the third semiconductor region 1311 may be the same as the impurity concentration of the first conductivity type in the first semiconductor region 311 of the pixel 101 in the pixel array region 12. The third semiconductor region 1311 of the first conductivity type may be formed simultaneously with the first semiconductor region 311 of the first conductivity type in the pixel 101 in the pixel array region 12.

[0068] The fourth semiconductor region 1315 of the second conductivity type may be formed in a region at the same depth (e.g., depth from the first surface S1) as the second semiconductor region 315 of the second conductivity type serving as an anode of the pixel 101 in the pixel array region 12. The second semiconductor region 315 and the fourth semiconductor region 1315 may be disposed between the second surface S2 and the second depth. The impurity concentration of the second conductivity type in the fourth semiconductor region 1315 may be the same as the impurity concentration of the second conductivity type in the second semiconductor region 315 of the pixel 101 in the pixel array region 12. The fourth semiconductor region 1315 of the second conductivity type may be formed simultaneously with the second semiconductor region 315 of the second conductivity type in the pixel 101 in the pixel array region 12. The fourth semiconductor region 1315 of the second conductivity type in the peripheral region 13 may be formed integrally with the second semiconductor region 315 of the second conductivity type in the pixel array region 12.

[0069] A semiconductor region 316 of the first conductivity type or the second conductivity type may be disposed between the fifth semiconductor region 1313 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type. When the semiconductor region 316 has the first conductivity type, the impurity concentration of the first conductivity type in the semiconductor region 316 is lower than the impurity concentration of the first conductivity type in the semiconductor region 1313. When the semiconductor region 316 has the second conductivity type, the impurity concentration of the second conductivity type in the semiconductor region 316 is lower than the impurity concentration of the second conductivity type in the semiconductor region 1315 of the second conductivity type. The semiconductor region 316 in the peripheral region 13 may have the same conductivity type and impurity concentration as the semiconductor region 316 in the pixel array region 12. The semiconductor region 316 may be an epitaxially grown layer.

[0070] Light (or photons) LL may be incident on the semiconductor region 316 in the peripheral region 13, for example, through an opening OP for the pad electrode PE or through a region without the light-shielding film LSM. The light LL incident on the semiconductor region 316 in the peripheral region 13 may generate electrons (e-) and holes (h+) through photoelectric conversion. If the charge drain section 1350 is not present in the peripheral region 13, the electrons and holes generated by the light incident on the peripheral region 13 may move to the pixel array region 12 and cause avalanche multiplication. Alternatively, the electrons and holes generated by the light incident on the peripheral region 13 may recombine to generate light, which may be detected by the pixels 101 in the pixel array region 12. Alternatively, the light incident on the peripheral region 13 may cause avalanche multiplication. These may degrade the quality of the image or signal detected by the photoelectric conversion device 100.

[0071] In the first embodiment, the charge drain section 1350 provided in the peripheral region 13 can operate to drain electrons and holes generated by light incident on the peripheral region 13. Here, when the first conductivity type is n-type and the second conductivity type is p-type, the generated electrons are drawn into the third semiconductor region 1311 of the first conductivity type, and the generated holes are drawn into the fourth semiconductor region 1315 of the second conductivity type.

[0072] In the peripheral region 13, a pinning layer 331 (shown by a thick line) may be arranged on the second surface S2 side of the second conductivity type fourth semiconductor region 1315. The pinning layer 331 is arranged to be in contact with the second surface S2 and may be formed by, for example, ALD (Atomic Layer Deposition). The pinning layer 331 may be formed of, for example, polycrystalline silicon, hafnium oxide, or aluminum oxide. The pinning layer 331 and the second surface S2 may be covered with an insulating film 321 such as a SiN film. The pinning layer 331 in the peripheral region 13 may have the same composition as the pinning layer 331 in the pixel array region 12 and may be formed simultaneously with the pinning layer 331 in the pixel array region 12.

[0073] The semiconductor layer 302 may have a second conductivity type isolation region 314 in the boundary region between the pixel array region 12 and the peripheral region 13. The isolation region 314 may be electrically connected to a second conductivity type second semiconductor region 315 and may be supplied with the same potential as the second conductivity type second semiconductor region 315. The second conductivity type isolation region 314 arranged in the boundary region between the pixel array region 12 and the peripheral region 13 may also constitute a charge drain section 1350.

[0074] The light-shielding film LSM may include a light-shielding structure LSS in a boundary region between the pixel array region 12 and the peripheral region 13, for example, in the isolation region 314 in a plan view. In one example, the light-shielding film LSM may be electrically connected to the second semiconductor region 315 of the second conductivity type and / or the fourth semiconductor region 1315 of the second conductivity type via the light-shielding structure LSS. The light-shielding structure LSS may include, for example, one or more walls. The one or more walls may penetrate the pinning layer 331 and be electrically connected to the second semiconductor region 315 of the second conductivity type and / or the fourth semiconductor region 1315 of the second conductivity type.

[0075] The configuration of the photoelectric conversion device 100 of the second embodiment will be described below with reference to Figures 12 and 13. The photoelectric conversion device 100 of the second embodiment provides an example in which a charge discharging section 1350 is applied to the photoelectric conversion device 100 having the configuration according to the first configuration example described with reference to Figures 6, 7A, and 7B. Explanation of matters that overlap with matters already described will be omitted. The photoelectric conversion device 100 of the second embodiment differs from the photoelectric conversion device 100 of the first embodiment in the configuration of the charge discharging section 1350 and / or the voltage supplied to the charge discharging section 1350.

[0076] The photoelectric conversion device 100 of the second embodiment may include a voltage generation unit VG. The voltage generation unit VG may generate a voltage (potential) to be supplied to the third semiconductor region 1311 of the first conductivity type. From another perspective, the voltage generation unit VG may generate a voltage to be supplied between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type. The voltage generation unit VG may generate a voltage (potential) to be supplied to the third semiconductor region 1311 of the first conductivity type by, for example, transforming a voltage supplied to one pad electrode PE of the multiple pad electrodes PE. The voltage generation unit VG may be disposed on, for example, the circuit board 401. Alternatively, the voltage (potential) to be supplied to the third semiconductor region 1311 of the first conductivity type may be supplied from outside the photoelectric conversion device 100.

[0077] The voltage supplied to the charge drain unit 1350, in other words, the voltage supplied between the third semiconductor region 1311 of the first conductivity type and the fourth semiconductor region 1315 of the second conductivity type, is lower than the voltage supplied between the anode and cathode of the pixel array region 12. In one example, the voltage supplied to the charge drain unit 1350 may be equal to or lower than half the voltage supplied between the anode and cathode of the pixel array region 12. Alternatively, the voltage (potential) supplied to the third semiconductor region 1311 of the first conductivity type may be the ground potential of the photoelectric conversion device 100. This is advantageous for simplifying the structure of the photoelectric conversion device 100.

[0078] If the electric field generated around the third semiconductor region 1311 of the first conductivity type is sufficiently weak, the fifth semiconductor region 1313 provided in the charge discharging section 1350 in the first embodiment may be removed. Figures 12 and 13 show an example of a charge discharging section 1350 in which the fifth semiconductor region 1313 is removed. This voltage can also be applied to a configuration having an insulating isolation section as shown in Figures 7A and 7B.

[0079] The configuration of a photoelectric conversion device 100 according to the third embodiment will be described below with reference to FIGS. 14, 15A, and 15B. The photoelectric conversion device 100 according to the third embodiment provides an example in which a charge drain section 1350 is applied to a photoelectric conversion device 100 having the configuration according to the first configuration example described with reference to FIGS. 6, 7A, and 7B. Explanations of matters that have already been described will be omitted. The photoelectric conversion device 100 according to the third embodiment differs from the photoelectric conversion device 100 according to the first embodiment in that it includes an insulating isolation section 324. Furthermore, for example, the photoelectric conversion device 100 according to the third embodiment differs from the photoelectric conversion device 100 according to the first embodiment in that it includes a concave-convex structure 325. The concave-convex structure 325 shown in FIGS. 15A and 15B is the same as the concave-convex structure 325 shown in FIGS. 7A and 7B.

[0080] A second conductivity type isolation region 314 may be arranged between adjacent pixels 101 among the plurality of pixels 101. Similarly, a second conductivity type isolation region 314 may be arranged between the pixel array region 12 and the peripheral region 13. A second conductivity type contact region 318 may be arranged between the second conductivity type isolation region 314 and the first surface S1 so as to be electrically connected to the second conductivity type isolation region 314. The second conductivity type impurity concentration in the second conductivity type contact region 318 is higher than the second conductivity type impurity concentration in the second conductivity type isolation region 314. The second conductivity type isolation region 314 may be arranged so as to be electrically connected to a second conductivity type second semiconductor region 315 serving as an anode. An anode voltage (anode potential) may be supplied to the second conductivity type contact region 318 via a conductive path arranged in the first wiring structure 303, thereby supplying the anode voltage (anode potential) to the second conductivity type second semiconductor region 315 serving as an anode.

[0081] In the pixel array region 12, an insulating isolation portion 324 may be disposed in the second conductivity type isolation region 314. Similarly, in the peripheral region 13, an insulating isolation portion 324 may be disposed in the second conductivity type isolation region 314. The insulating isolation portion 324 may include a groove provided in the isolation region 314 and an insulator disposed to cover at least the surface (inner surface) of the groove. The insulator may be a film, and the inside of the film may be filled with an insulating material or a conductive material. Such a film may be the pinning layer 331. The insulating isolation portion 324 may be referred to as a deep trench isolation (DTI). The insulating isolation portion 324 or the groove may be disposed to penetrate the first semiconductor layer 302, or may be disposed not to penetrate the first semiconductor layer 302. Furthermore, as shown in FIG. 15A , multiple insulating isolation portions may be provided to sandwich an opening OP. The difference in refractive index between the insulating material of the insulating isolation portion and the first semiconductor layer 302 can reduce the incidence of light through the opening OP.

[0082] In the pixel array region 12, the insulating isolation portion 324 or trench may electrically separate the second conductivity type isolation region 314 into an isolation region on one pixel 101 side and an isolation region on the adjacent pixel 101 side. Similarly, in the peripheral region 13, the insulating isolation portion 324 or trench may be arranged to electrically separate the second conductivity type isolation region 314 into a first isolation region 314A on the pixel array region 12 side and a second isolation region 314B on the peripheral region 13 side. The first wiring structure 303 stacked on the first semiconductor layer 302 may have a first conductive path that applies a potential to the first isolation region 314A and a second conductive path that applies a potential to the second isolation region 314B. The first conductive path and the second conductive path may be electrically connected within the first wiring structure 303. The conductive path may include, for example, a contact plug, a wiring, or the like.

[0083] The configuration of the photoelectric conversion device 100 of the fourth embodiment will be described below with reference to FIGS. 16A and 16B. The photoelectric conversion device 100 of the fourth embodiment provides an example in which a charge drain section 1350 is applied to the photoelectric conversion device 100 having the configuration according to the first configuration example described with reference to FIGS. 6, 7A, and 7B. Explanation of matters that have already been described will be omitted. The photoelectric conversion device 100 of the fourth embodiment has a configuration in which the second conductivity type semiconductor region 1315 is removed from the photoelectric conversion device 100 of the third embodiment. Note that the concave-convex structure 325 shown in FIGS. 16A and 16B is the same as the concave-convex structure 325 shown in FIGS. 7A and 7B.

[0084] In the fourth embodiment, the charge drain portion 1350 provided in the peripheral region 13 can also operate to drain electrons and holes generated by light incident on the peripheral region 13. Here, when the first conductivity type is n-type and the second conductivity type is p-type, the generated electrons can be attracted to the third semiconductor region 1311 of the first conductivity type and drained. On the other hand, the generated holes can be drained through the second conductivity type semiconductor region formed near the surface (near the second surface S2) of the semiconductor region 316 by charges induced by the pinning layer 331 in the vicinity of the surface, the isolation region 314, and the second conductivity type second semiconductor region 315. In this way, the second conductivity type semiconductor region formed in the surface region of the semiconductor region 316 by charges induced by the pinning layer 331 functions in the same manner as the fourth semiconductor region 1315 (extension portion EP) described above. When the second conductivity type is p-type, the charges induced by the pinning layer 331 are holes.

[0085] The configuration of the photoelectric conversion device 100 of the fifth embodiment will be described below with reference to FIG. 17. The photoelectric conversion device 100 of the seventh embodiment provides an example in which a charge drain section 1350 is applied to a photoelectric conversion device 100 having a configuration according to the second configuration example described with reference to FIGS. 8, 9A, and 9B. Explanation of matters that have already been described will be omitted. The first to fourth embodiments can also be applied to a photoelectric conversion device 100 having a configuration according to the second configuration example described with reference to FIGS. 8, 9A, and 9B. The concave-convex structure 325 shown in FIG. 17 is the same as the concave-convex structure 325 shown in FIGS. 9A and 9B.

[0086] Hereinafter, a photoelectric conversion system incorporating the photoelectric conversion device exemplarily described through the first to fifth embodiments will be described. An example of a photoelectric conversion system is shown in FIG. 18. The photoelectric conversion devices described in the first to fifth embodiments are applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion system.

[0087] The photoelectric conversion system is configured as, for example, an imaging system SYS. The imaging system SYS is a camera or an information terminal having a photographing function. The imaging device IS may further include a package PKG that houses the photoelectric conversion device 100 configured as an imaging device IC. The package PKG may include a base to which the imaging device IC is fixed, a lid facing the imaging device IC, and a connecting member that connects terminals provided on the base to terminals provided on the imaging device IC. The imaging device IS may also have multiple imaging device ICs mounted side by side in a common package PKG. The imaging device IS may also have imaging device ICs and other semiconductor device ICs mounted one on top of the other in a common package PKG.

[0088] The imaging system SYS may include an optical system OU that forms an image on the imaging device IS. The imaging system SYS may also include at least one of a control device CU that controls the imaging device IS, a processing device PU that processes signals obtained from the imaging device IS, and a display device DU that displays images obtained from the imaging device IS. The imaging system SYS may also include a storage device MU that stores images obtained from the imaging device IS.

[0089] FIG. 19(a) illustrates an example of the configuration of a photoelectric conversion system applied to an in-vehicle camera. The photoelectric conversion system 2300 may include a photoelectric conversion device 100 configured as an imaging device 2310. The photoelectric conversion system 2300 includes an image processing unit 2312 that performs image processing on multiple pieces of image data acquired by the imaging device 2310, and a parallax acquisition unit 2314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 2300. The photoelectric conversion system 2300 also includes a distance acquisition unit 2316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 2318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 2314 and the distance acquisition unit 2316 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 2318 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0090] The photoelectric conversion system 2300 is connected to a vehicle information acquisition device 2320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 2300 is also connected to a control ECU 2330, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 2318. The photoelectric conversion system 2300 is also connected to an alarm device 2340 that issues an alarm to the driver based on the determination result of the collision determination unit 2318. For example, if the collision determination unit 2318 determines that a collision is highly likely, the control ECU 2330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The alarm device 2340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, or vibrating a seat belt or steering wheel. In this embodiment, the photoelectric conversion system 2300 captures images of the surroundings of the vehicle, for example, the front or rear. 19(b) shows a photoelectric conversion system configured to capture an image of the area ahead of the vehicle (image capture range 2350). A vehicle information acquisition device 2320 sends instructions to the photoelectric conversion system 2300 or the image capture device 2310. This configuration can further improve the accuracy of distance measurement.

[0091] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0092] 20 shows an example of the configuration of a photoelectric conversion system configured as a range image sensor. Range image sensor 40 includes an optical system 407, a photoelectric conversion device 408, an image processing circuit 404, a monitor 405, and a memory 406. Range image sensor 40 is able to obtain a range image according to the distance to the subject by receiving light (modulated light or pulsed light) that is projected from a light source device 409 toward the subject and reflected from the surface of the subject.

[0093] The optical system 407 is configured with one or more lenses, and guides image light (incident light) from the subject to the photoelectric conversion device 408, forming an image on the light receiving surface (sensor unit) of the photoelectric conversion device 408. The photoelectric conversion device of each of the above-described embodiments is applied as the photoelectric conversion device 408, and a distance signal indicating a distance determined from a light receiving signal output from the photoelectric conversion device 408 is supplied to the image processing circuit 404.

[0094] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 408. The distance image (image data) obtained by this image processing is then supplied to a monitor 405 for display, or supplied to a memory 406 for storage (recording). In the range image sensor 40 configured in this way, by applying the above-described photoelectric conversion device, the pixel characteristics are improved, making it possible to obtain, for example, a more accurate range image.

[0095] Fig. 21 illustrates an example of the configuration of a photoelectric conversion system configured as an endoscopic surgery system. Fig. 21 illustrates a state in which an operator (doctor) 1131 is performing surgery on a patient 1132 on a patient bed 1133 using an endoscopic surgery system 1150. As illustrated, the endoscopic surgery system 1150 is composed of an endoscope 1100, a surgical tool 1110, and a cart 1134 on which various devices for endoscopic surgery are mounted.

[0096] The endoscope 1100 is composed of a lens barrel 1101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 1132, and a camera head 1102 connected to the base end of the lens barrel 1101. In the example shown, the endoscope 1100 is configured as a so-called rigid lens barrel having a rigid lens barrel 1101, but the endoscope 1100 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0097] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 1101. A light source device 1203 is connected to the endoscope 1100, and light generated by the light source device 1203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 1101, and is irradiated via the objective lens towards an observation target inside the body cavity of the patient 1132. The endoscope 1100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0098] An optical system and a photoelectric conversion device are provided inside the camera head 1102, and light reflected from an observation object (observation light) is focused onto the photoelectric conversion device by the optical system. The observation light is photoelectrically converted by the photoelectric conversion device to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observation image. The photoelectric conversion device may be any of the photoelectric conversion devices described in the above-described embodiments. The image signal is sent to a camera control unit (CCU) 1135 as RAW data.

[0099] The CCU 1135 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and performs overall control of the operations of the endoscope 1100 and the display device 1136. Furthermore, the CCU 1135 receives an image signal from the camera head 1102, and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0100] The display device 1136, under the control of the CCU 1135, displays an image based on an image signal that has been image processed by the CCU 1135. The light source device 1203 is composed of a light source such as an LED (Light Emitting Diode), and supplies irradiating light to the endoscope 1100 when photographing the surgical site, etc. The input device 1137 is an input interface for the endoscopic surgery system 1150. A user can input various information and commands to the endoscopic surgery system 1150 via the input device 1137. The treatment tool control device 1138 controls the driving of the energy treatment tool 1112 for cauterizing tissue, incising, sealing blood vessels, etc.

[0101] The light source device 1203, which supplies illumination light to the endoscope 1100 when photographing the surgical site, can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 1203. In this case, it is also possible to capture images corresponding to each RGB color in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 1102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0102] Furthermore, the light source device 1203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 1102 in synchronization with the timing of the change in the light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0103] The light source device 1203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation utilizes, for example, the wavelength dependency of light absorption in body tissue. Specifically, specific tissue, such as blood vessels on the surface of the mucous membrane, can be photographed with high contrast by irradiating light with a narrower band than the light (i.e., white light) used in normal observation. Alternatively, special light observation may involve fluorescence observation, in which an image is obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissue and observing the fluorescence from the body tissue, or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 1203 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0104] FIG. 22(a) illustrates an example of the configuration of a photoelectric conversion system configured as glasses 1600 (smart glasses). The glasses 1600 include a photoelectric conversion device 1602 to which the photoelectric conversion device 100 is applied. The photoelectric conversion device 1602 is the photoelectric conversion device described in each of the above embodiments. A display device including a light-emitting device such as an OLED or LED may be provided on the rear side of the lens 1601. The photoelectric conversion device 1602 may be one or more. A combination of multiple types of photoelectric conversion devices may also be used. The arrangement position of the photoelectric conversion device 1602 is not limited to that shown in FIG. 22(a).

[0105] The glasses 1600 further include a control device 1603. The control device 1603 functions as a power source that supplies power to the photoelectric conversion device 1602 and the display device. The control device 1603 also controls the operations of the photoelectric conversion device 1602 and the display device. The lens 1601 is formed with an optical system for focusing light onto the photoelectric conversion device 1602.

[0106] FIG. 22(b) illustrates the configuration of a photoelectric conversion system configured as glasses 1610 (smart glasses). The glasses 1610 include a control device 1612, which includes a photoelectric conversion device corresponding to the photoelectric conversion device 1602 and a display device. A lens 1611 includes an optical system for projecting light emitted from the photoelectric conversion device and the display device, and an image is projected onto the lens 1611. The control device 1612 functions as a power source for supplying power to the photoelectric conversion device and the display device, and controls the operation of the photoelectric conversion device and the display device. The control device may include a gaze detection unit that detects the gaze of the wearer. Infrared light may be used for gaze detection. The infrared light emitter emits infrared light toward the eyeball of a user gazing at a displayed image. An imaging unit with a light-receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. A reduction unit for reducing light from the infrared light emitter to the display unit in a planar view reduces degradation of image quality.

[0107] The user's line of sight with respect to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be applied to gaze detection using an image of the eyeball. As an example, a gaze detection method based on a Purkinje image formed by reflection of irradiated light on the cornea can be used. More specifically, gaze detection processing is performed based on the pupil-corneal reflex method. Using the pupil-corneal reflex method, a gaze vector representing the direction (rotation angle) of the eyeball is calculated based on the image of the pupil and the Purkinje image contained in the image of the eyeball, thereby detecting the user's gaze.

[0108] The display device of this embodiment may have a photoelectric conversion device having a light receiving element, and may control the image displayed on the display device based on information about the user's line of sight from the photoelectric conversion device.

[0109] Specifically, the display device determines a first field of view area where the user gazes and a second field of view area other than the first field of view area based on the line-of-sight information. The first field of view area and the second field of view area may be determined by a control device of the display device, or may be determined by an external control device and received. In the display area of ​​the display device, the display resolution of the first field of view area may be controlled to be higher than the display resolution of the second field of view area. In other words, the resolution of the second field of view area may be lower than that of the first field of view area.

[0110] The display area may include a first display area and a second display area different from the first display area, and a high-priority area may be determined from the first display area and the second display area based on line-of-sight information. The first and second field-of-view areas may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0111] Note that AI may be used to determine the first field of view area and areas with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from an image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the photoelectric conversion device, or an external device. If included in an external device, it is transmitted to the display device via communication.

[0112] When display control is performed based on visual recognition detection, the present invention is preferably applied to smart glasses that further include a photoelectric conversion device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0113] The photoelectric conversion device 100 of the above embodiment may be applied to electronic devices such as smartphones and tablets, as exemplified below. Fig. 23 is a diagram showing an example of the appearance of an electronic device 120 equipped with the photoelectric conversion device 100 configured as a solid-state imaging device. Fig. 23A shows the front side of the electronic device 120, and Fig. 23B shows the back side of the electronic device 120.

[0114] 23A, a display 121 for displaying an image is disposed in the center of the surface of the electronic device 120. Then, along the upper side of the surface of the electronic device 120, front cameras 122-1 and 122-2 using the photoelectric conversion device 100, an IR light source 123 for emitting infrared light, and a visible light source 124 for emitting visible light are disposed.

[0115] Also, as shown in B of Figure 23, rear cameras 125-1 and 125-2 using photoelectric conversion device 100, an IR light source 126 that emits infrared light, and a visible light source 127 that emits visible light are arranged along the upper edge of the back of electronic device 120.

[0116] In the electronic device 120 configured as described above, by applying the above-described photoelectric conversion device 100, it is possible to capture images with higher sensitivity, for example. The photoelectric conversion device 100 can also be applied to other electronic devices, such as infrared sensors, distance measurement sensors using active infrared light sources, security cameras, and personal or biometric authentication cameras. This can improve the sensitivity and performance of these electronic devices. Furthermore, it is possible to achieve low power consumption of the system by reducing the power consumption of the light source.

[0117] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0118] 12: pixel array region, 13: peripheral region, 301: sensor substrate, 302: first semiconductor layer, 303: first wiring structure, S1: first surface, S2: second surface, 311: first semiconductor region, 315: second semiconductor region, 1311: third semiconductor region, 1315: fourth semiconductor region, 1313: fifth semiconductor region

Claims

1. A photoelectric conversion device having a semiconductor layer including a pixel array region having a plurality of pixels and a peripheral region arranged around the pixel array region, the semiconductor layer has a first surface and a second surface; each pixel in the pixel array region includes a first semiconductor region of a first conductivity type arranged on the first surface side and a second semiconductor region of a second conductivity type arranged on the second surface side, and a predetermined voltage capable of causing an avalanche multiplication operation is supplied between the first semiconductor region and the second semiconductor region; the peripheral region includes a third semiconductor region of the first conductivity type arranged on the first surface side, a fourth semiconductor region of the second conductivity type arranged apart from the third semiconductor region, and a fifth semiconductor region of the first conductivity type arranged between the third semiconductor region and the fourth semiconductor region and adjacent to the third semiconductor region, a concentration of the impurity of the first conductivity type in the fifth semiconductor region is lower than a concentration of the impurity of the first conductivity type in the third semiconductor region, and a voltage is supplied between the third semiconductor region and the fourth semiconductor region; A photoelectric conversion device characterized by:

2. the voltage supplied between the third semiconductor region and the fourth semiconductor region is the predetermined voltage; 2. The photoelectric conversion device according to claim 1.

3. the fifth semiconductor region is disposed so as to surround the third semiconductor region; 3. The photoelectric conversion device according to claim 1 or 2.

4. A photoelectric conversion device having a semiconductor layer including a pixel array region having a plurality of pixels and a peripheral region arranged around the pixel array region, the semiconductor layer has a first surface and a second surface; each pixel in the pixel array region includes a first semiconductor region of a first conductivity type arranged on the first surface side, a second semiconductor region of a second conductivity type arranged on the second surface side, and a sixth semiconductor region of the second conductivity type arranged between the first semiconductor region and the second semiconductor region, and a predetermined voltage capable of causing an avalanche multiplication operation is supplied between the first semiconductor region and the second semiconductor region; an avalanche multiplication region is formed between the first semiconductor region and the sixth semiconductor region, and the peripheral region includes a third semiconductor region of the first conductivity type arranged on the first surface side, and a fourth semiconductor region of the second conductivity type arranged spaced apart from the third semiconductor region, a voltage lower than the predetermined voltage is supplied between the third semiconductor region and the fourth semiconductor region; a depth of the third semiconductor region from the first surface is equal to a depth of the first semiconductor region from the first surface; A photoelectric conversion device characterized by:

5. a depth of the third semiconductor region from the first surface is equal to a depth of the first semiconductor region from the first surface; 4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

6. a depth of the fourth semiconductor region from the first surface is equal to a depth of the second semiconductor region from the first surface; 6. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

7. further including a pinning layer disposed in contact with the second semiconductor region and the fourth semiconductor region; 7. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

8. the second conductivity type isolation region is disposed between the pixel array region and the peripheral region; 8. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

9. the fourth semiconductor region and the isolation region are electrically connected to each other; 9. The photoelectric conversion device according to claim 8.

10. An insulating isolation portion is provided in the isolation region.

10. The photoelectric conversion device according to claim 8 or 9.

11. the insulating isolation portion is disposed so as to penetrate the semiconductor layer.

11. The photoelectric conversion device according to claim 10.

12. the insulating separation portion is arranged so as to electrically separate the separation region into a first separation region on the pixel array region side and a second separation region on the peripheral region side.

12. The photoelectric conversion device according to claim 11.

13. a first conductive path for applying a potential to the first isolation region and a second conductive path for applying a potential to the second isolation region are provided in a wiring structure stacked on the semiconductor layer; 13. The photoelectric conversion device according to claim 12.

14. the first conductive path and the second conductive path are electrically connected in the wiring structure.

14. The photoelectric conversion device according to claim 13.

15. a groove is provided in the separation region; a pinning layer disposed so as to contact the second semiconductor region and the fourth semiconductor region and to cover a surface of the groove; 15. The photoelectric conversion device according to claim 8, wherein the first and second electrodes are electrically connected to each other.

16. the second conductivity type isolation region is disposed between adjacent pixels in the plurality of pixels; 16. The photoelectric conversion device according to claim 8, wherein the first and second electrodes are electrically connected to each other.

17. further comprising a light-shielding film disposed on the second surface; the light-shielding film is electrically connected to the fourth semiconductor region.

17. The photoelectric conversion device according to claim 1.

18. a plurality of third semiconductor regions including the third semiconductor region are arranged at a predetermined pitch in the peripheral region; the predetermined pitch is larger than the arrangement pitch of the plurality of pixels; 18. The photoelectric conversion device according to claim 1.

19. the fifth semiconductor region is disposed apart from the fourth semiconductor region; 4. The photoelectric conversion device according to claim 1, wherein the first and second electrodes are electrically connected to each other.

20. the fourth semiconductor region includes a portion extending from the second surface to the first surface, the extending portion is disposed between the first semiconductor region and the third semiconductor region, The separation region includes the extending portion.

17. The photoelectric conversion device according to claim 8, wherein the first and second electrodes are electrically connected to each other.

21. an end of the extending portion spaced apart from the first surface; 21. The photoelectric conversion device according to claim 20.

22. The photoelectric conversion device according to any one of claims 1 to 21, a signal processing unit that processes a signal output from the photoelectric conversion device.

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