Semiconductor Devices

Abstract

To provide semiconductor devices that improve high-frequency characteristics.SOLUTION: A semiconductor device has an insulating layer, a semiconductor layer, and a control electrode. The semiconductor layer is provided on the insulating layer and includes a first semiconductor region of first conductivity type, a second semiconductor region of first conductivity type spaced apart from the first semiconductor region, and a third semiconductor region of second conductivity type provided between the first and second semiconductor regions. The first and third semiconductor regions are aligned in a first direction along an interface between the insulating layer and the semiconductor layer. The control electrode is provided over the semiconductor layer through the first insulating film and includes first and third control sections aligned in the first direction. The first control section is provided between the second and third control sections and is electrically insulated from the second and third control sections by the second insulating film. The third semiconductor region is located between the insulating layer and the first control section.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Switching transistors are required to have improved high frequency characteristics. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] IEEE ELECTRON DEVICE LETTERS, VOL. 14, NO.5, 1993 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device that improves high frequency characteristics. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes an insulating layer, a semiconductor layer, and a control electrode. The semiconductor layer is provided on the insulating layer and includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type spaced apart from the first semiconductor region, and a third semiconductor region of a second conductivity type provided between the first semiconductor region and the second semiconductor region. The first to third semiconductor regions are aligned in a first direction along the interface between the insulating layer and the semiconductor layer. The control electrode is provided on the semiconductor layer via a first insulating film, and the first insulating film prevents the semiconductor region from being electrically connected to the control electrode. layer The semiconductor device includes first to third control portions that are electrically insulated from the insulating layer and aligned in the first direction. The first control portion is provided between the second control portion and the third control portion and is electrically insulated from the second control portion and the third control portion by a second insulating film. The third semiconductor region is located between the insulating layer and the first control portion. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment; [Figure 2] 1 is a schematic plan view showing a semiconductor device according to an embodiment; [Figure 3] FIG. 2 is another schematic cross-sectional view showing the semiconductor device according to the embodiment. [Figure 4] FIG. 2 is a schematic diagram showing an equivalent circuit of the semiconductor device according to the embodiment. [Figure 5] 1 is a graph showing characteristics of a semiconductor device according to an embodiment. [Figure 6] 10 is a graph showing other characteristics of the semiconductor device according to the embodiment. [Figure 7] 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 8] 8A to 8C are schematic cross-sectional views showing the manufacturing process following FIG. 7. [Figure 9] 9A to 9C are schematic cross-sectional views showing the manufacturing process following FIG. 8. [Figure 10] 10A to 10C are schematic cross-sectional views showing the manufacturing process following FIG. 9. [Figure 11] 10A to 10C are schematic cross-sectional views illustrating another manufacturing process of the semiconductor device according to the embodiment. [Figure 12] 12A to 12C are schematic cross-sectional views showing the manufacturing process following FIG. 11. [Figure 13] 1A to 1C are schematic plan views illustrating a manufacturing process of a semiconductor device according to an embodiment. [Figure 14] 14 is a schematic plan view showing the manufacturing process following FIG. 13. [Figure 15] 10 is another schematic plan view showing the manufacturing process of the semiconductor device according to the embodiment. [Figure 16] 16 is a schematic plan view showing the manufacturing process following FIG. 15. [Figure 17] FIG. 10 is a schematic plan view showing a semiconductor device according to a modified example of the embodiment. [Figure 18] FIG. 10 is a schematic diagram showing an equivalent circuit of a semiconductor device according to a modified example of the embodiment. [Figure 19]10 is a graph showing characteristics of a semiconductor device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a MOS transistor having an SOI (Silicon on Insulator) structure. The semiconductor device 1 is used, for example, as a high-frequency switching device.

[0010] 1, the semiconductor device 1 includes, for example, a substrate 10, an insulating layer 20, a semiconductor layer 30, a control electrode 40, and an interlayer insulating film 50. The substrate 10 is a semiconductor substrate or an insulating substrate. The substrate 10 is, for example, a silicon substrate. The embodiment is not limited to this example, and, for example, the substrate 10 and the insulating layer 20 may be integrated.

[0011] The insulating layer 20 is provided on the substrate 10. The insulating layer 20 is, for example, a silicon oxide layer. The semiconductor layer 30 is provided on the insulating layer 20. The semiconductor layer 30 is, for example, a silicon layer.

[0012] The control electrode 40 is provided on the semiconductor layer 30 via a first insulating film 41. The first insulating film 41 electrically insulates the control electrode 40 from the semiconductor layer 30. The first insulating film 41 is, for example, a gate insulating film. The first insulating film 41 is, for example, a silicon oxide film. The interlayer insulating film 50 is provided so as to cover the control electrode 40 and the semiconductor layer 30. The interlayer insulating film 50 is, for example, a silicon oxide film.

[0013] The semiconductor layer 30 includes a first semiconductor region 31 of a first conductivity type, a second semiconductor region 33 of the first conductivity type, and a third semiconductor region 34 of the second conductivity type. 3 and a semiconductor region 35. In the following description, the first conductivity type is referred to as n-type and the second conductivity type is referred to as p-type.

[0014] The first semiconductor region 31 is, for example, an n-type source region. The second semiconductor region 33 is, for example, an n-type drain region. The third semiconductor region 35 is, for example, a p-type body region. The first semiconductor region 31, the second semiconductor region 33, and the third semiconductor region 35 are aligned in a first direction, for example, the X direction, along the interface between the insulating layer 20 and the semiconductor layer 30. The third semiconductor region 35 is provided between the first semiconductor region 31 and the second semiconductor region 33. The third semiconductor region 35 is also located between the insulating layer 20 and the control electrode 40.

[0015] The control electrode 40 includes a first control unit GG, a second control unit GS, and a third control unit GD. The first control unit GG, the second control unit GS, and the third control unit GD are aligned in a first direction. The first control unit GG is provided between the second control unit GS and the third control unit. The second control unit GS is provided, for example, on the source side, and the third control unit GD is provided, for example, on the drain side. The first direction is the so-called gate length direction.

[0016] The first control unit GG faces the second control unit GS and the third control unit GD via the second insulating film 43. The second insulating film 43 electrically insulates the second control unit GS and the third control unit GD from the first control unit GG.

[0017] For example, sidewalls 47 are provided on both sides of the control electrode 40. The sidewalls 47 are provided on the respective side surfaces of the second control portion GS and the third control portion GD. The sidewalls 47 are, for example, silicon oxide films or silicon nitride films.

[0018] The semiconductor layer 30 further includes a fourth semiconductor region 37S of the second conductivity type and a fifth semiconductor region 37D of the second conductivity type. The fourth semiconductor region 37S is provided between the first semiconductor region 31 and the third semiconductor region 35. The fifth semiconductor region 37D is provided between the second semiconductor region 33 and the third semiconductor region 35. The fourth semiconductor region 37S and the fifth semiconductor region 37D are so-called halo regions, and contain a higher concentration of second conductivity type impurities than the second conductivity type impurities in the third semiconductor region 35.

[0019] 1, the third semiconductor region 35 is provided between the insulating layer 20 and the first control unit GG. The fourth semiconductor region 37S is provided, for example, between the insulating layer 20 and the second control unit GS. The fifth semiconductor region 37D is provided, for example, between the insulating layer 20 and the third control unit GD.

[0020] The first semiconductor region 31 is provided so as to be in contact with the first insulating film 41. The first semiconductor region 31 includes an extension portion 31e located below the sidewall 47. The extension portion 31e extends along the first insulating film 41 between the insulating layer 20 and the second control portion GS. In other words, the extension portion 31e extends between the fourth semiconductor region 37S and the first insulating film 41.

[0021] The second semiconductor region 33 is also provided so as to be in contact with the first insulating film 41. The second semiconductor region 33 includes an extension portion 33e located below another sidewall 47. The extension portion 33e extends along the first insulating film 41 between the insulating layer 20 and the third control portion GD. In other words, the extension portion 33e extends between the fifth semiconductor region 37D and the first insulating film 41.

[0022] The semiconductor device 1 further includes silicide regions 51, 53, 55S, 55G, and 55D. The silicide region 51 is provided on the first semiconductor region 31. The silicide region 53 is provided on the second semiconductor region 33. The silicide region 55G is provided on the first control unit GG. The silicide regions 55S and 55D are provided on the second control unit GS and the third control unit GD, respectively. Note that if the second control unit GS and the third control unit GD contribute to at least a portion of the gate resistance Rgd and the gate resistance Rgs, there may be regions where the silicide regions 55S and 55D are not provided. Hereinafter, the silicide regions 55G, 55S, and 55D may be referred to as the silicide region 55 without distinction.

[0023] Fig. 2 is a schematic plan view showing the semiconductor device 1 according to the embodiment. Fig. 2 is a plan view showing the control electrode 40 on the semiconductor layer 30. Note that Fig. 1 is a cross-sectional view taken along line AA shown in Fig. 2.

[0024] 2, the semiconductor layer 30 is surrounded by STI (Shallow Trench Isolation) in a plan view. The STI is, for example, a silicon oxide layer. The control electrode 40 includes a plurality of first control parts GG extending in a second direction, for example, the Y direction, on the semiconductor layer 30. The plurality of first control parts GG are provided on the semiconductor layer 30 so as to be connected to an extension part GEX extending in, for example, the X direction.

[0025] The second control unit GS and the third control unit GD are provided on both sides of the first control unit GG in the X direction, and face the first control unit GG via the second insulating film 43. Furthermore, the second control unit GS and the third control unit GD each face the lead-out unit GEX of the first control unit GG via the second insulating film 43.

[0026] The first control unit GG, the second control unit GS, and the third control unit GD each have an end GGE, an end GSE, and an end GDE extending over the STI. The end GSE of the second control unit GS is spaced apart from the end GDE of the third control unit GD across the end GGE of the first control unit GG.

[0027] The first control unit GG has a contact unit GGC provided on the STI. The lead unit GEX extends onto the STI and connects to the contact unit GGC. A contact plug GGP is connected to the contact unit GGC via a silicide region 55G (see FIG. 1). The contact plug GGP extends into the interlayer insulating film 50 (see FIG. 1) and electrically connects the first control unit GG to a control wiring (see FIG. 4) provided on the interlayer insulating film 50.

[0028] The second control unit GS has a contact portion GSC provided on the STI. The contact portion GSC is provided so as to connect to an end portion GSE of the second control unit GS. A contact plug GSP is connected to the contact portion GSC via a silicide region 55S (see FIG. 1). The contact plug GSP extends into the interlayer insulating film 50 (see FIG. 1) and electrically connects the second control unit GS to another control wiring (see FIG. 4) provided on the interlayer insulating film 50.

[0029] The third control unit GD has a contact unit GDC provided on the STI. The contact unit GDC is provided so as to connect to the end GDE of the third control unit GD. A contact plug GDP is connected to the contact unit GDC via a silicide region 55D (see FIG. 1). The contact plug GDP extends into the interlayer insulating film 50 (see FIG. 1) and electrically connects the third control unit GD to yet another control wiring (see FIG. 4) provided on the interlayer insulating film 50.

[0030] The first semiconductor regions 31 and the second semiconductor regions 33 are arranged alternately in a first direction, for example, the X direction. A first control unit GG, a second control unit GS, and a third control unit GD are arranged between the first semiconductor region 31 and the second semiconductor region 33 in a plan view. A contact plug SP is connected to the first semiconductor region 31 via a silicide region 51 (see FIG. 1), and a contact plug DP is connected to the second semiconductor region 33 via a silicide region 53 (see FIG. 1). The contact plugs SP and DP extend in the interlayer insulating film 50 (see FIG. 1) and electrically connect input / output lines (not shown) provided on the interlayer insulating film 50 to the first semiconductor region 31 and the second semiconductor region 33.

[0031] The semiconductor layer 30 further includes a sixth semiconductor region 39 of the second conductivity type. The sixth semiconductor region 39 is, for example, a body contact region. The sixth semiconductor region 39 is provided at a position facing the first semiconductor region 31 and the second semiconductor region 33 in a plan view. A contact plug BP is connected to the sixth semiconductor region 39 via a silicide region 57 (see FIG. 3). The contact plug BP extends into the interlayer insulating film 50 (see FIG. 1) and is in contact with a bias line (not shown) provided on the interlayer insulating film 50. 6 The semiconductor region 39 is electrically connected.

[0032] The lead portion GEX of the first control portion GG extends between the first semiconductor region 31 and the sixth semiconductor region 39 and between the second semiconductor region 33 and the sixth semiconductor region 39 in a plan view.

[0033] The control electrode 40 further includes a fourth control portion GB. In a plan view, the fourth control portion GB is located between the sixth semiconductor region 39 and the lead portion GEX of the first control portion GG. The lead portion GEX extends between the second control portion GS and the fourth control portion GB, and between the third control portion GD and the fourth control portion GB. The fourth control portion GB faces the lead portion GEX via a third insulating film 45. The fourth control portion GB is electrically connected to the first control portion GG at the contact portion GGC of the first control portion GG. The third insulating film 45 is, for example, a silicon oxide film.

[0034] 3 is another schematic cross-sectional view showing the semiconductor device 1 according to the embodiment, taken along the line BB in FIG.

[0035] 3, the semiconductor layer 30 further includes a seventh semiconductor region 37B of the second conductivity type. The seventh semiconductor region 37B is provided between the third semiconductor region 35 and the sixth semiconductor region 39. The seventh semiconductor region 37B contains a higher concentration of second conductivity type impurities than the concentration of second conductivity type impurities in the third semiconductor region 35. The sixth semiconductor region 39 contains a higher concentration of second conductivity type impurities than the concentration of second conductivity type impurities in the seventh semiconductor region 37B.

[0036] The third semiconductor region 35 is located between the insulating layer 20 and the lead-out portion GEX of the first control portion GG. The seventh semiconductor region 37B is provided between the insulating layer 20 and the fourth control portion GB. In addition, a silicide region 57 is provided on the sixth semiconductor region 39. The sixth semiconductor region 39 is electrically connected to the third semiconductor region 35 via the seventh semiconductor region 37B.

[0037] Fig. 4(a) is a schematic diagram showing an equivalent circuit of the semiconductor device 1 according to the embodiment, and Fig. 4(b) illustrates a method for controlling the semiconductor device 1.

[0038] As shown in FIG. 4(a), the semiconductor device 1 has gate terminals GT1 to GT3. The semiconductor device 1 also has a source terminal S, a drain terminal D, and a body terminal B. The gate terminal GT1 is electrically connected to the first control unit GG via a contact plug GGP. The gate terminal GT2 is electrically connected to the second control unit GS via a contact plug GSP. The gate terminal GT3 is electrically connected to the third control unit GD via a contact plug GDP.

[0039] The source terminal S is electrically connected to the first semiconductor region 31 via a contact plug SP (see FIG. 2). The drain terminal D is electrically connected to the second semiconductor region 33 via a contact plug DP (see FIG. 2). The body terminal B is electrically connected to the sixth semiconductor region 39 via a contact plug BP (see FIG. 2).

[0040] The semiconductor device 1 is controlled by, for example, a gate control circuit GCC. The gate control circuit GCC is connected to a gate terminal GT1 via a gate resistor Rgg. The gate control circuit GCC is also connected to a gate terminal GT2 via a gate resistor Rgs and to a gate terminal GT3 via a gate resistor Rgd.

[0041] 4(b), in the on state, the source terminal S and the body terminal B are biased to, for example, 0 V, and a radio frequency signal (RF) is input to the drain terminal D. The gate control circuit GCC applies a voltage higher than the gate threshold voltage, for example, 3 V, to the first control unit GG, the second control unit GS, and the third control unit GD. As a result, the radio frequency signal is transmitted from the drain terminal D to the source terminal S.

[0042] On the other hand, in the off state, the source terminal S is biased to, for example, 0 V, and the body terminal B is biased to, for example, −3 V. A radio frequency signal (RF) is input to the drain terminal D. The gate control circuit GCC applies, for example, −3 V to the first control unit GG, and reduces the voltages of the second control unit GS and the third control unit GD to, for example, 0 V. This electrically isolates the drain terminal D from the source terminal S, and prevents the radio frequency signal from being transmitted to the source terminal S.

[0043] 5(a) and 5(b) are graphs showing the characteristics of the semiconductor device 1 according to the embodiment. Fig. 5(a) shows the relationship between the drain capacitance Coff in the off state and the gate length. Fig. 5(b) shows the relationship between the high-frequency breakdown voltage between the source terminal S and the drain terminal D and the gate length. Here, the gate length is the width of the control electrode 40 in the X direction (see Fig. 1).

[0044] In a high-frequency switching device, for example, if the CR time constant, determined by the gate resistance and gate capacitance, is sufficiently larger than the high-frequency period, the gate will essentially be in a floating state, resulting in a small Coff. In this example, a high-frequency signal of 2 GHz is input, and the gate resistances Rgg, Rgs, and Rgd are each sufficiently high, at 1 MΩ or more.

[0045] 5(a) and 5(b), "SG" represents the characteristics of the semiconductor device according to the comparative example, and "TG" represents the characteristics of the semiconductor device 1 according to the embodiment. In the semiconductor device according to the comparative example, the control electrode is not divided as shown in FIG. 1 but is integral.

[0046] As shown in FIG. 5(a), Coff of the semiconductor device 1 is smaller than Coff of the semiconductor device according to the comparative example. Here, the gate resistances Rgg, Rgs, and Rgd are each 25 MΩ. The gate voltage Vgg applied to the first control unit GG is −3 V, and the gate voltages Vgs and Vgd applied to the second control unit GS and the third control unit GD are, for example, 0 to 3 V. The same gate voltage Vg (=−3 V) as that applied to the first control unit GG is applied to the control electrode of the semiconductor device according to the comparative example.

[0047] The Coff of the semiconductor device 1 does not depend on the gate voltage Vgs (=Vgd) and is reduced by approximately 19% compared to the Coff of the semiconductor device according to the comparative example. Furthermore, the Coff does not depend on the gate length.

[0048] 5(b), the high-frequency withstand voltage of the semiconductor device 1 is higher than that of the semiconductor device according to the comparative example. The high-frequency withstand voltage of the semiconductor device 1 depends on the gate voltage Vgs (=Vgd) and decreases as the gate voltage Vgs approaches the gate voltage Vgg. Furthermore, the high-frequency withstand voltage does not depend much on the gate length on the long-channel side.

[0049] 6 is a graph showing another characteristic of the semiconductor device 1 according to the embodiment. Fig. 6 shows the relationship between the on-resistance Ron and the film thickness Lox (see Fig. 1) of the second insulating film 43. The vertical axis represents the rate of increase in the on-resistance of the semiconductor device 1 relative to the on-resistance of the semiconductor device according to the comparative example.

[0050] As shown in FIG. 6, the on-resistance Ron increases as the film thickness Lox increases. For example, when the film thickness Lox is 8 nm, the on-resistance Ron increases by approximately 1.3%. This increase in the on-resistance Ron can be compensated for, for example, by reducing Coff. That is, in the semiconductor device 1, although the on-resistance increases, the Coff reduction effect is significant, and it is possible to reduce Ron×Coff, which is the figure of merit of a high-frequency switching device. This improves the performance of the switch.

[0051] In this way, in the semiconductor device 1 of the embodiment, by providing a control electrode 40 including the first control unit GG, the second control unit GS, and the third control unit GD, the high-frequency withstand voltage can be improved, and performance as a switch can be improved.

[0052] Hereinafter, a method for manufacturing the semiconductor device 1 will be described with reference to Fig. 7(a) to Fig. 16(c). Fig. 7(a) to Fig. 16(c) are schematic diagrams showing the manufacturing process of the semiconductor device 1 according to the embodiment. Fig. 7(a) to Fig. 10(c) are cross-sectional views taken along line AA shown in Fig. 2. Fig. 11(a) to Fig. 12(c) are cross-sectional views taken along line CC shown in Fig. 2. Fig. 13(a) to Fig. 16(c) are plan views partially showing the front surface side of the semiconductor layer 30.

[0053] As shown in FIG. 7(a), a first insulating film 41 is formed on the semiconductor layer 30. The semiconductor layer 30 contains a low concentration of second conductivity type impurities. The first insulating film 41 is, for example, a silicon oxide film. The first insulating film 41 is formed, for example, by thermally oxidizing the semiconductor layer 30.

[0054] 7(b), a conductive film 101 is formed on the first insulating film 41. The conductive film 101 is, for example, a polysilicon film. The conductive film 101 is formed by using, for example, CVD (Chemical Vapor Deposition).

[0055] 7(c), the first control part GG is formed by selectively removing the conductive film 101. The conductive film 101 is patterned using an etching mask formed by photolithography, for example.

[0056] As shown in FIG. 8(a), a fourth semiconductor region 37S and a fifth semiconductor region 37D are formed in the semiconductor layer 30. The fourth semiconductor region 37S and the fifth semiconductor region 37D are formed by ion-implanting a second conductivity type impurity, for example, boron (B), using the first control portion GG as a mask and activating the ion-implanted impurity by heat treatment. A third semiconductor region 35 is formed between the fourth semiconductor region 37S and the fifth semiconductor region 37D. The fourth semiconductor region 37S and the fifth semiconductor region 37D may be formed after the second control portion GS and the third control portion GD are formed (see FIG. 9(c)).

[0057] 8(b), a second insulating film 43 is formed on the surface of the first control unit GG. The second insulating film 43 is, for example, a silicon oxide film. The second insulating film 43 is formed, for example, by thermally oxidizing the first control unit GG, and covers the top and side surfaces of the first control unit GG.

[0058] As shown in FIG. 8(c), a conductive film 103 is formed on the first insulating film 41 and the second insulating film 43. The conductive film 103 is, for example, a polysilicon film. The conductive film 103 covers the first control unit GG. The conductive film 103 has a thickness in the Z direction that is thinner than the thickness of the first control unit GG in the Z direction. The conductive film 103 is formed using, for example, CVD.

[0059] As shown in FIG. 9(a), the conductive film 103 is selectively removed, leaving the portion formed on the side surface of the first control unit GG. The conductive film 103 is removed using, for example, RIE (Reactive Ion Etching). This forms the control electrode 40 including the first control unit GG, the second control unit GS, and the third control unit GD. The second control unit GS and the third control unit GD are formed on the side surface of the first control unit GG via the second insulating film 43.

[0060] As shown in FIG. 9(b), an extension 31e of the first semiconductor region 31 and an extension 33e of the second semiconductor region 33 (see FIG. 1) are formed in the semiconductor layer 30 on both sides of the control electrode 40. The extensions 31e and 33e are formed by ion-implanting a first conductivity type impurity, such as arsenic (As), and activating the ion-implanted impurities by heat treatment. By increasing the ion-implantation angle, the extension 31e is formed to extend below the second control unit GS. The extension 31e is formed on the fourth semiconductor region 37S, and the extension 33e is formed on the fifth semiconductor region 37D. Note that, since the overlap between the extension 31e and the second control unit GS and the overlap between the extension 33e and the third control unit GD in a planar view increases, Coff increases. Therefore, it is preferable to narrow the overlap width between the extension 31e and the second control unit GS and the overlap width between the extension 33e and the third control unit GD.

[0061] 9(c), sidewalls 47 are formed on the respective side surfaces of the second control portion GS and the third control portion GD. The sidewalls 47 are, for example, silicon nitride films. The sidewalls 47 are formed, for example, by selectively removing the silicon nitride film covering the control electrode 40 by RIE. At this time, the first insulating film 41 is removed on both sides of the control electrode 40, and the surface of the semiconductor layer 30 is exposed.

[0062] 10(a), a first semiconductor region 31 and a second semiconductor region 33 are formed in the semiconductor layer 30 on both sides of the control electrode 40. The first semiconductor region 31 and the second semiconductor region 33 are formed by ion-implanting a first conductivity type impurity, such as arsenic (As), and activating the impurity by heat treatment. The first semiconductor region 31 and the second semiconductor region 33 are diffused by heat treatment, for example, and come into contact with the insulating layer 20.

[0063] The fourth semiconductor region 37S is located between the first semiconductor region 31 and the third semiconductor region 35, and the fifth semiconductor region 37D is located between the second semiconductor region 33 and the third semiconductor region 35. In addition, the extending portion 31e of the first semiconductor region 31 extends between the fourth semiconductor region 37S and the first insulating film 41, and the extending portion 33e of the second semiconductor region 33 extends between the fifth semiconductor region 37D and the first insulating film 41.

[0064] 10(b), a silicide region 51 is formed on the first semiconductor region 31, and a silicide region 53 is formed on the second semiconductor region 33. A silicide region 55 is also formed on the control electrode 40. The silicide regions 51, 53, and 55 are formed by depositing a metal film made of, for example, nickel (Ni) or cobalt (Co) on the exposed surface of the semiconductor layer 30 and on the control electrode 40, and then performing a heat treatment.

[0065] 10(c), an interlayer insulating film 50 is formed to cover the silicide regions 51, 53, and 55. The interlayer insulating film 50 covers the semiconductor layer 30 and the control electrode 40. The interlayer insulating film 50 is, for example, a silicon oxide film. The interlayer insulating film 50 is formed by, for example, CVD.

[0066] In the above manufacturing process, the first conductivity type impurity and the second conductivity type impurity are also ion-implanted into the control electrode 40. For example, the first conductivity type impurity is implanted at a high dose when forming the first semiconductor region 31 and the second semiconductor region 33, and the control electrode 40 is formed to have conductivity of the second conductivity type.

[0067] 11(a) to 12(c) are other schematic cross-sectional views showing the manufacturing process of the semiconductor device 1 according to the embodiment, and show the transition of the structure in a cross section taken along line CC shown in FIG.

[0068] As shown in FIG. 11(a), when the semiconductor layer 30 is thick, an STI is provided on the semiconductor layer 30. The STI is formed to be thicker than the first insulating film 41, for example. The STI is formed by thermally oxidizing the semiconductor layer 30, for example. The STI is a silicon oxide film, for example. On the other hand, when the semiconductor layer 30 is thin, for example, 100 nm or less, the semiconductor layer 30 in the element isolation region is partially removed to expose the insulating layer 20. Thereafter, an oxide film is formed by thermally oxidizing the semiconductor layer 30, and further, an insulating material such as a CVD oxide film is embedded in the element isolation region to form the STI.

[0069] As shown in FIG. 11(b), the conductive film 101 (see FIG. 7(b)) is also formed on the STI.

[0070] As shown in FIG. 11(c), the conductive film 101 is selectively removed to form the first control portion GG, and then the second insulating film 43 is formed (see FIG. 8(b)). At this time, the portions that will become the contact portion GSC of the second control portion GS and the contact portion GDC of the third control portion GD are also left on the STI. At this time, the distance Ws between the first control portion GG and the remaining portion of the conductive film 101 is set to be smaller than twice the film thickness of the conductive film 103 (see FIG. 8(c)).

[0071] As shown in FIG. 12(a), an etching mask EM1 is formed on the STI. The etching mask EM1 has, for example, openings that partially expose the conductive film 101 and covers other portions. The etching mask EM1 is, for example, a resist mask formed by photolithography. Next, the second insulating film 43 covering the conductive film 101 is selectively removed using the etching mask EM1.

[0072] 12(b), a conductive film 103 is formed so as to cover the first control unit GG (see FIG. 8(c)). The conductive film 103 is formed so as to fill the space between the first control unit GG and the conductive film 101 with the second insulating film 43 interposed therebetween.

[0073] 12(c), the conductive film 103 is selectively removed, leaving behind the portion that fills the space between the first control unit GG and the conductive film 101. The conductive film 103 is also removed, leaving behind a portion (not shown) formed on the side surface of the conductive film 101. As a result, the contact portion GSC of the second control unit GS and the contact portion GDC of the third control unit GD are formed on the STI.

[0074] 13(a) to 14(c) are schematic plan views showing a manufacturing process of the semiconductor device 1 according to the embodiment. 13(a) to 14(c) are plan views partially showing the end GGE of the first control unit GG. Note that the second insulating film 43 on the first control unit GG and on the conductive film 101 is omitted in FIGS. 13(a) to 14(c).

[0075] As shown in FIG. 13(a), the first control part GG is formed to have an end GGE on the STI (see FIG. 8(a)). The second insulating film 43 is formed to cover the end GGE of the first control part GG as well. The end GGE of the first control part GG is formed to extend between the remaining portions of the conductive film 101.

[0076] As shown in FIG. 13(b), the second insulating film 43 covering the conductive film 101 is selectively removed using an etching mask EM1 (see FIG. 12(a)).

[0077] 13(c), after forming the conductive film 103 that covers the first control unit GG and the conductive film 101 (see FIGS. 8(c) and 12(b)), the conductive film 103 is removed, leaving only the side surfaces of the first control unit GG, the side surfaces of the conductive film 101, and the portion that fills the space between the first control unit GG and the conductive film 101. The conductive film 103 between the first control unit GG and the conductive film 101 is electrically connected to the conductive film 101 via the portion formed on the side surface of the conductive film 101.

[0078] 14(a), an etching mask EM2 is formed on the STI. The etching mask EM2 is formed so as to expose the tip of the first control part GG. The etching mask EM2 is, for example, a photoresist, and is formed by photolithography.

[0079] 14(b), the conductive film 103 formed on the side surface of the tip of the first control part GG is selectively removed using an etching mask EM2. The conductive film 103 is removed by, for example, dry etching.

[0080] 14(c), the second control unit GS and the third control unit GD are separated from each other by removing the conductive film 103 at the tip of the first control unit GG. The end GSE of the second control unit GS is separated from the end GDE of the third control unit GD, with the end GGE of the first control unit GG in between.

[0081] 15(a) to 16(c) are other schematic plan views showing the manufacturing process of the semiconductor device 1 according to the embodiment, and are plan views partially showing the contact portion GGC of the first control unit GG.

[0082] 15(a), the contact portion GGC of the first control portion GG is formed on the STI by patterning the conductive film 101 (see FIG. 7(c)). The lead portion GEX of the first control portion GG is connected to the contact portion GGC.

[0083] 15(b), the first control portion GG is thermally oxidized to form a second insulating film 43 (see FIG. 8(b)). The second insulating film 43 covers the contact portion GGC and the lead portion GEX.

[0084] As shown in Fig. 15(c), an etching mask EM1 is formed (see Fig. 12(a)). The etching mask EM1 is formed so as to expose a part of the contact portion GGC.

[0085] 16(a), an etching mask EM1 is used to partially remove the second insulating film 43. A part of the second insulating film 43 is separated as a third insulating film 45.

[0086] As shown in FIG. 16(b), after forming a conductive film 103 (see FIG. 8(c)) covering the first control unit GG, the conductive film 103 is removed (see FIG. 9(a)), leaving the portion formed on the side surface of the first control unit GG.

[0087] As shown in FIG. 16(c), the conductive film 103 formed on the side surface of the contact portion GGC is partially removed using an etching mask EM2, thereby separating the conductive film 103 into, for example, a third control portion GD and a fourth control portion GB.

[0088] The fourth control part GB faces the lead part GEX of the first control part GG via the third insulating film 45. The fourth control part GB is electrically connected to the first control part GG at the contact part GGC.

[0089] Although the method for manufacturing the first semiconductor device 1 has been described above with reference to FIGS. 7(a) to 16(c), the embodiment is not limited to the above example.

[0090] Fig. 17 is a schematic plan view showing a semiconductor device 2 according to a modified example of the embodiment. Fig. 17 is a plan view showing a control electrode 40 on a semiconductor layer 30. In this example, the control electrode 40 also includes a first control unit GG, a second control unit GS, a third control unit GD, and a fourth control unit GB.

[0091] 17, the control electrode 40 includes a second conductivity type isolation end GES provided at the tip of the STI. The isolation end GES faces the end GGE of the first control portion GG via the second insulating film 43. In this case, the first control portion GG, the second control portion GS, and the third control portion GD have conductivity of the first conductivity type. The isolation end GES is provided so as to connect to the end GSE of the second control portion GS and the end GDE of the third control portion GD.

[0092] 14(a), the isolation edge GES is formed by ion-implanting a second conductivity type impurity, for example, boron (B), without removing the conductive film 103. The isolation edge GES contains the second conductivity type impurity at a concentration lower than the concentration of the first conductivity type impurity in the second control part GS and the third control part GD.

[0093] The control electrode 40 has a parasitic MOS transistor including an isolation edge GES at its tip on the STI, that is, the second control portion GS and the third control portion GD function as a source and a drain, respectively, and the first control portion GG functions as a gate.

[0094] When the semiconductor device 2 is in the on state, for example, 3 V is applied to each of the first control unit GG, the second control unit GS, and the third control unit. Therefore, there is no problem even if the parasitic MOS transistor is turned on. On the other hand, when the semiconductor device 2 is in the off state, for example, −3 V is applied to the first control unit GG, and the second control unit GS and the third control unit GD are each biased to 0 V. Therefore, an inversion layer of the first conductivity type is not formed at the interface between the isolation edge GES and the second insulating film 43, and the parasitic MOS transistor is turned off. In this way, the second control unit GS and the third control unit GD are substantially isolated by the isolation edge GES.

[0095] The control electrode 40 further includes a second conductivity type separation portion GCS provided along the outer edge of the contact portion GGC of the first control portion GG. The separation portion GCS faces the contact portion GGC of the first control portion GG via the second insulating film 43. The separation portion GCS is also provided so as to be connected to the third control portion GD and the fourth control portion GB, for example.

[0096] Impurities of the second conductivity type are ion-implanted into the fourth control unit GB when the sixth semiconductor region 39 is formed. Therefore, the fourth control unit GB has conductivity of the second conductivity type. The fourth control unit GB is electrically connected to the first control unit GG, for example, via the contact unit GGC of the first control unit GG and a silicide region 55 (see FIG. 10(b)) provided on the fourth control unit GB.

[0097] The separation portion GCS is formed by ion-implanting a second conductivity type impurity, for example, boron (B), without removing the conductive film 103 in the step shown in FIG. 16(c).

[0098] By providing the separation portion GCS, the control electrode 40 has a parasitic diode at the outer edge of the contact portion GGC of the first control portion GG. That is, a PN junction is formed between the third control portion GD of the first conductivity type and the separation portion CCS of the second conductivity type. The separation portion GCS is electrically connected to the first control portion GG via the fourth control portion GB.

[0099] When the semiconductor device 2 is in the on state, for example, 3 V is applied to each of the first control unit GG, the second control unit GS, and the third control unit, and therefore no current flows through the parasitic diode. On the other hand, when the semiconductor device 2 is in the off state, for example, −3 V is applied to the first control unit GG, and the second control unit GS and the third control unit GD are each biased to 0 V. Therefore, the parasitic diode is reverse-biased. In this way, the third control unit GD and the fourth control unit GB are substantially isolated by the isolation unit GCS.

[0100] 18 is a schematic diagram showing an equivalent circuit of a semiconductor device 2 according to a modified example of the embodiment. As shown in FIG. 18, the semiconductor device 2 also has gate terminals GT1 to GT3, a source terminal S, a drain terminal D, and a body terminal B.

[0101] The gate control circuit GCC is connected to the gate terminal GT1 via a gate resistance Rgg. The gate control circuit GCC is also connected to the gate terminal GT2 via a gate resistance Rgs, and to the gate terminal GT3 via a gate resistance Rgd. In this example, a parasitic resistance Rgsd occurs between the gate terminal GT2 and the gate terminal GT3.

[0102] The parasitic resistance Rgsd represents the resistance between the source and drain of a parasitic MOS transistor provided at the tip of the control electrode 40. In other words, by providing the isolation edge GES, the second control unit GS and the third control unit GD are not completely electrically isolated from each other, and a parasitic resistance Rgsd occurs between them. The parasitic resistance Rgsd is a high resistance of, for example, 1 MΩ or more.

[0103] 19(a) and 19(b) are graphs showing the characteristics of a semiconductor device 2 according to a modified example of the embodiment. FIG. 19(a) shows the relationship between Coff and parasitic resistance Rgsd. FIG. 19(b) shows the relationship between high-frequency breakdown voltage and parasitic resistance Rgsd. Also, FIG. 19(a) and 19(b) show Coff and high-frequency breakdown voltage when the gate length is set to 0.18 to 0.25 micrometers.

[0104] Here, the gate resistances Rgg, Rgs, and Rgd are each 25 MΩ. In the off state, the gate voltage Vgg applied to the first control unit GG is −3 V, and the gate voltages Vgs and Vgd applied to the second control unit GS and the third control unit GD are, for example, 0 V.

[0105] 19(a), if the parasitic resistance Rgsd is, for example, 1 MΩ or more, the effect of reducing Coff can be obtained. It can also be seen that Coff does not depend on the gate length.

[0106] The high-frequency breakdown voltage shown in Figure 19(b) does not depend on the parasitic resistance Rgsd. Furthermore, the high-frequency breakdown voltage increases as the gate length increases. The high-frequency breakdown voltage shown in the figure is at its maximum when the gate length is 0.25 micrometers, which is almost the same as the maximum value of the high-frequency breakdown voltage shown in Figure 5(b).

[0107] In this way, even in a configuration in which the second control section GS and the third control section GD are separated by the separation end GES, it is possible to improve the switching characteristics and the high frequency withstand voltage.

[0108] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0109] (Appendix 1) an insulating layer; a semiconductor layer provided on the insulating layer, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type spaced apart from the first semiconductor region, and a third semiconductor region of a second conductivity type provided between the first semiconductor region and the second semiconductor region, the first to third semiconductor regions being aligned in a first direction along an interface between the insulating layer and the semiconductor layer; A first insulating film is provided on the semiconductor layer, and the first insulating film layer a control electrode including first to third control portions arranged in the first direction and electrically insulated from the insulating layer, wherein the first control portion is provided between the second control portion and the third control portion and is electrically insulated from the second control portion and the third control portion by a second insulating film, and the third semiconductor region is located between the insulating layer and the first control portion; A semiconductor device comprising: [Explanation of symbols]

[0110] REFERENCE SIGNS LIST 1, 2...Semiconductor device, 10...Substrate, 20...Insulating layer, 30...Semiconductor layer, 31...First semiconductor region, 31e, 33e...Extension portion, 33...Second semiconductor region, 35...Third semiconductor region, 37B...Seventh semiconductor region, 37D...Fifth semiconductor region, 37S...Fourth semiconductor region, 39...Sixth semiconductor region, 40...Control electrode, 41...First insulating film, 43...Second insulating film, 45...Third insulating film, 47...Sidewall, 50...Interlayer insulating film, 51, 53, 55, 55S, 55G, 55D...Silicide region, 101, 103...Conductive film, B...Body terminal, BP, DP, SP, GDP, GGP, GSP...Contact plug, D...Drain terminal, EM1, EM2...Etching mask, GB...Fourth control unit, GCC...Gate control circuit, GCS...separation part, GD...third control part, GDC, GGC, GSC...contact part, GDE, GGE, GSE...end part, GES...separation end, GEX...drawing part, GG...first control part, GS...second control part, GT1, GT2, GT3...gate terminal, Lox...film thickness, Rgd, Rgg, Rgs...gate resistance, Rgsd...parasitic resistance, S...source terminal

Claims

1. an insulating layer; a semiconductor layer provided on the insulating layer, the semiconductor layer including a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type spaced apart from the first semiconductor region, and a third semiconductor region of a second conductivity type provided between the first semiconductor region and the second semiconductor region, the first to third semiconductor regions being aligned in a first direction along an interface between the insulating layer and the semiconductor layer; a control electrode provided on the semiconductor layer via a first insulating film, electrically insulated from the semiconductor layer by the first insulating film, and including first to third control portions aligned in the first direction, wherein the first control portion is provided between the second control portion and the third control portion and electrically insulated from the second control portion and the third control portion by the second insulating film, and the third semiconductor region is located between the insulating layer and the first control portion; Equipped with the semiconductor layer further includes a sixth semiconductor region of the second conductivity type connected to the third semiconductor region, A semiconductor device, wherein the sixth semiconductor region extends in the first direction and is aligned with the first to third semiconductor regions in a second direction along the interface between the insulating layer and the semiconductor layer, the second direction being perpendicular to the first direction.

2. the semiconductor layer further includes a fourth semiconductor region of the second conductivity type provided between the first semiconductor region and the third semiconductor region, and a fifth semiconductor region of the second conductivity type provided between the second semiconductor region and the third semiconductor region, 2. The semiconductor device according to claim 1, wherein said fourth semiconductor region and said fifth semiconductor region contain a second conductivity type impurity at a concentration higher than a concentration of the second conductivity type impurity in said third semiconductor region.

3. the fourth semiconductor region is located between the insulating layer and the second control portion of the control electrode; 3. The semiconductor device according to claim 2, wherein said fifth semiconductor region is located between said insulating layer and said third control portion of said control electrode.

4. the first semiconductor region has a first extension portion that extends along the first insulating film between the second control portion of the control electrode and the insulating layer; the second semiconductor region has a second extension portion that extends along the first insulating film between the third control portion of the control electrode and the insulating layer, the fourth semiconductor region is located between the first extension portion of the first semiconductor region and the third semiconductor region, The semiconductor device according to claim 3 , wherein said fifth semiconductor region is located between said second extension portion of said second semiconductor region and said third semiconductor region.

5. the first semiconductor region of the semiconductor layer has a first extension portion extending along the first insulating film between the second control portion of the control electrode and the insulating layer; 2. The semiconductor device according to claim 1, wherein said second semiconductor region of said semiconductor layer has a second extension portion extending along said first insulating film between said third control portion of said control electrode and said insulating layer.

6. 2. The semiconductor device according to claim 1, wherein said first semiconductor region and said second semiconductor region are provided so as to be in contact with said insulating layer.

7. an insulating region provided above the insulating layer and surrounding the first to sixth semiconductor regions; The semiconductor device according to claim 1 , wherein said control electrode extends in said second direction and has an end located on said insulating region.

8. 8. The semiconductor device according to claim 7, wherein said second control portion and said third control portion of said control electrode each include a contact portion provided on said insulating region.

9. 8. The semiconductor device according to claim 7, wherein said second and third control portions of said control electrode are separated from each other at said end portions on said insulating region.

10. the control electrode has a connecting portion located at the end on the insulating region and connecting the second control portion and the third control portion; the first to third control portions contain impurities of the first conductivity type and have conductivity of the first conductivity type; 9. The semiconductor device according to claim 8, wherein the coupling portion faces the first control portion via the second insulating film, contains impurities of the second conductivity type, and has conductivity of the second conductivity type.

11. 11. The semiconductor device according to claim 10, wherein said coupling portion of said control electrode contains said second conductivity type impurity at a concentration lower than a concentration of said first conductivity type impurity in said second control portion and said third control portion.

12. 8. The semiconductor device according to claim 7, wherein the first control portion of the control electrode includes a lead portion provided on the sixth semiconductor region via the first insulating film, and another contact portion provided on the insulating region and connected to the lead portion.

13. The semiconductor device according to claim 12 , wherein the first control portion of the control electrode includes the lead portion extending in the first direction.

14. the control electrode further includes a fourth control portion connected to the first control portion; the lead-out portion of the first control portion extends between the second control portion and the fourth control portion and between the third control portion and the fourth control portion; The semiconductor device according to claim 13 , wherein the fourth control portion is connected to the first control portion at the other contact portion.

15. 15. The semiconductor device according to claim 14, wherein the first to third control portions of the control electrode have conductivity of the first conductivity type, and the fourth control portion has conductivity of the second conductivity type.

16. 16. The semiconductor device according to claim 15, wherein the fourth control portion of the control electrode extends along an outer edge of the other contact portion of the first control portion and is connected to the second control portion or the third control portion.

17. 16. The semiconductor device according to claim 15, wherein the fourth control unit is electrically connected to the first control unit via the other contact portion of the first control unit and a silicide region provided on the fourth control unit.

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