Detection Device

Abstract

A detection device according to the present invention has a plurality of photodiodes that are provided to a substrate, a light source that is arranged opposite the photodiodes, and a liquid crystal panel that is arranged between the photodiodes and the light source in the direction perpendicular to the substrate. The liquid crystal panel has a plurality of pixels. As seen in plan view, the photodiodes are larger than each of the pixels and are arranged at positions that coincide with pluralities of pixels. The liquid crystal panel puts at least one pixel of the plurality of pixels that coincide with a photodiode in a transmission state and puts the other pixels in a non-transmission state.

Description

[Technical Field]

[0001] The present invention relates to a detection device. [Background technology]

[0002] Patent Document 1 describes a display device with optical sensors that includes an active matrix substrate having a plurality of pixels and optical sensors provided in the pixel region. In the display device with optical sensors in Patent Document 1, the plurality of pixels and the plurality of optical sensors are provided on the same substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2011 / 074984 Summary of the Invention [Problem to be solved by the invention]

[0004] In the display device with optical sensors disclosed in Patent Document 1, the arrangement pitch of the optical sensors is larger than the arrangement pitch of the pixels, so the resolution of the optical sensors is low compared to the resolution of the pixels. In a detection device equipped with such optical sensors, there is a demand for improving the detection resolution.

[0005] An object of the present invention is to provide a detection device that includes an optical sensor and is capable of improving the detection resolution. [Means for solving the problem]

[0006] A detection device of one embodiment of the present invention comprises a photodiode provided on a substrate, a light source arranged opposite the photodiode, and a liquid crystal panel arranged between a plurality of the photodiodes and the light source in a direction perpendicular to the substrate, wherein the liquid crystal panel has a plurality of pixels, and in a planar view, the size of the photodiode is larger than the size of each of the plurality of pixels, the photodiode is arranged in a position overlapping the plurality of pixels, and the liquid crystal panel sets at least one of the plurality of pixels overlapping the photodiode in a transparent state and the other pixels in a non-transparent state. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view schematically showing a detection device according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of the detection control circuit according to the first embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a sensor pixel. [Figure 5] FIG. 5 is a plan view schematically showing a sensor pixel according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along the line VI-VI' in FIG. [Figure 7] FIG. 7 is a circuit diagram illustrating a pixel of the liquid crystal panel according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view schematically illustrating an example of the configuration of the liquid crystal panel according to the first embodiment. [Figure 9] FIG. 9 is a plan view schematically showing the arrangement relationship between a plurality of pixels of a liquid crystal panel and a plurality of sensor pixels of an optical sensor in the detection device according to the first embodiment. [Figure 10] FIG. 10 is an explanatory diagram for explaining an example of the detection operation of the detection device according to the first embodiment. [Figure 11] FIG. 11 is an explanatory diagram for explaining a method for generating a combined image in the detection device according to the first embodiment. [Figure 12] FIG. 12 is a diagram showing simulation results of detected images in the detection devices according to the example and the comparative example. [Figure 13] FIG. 13 is a plan view schematically showing the arrangement relationship between a plurality of pixels of a liquid crystal panel and a plurality of sensor pixels of an optical sensor in a detection device according to the second embodiment. [Figure 14] FIG. 14 is a cross-sectional view schematically illustrating an example of the configuration of a liquid crystal panel according to the second embodiment. [Figure 15] FIG. 15 is an explanatory diagram for explaining an example of the detection operation of the detection device according to the second embodiment. [Figure 16] FIG. 16 is an explanatory diagram for explaining an example of the detection operation of the detection device according to the modified example of the second embodiment. [Figure 17] FIG. 17 is a plan view schematically showing the arrangement relationship between a plurality of pixels of a liquid crystal panel and a plurality of sensor pixels of an optical sensor in a detection device according to the third embodiment. [Figure 18] FIG. 18 is a plan view showing an example of a sensitivity map of the optical sensor according to the third embodiment. [Figure 19] FIG. 19 is a flowchart illustrating a method for calculating a correction value in the detection device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Modes (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the present disclosure are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this disclosure and each figure, elements similar to those previously described with reference to the preceding figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0009] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0010] (First embodiment) 1 is a cross-sectional view schematically showing a detection device according to a first embodiment. As shown in FIG. 1, the detection device 1 includes an optical sensor 10, a liquid crystal panel 50, and a light source 80. The liquid crystal panel 50 and the light source 80 are stacked in this order on top of the optical sensor 10. A detection target 100 to be detected is disposed between the optical sensor 10 and the liquid crystal panel 50.

[0011] The light source 80 is disposed opposite the multiple photodiodes 30 (see FIG. 2) of the optical sensor 10, and irradiates parallel light toward the liquid crystal panel 50. The light source 80 may have any configuration, for example, a light emitting diode (LED) and a lens that converts the light incident from the LED into parallel light and irradiates it. The light source 80 may also include a translucent light guide plate or the like as necessary. The light source 80 is disposed with a space (air layer) between it and the liquid crystal panel 50. However, the light source 80 may also be bonded to the liquid crystal panel 50 with an optical resin or the like.

[0012] The liquid crystal panel 50 functions as an optical filter layer that switches between a light transmission state and a light non-transmission state for each of the plurality of pixels Pix (see FIG. 2). The liquid crystal panel 50 is disposed opposite the plurality of photodiodes 30 (see FIG. 2) of the optical sensor 10, and is disposed between the optical sensor 10 (the plurality of photodiodes 30) and the light source 80. The liquid crystal panel 50 transmits a portion of the parallel light from the light source 80 toward the optical sensor 10. The plurality of photodiodes 30 (see FIG. 2) of the optical sensor 10 can detect information about the detection object 100 based on the parallel light that has passed through the liquid crystal panel 50.

[0013] The object to be detected 100 is a minute object such as a cell. The detection device 1 can be applied to the detection of minute objects such as cells. However, the object to be detected 100 is not limited to this, and may be a living body such as a finger, palm, or wrist. For example, the optical sensor 10 may be configured as a fingerprint detection device that detects fingerprints or a vein detection device that detects blood vessel patterns such as veins.

[0014] 2 is a block diagram showing an example of the configuration of the detection device according to the first embodiment. As shown in Fig. 2, the detection device 1 further includes a host IC 70 that controls the optical sensor 10 and the liquid crystal panel 50. The optical sensor 10 includes an array substrate 2, a plurality of sensor pixels 3 (photodiodes 30) formed on the array substrate 2, gate line drive circuits 15A and 15B, a signal line drive circuit 16A, and a detection control circuit 11.

[0015] The array substrate 2 is formed using a substrate 21 as a base. Each of the sensor pixels 3 includes a photodiode 30, a plurality of transistors, and various wirings. The array substrate 2 on which the photodiodes 30 are formed is a drive circuit substrate that drives the sensors for each predetermined detection area, and is also called a backplane or active matrix substrate.

[0016] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area where a plurality of sensor pixels 3 (a plurality of photodiodes 30) are provided. The peripheral area GA is an area between the periphery of the detection area AA and the outer edge of the substrate 21, and is an area where a plurality of sensor pixels 3 are not provided. The gate line driving circuits 15A and 15B, the signal line driving circuit 16A, and the detection control circuit 11 are provided in the peripheral area GA.

[0017] Each of the plurality of sensor pixels 3 is an optical sensor having a photodiode 30 as a sensor element. The photodiode 30 outputs an electrical signal according to the light irradiated thereon. More specifically, the photodiode 30 is a PIN (Positive Intrinsic Negative) photodiode or an OPD (Organic Photodiode) using an organic semiconductor. The plurality of sensor pixels 3 (the plurality of photodiodes 30) are arranged in a matrix in the detection area AA.

[0018] The detection control circuit 11 is a circuit that supplies control signals Sa, Sb, and Sc to the gate line drive circuits 15A, 15B and the signal line drive circuit 16A, respectively, and controls their operations. Specifically, the gate line drive circuits 15A and 15B output gate drive signals to the sensor gate lines GLS (see FIG. 4) based on the control signals Sa and Sb. The signal line drive circuit 16A electrically connects the sensor signal line SLS selected based on the control signal Sc to the detection control circuit 11. The detection control circuit 11 also includes a signal processing circuit that processes the detection signals Vdet from the multiple photodiodes 30.

[0019] The photodiodes 30 included in the multiple sensor pixels 3 perform detection in accordance with gate drive signals supplied from the gate line drive circuits 15A and 15B. The multiple photodiodes 30 output electrical signals corresponding to the light irradiated thereon as detection signals Vdet to the signal line drive circuit 16A. The detection control circuit 11 processes the detection signals Vdet from the multiple photodiodes 30 and outputs a sensor value So based on the detection signals Vdet to the host IC 70. In this way, the detection device 1 detects information related to the object 100 to be detected.

[0020] Fig. 3 is a block diagram showing an example of the configuration of the detection control circuit according to the first embodiment. As shown in Fig. 3, the detection control circuit 11 has a detection signal amplitude adjustment circuit 41, an A / D conversion circuit 42, a signal processing circuit 43, and a detection timing control circuit 44. The detection timing control circuit 44 controls the detection signal amplitude adjustment circuit 41, the A / D conversion circuit 42, and the signal processing circuit 43 to operate synchronously based on a control signal supplied from the host IC 70 (see Fig. 2).

[0021] The detection signal amplitude adjustment circuit 41 is a circuit that adjusts the amplitude of the detection signal Vdet output from the photodiode 30, and is configured to include, for example, an amplifier. The A / D conversion circuit 42 converts the analog signal output from the detection signal amplitude adjustment circuit 41 into a digital signal. The signal processing circuit 43 is a circuit that processes the digital signal from the A / D conversion circuit 42 and transmits the sensor value So to the host IC 70.

[0022] Returning to FIG. 2, the liquid crystal panel 50 includes an array substrate SUB1, a plurality of pixels Pix formed on the array substrate SUB1, gate line driving circuits 15C and 15D, a signal line driving circuit 16B, and a pixel control circuit 12.

[0023] The array substrate SUB1 is formed using a first insulating substrate 51 as a base. A plurality of pixels Pix are arranged in a matrix in an area overlapping with the detection area AA of the array substrate SUB1. The array substrate SUB1 is a drive circuit substrate that drives a liquid crystal layer LC (see FIG. 8) for each of the plurality of pixels Pix.

[0024] The pixel control circuit 12 supplies control signals Sd, Se, and Sf to the gate line drive circuits 15C, 15D and the signal line drive circuit 16B, respectively, and controls their operation. Specifically, the gate line drive circuits 15C and 15D output drive signals to the gate lines GL (see FIG. 7) based on the control signals Sd and Se. The signal line drive circuit 16B supplies a pixel control signal to a signal line SL selected based on the control signal Sf. This controls the liquid crystal panel 50 to turn on (light transmitting state) or off (light non-transmitting state) for each of the multiple pixels Pix.

[0025] The host IC 70 has a sensor value storage circuit 71, a sensitivity map storage circuit 72, and a correction value generation circuit 73 as control circuits on the optical sensor 10 side. The sensor value storage circuit 71 is a circuit that stores the sensor value So output from the detection control circuit 11 of the optical sensor 10. The sensitivity map storage circuit 72 is a circuit that stores, as a sensitivity map, the distribution of detection sensitivity of the photodiodes 30 when the object to be detected 100 is not in the detection area AA. The correction value generation circuit 73 is a circuit that generates a correction value for the gradation of the combined image based on the sensitivity map. The sensitivity map storage circuit 72 and the correction value generation circuit 73 will be described in detail in the third embodiment (FIGS. 17 to 19).

[0026] The host IC 70 has an image generation circuit 74 and an image storage circuit 75 as control circuits on the liquid crystal panel 50 side. The image storage circuit 75 is a circuit that stores information on the arrangement pattern of the multiple pixels Pix (on (light transmitting state) and off (light non-transmitting state)) for each detection period F (see FIG. 10). The image generation circuit 74 is a circuit that generates a pixel control signal based on the arrangement pattern information of the image storage circuit 75. The image generation circuit 74 outputs a pixel control signal including information on the arrangement pattern of the pixels Pix (on / off) to the signal line drive circuit 16B for each detection period F.

[0027] The host IC 70 further includes a combined image generation circuit 76. The combined image generation circuit 76 is a circuit that generates one combined image by synthesizing images from multiple detection periods F (see FIG. 10) based on the sensor values ​​So from the sensor value storage circuit 71 and information on the arrangement pattern in the image storage circuit 75. A detailed example of the operation of the combined image generation circuit 76 will be described later with reference to FIGS. 10 and 11.

[0028] Although not shown, the host IC 70 has a control circuit that synchronously controls the detection control circuit 11 and the pixel control circuit 12. That is, based on a control signal from the host IC 70, the on / off switching of the arrangement pattern of the multiple pixels Pix on the liquid crystal panel 50 and the detection of the multiple photodiodes 30 on the optical sensor 10 are synchronously controlled. Note that the optical sensor 10 has two gate line drive circuits 15A and 15B, but may have only one gate line drive circuit. The liquid crystal panel 50 has two gate line drive circuits 15C and 15D, but may have only one gate line drive circuit.

[0029] Next, a configuration example of the optical sensor 10 will be described. FIG. 4 is a circuit diagram showing a sensor pixel. As shown in FIG. 4, the sensor pixel 3 includes a photodiode 30, a capacitance element Ca, and a first transistor TrS. The first transistor TrS is provided corresponding to the photodiode 30. The first transistor TrS is configured by a thin film transistor, and in this example, is configured by an n-channel MOS (Metal Oxide Semiconductor) TFT (Thin Film Transistor). The gate of the first transistor TrS is connected to a sensor gate line GLS. The source of the first transistor TrS is connected to a sensor signal line SLS. The drain of the first transistor TrS is connected to the anode of the photodiode 30 and the capacitance element Ca.

[0030] A power supply potential SVS is supplied to the cathode of the photodiode 30 from the detection control circuit 11. Furthermore, a reference potential VR1, which is the initial potential of the capacitance element Ca, is supplied from the detection control circuit 11 to the capacitance element Ca.

[0031] When light is irradiated onto the sensor pixel 3, a current corresponding to the amount of light flows through the photodiode 30, causing charge to accumulate in the capacitance element Ca. When the first transistor TrS is turned on, a current corresponding to the charge accumulated in the capacitance element Ca flows through the sensor signal line SLS. The sensor signal line SLS is connected to the detection control circuit 11 via the signal line drive circuit 16A. This allows the optical sensor 10 of the detection device 1 to detect a signal corresponding to the amount of light irradiated onto the photodiode 30 for each sensor pixel 3.

[0032] The first transistor TrS is not limited to an n-type TFT, and may be a p-type TFT. The pixel circuit of the sensor pixel 3 shown in FIG. 4 is merely an example, and the sensor pixel 3 may be provided with multiple transistors corresponding to one photodiode 30.

[0033] Next, a detailed description will be given of the configuration of the optical sensor 10. Fig. 5 is a plan view schematically showing a sensor pixel according to the first embodiment.

[0034] In the following description, the first direction Dx is a direction in a plane parallel to the substrate 21 (see FIG. 6). The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is a normal direction to the main surface of the substrate 21. Furthermore, "planar view" refers to the positional relationship when viewed from a direction perpendicular to the substrate 21.

[0035] As shown in FIG. 5, the sensor pixel 3 is an area surrounded by the sensor gate line GLS and the sensor signal line SLS. In this embodiment, the sensor gate line GLS includes a first sensor gate line GLA and a second sensor gate line GLB. The first sensor gate line GLA is provided to overlap the second sensor gate line GLB. The first sensor gate line GLA and the second sensor gate line GLB are provided in different layers with insulating layers 22c and 22d (see FIG. 6) interposed therebetween. The first sensor gate line GLA and the second sensor gate line GLB are electrically connected at an arbitrary location and are supplied with a gate drive signal having the same potential. At least one of the first sensor gate line GLA and the second sensor gate line GLB is connected to the gate line drive circuits 15A and 15B. Although the first sensor gate line GLA and the second sensor gate line GLB have different widths in FIG. 5, they may have the same width.

[0036] The photodiodes 30 are provided in an area surrounded by the sensor gate lines GLS and the sensor signal lines SLS. An upper electrode 34 and a lower electrode 35 are provided corresponding to each photodiode 30. The photodiodes 30 are, for example, PIN photodiodes. The lower electrode 35 is, for example, an anode electrode of the photodiode 30. The upper electrode 34 is, for example, a cathode electrode of the photodiode 30.

[0037] The upper electrode 34 is connected to the power supply signal line Lvs via a connection wiring 36. The power supply signal line Lvs is a wiring that supplies a power supply potential SVS to the photodiode 30. In this embodiment, the power supply signal line Lvs overlaps with the sensor signal line SLS and extends in the second direction Dy. A plurality of sensor pixels 3 arranged in the second direction Dy are connected to a common power supply signal line Lvs. This configuration allows the aperture of the sensor pixel 3 to be large. The lower electrode 35, the photodiode 30, and the upper electrode 34 are each substantially rectangular in plan view. However, this is not limited thereto, and the shapes of the lower electrode 35, the photodiode 30, and the upper electrode 34 can be changed as appropriate.

[0038] The first transistor TrS is provided near the intersection of the sensor gate GLS and the sensor signal line SLS, and includes a semiconductor layer 61, a source electrode 62, a drain electrode 63, a first gate electrode 64A, and a second gate electrode 64B.

[0039] The semiconductor layer 61 is an oxide semiconductor. More preferably, the semiconductor layer 61 is a transparent amorphous oxide semiconductor (TAOS) among oxide semiconductors. By using an oxide semiconductor for the first transistor TrS, the leakage current of the first transistor TrS can be suppressed. That is, the first transistor TrS can reduce the leakage current from the unselected sensor pixels 3. This allows the optical sensor 10 to improve the S / N ratio. However, the semiconductor layer 61 is not limited to this, and may be a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, polysilicon, low temperature polycrystalline silicon (LTPS), etc.

[0040] The semiconductor layer 61 is provided along the first direction Dx and intersects with the first gate electrode 64A and the second gate electrode 64B in a plan view. The first gate electrode 64A and the second gate electrode 64B are provided branching off from the first sensor gate line GLA and the second sensor gate line GLB, respectively. In other words, portions of the first sensor gate line GLA and the second sensor gate line GLB that overlap with the semiconductor layer 61 function as the first gate electrode 64A and the second gate electrode 64B. The first gate electrode 64A and the second gate electrode 64B are made of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof. In addition, a channel region is formed in the portion of the semiconductor layer 61 that overlaps with the first gate electrode 64A and the second gate electrode 64B.

[0041] One end of the semiconductor layer 61 is connected to the source electrode 62 via a contact hole H1. The other end of the semiconductor layer 61 is connected to the drain electrode 63 via a contact hole H2. The portion of the sensor signal line SLS that overlaps with the semiconductor layer 61 serves as the source electrode 62. The portion of the third conductive layer 67 that overlaps with the semiconductor layer 61 functions as the drain electrode 63. The third conductive layer 67 is connected to the lower electrode 35 via a contact hole H3. With this configuration, the first transistor TrS can switch between connecting and disconnecting the photodiode 30 and the sensor signal line SLS.

[0042] Next, a description will be given of the layer structure of the optical sensor 10. Fig. 6 is a cross-sectional view taken along line VI-VI' in Fig. 5.

[0043] In the description of the detection device 1 including the optical sensor 10, the direction from the substrate 21 toward the photodiode 30 in the direction perpendicular to the surface of the substrate 21 (third direction Dz) will be referred to as the "upper side" or "top." The direction from the photodiode 30 toward the substrate 21 will be referred to as the "lower side" or "bottom."

[0044] 6, the substrate 21 is an insulating substrate, and may be, for example, a glass substrate such as quartz or alkali-free glass. The first transistor TrS, various wirings (sensor gate line GLS and sensor signal line SLS), and an insulating layer are provided on one surface of the substrate 21 to form the array substrate 2. A plurality of photodiodes 30 are arranged on the array substrate 2, i.e., on one surface of the substrate 21. The substrate 21 may be a resin substrate or a resin film made of a resin such as polyimide.

[0045] The insulating layers 22a and 22b are provided on the substrate 21. The insulating layers 22a, 22b, 22c, 22d, 22e, 22f, and 22g are inorganic insulating films, such as silicon oxide (SiO2), silicon nitride (SiN), etc. Furthermore, each inorganic insulating layer is not limited to a single layer and may be a multilayer film.

[0046] The first gate electrode 64A is provided on the insulating layer 22b. The insulating layer 22c is provided on the insulating layer 22b, covering the first gate electrode 64A. The semiconductor layer 61, the first conductive layer 65, and the second conductive layer 66 are provided on the insulating layer 22c. The first conductive layer 65 is provided to cover the end of the semiconductor layer 61 that is connected to the source electrode 62. The second conductive layer 66 is provided to cover the end of the semiconductor layer 61 that is connected to the drain electrode 63.

[0047] The insulating layer 22d is provided on the insulating layer 22c, covering the semiconductor layer 61, the first conductive layer 65, and the second conductive layer 66. The second gate electrode 64B is provided on the insulating layer 22d. The semiconductor layer 61 is provided between the first gate electrode 64A and the second gate electrode 64B in the direction perpendicular to the substrate 21. In other words, the first transistor TrS has a so-called dual-gate structure. However, the first transistor TrS may have a bottom-gate structure in which the first gate electrode 64A is provided but the second gate electrode 64B is not provided, or a top-gate structure in which the first gate electrode 64A is not provided but only the second gate electrode 64B is provided.

[0048] The insulating layer 22e is provided on the insulating layer 22d, covering the second gate electrode 64B. The source electrode 62 (sensor signal line SLS) and the drain electrode 63 (third conductive layer 67) are provided on the insulating layer 22e. In this embodiment, the drain electrode 63 is the third conductive layer 67 provided on the semiconductor layer 61 via the insulating layers 22d and 22e. The source electrode 62 is electrically connected to the semiconductor layer 61 via a contact hole H1 and a first conductive layer 65. The drain electrode 63 is electrically connected to the semiconductor layer 61 via a contact hole H2 and a second conductive layer 66.

[0049] The third conductive layer 67 is provided in a region overlapping with the photodiode 30 in plan view. The third conductive layer 67 is also provided above the semiconductor layer 61, the first gate electrode 64A, and the second gate electrode 64B. That is, the third conductive layer 67 is provided between the second gate electrode 64B and the lower electrode 35 in the direction perpendicular to the substrate 21. As a result, the third conductive layer 67 functions as a protective layer that protects the first transistor TrS.

[0050] The second conductive layer 66 extends opposite the third conductive layer 67 in a region not overlapping with the semiconductor layer 61. Furthermore, a fourth conductive layer 68 is provided on the insulating layer 22d in a region not overlapping with the semiconductor layer 61. The fourth conductive layer 68 is provided between the second conductive layer 66 and the third conductive layer 67. As a result, a capacitance is formed between the second conductive layer 66 and the fourth conductive layer 68, and a capacitance is formed between the third conductive layer 67 and the fourth conductive layer 68. The capacitance formed by the second conductive layer 66, the third conductive layer 67, and the fourth conductive layer 68 is the capacitance of the capacitive element Ca shown in FIG. 4.

[0051] The first organic insulating layer 23a is provided on the insulating layer 22e, covering the source electrode 62 (sensor signal line SLS) and the drain electrode 63 (third conductive layer 67). The first organic insulating layer 23a is a planarizing layer that flattens unevenness formed by the first transistor TrS and various conductive layers.

[0052] Next, a description will be given of the cross-sectional structure of the photodiode 30. The photodiode 30 is formed by stacking a lower electrode 35, the photodiode 30, and an upper electrode 34 on the first organic insulating layer 23a of the array substrate 2 in this order.

[0053] The lower electrode 35 is provided on the first organic insulating layer 23a and is electrically connected to the third conductive layer 67 through a contact hole H3. The lower electrode 35 is the anode of the photodiode 30 and is an electrode for reading out the detection signal Vdet. The lower electrode 35 is made of a metal material such as molybdenum (Mo) or aluminum (Al). Alternatively, the lower electrode 35 may be a laminated film in which a plurality of these metal materials are laminated. The lower electrode 35 may also be made of a light-transmitting conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0054] The photodiode 30 includes, as semiconductor layers, an i-type semiconductor layer 31, an n-type semiconductor layer 32, and a p-type semiconductor layer 33. The i-type semiconductor layer 31, the n-type semiconductor layer 32, and the p-type semiconductor layer 33 are formed of, for example, amorphous silicon (a-Si). In FIG. 6, the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 are stacked in this order in the direction perpendicular to the surface of the substrate 21. However, the opposite configuration, that is, the n-type semiconductor layer 32, the i-type semiconductor layer 31, and the p-type semiconductor layer 33 may also be used. Each semiconductor layer may be a photoelectric conversion element made of an organic semiconductor.

[0055] The n-type semiconductor layer 32 is formed by doping impurities into a-Si to form an n+ region. The p-type semiconductor layer 33 is formed by doping impurities into a-Si to form a p+ region. The i-type semiconductor layer 31 is, for example, an undoped intrinsic semiconductor and has lower conductivity than the n-type semiconductor layer 32 and the p-type semiconductor layer 33.

[0056] The upper electrode 34 is a cathode of the photodiode 30 and is an electrode for supplying the power supply potential SVS to the photoelectric conversion layer. The upper electrode 34 is a light-transmitting conductive layer made of, for example, ITO, and a plurality of upper electrodes 34 are provided for each photodiode 30.

[0057] Insulating layers 22f and 22g are provided on the first organic insulating layer 23a. Insulating layer 22f covers the periphery of the upper electrode 34, and an opening is provided in the insulating layer 22f at a position where it overlaps with the upper electrode 34. The connecting wiring 36 is connected to the upper electrode 34 at a portion of the upper electrode 34 where insulating layer 22f is not provided. Insulating layer 22g is provided on insulating layer 22f, covering the upper electrode 34 and the connecting wiring 36. A second organic insulating layer 23b, which is a planarizing layer, is provided on insulating layer 22g. In the case of an organic semiconductor photodiode 30, an insulating layer 22h may be further provided thereon.

[0058] Next, an example of the configuration of the liquid crystal panel 50 will be described. Fig. 7 is a circuit diagram showing a pixel of the liquid crystal panel according to the first embodiment. As shown in Fig. 7, the pixel Pix includes a second transistor Tr and a capacitance CS of the liquid crystal layer LC. The second transistor Tr is formed of a thin film transistor, and in this example, is formed of an n-channel MOS type TFT.

[0059] One of the source electrode and drain electrode of the second transistor Tr is connected to the signal line SL, the gate electrode is connected to the scanning line GL, and the other of the source electrode and drain electrode is connected to one end of a capacitance CS of the liquid crystal layer LC, which will be described later. One end of the capacitance CS of the liquid crystal layer LC is connected to the second transistor Tr via a pixel electrode 55 (see FIG. 8), and the other end is connected to a common potential line COML via a common electrode 53 (FIG. 8).

[0060] Fig. 8 is a cross-sectional view schematically showing an example of the configuration of a liquid crystal panel according to the first embodiment. As shown in Fig. 8, the liquid crystal panel 50 includes, for example, an array substrate SUB1, a counter substrate SUB2, and a liquid crystal layer LC. The counter substrate SUB2 is disposed opposite the array substrate SUB1. The liquid crystal layer LC is sealed between the array substrate SUB1 and the counter substrate SUB2.

[0061] The array substrate SUB1 has a first insulating substrate 51, a circuit-forming layer 52, a common electrode 53, an insulating film 54, a pixel electrode 55, and a lower alignment film 56. The circuit-forming layer 52, the common electrode 53, the insulating film 54, the pixel electrode 55, and the lower alignment film 56 are stacked in this order on the first insulating substrate 51 in the third direction Dz.

[0062] The first insulating substrate 51 is a light-transmitting glass substrate or film substrate. The circuit formation layer 52 is a layer on which a pixel circuit including the second transistor Tr of the pixel Pix shown in FIG. 7 and various wirings is formed. The common electrode 53 is an electrode to which a predetermined constant potential is applied. The insulating film 54 insulates the common electrode 53 from the pixel electrodes 55. The pixel electrodes 55 are provided for each pixel Pix, and the potential of each electrode is individually controlled. The lower alignment film 56 is provided to cover the pixel electrodes 55 and the insulating film 54.

[0063] The counter substrate SUB2 has a second insulating substrate 59 and an upper alignment film 58. The upper alignment film 58 is provided on the surface of the second insulating substrate 59 facing the first insulating substrate 51. The upper alignment film 58 forms the surface of the counter substrate SUB2 on the liquid crystal layer LC side. In this embodiment, no color filter CF (see FIG. 14) is provided on the array substrate SUB1 or the counter substrate SUB2. That is, the liquid crystal panel 50 emits monochrome light toward the photodiode 30.

[0064] Although not shown in Fig. 8, optical elements including polarizing plates are provided on the outer surfaces of the first insulating substrate 51 and the second insulating substrate 59, respectively. The polarization axes of the pair of polarizing plates are in a crossed Nicol positional relationship in a plan view. Furthermore, the counter substrate SUB2 may be provided with a color filter or a light-shielding film as necessary.

[0065] The liquid crystal layer LC modulates light passing therethrough according to the state of an electric field, and uses, for example, a liquid crystal in a transverse electric field mode such as IPS (In-Plane Switching) including FFS (Fringe Field Switching). In this embodiment, the liquid crystal layer LC is driven by a transverse electric field generated between the pixel electrodes 55 and the common electrode 53 provided on the array substrate, and the orientation of the liquid crystal molecules 57 of the liquid crystal layer LC is controlled.

[0066] However, the liquid crystal panel 50 is not limited to this configuration, and may be a vertical electric field type. In this case, the pixel electrodes are provided on the array substrate SUB1, and the common electrode is provided on the counter substrate SUB2. Vertical electric field type liquid crystal panels include TN (Twisted Nematic), VA (Vertical Alignment), and ECB (Electrically Controlled Birefringence), in which a so-called vertical electric field is applied to the liquid crystal layer.

[0067] Next, an example of the positional relationship and detection operation between the liquid crystal panel 50 and the optical sensor 10 will be described. Fig. 9 is a plan view schematically showing the positional relationship between a plurality of pixels of the liquid crystal panel and a plurality of sensor pixels of the optical sensor in the detection device according to the first embodiment.

[0068] As shown in FIG. 9, one photodiode 30 is arranged at a position overlapping multiple pixels Pix. In FIG. 9, one photodiode 30 is arranged overlapping four pixels Pix. That is, in a plan view, the size of the photodiode 30 is larger than the size of each of the multiple pixels Pix. In this embodiment, the size of the photodiode 30 is defined as the area of ​​a region surrounded by a sensor gate line GLS and a sensor signal line SLS (see FIG. 5). Similarly, the size of a pixel Pix is ​​defined as the area of ​​a region surrounded by a scanning line GL and a signal line SL (see FIG. 7).

[0069] Furthermore, the arrangement pitch PL1 of the pixels Pix in the first direction Dx is smaller than the arrangement pitch PS1 of the photodiodes 30 in the first direction Dx. The arrangement pitch PL2 of the pixels Pix in the second direction Dy is smaller than the arrangement pitch PS2 of the photodiodes 30 in the second direction Dy. More preferably, the arrangement pitch PS1 of the photodiodes 30 in the first direction Dx is an integer multiple of the arrangement pitch PL1 of the pixels Pix in the first direction Dx. The arrangement pitch PS2 of the photodiodes 30 in the second direction Dy is an integer multiple of the arrangement pitch PL2 of the pixels Pix in the second direction Dy. In the example shown in FIG. 9 , the arrangement pitches PS1 and PS2 of the photodiodes 30 are twice the arrangement pitches PL1 and PL2 of the pixels Pix.

[0070] The arrangement pitch PS1 of the photodiodes 30 in the first direction Dx is determined by the arrangement pitch of the sensor signal lines SLS in the first direction Dx. The arrangement pitch PS2 of the photodiodes 30 in the second direction Dy is determined by the arrangement pitch of the sensor gate lines GLS in the second direction Dy. Similarly, the arrangement pitch PL1 of the pixels Pix in the first direction Dx is determined by the arrangement pitch of the signal lines SL in the first direction Dx. The arrangement pitch PL2 of the pixels Pix in the second direction Dy is determined by the arrangement pitch of the scanning lines GL in the second direction Dy.

[0071] FIG. 9 shows two rows and two columns of sensor pixels 3 (photodiodes 30). Two rows and two columns of pixels Pix are arranged so as to overlap one photodiode 30. In the following description, the pixels Pix overlapping one photodiode 30 will be referred to as a first pixel Pix-1, a second pixel Pix-2, a third pixel Pix-3, and a fourth pixel Pix-4. The first pixel Pix-1 and the second pixel Pix-2 are arranged adjacent to each other in the first direction Dx. The third pixel Pix-3 and the fourth pixel Pix-4 are arranged adjacent to each other in the first direction Dx. The first pixel Pix-1 and the second pixel Pix-2 aligned in the first direction Dx are adjacent to the third pixel Pix-3 and the fourth pixel Pix-4, respectively, in the second direction Dy. However, when there is no need to distinguish between the first pixel Pix-1, the second pixel Pix-2, the third pixel Pix-3, and the fourth pixel Pix-4, they will be simply referred to as pixels Pix.

[0072] FIG. 10 is an explanatory diagram illustrating an example of the detection operation of the detection device according to the first embodiment. FIG. 11 is an explanatory diagram illustrating a method for generating a combined image by the detection device according to the first embodiment. In FIG. 10, pixels Pix in a transmissive state are shown without hatching (white), and pixels Pix in a non-transmissive state are shown with hatching. FIG. 10 illustrates a case in which the object to be detected 100 is arranged so as to overlap one photodiode 30 located at the upper left among the multiple photodiodes 30. FIG. 11 illustrates the detection signal (sensor value So) output from the photodiode 30 for each of the detection periods F1, F2, F3, and F4, in association with the pixel Pix in a transmissive state in each detection period F.

[0073] In the following description, when it is not necessary to distinguish between the detection periods F1, F2, F3, and F4, they will simply be referred to as the detection period F. Furthermore, when it is not necessary to distinguish between the first sensor value So1, the second sensor value So2, the third sensor value So3, and the fourth sensor value So4, they will simply be referred to as the sensor value So.

[0074] 10, the liquid crystal panel 50 sets at least one pixel Pix of the multiple pixels Pix overlapping the photodiode 30 in a transmissive state and the other pixels Pix in a non-transmissive state. The photodiode 30 of each sensor pixel 3 detects the object 100 based on light that is emitted from the light source 80 and that has passed through the transmissive pixels Pix. In other words, the light emitted from the light source 80 is blocked in the portion of the photodiode 30 that overlaps with the non-transmissive pixels Pix, and the object 100 is not detected.

[0075] The liquid crystal panel 50 sequentially scans the transmissive pixels Pix among the plurality of pixels Pix overlapping the photodiode 30 for each of the predetermined detection periods F1, F2, F3, and F4. That is, the liquid crystal panel 50 switches the arrangement pattern of the transmissive pixels Pix and the non-transmissive pixels Pix among the plurality of pixels Pix overlapping the photodiode 30 for each of the detection periods F1, F2, F3, and F4. The photodiode 30 sequentially outputs a detection signal Vdet (sensor value So) corresponding to light transmitted through the transmissive pixels Pix for each of the detection periods F1, F2, F3, and F4.

[0076] Specifically, during the detection period F1, the liquid crystal panel 50 sets the first pixel Pix-1 of the multiple pixels Pix overlapping the photodiode 30 to a transmissive state, and sets the second pixel Pix-2, the third pixel Pix-3, and the fourth pixel Pix-4 to a non-transmissive state. During the detection period F1, the photodiode 30 outputs a detection signal (first sensor value So1) corresponding to the light that has passed through the transmissive first pixel Pix-1. During the detection period F1 in FIG. 10, in one photodiode 30 located at the upper left, light from the light source 80 passes through a portion of the object 100 that overlaps with the transmissive first pixel Pix-1. During the detection period F1, the photodiode 30 detects the portion of the object 100 that overlaps with the first pixel Pix-1.

[0077] During the next detection period F2, the liquid crystal panel 50 sets the second pixel Pix-2 of the multiple pixels Pix overlapping the photodiode 30 to a transmissive state, and sets the first pixel Pix-1, the third pixel Pix-3, and the fourth pixel Pix-4 to a non-transmissive state. During the detection period F2, the photodiode 30 outputs a detection signal (second sensor value So2) corresponding to the light that has passed through the second pixel Pix-2 in the transmissive state. During the detection period F2 in FIG. 10, in one photodiode 30 located at the upper left, light from the light source 80 passes through a portion of the object 100 that overlaps with the second pixel Pix-2 in the transmissive state. During the detection period F2, the photodiode 30 detects the portion of the object 100 that overlaps with the second pixel Pix-2.

[0078] During the next detection period F3, the liquid crystal panel 50 sets the third pixel Pix-3 of the multiple pixels Pix overlapping the photodiode 30 to a transmissive state, and sets the first pixel Pix-1, the second pixel Pix-2, and the fourth pixel Pix-4 to a non-transmissive state. During the detection period F3, the photodiode 30 outputs a detection signal (third sensor value So3) corresponding to the light that has passed through the transmissive third pixel Pix-3. During the detection period F3 in FIG. 10, in one photodiode 30 located at the upper left, light from the light source 80 passes through a portion of the object 100 that overlaps with the transmissive third pixel Pix-3. During the detection period F3, the photodiode 30 detects the portion of the object 100 that overlaps with the third pixel Pix-3.

[0079] During the next detection period F4, the liquid crystal panel 50 sets the fourth pixel Pix-4 of the multiple pixels Pix overlapping the photodiode 30 to a transmissive state, and sets the first pixel Pix-1, the second pixel Pix-2, and the third pixel Pix-3 to a non-transmissive state. During the detection period F4, the photodiode 30 outputs a detection signal (fourth sensor value So4) corresponding to the light that has passed through the transmissive fourth pixel Pix-4. During the detection period F4 in FIG. 10, in one photodiode 30 located at the upper left, light from the light source 80 passes through a portion of the object 100 that overlaps with the transmissive fourth pixel Pix-4. During the detection period F4, the photodiode 30 detects the portion of the object 100 that overlaps with the transmissive fourth pixel Pix-4.

[0080] 10, even if the object 100 is a minute object whose size is smaller than the arrangement pitches PS1 and PS2 of the photodiodes 30, by scanning the pixels Pix in the transmitting state, the detection device 1 according to this embodiment can detect information on each portion of the object 100 that overlaps with the pixels Pix in the transmitting state using one photodiode 30. In the example shown in FIG. 10, four detection signals (sensor values ​​So) are output from one photodiode 30.

[0081] The sensor value storage circuit 71 (see FIG. 2) of the host IC 70 stores the first sensor value So1, the second sensor value So2, the third sensor value So3, and the fourth sensor value So4 output from the photodiode 30 for each of the detection periods F1, F2, F3, and F4. The combined image generation circuit 76 (see FIG. 2) acquires information on each sensor value So for each of the detection periods F1, F2, F3, and F4 from the sensor value storage circuit 71. The combined image generation circuit 76 also acquires information on the arrangement pattern of multiple pixels Pix in a transmissive state and pixels Pix in a non-transmissive state for each of the detection periods F1, F2, F3, and F4 from the image storage circuit 75.

[0082] 11, the combined image generation circuit 76 integrates the multiple sensor values ​​So based on the multiple detection signals (first sensor value So1, second sensor value So2, third sensor value So3, and fourth sensor value So4) for each of the detection periods F1, F2, F3, and F4 and information (position information) of the pixels Pix in the transparent state for each of the detection periods F1, F2, F3, and F4. As a result, the combined image generation circuit 76 synthesizes the images for the multiple detection periods F1, F2, F3, and F4 to generate a single combined image.

[0083] As described above, the detection device 1 scans the pixels Pix in the transmissive state for each detection period F and generates a combined image by integrating multiple sensor values ​​So for each detection period F, thereby improving the effective resolution of the optical sensor 10 to at least the arrangement pitches PS1, PS2 of the multiple photodiodes 30. The effective resolution of the generated combined image can be improved to approximately the same as the arrangement pitches PL1, PL2 of the pixels Pix on the liquid crystal panel 50.

[0084] 10 , for example, in the first pixel row, the liquid crystal panel 50 arranges transmissive pixels Pix and non-transmissive pixels Pix alternately in the first direction Dx. The arrangement pitch PLon1 of the transmissive pixels Pix in the first direction Dx is equal to or greater than the arrangement pitch PS1 of the multiple photodiodes 30 in the first direction Dx. Similarly, in the leftmost pixel column, the liquid crystal panel 50 arranges transmissive pixels Pix and non-transmissive pixels Pix alternately in the second direction Dy. The arrangement pitch PLon2 of the transmissive pixels Pix in the second direction Dy is equal to or greater than the arrangement pitch PS2 of the multiple photodiodes 30 in the second direction Dy.

[0085] By using such an arrangement pattern of the transmissive pixels Pix and the non-transmissive pixels Pix, it is possible to prevent two or more transmissive pixels Pix from being arranged apart in an area overlapping one photodiode 30. This allows the detection device 1 to effectively improve the substantial resolution of the optical sensor 10.

[0086] As described above, the light source 80 (see FIG. 1) irradiates the liquid crystal panel 50 with parallel light. As a result, the light that passes through the pixel Pix in the transmissive state passes through a portion of the object 100 that overlaps with the pixel Pix in the transmissive state and is incident on the photodiode 30 that overlaps with the pixel Pix in the transmissive state. In other words, compared to when light is incident on the pixel Pix in the transmissive state from an oblique direction, the light that has passed through the pixel Pix in the transmissive state can be prevented from passing through a portion of the object 100 that does not overlap with the pixel Pix in the transmissive state, or from being incident on another photodiode 30 adjacent to the photodiode 30 that overlaps with the pixel Pix in the transmissive state. Therefore, the detection device 1 can prevent image blurring.

[0087] 10, the arrangement pattern of the transmissive pixels Pix and the non-transmissive pixels Pix in one detection period F is the same for each of the multiple photodiodes 30. However, this is not limited to this, and the arrangement patterns may be different for the multiple photodiodes 30. Furthermore, for one photodiode 30, the transmissive pixels Pix in each detection period F may be scanned in any order.

[0088] 12 is a diagram showing simulation results of images detected by the detection devices according to the example and the comparative example. As shown in FIG. 12, the simulation results of images detected by the detection device 1 according to the example and the detection device 200 according to the comparative example are shown, where the same annular detectable object 100a is detected.

[0089] The detection device 200 according to the comparative example does not include a liquid crystal panel 50. As shown in Fig. 9, the detection device 200 according to the comparative example has a low image resolution for the object 100a to be detected, making it difficult to distinguish the shape of the object 100a. In the detection device 200 according to the comparative example, the resolution of the detected image is determined by the arrangement pitches PS1 and PS2 of the multiple photodiodes 30.

[0090] 9, when the object to be detected 100 is a minute object whose size is smaller than the arrangement pitches PS1 and PS2 of the photodiodes 30, one detection signal (sensor value So) is output from one photodiode 30. In other words, the detection device 200 of the comparative example can only detect the presence or absence of the object to be detected 100, which is a minute object, and it may be difficult to detect the outer shape.

[0091] In contrast, the detection device 1 according to the embodiment is configured by combining a plurality of photodiodes 30 and a liquid crystal panel 50. The arrangement pitches PL1, PL2 of the plurality of pixels Pix are approximately ¼ of the arrangement pitches PS1, PS2 of the plurality of photodiodes 30. As shown in FIG. 12 , the detection device 1 according to the embodiment has improved resolution compared to the detection device 200 of the comparative example, and detects an annular image close to the detection target 100a. It was shown that the detection device 1 according to the embodiment can improve the substantial resolution of the generated combined image to the same extent as the arrangement pitches PL1, PL2 of the plurality of pixels Pix.

[0092] 9 to 11 are shown schematically to facilitate understanding, and the shapes, numbers, and relative positions of the photodiodes 30 and the pixels Pix can be changed as appropriate. For example, the number of pixels Pix overlapping one photodiode 30 may be two, three, or five or more. While the optical sensor 10 has been described as having multiple photodiodes 30, this is not limiting. The optical sensor 10 only needs to have at least one photodiode 30, and the detection device 1 may have multiple pixels Pix of the liquid crystal panel 50 overlapping one photodiode 30.

[0093] (Second embodiment) Fig. 13 is a plan view schematically showing the arrangement relationship between a plurality of pixels of a liquid crystal panel and a plurality of sensor pixels of an optical sensor in a detection device according to a second embodiment. Fig. 14 is a cross-sectional view schematically showing an example of the configuration of a liquid crystal panel according to the second embodiment. In the following description, the same components as those described in the above embodiments are assigned the same reference numerals, and redundant description will be omitted.

[0094] 13, in the detection device 1A according to the second embodiment, each of the pixels Pix has a first subpixel SPixR, a second subpixel SPixG, and a third subpixel SPixB. In Fig. 13, one photodiode 30 is arranged to overlap four pixels Pix, i.e., 12 subpixels SPix.

[0095] The first subpixel SPixR, second subpixel SPixG, and third subpixel SPixB are arranged side by side in this order in the first direction Dx. The first subpixel SPixR has a first-color color filter CFR (see FIG. 14) and emits red (R) light. The second subpixel SPixG has a second-color color filter CFG (see FIG. 14) and emits green (G) light. The third subpixel SPixB has a third-color color filter CFB (see FIG. 14) and emits blue (B) light.

[0096] 14, the counter substrate SUB2 of the liquid crystal panel 50A according to the second embodiment has a color filter CF. The color filter CF is provided on the surface of the second insulating substrate 59 facing the first insulating substrate 51. An upper alignment film 58 is provided to cover the color filter CF. The color filter CF has a first-color color filter CFR, a second-color color filter CFG, and a third-color color filter CFB, and color regions colored in three colors, red (R), green (G), and blue (B), are periodically arranged.

[0097] The color filter CF may include four or more color regions, and in this case, the pixel Pix may include four or more sub-pixels SPix.

[0098] Fig. 15 is an explanatory diagram for explaining an example of the detection operation of the detection device according to the second embodiment. Note that Fig. 15 shows an example in which the transmissive sub-pixels SPix of the first pixel Pix-1 and the second pixel Pix-2 are scanned, and the third pixel Pix-3 and the fourth pixel Pix-4 are not shown.

[0099] As shown in FIG. 15, the liquid crystal panel 50A sets one sub-pixel SPix of the pixels Pix overlapping one photodiode 30 in a transmissive state and the other sub-pixels SPix in a non-transmissive state.

[0100] Specifically, during the detection period SF1 (first period), the liquid crystal panel 50A sets the first subpixel SPixR of the first pixel Pix-1, among the multiple pixels Pix overlapping the photodiode 30, to a transmissive state, and sets the second subpixel SPixG, third subpixel SPixB, second pixel Pix-2, third pixel Pix-3, and fourth pixel Pix-4 of the first pixel Pix-1 to a non-transmissive state. During the detection period SF1, the photodiode 30 outputs a detection signal (first sensor value So1) corresponding to light that has passed through the first subpixel SPixR of the first pixel Pix-1, which is in a transmissive state.

[0101] During the detection period SF2 (second period), the liquid crystal panel 50A sets the second subpixel SPixG of the first pixel Pix-1, among the multiple pixels Pix overlapping the photodiode 30, to a transmissive state, and sets the first subpixel SPixR, third subpixel SPixB, second pixel Pix-2, third pixel Pix-3, and fourth pixel Pix-4 of the first pixel Pix-1 to a non-transmissive state. During the detection period SF2, the photodiode 30 outputs a detection signal (second sensor value So2) corresponding to light that has passed through the second subpixel SPixG of the first pixel Pix-1, which is in a transmissive state.

[0102] During the detection period SF3 (third period), the liquid crystal panel 50A sets the third subpixel SPixB of the first pixel Pix-1 of the multiple pixels Pix overlapping the photodiode 30 to a transmissive state, and sets the first subpixel SPixR, second subpixel SPixG, second pixel Pix-2, third pixel Pix-3, and fourth pixel Pix-4 of the first pixel Pix-1 to a non-transmissive state. During the detection period SF3, the photodiode 30 outputs a detection signal (third sensor value So3) corresponding to light that has passed through the third subpixel SPixB of the first pixel Pix-1 in a transmissive state.

[0103] Thereafter, the detection periods SF1, SF2, and SF3 are repeatedly executed for the subpixels SPix of the second pixel Pix-2, the third pixel Pix-3, and the fourth pixel Pix-4. That is, in the second pixel Pix-2, the first subpixel SPixR, the second subpixel SPixG, and the third subpixel SPixB are sequentially set to the transmissive state in a time-division manner. Next, in the third pixel Pix-3, the first subpixel SPixR, the second subpixel SPixG, and the third subpixel SPixB are sequentially set to the transmissive state in a time-division manner. Next, in the fourth pixel Pix-4, the first subpixel SPixR, the second subpixel SPixG, and the third subpixel SPixB are sequentially set to the transmissive state in a time-division manner.

[0104] The combined image generation circuit 76 (see FIG. 2) acquires information on the sensor values ​​So for each of the detection periods SF1, SF2, and SF3 from the sensor value storage circuit 71. In the example shown in FIG. 15, the combined image generation circuit 76 acquires information on 12 sensor values ​​So for each photodiode 30. The combined image generation circuit 76 also acquires a total of 12 pieces of information on the arrangement pattern of multiple transmissive sub-pixels SPix and non-transmissive sub-pixels SPix for each of the detection periods SF1, SF2, and SF3 from the image storage circuit 75.

[0105] The combined image generation circuit 76 acquires red image information based on first sensor values ​​So1 during multiple detection periods SF1. The combined image generation circuit 76 acquires green image information based on second sensor values ​​So2 during multiple detection periods SF2. The combined image generation circuit 76 acquires blue image information based on third sensor values ​​So3 during multiple detection periods SF3. The combined image generation circuit 76 synthesizes the images during multiple detection periods SF1, SF2, and SF3 to generate a single combined color image.

[0106] As described above, the detection device 1A according to the second embodiment switches the arrangement pattern of the transmissive and non-transmissive sub-pixels SPix for each of the detection periods SF1, SF2, and SF3, allowing the detection device 1A to generate a color image with a resolution equal to or greater than the arrangement pitches PS1 and PS2 of the multiple photodiodes 30.

[0107] (Modification of the second embodiment) 16 is an explanatory diagram for explaining an example of the detection operation of a detection device according to a modification of the second embodiment. In the detection device 1B according to the modification of the second embodiment, the liquid crystal panel 50A is similar to that of the second embodiment (see FIGS. 13 and 14), and includes a color filter CF and a plurality of sub-pixels SPix.

[0108] 16, during the detection period F1, the liquid crystal panel 50A simultaneously sets the first subpixel SPixR, the second subpixel SPixG, and the third subpixel SPixB of the first pixel Pix-1 to a transmissive state. Furthermore, during the detection period F1, the liquid crystal panel 50A sets the second pixel Pix-2 and the third pixel Pix-3 to a non-transmissive state. In other words, the light that passes through the first pixel Pix-1 becomes white light, and the liquid crystal panel 50A emits monochrome light toward the photodiode 30.

[0109] The detection device 1B according to a modification of the second embodiment can generate a monochrome image even if the liquid crystal panel 50A has a color filter CF and multiple sub-pixels SPix. In this case, the time required for detection is shortened and the load required for processing various information in the host IC 70 is reduced compared to the second embodiment. Furthermore, the detection devices 1A and 1B shown in the second embodiment and the modification have a common configuration in which the liquid crystal panel 50A has a color filter CF and multiple sub-pixels SPix, and can switch between detecting monochrome images and detecting color images by driving the pixels Pix differently.

[0110] (Third embodiment) 17 is a plan view schematically showing the arrangement relationship between a plurality of pixels of a liquid crystal panel and a plurality of sensor pixels of an optical sensor in a detection device according to the third embodiment. In the first embodiment, the second embodiment, and the modified example described above, the arrangement pitches PS1 and PS2 of the photodiodes 30 are integer multiples of the arrangement pitches PL1 and PL2 of the pixels Pix, but the present invention is not limited to this.

[0111] 17, in the detection device 1C according to the third embodiment, the arrangement pitches PS1 and PS2 of the photodiodes 30 are non-integer multiples of the arrangement pitches PL1 and PL2 of the pixels Pix. Specifically, 10 rows and 10 columns of pixels Pix are arranged side by side, overlapping the photodiodes 30 arranged in 3 rows and 3 columns. In other words, the arrangement pitches PS1 and PS2 of the photodiodes 30 are approximately 3.33 times the arrangement pitches PL1 and PL2 of the pixels Pix.

[0112] In this embodiment, at least one pixel Pix among the multiple pixels Pix is ​​arranged across the boundary BD between two adjacent photodiodes 30. In this embodiment, as in the first embodiment described above, the arrangement pattern of the pixels Pix in the transmissive state and the pixels Pix in the non-transmissive state is switched for each detection period F.

[0113] For pixels Pix that do not overlap the boundary BD of the photodiode 30, the photodiode 30 outputs a sensor value So for each pixel Pix, as in the first embodiment described above. In contrast, when a pixel Pix that overlaps the boundary BD of the photodiode 30 is in a transparent state (indicated by the symbol Pix-on in FIG. 17), light that has passed through the pixel Pix in the transparent state is split and irradiated onto the two photodiodes 30. Therefore, near the boundary BD, the amount of light irradiated onto each of the two photodiodes 30 decreases, which may result in a decrease in detection sensitivity.

[0114] FIG. 18 is a plan view showing an example of a sensitivity map of an optical sensor according to the third embodiment. The sensitivity map shown in FIG. 18 shows the distribution of detection sensitivity of the photodiodes 30. Specifically, the distribution of detection sensitivity is the distribution of gradation values ​​of the combined image. However, this is not limited to this, and the sensitivity map may use other values, such as the sensor value So. In the sensitivity map shown in FIG. 18, the sensitivity decreases in the order of the white display area, the hatched area, and the black display area. The hatched area and the black display area in the sensitivity map are areas along the boundary BD of the photodiodes 30.

[0115] As shown in FIG. 17, pixels Pix overlapping the boundary BD are arranged to be biased so as to be asymmetric with respect to the boundary BD. That is, the area where one pixel Pix overlapping the boundary BD overlaps with one of the photodiodes 30 adjacent to the boundary BD is different from the area where the one pixel Pix overlaps with the other photodiode 30 adjacent to the boundary BD. As a result, as shown in FIG. 18, in the vicinity of the boundary BD, there are a black display area with low sensitivity and a shaded area with medium sensitivity.

[0116] Next, a method for correcting the sensor value So using the sensitivity map will be described. FIG. 19 is a flowchart for explaining a method of calculating a correction value of the detection device according to the third embodiment. As shown in FIG. 19, the detection device 1C scans and detects the pixels Pix in the transmission state with the detected object 100 not arranged in the detection area AA (step ST1).

[0117] The combined image generation circuit 76 integrates a plurality of detection signals (sensor values So) for each of the plurality of detection periods F and information (position information) of the pixels Pix in the transmission state for each of the detection periods F, based on the same as in the first embodiment described above. Thereby, the combined image generation circuit 76 generates one combined image in a state where the detected object 100 is not arranged in the detection area AA (step ST2).

[0118] The sensitivity map storage circuit 72 (see FIG. 2) stores the combined image obtained in step ST2 as a sensitivity map (step ST3). The sensitivity map storage circuit 72 stores, for example, the distribution of the gradation values of the combined image as the sensitivity map. In the sensitivity map in FIG. 18, for example, the sensitivity map storage circuit 72 stores the distribution of these gradation values with the gradation value of the white display area being 256, the gradation value of the shaded area being gradation A (A < 256), and the gradation value of the black display area being gradation B (B < A).

[0119] The correction value generation circuit 73 calculates a correction value for the gradation value of the combined image acquired by the multiple photodiodes 30. The correction value generation circuit 73 (see FIG. 2) calculates a correction value based on the reciprocal of the sensitivity map stored in advance in the sensitivity map storage circuit 72 (step ST4). In this case, the reciprocal of the sensitivity map is a coefficient corresponding to the reciprocal of the gradation value. When the gradation value of the white display area is 256, the gradation value of the hatched area is 171, and the gradation value of the black display area is 85, the correction value generation circuit 73 calculates the correction value for the white display area as 1 (=256 / 256), the correction value for the hatched area as 256 / A, and the correction value for the black display area as 256 / B.

[0120] In this way, the correction value generation circuit 73 generates a correction value that increases the gradation of the acquired combined image in an area where one pixel Pix is ​​arranged straddling the boundary BD between two adjacent photodiodes 30.

[0121] The combined image generating circuit 76 corrects the combined image of the object 100 based on the correction value calculated by the correction value generating circuit 73 (step ST5). As a result, the gradation value near the boundary BD where the detection sensitivity is low is corrected, and a good combined image is obtained.

[0122] In this way, the detection device 1C can correct the combined image based on a sensitivity map acquired in advance. Therefore, even if the arrangement pitches PS1, PS2 of the photodiodes 30 are not an integer multiple of the arrangement pitches PL1, PL2 of the pixels Pix, the detection device 1C can correct the distribution of detection sensitivity and obtain a good combined image. In other words, the detection device 1C of this embodiment can improve the degree of freedom in arranging the multiple photodiodes 30 and the multiple pixels Pix.

[0123] Note that the method of calculating the correction values ​​by the correction value generation circuit 73 is shown schematically for ease of understanding, and any method may be used. Furthermore, in this embodiment, an example has been shown in which the liquid crystal panel 50 emits monochrome light, but this is not limiting and the present invention can be combined with the second embodiment. That is, the detection device 1C may generate a correction value for a red (R) image of the first subpixel SPixR, a correction value for a green (G) image of the second subpixel SPixG, and a correction value for a blue (B) image of the third subpixel SPixB.

[0124] Although preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally fall within the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of each of the above-described embodiments and modifications. [Explanation of symbols]

[0125] 1, 1A, 1B, 1C Detector 3 sensor pixels 10 Optical Sensor 11 Detection control circuit 12 Pixel control circuit 21 PCB 30 Photodiode 50, 50A LCD panel 70 Host IC 71 Sensor value storage circuit 72 Sensitivity map memory circuit 73 Correction value generation circuit 76 Combined image generation circuit 80 light source LC liquid crystal layer Vdet detection signal Pix Pix-1 1st pixel Pix-2 2nd pixel Pix-3 3rd pixel Pix-4 4th pixel SPixR 1st subpixel SPixG 2nd subpixel SPixB 3rd subpixel So sensor value

Claims

1. a plurality of photodiodes provided on a substrate; a light source disposed opposite the photodiode; a liquid crystal panel disposed between the plurality of photodiodes and the light source in a direction perpendicular to the substrate; The liquid crystal panel has a plurality of pixels, a size of the photodiode is larger than a size of each of the plurality of pixels in a plan view, and the photodiode is disposed at a position overlapping the plurality of pixels; the liquid crystal panel sets at least one of the plurality of pixels overlapping the photodiode in a transmissive state and the other pixels in a non-transmissive state; At least one of the plurality of pixels is arranged across a boundary between two adjacent photodiodes, a storage circuit that stores a distribution of detection sensitivities of the plurality of photodiodes; a correction value generation circuit that calculates a correction value for the gradation of an image acquired by the plurality of photodiodes based on the distribution of the detection sensitivities; Detection device.

2. The correction value generation circuit generates the correction value for increasing the gradation of the acquired image in an area where one pixel is arranged straddling a boundary between two adjacent photodiodes. The detection device according to claim 1 .

3. The arrangement pitch of the plurality of photodiodes in a first direction is an integer multiple of the arrangement pitch of the pixels in the first direction. The detection device according to claim 1 .

4. The liquid crystal panel emits monochrome light toward the photodiode. The detection device according to claim 1 .

5. Each pixel of the liquid crystal panel includes a first sub-pixel having a color filter of a first color, a second sub-pixel having a color filter of a second color, and a third sub-pixel having a color filter of a third color. The detection device according to claim 1 .

6. a plurality of photodiodes provided on a substrate; a light source disposed opposite the photodiode; a liquid crystal panel disposed between the plurality of photodiodes and the light source in a direction perpendicular to the substrate; The liquid crystal panel has a plurality of pixels, a size of the photodiode is larger than a size of each of the plurality of pixels in a plan view, and the photodiode is disposed at a position overlapping the plurality of pixels; the liquid crystal panel sets at least one of the plurality of pixels overlapping the photodiode in a transmissive state and the other pixels in a non-transmissive state; Each pixel of the liquid crystal panel includes a first sub-pixel having a color filter of a first color, a second sub-pixel having a color filter of a second color, and a third sub-pixel having a color filter of a third color; The liquid crystal panel simultaneously causes the first subpixel, the second subpixel, and the third subpixel to be in a transmissive state. Detection device.

7. The light source irradiates parallel light toward the liquid crystal panel. The detection device according to any one of claims 1 to 6.

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