49results about How to "Short etching time" patented technology

The invention provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the steps that a semiconductor substrate is provided; a mask layer and a sacrificial material layer located on the surface of the mask layer are sequentially formed on the surface of the semiconductor substrate; the sacrificial material layer is etched to form a plurality of discrete sacrificial layers; side walls are formed on the side wall surfaces of the sacrificial layers; the sacrificial layers are removed; and supplement side walls are formed on the side wall surfaces of the side walls. By the method, improvement of the performance of the formed semiconductor structure is facilitated.

A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

The invention concerns a PC board with laminates for electrical circuits, the PC board comprising at least one carrier (1) and at least one copper surface layer (7), intended to, after the removal of selected parts, e.g. by etching, function as conductors on the PC board. The new thing is that the carrier at least at some parts has a surface roughness of up to mainly the same size as the thickness of the copper layer and that at least at the above named rough parts is arranged a surface levelling layer (5a,b) between the carrier (1) and the copper layer (7). Further, the invention concerns a method for producing PC board laminate for electrical circuits as above, the laminate comprising a copper layer and a carrier that has a surface roughness of mainly the same size as the thickness of the copper layer. The new thing here is that a layer (5a,b) of liquid epoxy is applied on the one or those surface parts of the carrier which in the end are to carry a copper layer, that the epoxy layer is dried and hardened, and that copper layers (7) are plated on the epoxy layers (5a,b).

The invention relates to a forming method of a transistor. The forming method of the transistor includes the following steps that: a semiconductor substrate is provided, wherein the semiconductor substrate includes a first region and a second region; a dummy gate dielectric material layer is formed on the surface of the semiconductor substrate, wherein the dummy gate dielectric material layer includes a first insulating material layer and a second insulating material layer; a dummy gate and a second gate are formed; the dummy gate dielectric material layer is etched with the dummy gate and the second gate adopted as a mask, so that a dummy gate dielectric layer and a second gate dielectric layer are formed; first source / drain areas are formed in the first region, and second source / drain areas are formed in the second region; a dielectric layer is formed on the surface of the semiconductor substrate, and the surface of the dielectric layer is flush with the surface of the dummy gate; and the second insulating material layer in the dummy gate dielectric material layer is removed through adopting a dry etching process, and the first insulating material layer in the dummy gate dielectric material layer is removed through adopting a wet etching process, and therefore, a groove can be formed; and a first gate structure is formed in the groove. With the forming method of the transistor adopted, steps can be decreased, and the performance of the transistor can be improved.

A manufacturing method of a semiconductor device includes the following steps. A barrier layer is formed in a first region and a second region of a semiconductor substrate. The barrier layer formed in the first region is thinned before a step of forming a first work function layer on the barrier layer. The first work function layer formed on the first region is then removed. The process of thinning the barrier layer in the first region and the process of removing the first work function layer in the first region are performed separately for ensuring the coverage of the first work function layer in the second region. The electrical performance of the semiconductor device and the uniformity of the electrical performance of the semiconductor device may be improved accordingly.

The present invention provides a manufacturing method in which a laminate consisting of a conductive inorganic layer-insulating layer-conductive inorganic layer or an insulating layer of a laminate consisting of a conductive inorganic layer-insulating layer is wet-etched. When manufacturing electronic parts, the cost is low, and there is no need to use organic solvents, which are problematic in waste disposal, to manufacture electronic parts. It relates to a manufacturing method of an electronic component, which conducts electrical conductivity by wet etching a laminate composed of a conductive inorganic layer-insulating layer-conductive inorganic layer or a laminate composed of a conductive inorganic layer-insulating layer. The layout of the inorganic layer is followed by the layout of the insulating layer by wet etching. The insulating layer in the laminated body can be wet-etched, and has a single-layer structure or a laminated structure of more than two insulating unit layers, including using a photosensitive adhesive film to perform layout of the insulating layer through the wet-etching.

A method of synthesizing corrugated and nanoporous microspheres including the steps of synthesizing substantially smooth spherical microspheres, and controlled wet-etching of the substantially smooth spherical microspheres with a basic solution having a pH above 10.00 is provided. The microspheres can include, for example, silica microspheres or titania microspheres of various sized diameters of between 50 nm and 600 nm. The basic solution can include an aqueous potassium cyanide solution or an aqueous potassium hydroxide solution. Methods of using the corrugated and nanoporous microspheres described herein are also provided.

The invention relates to a method for forming a transistor, which comprises the steps of providing a substrate; forming a pseudo-grid structure in a first region, wherein the pseudo-grid structure comprises a pseudo-grid dielectric layer and a pseudo-grid electrode; forming a second grid electrode structure in a second region, wherein the second grid electrode structure comprises a second grid dielectric layer and a second grid electrode, the thickness of the pseudo-grid dielectric layer is less than the thickness of the second grid dielectric layer, and the top surface of the pseudo-grid electrode is flush with the top surface of the second grid electrode; forming a side wall at the side wall surface of the pseudo-grid structure and the side wall surface of the second grid electrode structure; forming a first dielectric layer on the substrate; removing the pseudo-grid structure, and forming a groove in the first region; and forming the first grid electrode structure in the groove, wherein the first grid electrode structure comprises a first grid dielectric layer located at the inner wall surface of the groove and the second grid electrode structure which is located at the surface of the first grid dielectric layer and fully fills the groove. The method provided by the invention can improve the performance of the transistor of a core region.

The invention discloses a method for producing a dual damascene structure. The method comprises the following steps of: depositing a part of silicon-containing coating in a through hole; then depositing a bottom antireflective coating; carrying out interconnected groove etching; and when the silicon-containing coating is exposed, introducing CF4, N2 and Ar and continuously etching, or introducingCF4, N2 and Ar for etching and then introducing CF4, N2, Ar and C4F8 and continuously etching. In the environment of the CF4, the N2 and the Ar, the ratio of the etching rate of the silicon-containing coating to the etching rate of a dielectric layer with a low dielectric constant can reach 1.1; in the environment of the CF4, the N2, the Ar and the C4F8, the ratio of the etching rate of the silicon-containing coating to the etching rate of the dielectric layer with the low dielectric constant can reach 3, thereby over etching of the silicon-containing coating is extremely realized when the interconnected groove etching is carried out. Therefore, the method is beneficial to enabling the top of a through hole and the bottom of the interconnected groove to form a circular corner, avoids the damage to the side of the interconnected groove and enables the interconnected groove to keep vertical.

The present invention provides a preparation method to prepare silicon -based microneedles with metal auxiliary wet etching, including: the pre -processing silicon wafer surface is applied to the graphic processing to obtain the sample;Fluoric acid 纯 ultra -pure water hybrid solution is deposited to obtain sedimentary silicon wafers; the sedimentary silicon wafers are carved in the hydrogen hydrogen peroxide hydrogen peroxide mixed solution, soaked in the ingredients solution after washing, and then removed the silicon nano wire., Get the silicon -based microneedle.The method provided by the present invention only needs to be treated with a simple map with photoresist, and then the metal auxiliary wetting method is used to etched out large -sized microcliclement under acidic conditions.The etching time is short, the process is simple, and the effect is significant.The height of the silicon -based microneedle is 90 to 137 microns; the prepared sensors have a good linear response to hydrogen peroxide, and the response current is large. It can detect changes in the concentration of hydrogen peroxide at no less than 4 hours.

The invention relates to a forming method of a transistor. The forming method of the transistor includes the following steps that: a semiconductor substrate is provided, wherein the semiconductor substrate includes a first region and a second region; a dummy gate dielectric material layer is formed on the surface of the semiconductor substrate, wherein the dummy gate dielectric material layer includes a first insulating material layer and a second insulating material layer; a dummy gate and a second gate are formed; the dummy gate dielectric material layer is etched with the dummy gate and the second gate adopted as a mask, so that a dummy gate dielectric layer and a second gate dielectric layer are formed; first source / drain areas are formed in the first region, and second source / drain areas are formed in the second region; a dielectric layer is formed on the surface of the semiconductor substrate, and the surface of the dielectric layer is flush with the surface of the dummy gate; and the second insulating material layer in the dummy gate dielectric material layer is removed through adopting a dry etching process, and the first insulating material layer in the dummy gate dielectric material layer is removed through adopting a wet etching process, and therefore, a groove can be formed; and a first gate structure is formed in the groove. With the forming method of the transistor adopted, steps can be decreased, and the performance of the transistor can be improved.

The present application provides an MRAM device and a manufacturing method thereof. The manufacturing method includes: step S1, arranging a first interconnection part and a second interconnection part in an interconnection medium layer; step S2, arranging a first etch barrier layer and a first dielectric layer in sequence on the surface of an interconnection medium layer layer; step S3, forming a first metal hole in the first etching barrier layer and the first dielectric layer above the first interconnection; step S4, sequentially forming a first metal hole on the surface of the first dielectric layer above the first interconnection Setting the bottom electrode, the MTJ unit, the top electrode, and the second etch barrier layer; step S5, sequentially setting the third dielectric layer, the third etch barrier layer and the fourth dielectric layer on the surface of the second dielectric layer away from the first dielectric layer Dielectric layer; Step S6, opening the second through hole and the third through hole; Step S7, filling the second through hole and the third through hole with metal. The manufacturing method reduces the process difficulty and improves the cost rate of the device.