Method for producing dual damascene structure

Abstract

The invention discloses a method for producing a dual damascene structure. The method comprises the following steps of: depositing a part of silicon-containing coating in a through hole; then depositing a bottom antireflective coating; carrying out interconnected groove etching; and when the silicon-containing coating is exposed, introducing CF4, N2 and Ar and continuously etching, or introducingCF4, N2 and Ar for etching and then introducing CF4, N2, Ar and C4F8 and continuously etching. In the environment of the CF4, the N2 and the Ar, the ratio of the etching rate of the silicon-containing coating to the etching rate of a dielectric layer with a low dielectric constant can reach 1.1; in the environment of the CF4, the N2, the Ar and the C4F8, the ratio of the etching rate of the silicon-containing coating to the etching rate of the dielectric layer with the low dielectric constant can reach 3, thereby over etching of the silicon-containing coating is extremely realized when the interconnected groove etching is carried out. Therefore, the method is beneficial to enabling the top of a through hole and the bottom of the interconnected groove to form a circular corner, avoids the damage to the side of the interconnected groove and enables the interconnected groove to keep vertical.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a method for preparing a double damascene structure. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the characteristic line width of semiconductor chips continues to shrink; at the same time, as the number of transistors in the chip continues to increase and the functions become stronger and stronger, the metal wiring of the chip is getting thinner and thinner. There are more and more layers. This makes the RC delay caused by the connection resistance and the capacitance of the dielectric layer between the connections more and more influential on the chip speed, even exceeding the gate delay that determines the speed of the transistor itself. Therefore, trying to reduce the connection resistance and reduce the capacitance between the connections has become the key to further increase the chip speed. ...

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Problems solved by technology

[0035] The object of the present invention is to provide a method for preparing a double damascene structure, so as to solve the problem that the existing method for preparing double damascene can not meet the requirement that the top of the through hole and the bottom of the interconnection trench form a rounded corner and the interconnection trench The problem with these two requirements of lateral verticality

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