Method of forming a transistor

Abstract

The invention relates to a method for forming a transistor, which comprises the steps of providing a substrate; forming a pseudo-grid structure in a first region, wherein the pseudo-grid structure comprises a pseudo-grid dielectric layer and a pseudo-grid electrode; forming a second grid electrode structure in a second region, wherein the second grid electrode structure comprises a second grid dielectric layer and a second grid electrode, the thickness of the pseudo-grid dielectric layer is less than the thickness of the second grid dielectric layer, and the top surface of the pseudo-grid electrode is flush with the top surface of the second grid electrode; forming a side wall at the side wall surface of the pseudo-grid structure and the side wall surface of the second grid electrode structure; forming a first dielectric layer on the substrate; removing the pseudo-grid structure, and forming a groove in the first region; and forming the first grid electrode structure in the groove, wherein the first grid electrode structure comprises a first grid dielectric layer located at the inner wall surface of the groove and the second grid electrode structure which is located at the surface of the first grid dielectric layer and fully fills the groove. The method provided by the invention can improve the performance of the transistor of a core region.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a transistor. Background technique [0002] With the continuous improvement of the integration level of semiconductor devices and the reduction of technology nodes, the traditional gate dielectric layer continues to become thinner, and the leakage of transistors increases accordingly, causing problems such as waste of power consumption of semiconductor devices. In order to solve the above problems, the prior art provides a solution of replacing the polysilicon gate with a metal gate. Among them, the "gate last" process is a main process for forming high-K metal gate transistors. [0003] At the same time, due to the increasing integration of chips and the increasing scale, a single chip usually includes a core transistor area and an input / output (I / O) transistor area, and the operating voltage of the core logic transistor is generally low. System pow...

AI Technical Summary

Problems solved by technology

[0005] The performance of the transistors in the core area formed by the prior art needs to be further improved

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