Method for generating data for a regression model for determining circuit element values ​​- Patent Application 20070122967

Abstract

A method, a computer program, and a computer system for fault detection in an electrical network are provided. Based on measuring a fault current, an inductance between a reference point and the fault point at a first time can be determined. Based on measuring the derivative of the fault current as zero, a resistance between the reference point and the fault point at a second time can be determined. Based on the inductance and resistance, a location of the fault point can be identified.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 046,264 (filed June 30, 2020) in the U.S. Patent and Trademark Office, which is incorporated herein by reference in its entirety.

[0002] This disclosure relates generally to the field of power systems, and more particularly to fault detection. [Background technology]

[0003] Instantaneous sag faults in distribution feeders can exhibit characteristic signature behavior in fewer than a few transient cycles. In many cases, the signature can appear in less than one cycle. The system can then return to normal behavior. These signatures can include subcycle faults, incipient faults, transient faults, and self-clearing faults, among others. Self-clearing transient faults in underground cables can be caused by the development of water trees inside the cable or moisture accumulation in cable splices, which can result in instantaneous insulation breakdown followed by arcing. This, in turn, can cause rapid moisture evaporation and temporary insulation recovery. Summary of the Invention

[0004] Embodiments relate to methods, systems, and computer-readable media for fault detection in an electrical network. According to one aspect, a method for fault detection in an electrical network is provided. The method may include determining an inductance between a reference point and a fault point at a first time based on measuring a fault current. A resistance between the reference point and the fault point may be determined at a second time based on measuring a derivative of the fault current as zero. A location of the fault point may be identified based on the inductance and resistance.

[0005] According to another aspect, a computer system for fault detection in an electrical network is provided. The computer system may include one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage devices, and program instructions stored in at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, thereby enabling the computer system to perform a method. The method may include determining an inductance between a reference point and the fault point at a first time based on measuring a fault current. A resistance between the reference point and the fault point may be determined at a second time based on measuring a derivative of the fault current as zero. A location of the fault point may be identified based on the inductance and resistance.

[0006] According to yet another aspect, a computer-readable medium for fault detection in an electrical network is provided. The computer-readable medium may include one or more computer-readable storage devices and program instructions stored on at least one of the one or more tangible storage devices, the program instructions being executable by a processor. The program instructions are executable by the processor to perform a method that may optionally include determining an inductance between a reference point and the fault point at a first time based on measuring a fault current. A resistance between the reference point and the fault point may be determined at a second time based on measuring a derivative of the fault current as zero. A location of the fault point may be identified based on the inductance and resistance. [Brief explanation of the drawings]

[0007] These and other objects, features and advantages will become apparent from the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings. Since the illustrations, together with the detailed description, are for ease and clarity of understanding by those skilled in the art, various features of the drawings are not to scale. In the drawings:

[0008] [Figure 1] 1 illustrates a networked computer environment in accordance with at least one embodiment. [Figure 2A] FIG. 1 is a diagram of a circuit according to at least one embodiment. [Figure 2B] FIG. 1 is a diagram of a circuit with an injection voltage and a power supply voltage disabled, according to at least one embodiment. [Figure 3] 1 is a system for determining circuit element values ​​according to at least one embodiment. [Figure 4] 1 is an operational flowchart illustrating steps performed by a program for fault detection in an electrical network, according to at least one embodiment. [Figure 5] FIG. 2 is a block diagram of the internal and external components of the computer and server shown in FIG. 1, according to at least one embodiment. [Figure 6] 2 is a block diagram of an exemplary cloud computing environment including the computer system shown in FIG. 1 according to at least one embodiment. [Figure 7] FIG. 7 is a block diagram of functional layers of the exemplary cloud computing environment of FIG. 6 according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, these structures and methods may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey its scope to those skilled in the art. The description may omit details of well-known features and techniques to avoid unnecessarily obscuring the presented embodiments.

[0010] FIELD Embodiments relate generally to the field of power systems, and more particularly to fault determination. The exemplary embodiments described below provide, among other things, systems, methods, and computer programs for determining the precise location of self-clearing transient faults. Accordingly, some embodiments may be capable of improving the field of computing by enabling computers to determine fault locations and prevent permanent failures or unplanned outages, thereby eliminating costly and time-consuming fault location methods that stress system components exposed to fault currents.

[0011] As previously mentioned, instantaneous sag faults in distribution feeders can exhibit characteristic signature behavior in fewer than a few transient cycles. In many cases, the signature can appear in less than one cycle. The system may then return to normal behavior. These signatures can include subcycle faults, incipient faults, transient faults, and self-clearing faults, among others. Self-clearing transient faults in underground cables can be caused by the development of water trees inside the cable or moisture accumulation in cable splices, which can cause instantaneous insulation breakdown followed by arcing. This can cause the moisture to rapidly evaporate, temporarily restoring the insulation.

[0012] Previous approaches focused on solving for the unknown location variables (line resistance and line reactance to the fault) for the fault loop using discrete inverse time-domain differential equations. However, these approaches ignored the resistance to the fault in the discrete inverse differential equations because there were two unknown variables in the single fault loop equation. In certain situations and conductor types, excluding the resistance to the fault can cause unacceptable errors in the fault location determination. Therefore, it can be advantageous to solve for the two unknowns from the single fault loop equation.

[0013] Because the voltage equation contains two terms (i.e., the first term for the resistance multiplied by the fault current, and the second term for the inductance multiplied by the derivative of the fault current), the time t1 at which the fault current becomes zero can be determined. At time t1, the first term can disappear and the equation can be left with only one variable: the inductance to the fault. Similarly, the time t2 at which the derivative of the fault current becomes zero can be determined. At time t2, the second term can disappear and the equation can be left with only one variable: the resistance to the fault.

[0014] Discrete parameter estimation by least squares may be used during periods when the fault current does not become zero, when there may be multiple zero derivative points of the fault current due to noise in the fault current signal, and when there may be harmonic oscillations that result in multiple zero derivative points. The discrete least squares approach may use concatenated measurement data of voltage and current signals taken at a substation that may serve multiple circuits, one of which may experience a self-clearing fault.

[0015] Aspects are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer-readable media according to various embodiments. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0016] Referring now to Figure 1, a functional block diagram of a networked computing environment illustrating a fault detection system 100 (hereinafter "system") for fault detection in an electrical network is shown. It should be understood that Figure 1 provides only an example of one implementation and is not intended to imply any limitations with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made based on design and implementation requirements.

[0017] System 100 may include a computer 102 and a server computer 114. Computer 102 may communicate with server computer 114 via communications network 110 (hereinafter, "network"). Computer 102 may include a processor 104 and software programs 108 stored on a data storage device 106 that enable interface with a user and communication with server computer 114. As discussed below with reference to FIG. 5 , computer 102 may include internal components 800A and external components 900A, respectively, and server computer 114 may include internal components 800B and external components 900B, respectively. Computer 102 may be, for example, a mobile device, a phone, a personal digital assistant, a netbook, a laptop computer, a tablet computer, a desktop computer, or any type of computing device capable of running programs, accessing a network, and accessing a database.

[0018] The server computer 114 may also operate in a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (laaS), as discussed below with respect to Figures 6 and 7. The server computer 114 may also be located in a cloud computing deployment model, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud.

[0019] The server computer 114, which may be utilized to detect faults in the electrical system, may execute a fault detection program 116 (hereinafter, "program") that may interact with the database 112. The fault detection program method is described in more detail below with respect to FIG. 4. In one embodiment, the computer 102 may act as an input device, including a user interface, while the program 116 may primarily execute on the server computer 114. In an alternative embodiment, the program 116 may primarily execute on one or more computers 102, while the server computer 114 may be utilized for processing and storage of data utilized by the program 116. Note that the program 116 may be a standalone program or may be integrated into a larger fault detection program.

[0020] However, it should be noted that processing of program 116 may, in some cases, be shared between computer 102 and server computer 114 in any proportion. In another embodiment, program 116 may run on multiple computers, server computers, or some combination of computers and server computers, e.g., multiple computers 102 communicating with a single server computer 114 over network 110. In another embodiment, for example, program 116 may run on multiple server computers 114 communicating with multiple client computers over network 110. Alternatively, the program may run on a network server that communicates with the server and multiple client computers over the network.

[0021] Network 110 may include wired connections, wireless connections, fiber optic connections, or some combination thereof. In general, network 110 can be any combination of connections and protocols that support communication between computer 102 and server computer 114. Network 110 may include various types of networks, such as, for example, a local area network (LAN), a wide area network (WAN) such as the Internet, a communications network such as a public switched telephone network (PSTN), a wireless network, a public switched network, a satellite network, a cellular network (e.g., a fifth generation (5G) network, a long term evolution (LTE) network, a third generation (3G) network, a code division multiple access (CDMA) network, etc.), a public land mobile network (PLMN), a metropolitan area network (MAN), a private network, an ad hoc network, an intranet, a fiber optic based network, etc., and / or a combination of these or other types of networks.

[0022] The number and arrangement of devices and networks shown in Figure 1 are provided as an example. In practice, there may be additional devices and / or networks, fewer devices and / or networks, different devices and / or networks, or devices and / or networks arranged differently from those shown in Figure 1. Furthermore, two or more devices shown in Figure 1 may be implemented within a single device, or a single device shown in Figure 1 may be implemented as multiple distributed devices. Additionally or alternatively, a set of devices (e.g., one or more devices) of system 100 may perform one or more functions that are described as being performed by another set of devices of system 100.

[0023] Referring now to FIG. 2A, a circuit 200A is shown. For example, consider a simple circuit for a single line-to-ground fault on phase A at location x in a circuit in a substation serving multiple circuits. Circuit 200A may include a circuit for a single line-to-ground fault on phase A, with all resistance components ignored. As previously mentioned, resistance to the fault may be ignored. The circuit may be equivalently represented by a sinusoidal source E with source inductance LS, substation capacitance C for power factor correction, inductance Lline of the circuit from the substation to the fault, and inductance Lr of the remaining circuit, with all resistance components ignored. The only variables measurable at the substation via CTs and PTs may be the current through source impedance LS and the bus voltage, and the approach is intended to calculate inductance Lline relative to x using only two measurement signals.

[0024] When a self-clearing earth fault occurs on phase A at time t=0, at that moment the voltage at x becomes zero, which means that if we assume that the normal voltage at x can be the same as the substation voltage, then the negative voltage -V ax This can be equivalent to injecting (0) at position x. Due to the principle of superposition, the focus must be on the "net fault voltage and net fault current" of the target circuit, not the entire bus, so the net fault value can be obtained from the injected voltage alone.

[0025] 2B, a circuit diagram 200B of the circuit with the injection voltage and the power supply voltage deactivated is shown. aF , i CF , i alF , and v anF can be the net fault current and voltage, respectively, contributed only by the injected voltage source. The net fault variable i aF and v anF can be obtained by subtracting the normal pre-fault value from the fault value. With this configuration, the circuit is the transient response of the injected voltage source switched on at t=0.

[0026] The inverse time domain equation for the inductance to the fault point can be given as:

[0027]

number

[0028] V aN The value of (0) can be assumed to be the voltage at the bus at the moment of fault initiation. Alternatively, the value can be approximated to the peak of the normal voltage, since self-clearing faults occur at peak positive or negative voltages.

[0029] An early self-clearing fault location approach can be similar to solving an arcsine transient problem. A typical transient problem is to find the transient response for a given circuit with known resistances and inductances. The inversion of the problem asks what the actual values ​​of the components can be for a given response, i.e., voltage and current shapes. In this regard, from a simple RL fault loop, the following can be obtained from the voltage equation for that loop:

[0030]

number

[0031] Where v(t) and i(t) are measured, the inductance to the fault point, L, can be determined by:

[0032]

number

[0033] If the equation for inductance to the fault can be evaluated at a point where the current can be zero, the R component term can be eliminated, leaving only all measured voltage and current values. In other words, the equation can be reduced to the following simplified equation:

[0034]

number

[0035] Similarly, R can be determined by evaluating it at time di(t) / dt=0.

[0036]

number

[0037] The weaknesses of the improved method are (a) the absence of a zero fault current point available during very short transient periods (e.g., less than half a cycle), and (b) the presence of multiple current zero points due to the emission of noise and harmonic signals in the fault current signal.In the next section, we discuss a new method, a least-squares discrete parameter estimation approach.

[0038] M scalar measurements of a signal y(t) (e.g., voltage) at time t k-M ,t k-M+1 ,…,t k-1 ,t k If the measurement of y(t) can be assumed to be a linear combination of two parameters β0 and β1 (R and L) and a particular parameter x(t) (e.g., current), then y(t) = x0(t)β0 + x1(t)β1 + v(t), where v(t) can be a zero-mean measurement error.

[0039] Let x = [x0(t), x1(t)] and β = [β0, β1], then the M measurements of y(t) are denoted as time t for simplicity of notation. k Simply replacing with k, we can express it as follows:

[0040] y(k)=x(k)β+v(k) y(k-1)=x(k-1)β+v(k-1) : y(kM)=x(kM)β+v(kM)

[0041] The above equation can be expressed in a more convenient vector form as Y = Xβ + V. In the absence of measurement errors, the deterministic equation can be Y = Xβ, and the parameter β can be expressed as β = X -1 However, if the system can be overdetermined with only two variables and more measurements, Y may be approximated as

[0042]

number

[0043] where:

[0044]

number

[0045] can be obtained by a least squares estimation method that minimizes the weighted sum of the squares of the errors in the following equation:

[0046]

number

[0047] The least squares estimate of β is

[0048]

number

[0049] can be given by

[0050] To apply the discrete least squares method with excessive deterministic equation error, the difference equation of the fault loop can be given as follows:

[0051]

number

[0052] Then rearranging the equation gives:

[0053]

number

[0054] The resulting matrix equation is:

[0055]

number

[0056] By including M number of measurements, the matrix is ​​expanded as follows:

[0057]

number

[0058] The first matrix above may be labeled X, the second β, and the third Y, and the above equation may be written as X β = Y Δt, which may be the same equation discussed in the theory of least squares estimation.

[0059]

number

[0060] can be obtained by:

[0061]

number

[0062] Finally, the two parameters L and R to the fault point can be obtained from the row components of β.

[0063]

number

[0064] and

[0065]

number

[0066] For the number of measurements (M) in a practical application, a half-cycle sample of the signal may be used. Thus, if the signal is sampled at a rate of 7680 samples per second, 64 measurements starting from the beginning of the fault may be included in the X and Y matrix configuration. At this particular sampling rate, Δt may be 0.1302 ms.

[0067] The fault current may be generated by:

[0068]

number

[0069] where E may be the voltage magnitude 12 kV and Iz(0) may be the normal current level at which a fault may be initiated.

[0070] The phase angle can be obtained as follows:

[0071]

number

[0072] A voltage signal can be generated using the current generated above.

[0073]

number

[0074] where:

[0075]

number

[0076] For matrix construction of voltage and current, the first 64 samples of the second cycle (solid signal) can be used to represent the first half cycle of the measured fault voltage and current.

[0077] Referring now to FIG. 3, a system 300 for determining circuit element values ​​is illustrated. According to one or more embodiments, a first matrix having elements resulting from n sampled voltages beginning at t0 and ending at (n-1)Δt 301 is multiplied by a sampling period 302 to form an n-by-1 dimensional Y matrix 303. A second matrix (X 304) includes two columns of elements each with n rows of sampled currents, where the first column (X1 305) includes rows sampled from time t0+Δt to time t0+nΔt 307, while the second column (X2 306) can be created by samples from time t0 to (n-1)Δt 308, as was done for the Y matrix. These two columns form the n-by-2 dimensional X matrix 304 described above.

[0078] A third matrix of dimension 2x1 contains the two unknowns we are trying to find. Thus, when the matrices X and Y formed by the above description can be provided to the regression model 309, the coefficient matrix b can be calculated as b=(X T X) -1 X T It may be obtained from a regression model by Y, or similarly by various regression methods or algorithms. As the output of the system, the unknowns R and L may be obtained by L=b1 (the first row element of matrix b, which may be b1 310), and R=(b1+b2) / Δt, 311, where b2 may be the second row element of matrix b, and Δt may be the sampling period.

[0079] Two matrices, Y and X, can be formed from the discrete voltage and current waveforms obtained for the circuit using a conventional regression model, Y=Xb. Unknown element values, such as the resistance (R) and inductance (L) of the circuit, can be derived from the regression result b. These derived circuit elements can be used to locate faults in the power circuit.

[0080] When the number of rows in Y and X can be greater than the elements of the coefficient matrix b, sometimes called an overdeterministic situation, b can be calculated by the least squares method or its variants as b = (X T X) -1 X T A similar variant of finding Y or b can be obtained, while minimizing the error between Y and the actual measured data corresponding to Y. T may be the transpose of X, (X T X) -1 is (X T X).

[0081] Consider a circuit having elements R and L and may be powered by a sinusoidal source v(t). Then, the equation for the voltage of the circuit may be given by v(t) = R * i(t) + L * di(t) / dt, where i(t) may be the circuit current and di(t) / dt may be the time derivative of the current. Time t represents discrete time as t = 0, 1, 2, ..., n or more generally t = t0 + 1 * Δt, t0 + 2 * Δt, ..., t0 + n * Δt for n samples of v(t) and i(t), where Δt may be the sampling period and t0 may be the initial time.

[0082] The differential part of the equation can be reduced to a difference equation using the basic definition of time derivative as v(t) = R*i(t) + L*[i(t + Δt) - i(t)] / Δt. Then, rearranging the equation, we can derive v(t) * Δt = L*i(t + Δt) + [R* Δt - L] * i(t).

[0083] For n samples for both v(t) and i(t), there are n possible equations:

[0084] v(t0)*Δt=L*i(t0+Δt)+[R*Δt-L]*i(t0) v(t0+Δt)*Δt=L*i(t0+2Δt)+[R*Δt-L]*i(t0+Δt) v(t0+2Δt)*Δt=L*i(t0+3Δt)+[R*Δt-L]*i(t0+2Δt) ... v(t0+(n-1)Δt)*Δt=L*i(t0+nΔt)+[R*Δt-L]*i(t0+(n-1)Δt)

[0085] The above equations can be expressed in matrix form as follows:

[0086] |v(t0)*Δt | |i(t0+Δt) i(t0) | |v(t0+Δt)*Δt | |i(t0+2Δt) i(t0+Δt) | |v(t0+2Δt)*Δt | = |i(t0+3Δt) i(t0+2Δt) | | L | | : | | : : | | R*Δt - L | | : | | : : | |v(t0+(n-1)Δt)*Δt | |i(t0+nΔt) i(t0+(n-1)Δt)| [ nx1 ] [ nx2 ] [ 2x1 ]

[0087] Referring now to FIG. 4, there is shown an operational flow chart illustrating the steps of a method 400 performed by a program for detecting faults in an electrical network.

[0088] At 402, the method 400 may include determining an inductance between a reference point and a fault point at a first time based on measuring the fault current as zero.

[0089] At 404, the method 400 may include determining a resistance between the reference point and the fault point at a second time based on measuring the derivative of the fault current as zero.

[0090] At 406, the method 400 may include locating the fault based on the inductance and resistance.

[0091] It should be understood that Figure 4 depicts only one example and is not intended to imply any limitations on how different embodiments may be implemented. Many modifications to the depicted environments may be made based on design and implementation requirements.

[0092] Figure 5 is a block diagram 500 of the internal and external components of the computer shown in Figure 1, according to an exemplary embodiment. It should be appreciated that Figure 5 is provided only as an illustration of one implementation and is not intended to imply any limitation with respect to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made based on design and implementation requirements.

[0093] The computer 102 (FIG. 1) and the server computer 114 (FIG. 1) may include respective sets of internal components 800A, B and external components 900A, B, as illustrated in FIG. 6. Each of the set of internal components 800 includes one or more processors 820, one or more computer-readable RAMs 822 and one or more computer-readable ROMs 824 on one or more buses 826, one or more operating systems 828, and one or more computer-readable tangible storage devices 830.

[0094] The processor 820 may be implemented in hardware, firmware, or a combination of hardware and software. The processor 820 may be a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or other type of processing component. In some implementations, the processor 820 includes one or more processors that can be programmed to perform functions. The bus 826 includes components that enable communication between the internal components 800A,B.

[0095] One or more operating systems 828, software programs 108 (FIG. 1), and fault detection programs 116 (FIG. 1) on server computer 114 (FIG. 1) are stored on one or more respective computer-readable tangible storage devices 830 for execution by one or more respective processors 820 via one or more respective RAMs 822 (which typically include cache memory). In the embodiment shown in FIG. 5, each of computer-readable tangible storage devices 830 is an internal hard drive magnetic disk storage device. Alternatively, each of computer-readable tangible storage devices 830 is a semiconductor storage device such as ROM 824, EPROM, flash memory, optical disk, magneto-optical disk, solid-state disk, compact disk (CD), digital versatile disk (DVD), floppy disk, cartridge, magnetic tape, and / or other type of non-transitory computer-readable tangible storage device capable of storing computer programs and digital information.

[0096] Each set of internal components 800A,B also includes an R / W drive or interface 832 for reading from and writing to one or more portable computer-readable tangible storage devices 936, such as CD-ROMs, DVDs, memory sticks, magnetic tapes, magnetic disks, optical disks, or semiconductor storage devices. Software programs, such as software program 108 (FIG. 1) and fault detection program 116 (FIG. 1), may be stored on one or more respective portable computer-readable tangible storage devices 936, read via the respective R / W drive or interface 832, and loaded onto the respective hard drives 830.

[0097] Each set of internal components 800A,B also includes a network adapter or interface 836, such as a TCP / IP adapter card, a wireless Wi-Fi interface card, a 3G, 4G, or 5G wireless interface card, or other wired or wireless communication link. The software program 108 (FIG. 1) and the fault detection program 116 (FIG. 1) on the server computer 114 (FIG. 1) can be downloaded to the computer 102 (FIG. 1) and the server computer 114 from an external computer via a network (e.g., the Internet, a local area network, or other wide area network) and the respective network adapters or interfaces 836. From the network adapters or interfaces 836, the software program 108 and the fault detection program 116 on the server computer 114 are loaded onto the respective hard drives 830. The network may include copper wire, optical fiber, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers.

[0098] Each of the set of external components 900A,B may include a computer display monitor 920, a keyboard 930, and a computer mouse 934. The external components 900A,B may also include touch screens, virtual keyboards, touchpads, pointing devices, and other human interface devices. Each of the set of internal components 800A,B also includes a device driver 840 for interfacing to the computer display monitor 920, the keyboard 930, and the computer mouse 934. The device driver 840, the R / W drive or interface 832, and the network adapter or interface 836 include hardware and software (stored in the storage device 830 and / or the ROM 824).

[0099] Although this disclosure includes detailed descriptions of cloud computing, it is understood in advance that implementation of the teachings referred to herein is not limited to a cloud computing environment. Rather, some embodiments can be implemented in conjunction with any other type of computing environment now known or later developed.

[0100] Cloud computing is a service delivery model for providing convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal administrative effort or interaction with service providers. The cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0101] The features are as follows: On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time and network storage, automatically as needed without requiring human interaction with the service provider. Broad network access: Functionality is available over the network and accessed through standard mechanisms that facilitate usage by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). Resource Pooling: Provider computing resources are pooled to serve multiple consumers utilizing a multi-tenant model, with different physical and virtual resources dynamically allocated and reallocated on demand. While consumers generally do not control or know the exact location of the resources provided, there is a sense of location independence in that it may be possible to specify location at a higher level of abstraction (e.g., country, region, or data center). Rapid Elasticity: Capabilities can be quickly and elastically provisioned, in some cases automatically, quickly scaled out, quickly released, and quickly scaled in. To the consumer, the capabilities available for provisioning often appear unlimited, and any quantity can be purchased at any time. Metered Services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at several levels of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services used.

[0102] The service model is as follows: Software as a Service (SaaS): The functionality offered to the consumer is the use of a provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, storage, or individual application functions, with the possible exception of limited user-specific application configuration settings. Platform as a Service (PaaS): The functionality offered to the consumer is the deployment onto a cloud infrastructure of applications that the consumer creates or acquires, written using programming languages ​​and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does control the deployed applications and, in some cases, the application hosting environment configuration. Infrastructure as a Service (IaaS): The functionality offered to consumers is the provisioning of processing, storage, network, and other basic computing resources, upon which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does have control over the operating system, storage, deployed applications, and possibly limited control over select network components (e.g., host firewalls).

[0103] The deployment model is as follows: Private Cloud: Cloud infrastructure is operated solely for an organization. It may be managed by the organization or a third party and may be on-premise or off-premise. Community Cloud: Cloud infrastructure is shared by several organizations to support a specific community with shared interests (e.g., mission, security requirements, policies, and compliance motivations). It may be managed by the organization or a third party and may be on-premise or off-premise. Public cloud: cloud infrastructure is made available to the general public or large industry groups and is owned by an organization that sells cloud services. Hybrid Cloud: A cloud infrastructure is a blend of two or more clouds (private, community, or public) that remain their own entity but are joined by standard or proprietary technologies that allow data and application portability (e.g., cloud bursting for load balancing between clouds).

[0104] Cloud computing environments are service-oriented with an emphasis on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that comprises a network of interconnected nodes.

[0105] Referring to FIG. 6, an exemplary cloud computing environment 600 is illustrated. As shown, the cloud computing environment 600 includes one or more cloud computing nodes 10, which may communicate with local computing devices utilized by cloud consumers, such as a personal digital assistant (PDA) or cellular phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automobile computer system 54N. The cloud computing nodes 10 may communicate with each other. They may be physically or virtually grouped (not shown) within one or more networks, such as private, community, public, or hybrid clouds, or combinations thereof, as described above. This enables the cloud computing environment 600 to provide infrastructure, platform, and / or software as a service, without the cloud consumer having to manage resources on their local computing devices. The types of computing devices 54A-N illustrated in FIG. 6 are for illustrative purposes only, and it will be understood that the cloud computing nodes 10 and the cloud computing environment 600 may communicate with any type of computerized device over any type of network and / or network-addressable connection (e.g., utilizing a web browser).

[0106] Referring to Figure 7, a set of functional abstraction layers 700 provided by cloud computing environment 600 (Figure 6) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 7 are for illustrative purposes only and embodiments are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0107] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, reduced instruction set computer (RISC) architecture-based server 62, server 63, blade server 64, storage device 65, and network and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0108] The virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities are provided: virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75.

[0109] In one example, the management layer 80 may provide the functions described below. Resource provisioning 81 provides dynamic acquisition of computing resources and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 82 provides cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, and protection for data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management so that required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides advance arrangement and procurement of cloud computing resources in anticipation of future requirements according to SLAs.

[0110] The workload layer 90 provides examples of functions for which a cloud computing environment may be utilized. Examples of workloads and functions that may be provided from this layer include mapping and navigation 91, software deployment and lifecycle management 92, virtual classroom instructional delivery 93, data analytics processing 94, transaction processing 95, and fault detection 96. Fault detection 96 may detect transient and intermittent faults in an electrical network.

[0111] Some embodiments may relate to systems, methods, and / or computer-readable media at any possible level of technical detail of integration. The computer-readable media may include computer-readable non-transitory storage media (or media) having computer-readable program instructions for causing a processor to perform operations.

[0112] A computer-readable storage medium can be a tangible device that can hold and store instructions utilized by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or raised structures in grooves having instructions recorded thereon, and any suitable combination thereof. Computer-readable storage media as used herein should not be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses propagating through a fiber optic cable), or electrical signals transmitted over wires.

[0113] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions to a computer-readable storage medium in each computing / processing device for storage.

[0114] The computer-readable program code / instructions for carrying out operations may be either source code or object code written in any combination of one or more programming languages, including assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for an integrated circuit, or object-oriented programming languages ​​such as Smalltalk, C++, or procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry to perform aspects or operations.

[0115] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to cause a machine, such that the instructions, executing via the processor of the computer or other programmable data processing apparatus, generate means for implementing the functions / acts identified in the flowchart and / or block diagram block or blocks. These computer-readable program instructions may be stored on a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions that implement aspects of the functions / acts identified in the flowchart and / or block diagram block or blocks.

[0116] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing, or other device, and a series of operational steps may be executed on the computer, other programmable data processing, or other device to create a computer-implemented process, and the instructions executed on the computer, other programmable device, or other device implement the functions / operations identified in the flowchart and / or block diagram blocks or blocks.

[0117] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer-readable media according to various embodiments. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a particular logical function. The methods, computer systems, and computer-readable media may include additional, fewer, different, or differently arranged blocks than those illustrated in the figures. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may actually be executed concurrently or substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs particular functions or operations, or by a combination of special-purpose hardware and computer instructions.

[0118] It will be apparent that the systems and / or methods described herein may be implemented in different forms, such as hardware, firmware, or a combination of hardware and software. The actual specific control hardware or software code utilized to implement these systems and / or methods is not intended to limit the implementation. Thus, the operation and behavior of the systems and / or methods are described herein without reference to specific software code, with the understanding that software and hardware may be designed to implement the systems and / or methods based on the description herein.

[0119] No element, act, or instruction used herein should be construed as critical or essential unless explicitly stated otherwise. Additionally, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more." Additionally, as used herein, the term "set" is intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items, etc.) and may be used interchangeably with "one or more." When only one item is intended, the term "one" or similar language is used. Additionally, as used herein, the terms "have," "have," "having," and the like are intended to be open-ended terms. Additionally, the phrase "based on" is intended to mean "based at least in part on," unless expressly stated otherwise.

[0120] The descriptions of various aspects and embodiments are presented for illustrative purposes and are not intended to be exhaustive or limited to the disclosed embodiments. While combinations of features are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of possible implementations. Indeed, many of these features may be combined in ways not specifically recited in the claims and / or disclosed in the specification. While each dependent claim listed below may depend directly on only one claim, the disclosure of possible implementations includes each dependent claim in combination with any other claim in the claim set. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, their practical application to commercially available technology, or technical improvements thereon, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A method for detecting transient faults in an electrical network, executable by a processor, comprising: determining an inductance between the reference point and the fault point based on measuring the fault current for a length of one-half cycle of the discretely sampled data; determining a resistance between the reference point and the fault point based on measuring the derivative of the fault current as zero for a length of one-half cycle of the discretely sampled data; determining a line inductance and a line resistance of a fault loop associated with the fault point based on the inductance and the resistance; A method comprising:

2. the resistance and the inductance are determined based on a least squares estimation; The method of claim 1.

3. the least squares estimation is performed based on a first matrix corresponding to one or more sampled fault voltages, a second matrix corresponding to one or more sampled fault currents, and a third matrix corresponding to the resistance and the inductance; the resistance and the inductance are determined for the third matrix based on performing a regression on the first matrix and the second matrix. The method of claim 2.

4. The fault point corresponds to an intermittent fault. The method of claim 1.

5. 1. A method for fault detection in an electrical network, executable by a processor, comprising: determining an inductance between the reference point and the fault point at a first time based on measuring the fault current; determining a resistance between the reference point and the fault point at a second time based on measuring the derivative of the fault current as zero; determining a location of the fault based on the inductance and the resistance; Including, The method of claim 1, wherein the resistance and the inductance are determined based on least squares estimation, the least squares estimation being performed based on a first matrix corresponding to one or more sampled fault voltages, a second matrix corresponding to one or more sampled fault currents, and a third matrix corresponding to the resistance and the inductance, and the resistance and the inductance are determined for the third matrix based on performing a regression on the first matrix and the second matrix.

6. 1. A computer system for detecting transient faults in an electrical network, the computer system comprising: one or more computer-readable non-transitory storage media configured to store computer program code; one or more computer processors configured to access the computer program code and to operate as directed by the computer program code, the computer program code comprising: first determination code configured to cause the one or more computer processors to determine an inductance between a reference point and a fault point based on measuring a fault current for a length of one-half cycle of discretely sampled data; second decision code configured to cause the one or more computer processors to determine a resistance between the reference point and the fault point based on measuring a derivative of the fault current as zero for a length of one-half cycle of the discretely sampled data; and an identification code configured to cause the one or more computer processors to identify a line inductance and a line resistance of a fault loop associated with the fault point based on the inductance and the resistance; 2. A computer system comprising:

7. the resistance and the inductance are determined based on a least squares estimation; 7. The computer system of claim 6.

8. the least squares estimation is performed based on a first matrix corresponding to one or more sampled fault voltages, a second matrix corresponding to one or more sampled fault currents, and a third matrix corresponding to the resistance and the inductance; the resistance and the inductance are determined for the third matrix based on performing a regression on the first matrix and the second matrix.

8. The computer system of claim 7.

9. The fault point corresponds to an intermittent fault.

7. The computer system of claim 6.

10. 1. A computer system for fault detection in an electrical network, said computer system comprising: one or more computer-readable non-transitory storage media configured to store computer program code; one or more computer processors configured to access the computer program code and to operate as directed by the computer program code, the computer program code comprising: first determination code configured to cause the one or more computer processors to determine an inductance between a reference point and a fault point at a first time based on measuring a fault current; second decision code configured to cause the one or more computer processors to determine a resistance between the reference point and the fault point at a second time based on measuring the derivative of the fault current as zero; and an identification code configured to cause the one or more computer processors to identify the location of the fault based on the inductance and the resistance; Including, The resistance and the inductance are determined based on least squares estimation, the least squares estimation being performed based on a first matrix corresponding to one or more sampled fault voltages, a second matrix corresponding to one or more sampled fault currents, and a third matrix corresponding to the resistance and the inductance, and the resistance and the inductance are determined for the third matrix based on performing a regression on the first matrix and the second matrix.

11. 1. A non-transitory computer readable medium having stored thereon a computer program for detecting transient faults in an electrical network, the computer program being configured to cause one or more computer processors to: determining an inductance between the reference point and the fault point based on measuring the fault current for a length of one-half cycle of the discretely sampled data; determining a resistance between the reference point and the fault point based on measuring the derivative of the fault current as zero for a length of one-half cycle of the discretely sampled data; determining a line inductance and a line resistance of a fault loop associated with the fault point based on the inductance and the resistance; 2. A computer-readable medium configured to:

12. the resistance and the inductance are determined based on a least squares estimation; The computer-readable medium of claim 11.

13. the least squares estimation is performed based on a first matrix corresponding to one or more sampled fault voltages, a second matrix corresponding to one or more sampled fault currents, and a third matrix corresponding to the resistance and the inductance; the resistance and the inductance are determined for the third matrix based on performing a regression on the first matrix and the second matrix. The computer-readable medium of claim 12.

14. 1. A non-transitory computer readable medium having stored thereon a computer program for fault detection in an electrical network, the computer program being configured to cause one or more computer processors to: determining an inductance between the reference point and the fault point at a first time based on measuring the fault current; determining a resistance between the reference point and the fault point at a second time based on measuring the derivative of the fault current as zero; The location of the fault point is identified based on the inductance and the resistance. It is configured as follows: A computer-readable medium, wherein the resistance and the inductance are determined based on least squares estimation, the least squares estimation being performed based on a first matrix corresponding to one or more sampled fault voltages, a second matrix corresponding to one or more sampled fault currents, and a third matrix corresponding to the resistance and the inductance, and the resistance and the inductance are determined for the third matrix based on performing a regression on the first matrix and the second matrix.

Images