Semiconductor Devices

Abstract

To increase clamp tolerance.SOLUTION: An output stage switch 1a is connected to an L load 2 and operates the L load 2 by switching. A voltage detection circuit 1b outputs a detection signal if an overvoltage due to counter electromotive force generated in the L load 2 at turn-off following turn-on of the output stage switch 1a is detected to be a predetermined voltage of a clamp voltage or more. A driving circuit 1c causes the output stage switch 1a to be turned-on by applying a driving signal V1 having a threshold voltage Vth1 to the gate of the output stage switch 1a in a state that the overvoltage is less than the predetermined voltage. A voltage application circuit 1d causes the output stage switch 1a to be turned-on by applying a voltage signal V2 having a threshold voltage Vth2 higher than the threshold voltage Vth1 to the gate of the output stage switch 1a if the overvoltage becomes the predetermined voltage or more and the detection signal outputted from the voltage detection circuit 1b is received.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device that drives an inductive load with a semiconductor switch element. [Background technology]

[0002] In recent years, progress has been made in the development of a semiconductor device called an IPS (Intelligent Power Switch), which integrates a switch element using a power semiconductor element, a drive circuit for the switch element, and a peripheral protection circuit, etc., into a single chip.

[0003] IPS is widely used in vehicle electrical systems, such as transmissions, engines, and brakes, and there is a demand for products that meet the requirements of miniaturization, high performance, and high reliability.

[0004] Figure 7 is a diagram showing an example of the configuration of a conventional IPS. It shows a schematic circuit configuration around the IPS output stage (protection circuits and the like are omitted from the illustration). IPS 30 has an OUT terminal, an IN terminal, and a GND terminal. An inductive load 2 is connected to the OUT terminal. The inductive load 2 is, for example, an inductive load such as a solenoid valve widely used in automobiles (hereinafter, sometimes referred to as L load 2). A CPU (Central Processing Unit) (not shown) is connected to the IN terminal, and a control signal output from the CPU is input. GND (ground) is connected to the GND terminal.

[0005] The IPS 30 includes a drive circuit 31, a constant current source I0, diodes d0, d1, and d2, and an output stage switch m0 which is an N-channel metal-oxide-semiconductor field-effect transistor (MOSFET).

[0006] Regarding the connection relationship of each element, the IN terminal is connected to the input terminal of the drive circuit 31. The OUT terminal is connected to the cathode of the diode d0, the drain of the output stage switch m0, the cathode of the diode d1, and one end of the L load 2. The other end of the L load 2 is connected to GND. The anode of the diode d1 is connected to the anode of the diode d2.

[0007] The cathode of diode d2 is connected to the output terminal of drive circuit 31, the input terminal of constant current source I0, and the gate of output stage switch m0. The GND terminal is connected to the GND terminal of drive circuit 31, the output terminal of constant current source I0, the source of output stage switch m0, and the anode of diode d0.

[0008] When an H-level control signal transmitted from the CPU is input to the IN terminal, the drive circuit 31 outputs an H-level signal to the gate of the output-stage switch m0 to turn on the output-stage switch m0. When an L-level control signal transmitted from the CPU is input to the IN terminal, the drive circuit 31 outputs an L-level signal to the gate of the output-stage switch m0 to turn off the output-stage switch m0.

[0009] The output stage switch m0 is a switch element for controlling the current flowing through the L load 2, and as shown in the figure, a diode d0 is connected to the output stage switch m0. At the moment the output stage switch m0 is turned off, a back electromotive force is generated from the L load 2. For this reason, the diode d0 is connected in anti-parallel to the output stage switch m0 and functions as an FWD (Free Wheel Diode) that circulates the current flowing through the L load 2 at this time.

[0010] On the other hand, the diode d1 functions as a clamp diode that protects the output stage switch m0 from an overvoltage generated by the inductance of the L load 2 when the output stage switch m0 is turned off, and the diode d2 functions as a backflow prevention diode.

[0011] As a related technology, a technology has been proposed in which a resistor detects the current of a diode that breaks down due to the voltage applied to both ends of a switch element, and the voltage across the resistor is amplified to control the current of the switch element, thereby controlling the conduction of the switch element according to the voltage across the resistor (Patent Document 1).

[0012] Also, a technology has been proposed for driving the gate by including a switching control circuit that outputs a gate drive signal to the gate of the insulated gate element, and a gate potential control circuit that controls the gate potential so that the gate is discharged when the insulated gate element is turned on and the gate is charged when the insulated gate element is turned off (Patent Document 2). [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-26838 [Patent Document 2] Japanese Patent Application Laid-Open No. 2003-70233 Summary of the Invention [Problem to be solved by the invention]

[0014] Figure 8 shows an example of the operating waveforms of a conventional IPS. It shows the operating waveforms of the above-mentioned IPS 30 when clamping the L load 2. In graph g1, the vertical axis is voltage and the horizontal axis is time, showing the waveform of the voltage signal VIN at the IN terminal. In graph g2, the vertical axis is current and the horizontal axis is time, showing the waveform of the current signal IOUT flowing from the OUT terminal to the output stage switch m0. In graph g3, the vertical axis is voltage and the horizontal axis is time, showing the waveform of the voltage signal VOUT at the OUT terminal.

[0015] [Period t1] The voltage signal VIN goes low. At this time, the gate of the output stage switch m0 is low, so the output stage switch m0 turns off. Because the output stage switch m0 is off, the current signal IOUT does not flow. Also, a battery is placed upstream of the L load 2, and 12 V from the battery is applied to the OUT terminal even when the output stage switch m0 is off, so the voltage signal VOUT is 12 V.

[0016] [Period t2] The voltage signal VIN goes to H level (for example, 5V). At this time, the gate of the output stage switch m0 is H level, so the output stage switch m0 turns on. Because the output stage switch m0 is on, the current signal IOUT flows from the L load 2 to the OUT terminal, and the current signal IOUT increases. Also, because the output stage switch m0 is on, the on-resistance of the output stage switch m0 approaches 0, and because V = IR, the voltage signal VOUT drops to the GND level.

[0017] [Period t3] The voltage signal VIN goes low. At this time, the gate of the output stage switch m0 is low, turning the output stage switch m0 off. As a result, the flow of the current signal IOUT from the L load 2 to the OUT terminal decreases as it is cut off.

[0018] Meanwhile, L load 2 is connected to the OUT terminal, and when the output stage switch m0 transitions from on to off to interrupt the flow of the current signal IOUT, the current that was flowing through L load 2 attempts to maintain its flow, and a back electromotive force in the direction that tries to cause the current signal IOUT to flow is generated in L load 2. This causes the voltage signal VOUT to rise, and in the example in Figure 8, the voltage signal VOUT rises to 50V.

[0019] The peak voltage of 50V applied to the OUT pin and GND during period t3 is the clamp voltage, and this clamp voltage is applied to the diode d1 of Depends on the breakdown voltage and threshold voltage of the output stage switch m0.

[0020] Here, let us assume that the breakdown voltage of diode d1 is 49 V, the threshold voltage of output stage switch m0 is 1 V, and 50 V is applied between the OUT terminal and GND. In this case, when diode d1 breaks down at 49 V, the current signal IOUT flows in the reverse direction through diode d1.

[0021] Also, because 1V is applied between the gate and source of output stage switch m0, output stage switch m0 turns on and current signal IOUT flows through output stage switch m0 toward the GND terminal. Furthermore, the remaining current signal IOUT that did not flow toward output stage switch m0 flows through diode d2 and constant current source I0 toward the GND terminal. This type of control disposes of the energy stored in the inductance of L load 2 when it is clamped (disposing of the surge current when L load 2 is clamped).

[0022] [Period t4] When the energy processing of L load 2 is completed, the same operation as in period t1 occurs. As described above, when the voltage signal VIN goes high, the output stage switch m0 turns on, causing a current to flow through the L load 2, and when the output stage switch m0 turns off, the voltage signal VOUT is raised by the back electromotive force generated in the L load 2. At this time, if the withstand voltage of the diode d1 inserted between the drain and gate of the output stage switch m0 is exceeded, a current flows into the constant current source I0 and the gate of the output stage switch m0, turning on the output stage switch m0 and enabling the energy stored in the L load 2 to be processed.

[0023] FIG. 9 is a diagram illustrating an example of determining the clamp voltage. The vertical axis represents current, and the horizontal axis represents voltage. Load curve k1 shows the time variation of the clamp diode (diode d1), and load curve k2 shows the time variation of the constant current source I0. The clamp voltage is determined by the cross point between the load curve k1 of the clamp diode and the load curve k2 of the constant current source I0, which is the threshold voltage Vth of the output stage switch m0.

[0024] Here, if the gate voltage applied to the gate of the output stage switch m0 is smaller than the voltage of the cross point, the output stage switch m0 does not turn on, and therefore the voltage signal VOUT rises as a rising line from GND to the peak voltage during period t3.

[0025] Then, when the gate voltage reaches the cross point voltage, the output stage switch m0 turns on, so that the voltage signal VOUT during the period t3 maintains a constant peak voltage and the current signal IOUT flows through the path described above, thereby disposing of energy in the L load 2.

[0026] FIG. 10 is a diagram showing the relationship between the clamp voltage and the time required for the L load to process energy. The vertical axis is voltage, and the horizontal axis is time. The solid line graph g3 is the same as in FIG. 8, and shows the case where the clamp voltage is 50V. The dotted line graph g4 shows the case where the clamp voltage is 30V. When the clamp voltage is 50V, the time required for the L load 2 to process energy is T1, and when the clamp voltage is 30V, the time required for the L load 2 to process energy is T2, and time T2 is longer than time T1 (T1 <T2)。

[0027] 11 is a diagram showing the relationship between clamp voltage and clamp withstand capability. The vertical axis represents clamp withstand capability (mJ) and the horizontal axis represents clamp voltage (V). When the clamp voltage is 50V, clamp withstand capability j1 is smaller than clamp withstand capability j2 when the clamp voltage is 30V.

[0028] 10 and 11, when the clamp voltage is 50 V, the energy processing of the L load 2 is completed in a shorter time than when the clamp voltage is 30 V. However, when the energy processing is completed in a shorter time, the output stage switch m0 generates more heat, the clamp withstand capability is smaller than when the clamp voltage is 30 V, and the element is more likely to be destroyed.

[0029] On the other hand, recent MOSFETs have low on-resistance / A (A:die size)The amount of current passing per unit area is increasing due to miniaturization of wafer processes aimed at achieving this. The output stage switch m0, for example, is made up of miniaturized MOSs (hereinafter sometimes referred to as miniaturized MOSs) arranged in parallel, and the threshold voltages of the miniaturized MOSs vary, and even if the rated value of the threshold voltage is 1V, miniaturized MOSs with threshold voltages less than 1V are included.

[0030] 12 is a diagram showing an example of the cross-sectional structure of an output stage switch. In an NMOS transistor that is the output stage switch m0, a p-type region 102 is provided above a drain layer 101, and an epitaxial layer 103 is provided above the p-type region 102. A source region 104 is provided above the epitaxial layer 103. Inside the epitaxial layer 103, a p + A p-type contact region 103a is provided. + Adjacent to the n-type contact region + The n-type source region 103b is provided. + Gate trenches gt1, . . . , gt4 are provided between the source and drain regions.

[0031] 13 is a diagram showing an example of the arrangement of gate trenches of the output stage switch, showing the planar structure of the output stage switch m0, in which gate trenches gt1, . . . , gt4 are provided above the p-type region 102.

[0032] As shown in Figures 12 and 13, the output stage switch m0 has a structure in which multiple fine MOSs are arranged in parallel, and it can be seen that it has multiple MOS sections. Because the output stage switch m0 has such a structure, there is a variation in the thickness of the gate insulating film between the gate trenches of the MOS sections (process variation). For this reason, Between gate trenches Threshold Voltage Gaba It will become a problem.

[0033] Therefore, when a current generated by the clamp voltage flows through the output stage switch m0, there is a possibility that the current will be locally concentrated in a fine MOS with a low threshold voltage. This means that energy processing is performed by a fine MOS with a low threshold voltage, and the clamp withstand capability of the MOSFET will decrease even if the clamp voltage itself does not decrease. For this reason, in order to increase the clamp withstand capability, a whole There is a need for circuits that can process energy.

[0034] In one aspect, the present invention aims to provide a semiconductor device with improved clamping resistance. [Means for solving the problem]

[0035] To solve the above problems, a semiconductor device is provided. The semiconductor device includes an output stage switch, a voltage detection circuit, a drive circuit, and a voltage application circuit. The output stage switch is connected to an inductive load and operates the inductive load by switching. The voltage detection circuit detects an overvoltage based on a back electromotive force generated in the inductive load when the output stage switch is turned on and then turned off. Where When it detects that the overvoltage has exceeded a certain voltage, it outputs a detection signal. The drive circuit applies a drive signal having a first threshold voltage to the gate of the output stage switch to turn on the output stage switch. When the voltage application circuit receives a detection signal output from the voltage detection circuit indicating that the overvoltage has exceeded a predetermined voltage, it applies a voltage signal having a second threshold voltage higher than the first threshold voltage to the gate of the output stage switch to turn on the output stage switch. The voltage detection circuit includes a first diode group in which a plurality of first diodes are connected in series, a constant current source, and a latch circuit. The voltage application circuit includes a resistor, a MOS (Metal-Oxide-Semiconductor) transistor, a second diode group in which a plurality of second diodes are connected in series, and an output diode. The cathodes of first ends of the first diode group are connected to the drain of the output stage switch and one end of the inductive load. The anodes of second ends of the first diode group are connected to the input end of the constant current source and one input end of the latch circuit. an output end of the constant current source is connected to ground, one end of the resistor is connected to the drain of the output stage switch and one end of the inductive load, the other end of the resistor is connected to the drain of the MOS transistor, the gate of the MOS transistor is connected to the output end of the latch circuit, the source of the MOS transistor is connected to the anode of the third end of the second diode group and the anode of the output diode, the cathode of the fourth end of the second diode group is connected to ground, and the cathode of the output diode is connected to the gate of the output stage switch. [Effects of the Invention]

[0036] According to one aspect, it is possible to increase clamp resistance. [Brief explanation of the drawings]

[0037] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device of the present invention. [Figure 2] FIG. 1 is a diagram illustrating an example of the configuration of an IPS of the present invention. [Figure 3] FIG. 2 is a diagram illustrating an example of the internal configuration of a voltage detection circuit and a voltage application circuit. [Figure 4] FIG. 10 is a diagram illustrating an example of voltage distribution of a diode. [Figure 5] FIG. 1 is a diagram illustrating an example of the configuration of a voltage detection circuit including a reset circuit. [Figure 6] FIG. 2 is a diagram illustrating an example of an internal configuration of a reset circuit. [Figure 7] FIG. 1 is a diagram illustrating an example of the configuration of a conventional IPS. [Figure 8] FIG. 1 is a diagram showing an example of an operating waveform of a conventional IPS. [Figure 9] FIG. 10 is a diagram for explaining an example of determining a clamp voltage. [Figure 10] FIG. 10 is a diagram showing the relationship between the clamp voltage and the time required to process the energy of an L load. [Figure 11] FIG. 10 is a diagram showing the relationship between clamp voltage and clamp withstand voltage. [Figure 12] FIG. 2 is a diagram illustrating an example of a cross-sectional structure of an output stage switch. [Figure 13] FIG. 10 is a diagram showing an example of the arrangement of gate trenches of an output stage switch. DETAILED DESCRIPTION OF THE INVENTION

[0038] The present embodiment will be described below with reference to the drawings. FIG. 1 is a diagram illustrating an example of a semiconductor device of the present invention. The semiconductor device 1 has an OUT terminal, an IN terminal, and a GND terminal. An inductive load (L load) 2 is connected to the OUT terminal. A CPU (not shown) is connected to the IN terminal, and a control signal output from the CPU is input. GND is connected to the GND terminal. The semiconductor device 1 also has an output stage switch 1a, a voltage detection circuit 1b, a drive circuit 1c, and a voltage application circuit 1d. The output stage switch 1a is, for example, an NMOS transistor.

[0039] The IN terminal is connected to the input terminal of the drive circuit 1c. The OUT terminal is connected to the drain of the output stage switch 1a, the input terminal of the voltage detection circuit 1b, and one terminal of the L load 2. The other terminal of the L load 2 is connected to GND. The output terminal of the voltage detection circuit 1b is connected to the input terminal of the voltage application circuit 1d. The gate of the output stage switch 1a is connected to the output terminal of the drive circuit 1c and the output terminal of the voltage application circuit 1d. The source of the output stage switch 1a is connected to the GND terminal. Although not shown, the voltage detection circuit 1b, drive circuit 1c, and voltage application circuit 1d also have GND terminals that are connected to the GND terminals.

[0040] Here, output stage switch 1a switches on and off to operate L load 2. Voltage detection circuit 1b outputs a detection signal when it detects that an overvoltage caused by a back electromotive force generated in L load 2 when output stage switch 1a is turned on and then turned off exceeds a predetermined voltage within the clamp voltage. Drive circuit 1c drives output stage switch 1a based on a control signal input from a CPU or the like via the IN terminal. Furthermore, output stage switch 1a is controlled based on the following states St1 and St2 according to the level of the overvoltage.

[0041] [State St1] The overvoltage is less than a predetermined voltage of the clamp voltage. During normal operation The drive circuit 1c applies a drive signal V1 having a threshold voltage Vth1 (first threshold voltage) to the gate of the output stage switch 1a to turn on the output stage switch 1a.

[0042] [State St2] When the overvoltage exceeds a predetermined voltage of the clamp voltage, the voltage application circuit 1d receives a detection signal output from the voltage detection circuit 1b indicating that the overvoltage has exceeded the predetermined voltage, and applies a voltage signal V2 having a threshold voltage Vth2 (second threshold voltage) higher than the threshold voltage Vth1 to the gate of the output stage switch 1a, turning on the output stage switch 1a.

[0043] With this configuration of the semiconductor device 1, when clamping the L load 2, a threshold voltage Vth2 exceeding the threshold voltage Vth1 during normal operation is forcibly applied to the gate of the output stage switch 1a. This reliably turns on all the fine MOS transistors of the output stage switch 1a, and energy processing is performed by the gate of the output stage switch 1a. whole This makes it possible to increase the clamping resistance.

[0044] Figure 2 is a diagram showing an example of the configuration of an IPS of the present invention. The IPS 10 has the functions of the semiconductor device 1 in Figure 1. Note that while Figure 2 shows the configuration of a low-side IPS, the basic configuration of a high-side IPS is similar. The IPS 10 has an OUT terminal, an IN terminal, an ST terminal, and a GND terminal as external connection terminals.

[0045] The OUT terminal is a terminal that outputs a signal for driving the L load 2. The IN terminal is a terminal that receives a control signal output from the CPU 3. The ST terminal is a terminal that notifies the CPU 3 of the internal state of the IPS 10 (overheat state, overcurrent state, etc.).

[0046] The IPS 10 also includes a logic circuit 11, a gate drive circuit 12, an overheat detection circuit 13, an overcurrent detection circuit 14, a voltage detection circuit 15, and a voltage application circuit 16. The voltage detection circuit 15 has the function of the voltage detection circuit 1b in FIG. 1, and the voltage application circuit 16 has the function of the voltage application circuit 1d in FIG.

[0047] Furthermore, the IPS10 includes diodes D0, ..., D5, resistors R1 and R2, an output stage switch M0, and NMOS transistors M1, M2, and M3. The output stage switch M0 corresponds to the output stage switch 1a in Figure 1. The diode D1 is a diode built into the NMOS transistor M1, and the diode D2 is a diode built into the NMOS transistor M2.

[0048] The connections of each component will now be explained. The IN terminal is connected to the output terminal of CPU3, the cathode of diode D5, and the input terminal i1 of logic circuit 11. The ST terminal is connected to the input terminal of CPU3, one end of resistor R0, the cathode of diode D4, the cathode of diode D1, the drain of NMOS transistor M1, the cathode of diode D2, and the drain of NMOS transistor M2. The other end of resistor R0 is connected to a 5V power supply.

[0049] The GND terminal is connected to the anode of diode D5, the anode of diode D4, the anode of diode D1, the source of NMOS transistor M1, the anode of diode D2, the source of NMOS transistor M2, the anode of diode D3, and the GND terminal of logic circuit 11. Furthermore, the GND terminal is connected to the source of NMOS transistor M3, the GND terminal of voltage detection circuit 15, the GND terminal of voltage application circuit 16, the source of output stage switch M0, the anode of diode D0, and one end of resistor R2.

[0050] The OUT terminal is connected to one end of the L load 2, one end of the resistor R1, the cathode of the diode D0, the drain of the output stage switch M0, the input end of the voltage detection circuit 15, and one input end of the voltage application circuit 16. The other end of the L load 2 is connected to GND. The output end of the voltage detection circuit 15 is connected to the other input end of the voltage application circuit 16.

[0051] An input terminal i2 of the logic circuit 11 is connected to an output terminal of the overheat detection circuit 13, and an input terminal i3 of the logic circuit 11 is connected to an output terminal of the overcurrent detection circuit 14. An output terminal o1 of the logic circuit 11 is connected to an input terminal of the gate drive circuit 12, and an output terminal o2 of the logic circuit 11 is connected to the gate of the NMOS transistor M3. An output terminal o3 of the logic circuit 11 is connected to the gate of the NMOS transistor M1.

[0052] The output terminal of the gate drive circuit 12 is connected to the drain of the NMOS transistor M3, the output terminal of the voltage application circuit 16, and the gate of the output stage switch M0. The input terminal of the overcurrent detection circuit 14 is connected to the gate of the NMOS transistor M2, the cathode of the diode D3, the other terminal of the resistor R1, and the other terminal of the resistor R2.

[0053] Here, when the logic circuit 11 receives a high-level control signal input from the IN terminal, it outputs an ONBH (ON By H) signal for turning on the output stage switch M0. The gate drive circuit 12 uses the ONBH signal output from the logic circuit 11 to turn on the output stage switch M0 during normal operation. Rure The logic circuit 11 generates a signal boosted to the threshold and applies it to the gate of the output stage switch M0. The logic circuit 11 also collectively recognizes the state detection signals output from the overheat detection circuit 13 and the overcurrent detection circuit 14.

[0054] When the temperature of the output stage switch M0 becomes abnormally higher than the rated temperature, the overheat detection circuit 13 sends an abnormality signal to the logic circuit 11. Upon receiving the abnormality signal sent from the overheat detection circuit 13, the logic circuit 11 outputs an H-level signal to the gate of the NMOS transistor M3 to turn on the NMOS transistor M3. When the NMOS transistor M3 turns on, the signal output from the gate drive circuit 12 is pulled out, the gate of the output stage switch M0 becomes L-level, and the output stage switch M0 turns off.

[0055] Furthermore, when the logic circuit 11 detects that the temperature rise of the output stage switch M0 is below the threshold based on the temperature state detection signal from the overheat detection circuit 13, it outputs an L level to the gate of the NMOS transistor M1 to turn off the NMOS transistor M1. Furthermore, when the logic circuit 11 detects that the temperature rise of the output stage switch M0 is equal to or greater than the threshold based on the state detection signal from the overheat detection circuit 13, it outputs an H level to the gate of the NMOS transistor M1 to turn on the NMOS transistor M1.

[0056] In this case, the NMOS transistor M1 functions as a switch element for detecting an overheating state, and if the temperature rise of the output stage switch M0 is less than the threshold, it turns off and pulls up the ST terminal to the H level, and if the temperature rise of the output stage switch M0 is equal to or greater than the threshold, it turns on and pulls down the ST terminal to the L level, and notifies the CPU 3 of the overheating state.

[0057] On the other hand, the overcurrent detection circuit 14 forms a current mirror circuit together with the output stage switch M0, for example, and generates a current identical to the current flowing through the output stage switch M0. When it detects that a current abnormally larger than the rated current is flowing, it sends an abnormality signal to the logic circuit 11.

[0058] The logic circuit 11 receives the abnormality signal sent from the overcurrent detection circuit 14 and outputs an H-level signal to the gate of the NMOS transistor M3 to turn on the NMOS transistor M3. When the NMOS transistor M3 turns on, the signal output from the gate drive circuit 12 is pulled out, the gate of the output stage switch M0 goes to L level, and the output stage switch M0 turns off.

[0059] Furthermore, when the logic circuit 11 detects based on the current state detection signal from the overcurrent detection circuit 14 that the current flowing through the output stage switch M0 is less than the threshold, it outputs an L level to the gate of the NMOS transistor M1 to turn off the NMOS transistor M1. Furthermore, when the logic circuit 11 detects based on the current state detection signal from the overcurrent detection circuit 14 that the current flowing through the output stage switch M0 is equal to or greater than the threshold, it outputs an L level to the gate of the NMOS transistor M1 to turn off the NMOS transistor M1. 1 A high level is output to the gate of the NMOS transistor M 1 Turn on.

[0060] NMOS transistor M 1 In this case, it functions as a switch element for detecting an overcurrent state, and when the current flowing through the output stage switch M0 is less than the threshold, it turns off and pulls up the ST terminal to the H level, and when the current flowing through the output stage switch M0 is greater than or equal to the threshold, it turns on and pulls down the ST terminal to the L level, and notifies the CPU 3 of the overcurrent state.

[0061] On the other hand, the connection point between the gate of the NMOS transistor M2 and the other end of the resistor R1 and the other end of the resistor R2 p0 The line La connecting to functions as a disconnection detection line. If the L load 2 is shorted when the IN terminal is at L level, the OUT terminal goes to L level, and L level is applied to the gate of the NMOS transistor M2 via line La, turning off the NMOS transistor M2. Therefore, when the IN terminal is at L level, the ST terminal goes to H level, and the short circuit of the L load 2 is notified to the CPU 3.

[0062] The voltage detection circuit 15 monitors the overvoltage applied between the drain and source of the output stage switch M0. When the overvoltage exceeds a predetermined voltage, the voltage application circuit 16 applies a threshold voltage Vth2, which is higher than the threshold voltage Vth1 of the output stage switch M0 during normal operation, to the gate of the output stage switch M0.

[0063] 3 is a diagram showing an example of the internal configuration of a voltage detection circuit and a voltage application circuit. The voltage detection circuit 15 includes a diode group Dg1 (first diode group), an NMOS transistor M11, and a latch circuit 15a. The voltage application circuit 16 includes a diode group Dg2 (second diode group), a resistor R10, an NMOS transistor M21, and a diode D20 (output diode). The diode group Dg1 includes diodes D11, . . . , D14 (plurality of first diodes), and the diode group Dg2 includes diodes D21, D22, and D23 (plurality of second diodes).

[0064] The connection relationships of the constituent elements will be explained below. Diodes D11, ..., D14 are connected in series, the cathode of diode D11 (the cathode of the first end of the first diode group) is connected to the OUT terminal (the drain of the output stage switch M0 and one end of the L load 2), the anode of diode D11 is connected to the cathode of diode D12, and the anode of diode D12 is connected to the cathode of diode D13. Furthermore, the anode of diode D13 is connected to the cathode of diode D14.

[0065] The anode of diode D14 (the anode at the second end of the first diode group) is connected to the drain of NMOS transistor M11 and the input terminal of latch circuit 15a. The gate of NMOS transistor M11 is connected to the source of NMOS transistor M11 and the GND terminal. Note that NMOS transistor M11 is a depletion-type MOSFET with its gate shorted to its source, and current flows between its drain and source even when the voltage between its gate and source is zero (NMOS transistor M11 functions as a constant current source).

[0066] One end of the resistor R10 is connected to the OUT terminal, and the other end of the resistor R10 is connected to the drain of an NMOS transistor M21. The gate of the NMOS transistor M21 is connected to the output terminal of the latch circuit 15a.

[0067] The source of the NMOS transistor M21 is connected to the anode of the diode D20 and the anode of the diode D21 (the anode of the third end of the second diode group). The cathode of the diode D20 is connected to the gate of the output stage switch M0 and the output terminal of the gate drive circuit 12 shown in FIG.

[0068] The cathode of the diode D21 is connected to the anode of the diode D22, and the cathode of the diode D22 is connected to the anode of the diode D23. The cathode of the diode D23 (the cathode of the fourth end of the second diode group) is connected to the GND terminal.

[0069] Here, when the voltage detection circuit 15 detects that the overvoltage due to the back electromotive force generated in the L load 2 when the output stage switch M0 is turned on and then turned off has reached or exceeded a predetermined voltage of the clamp voltage, it outputs an H-level detection signal a.

[0070] When the overvoltage reaches or exceeds a predetermined voltage and receives an H-level detection signal a output from the voltage detection circuit 15, the voltage application circuit 16 quickly applies a voltage signal b having a threshold voltage Vth2 higher than the threshold voltage Vth1 during normal operation to the gate of the output stage switch M0, thereby turning on the output stage switch M0.

[0071] 4 is a diagram showing an example of voltage distribution of diodes. The clamp voltage applied between the OUT terminal and GND is set to 50V, the breakdown voltage of the diode group Dg1 is set to 49V, and the threshold voltage Vth1 of the output stage switch M0 is set to 1V.

[0072] In this case, if the reverse voltage Vr of each of the diodes D11, ..., D14 is 12.25 V, the voltage applied to the anode of the diode D14 and the drain of the NMOS transistor M11 will be 1 V (= 50 V - 12.25 V × 4), and at this time, a set signal SET is input to the input terminal (set input terminal) of the latch circuit 15 a. When the set signal SET is input, the latch circuit 15 a latches and outputs an H-level detection signal a and applies it to the gate of the NMOS transistor M21.

[0073] Meanwhile, the forward voltage Vf of diodes D21, D22, D23 and diode D20 is each 0.6V. When a high-level detection signal a is applied to the gate of NMOS transistor M21, NMOS transistor M21 turns on, and at this time, the voltage applied to the source of NMOS transistor M21 becomes 1.8V (=0.6V×3). Furthermore, since the forward voltage Vf of diode D20 is also 0.6V, the voltage at the cathode of diode D20 becomes 1.2V (=1.8V−0.6V), and this 1.2V voltage signal b is applied to the gate of output stage switch M0.

[0074] Here, if the threshold voltage of the output stage switch M0 during normal operation is 1V and the upper limit of the variation in threshold voltage of the fine MOS transistors of the output stage switch M0 is, for example, 0.1V, then 1.1V or more is required to turn on all the fine MOS transistors.

[0075] Therefore, in the above example, a voltage of 1.2V is applied to the gate of the output stage switch M0 to process the energy of the L load 2 when the L load 2 is clamped. In this way, by forcibly applying a voltage of 1.1V or more when clamping, all of the fine MOS transistors of the output stage switch M0 are reliably turned on, and the energy processing of the L load 2 is performed by the gate of the output stage switch M0. whole This makes it possible to improve the clamp resistance.

[0076] Since the diode size of the diode group Dg1 can be set to be variable, the predetermined voltage of the clamp voltage (49 V in the above example) can be flexibly adjusted, and since the diode sizes of the diode group Dg2 and the diode D20 can be set to be variable, the threshold voltage Vth2 can be flexibly adjusted. Furthermore, the above configuration can be combined with a power device such as an IGBT (Insulated Gate Bipolar Transistor).

[0077] 5 is a diagram showing an example of the configuration of a voltage detection circuit including a reset circuit. The voltage detection circuit 15-1 includes a diode group Dg1, an NMOS transistor M11, a latch circuit 15a, and a reset circuit 15b.

[0078] When the reset circuit 15b detects that the clamp voltage has become lower than the breakdown voltage of the diode group Dg1, it outputs a reset signal RES to release the latching operation of the latch circuit 15a. When the latch circuit 15a receives the reset signal RES, it releases the latching operation and stops outputting the H-level detection signal a (changing the detection signal a from H to L).

[0079] 6 is a diagram showing an example of the internal configuration of the reset circuit 15b. The reset circuit 15b includes a diode group Dg3 (third diode group) and an NMOS transistor M31 (reset constant current source). The diode group Dg3 includes diodes D31 and D32 (third diodes).

[0080] The diodes D31 and D32 are connected in series, with the cathode of the diode D31 (the cathode of the fifth end of the third diode group) connected to the OUT terminal and the anode of the diode D31 connected to the cathode of the diode D32. Furthermore, the anode of the diode D32 (the anode of the sixth end of the third diode group) is connected to the input terminal of the latch circuit 15a and the drain of the NMOS transistor M31. The gate of the NMOS transistor M31 is connected to the source of the NMOS transistor M31 and the GND terminal.

[0081] Here, the clamp voltage applied between the OUT terminal and GND is set to 50 V, and the breakdown voltage of the diode group Dg3 is set to 24.5 V. In this case, if the reverse voltage Vr of each of the diodes D31 and D32 is set to 12.25 V, the voltage applied to the anode of the diode D32 and the drain of the NMOS transistor M31 becomes 25.5 V (= 50 V - 12.25 V × 2), and at this time, a reset signal RES is output to the input terminal (reset input terminal) of the latch circuit 15 a.

[0082] In this way, by setting the breakdown voltage of the diode group Dg3 to a value lower than the breakdown voltage of the diode group Dg2, the reset circuit 15b detects a drop in the clamp voltage and outputs a reset signal RES to unlatch the latch circuit 15a.

[0083] Although the embodiments have been described above, the configuration of each part shown in the embodiments can be replaced with other parts having similar functions. Also, any other components or processes may be added. Furthermore, any two or more configurations (features) of the above-described embodiments may be combined. [Explanation of symbols]

[0084] 1. Semiconductor device 1a Output stage switch 1b Voltage detection circuit 1c Drive circuit 1d Voltage application circuit 2 Inductive load (L load) V1 drive signal V2 voltage signal Vth1 First threshold voltage Vth2 Second threshold voltage

Claims

1. an output stage switch connected to the inductive load and actuating the inductive load by switching; a voltage detection circuit that outputs a detection signal when detecting that an overvoltage caused by a back electromotive force generated in the inductive load when the output stage switch is turned off following its turn on has reached a predetermined voltage or higher; a drive circuit that applies a drive signal having a first threshold voltage to a gate of the output stage switch to turn on the output stage switch; a voltage application circuit that, when receiving the detection signal output from the voltage detection circuit because the overvoltage has reached or exceeded the predetermined voltage, applies a voltage signal having a second threshold voltage higher than the first threshold voltage to a gate of the output stage switch to turn on the output stage switch, the voltage detection circuit includes a first diode group in which a plurality of first diodes are connected in series, a constant current source, and a latch circuit; the voltage application circuit includes a resistor, a MOS (Metal-Oxide-Semiconductor) transistor, a second diode group in which a plurality of second diodes are connected in series, and an output diode; cathodes of first ends of the first diode group are connected to a drain of the output stage switch and one end of the inductive load, anodes of second ends of the first diode group are connected to an input terminal of the constant current source and one input terminal of the latch circuit, and an output terminal of the constant current source is connected to ground; one end of the resistor is connected to a drain of the output stage switch and one end of the inductive load, the other end of the resistor is connected to a drain of the MOS transistor, a gate of the MOS transistor is connected to an output end of the latch circuit, a source of the MOS transistor is connected to an anode of a third end of the second diode group and an anode of the output diode, a cathode of a fourth end of the second diode group is connected to ground, and a cathode of the output diode is connected to the gate of the output stage switch. Semiconductor device.

2. one end of the inductive load and an input end of the voltage detection circuit are connected to the drain of the output stage switch, and a ground is connected to the source of the output stage switch, and the voltage detection circuit monitors the overvoltage applied between the drain and source of the output stage switch. The semiconductor device according to claim 1.

3. When the predetermined voltage is applied to the first diode group and the first diode group breaks down, a set signal is input from the anodes of the second ends of the first diode group to one input terminal of the latch circuit, and upon receiving the set signal, the latch circuit latches and outputs the detection signal. The semiconductor device according to claim 1.

4. the MOS transistor is turned on by the detection signal to apply a voltage based on a voltage drop of a forward voltage of the second diode group to the output diodes, and the voltage signal obtained by subtracting the forward voltage of the output diodes from the voltage is applied to the gate of the output stage switch as the second threshold voltage; The semiconductor device according to claim 1.

5. the voltage application circuit applies, to the gate of the output stage switch, the second threshold voltage, which is equal to or greater than a voltage value obtained by adding an upper limit value of variation to the first threshold voltage, where variation occurs due to a plurality of gate trenches provided in the output stage switch; The semiconductor device according to claim 1.

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