Semiconductor device and manufacturing method thereof

Abstract

To realize a semiconductor element that can achieve good contact with a 2DEG layer.SOLUTION: A semiconductor element, having a substrate 10, a channel layer 12 formed on the substrate 10 and made of a Group III nitride semiconductor, and a barrier layer 13 formed on and in contact with the channel layer 12 and made of a Group III nitride semiconductor having a higher Al composition than the channel layer 12, includes a recess 20 formed in a partial region of the surface of the barrier layer 13 and having a depth reaching the channel layer 12, and an electrode provided so as to cover the recess 20, and the recess has a first side face on which the barrier layer 13 is exposed and which is angled with respect to the main surface of the substrate 10, a terrace which is connected to the first side face and on which the surface of the channel layer 12 is exposed, and a second side face which is connected to the terrace and on which the channel layer 12 is exposed, the second side face inclined with respect to the main surface of the substrate and having an inclination angle smaller than that of the first side face.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] A semiconductor device is known that has a heterojunction structure in which a channel layer made of GaN and a barrier layer made of AlGaN are stacked in this order, and operates using a two-dimensional electron gas (2DEG) layer formed at the heterojunction interface as a channel.

[0003] In such semiconductor devices, a recess structure is sometimes provided to allow good contact between the electrodes and the 2DEG layer (see, for example, Patent Document 1). The recess structure is a structure in which a groove (recess) is provided in a partial region of the barrier layer surface, deep enough to reach the channel layer, a heterojunction interface is exposed on the side surface of the groove, and electrodes are provided along the top, side, and bottom surfaces of the recess. This structure allows the electrodes to contact the 2DEG layer, thereby reducing contact resistance.

[0004] Patent Documents 2 and 3 describe HFETs with two sloped recess sides, where the slope angle of the recess side changes at the position where the barrier layer is exposed, making the slope of the upper side gentler than that of the lower side. Patent Document 4 also describes a configuration in which the slope angle of the recess side is changed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5329606 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-99542 [Patent Document 3] Patent No. 5625314 [Patent Document 4] Patent No. 7057473 Summary of the Invention [Problem to be solved by the invention]

[0006] However, since the recess is formed by dry etching, etching damage to the recess occurs, and this etching damage cannot be removed.

[0007] Furthermore, since the side surfaces of the recess are inclined, the effective thickness of the AlGaN layer becomes thin, resulting in a decrease in the 2DEG concentration near the recess.

[0008] Furthermore, when forming an electrode in the recess, it is necessary to precisely fit the electrode along the recess steps to prevent the electrode from being disconnected or not making contact with the 2DEG layer. Therefore, sputtering, which has excellent step coverage, must be selected as the electrode formation method. However, sputtering can potentially damage the semiconductor.

[0009] The present invention has been made in view of the above background, and aims to provide a semiconductor element that allows good contact with the 2DEG layer, and a method for manufacturing the same. [Means for solving the problem]

[0010] One aspect of the present invention is A semiconductor device having a substrate, a channel layer formed on the substrate and made of a Group III nitride semiconductor, and a barrier layer formed on and in contact with the channel layer and made of a Group III nitride semiconductor having a higher Al composition than the channel layer, a recess provided in a partial region of the surface of the barrier layer, the recess having a depth reaching the channel layer; an electrode provided so as to cover the recess, The recess is a first side surface that is an exposed surface of the barrier layer and that is angled with respect to the main surface of the substrate; a terrace connected to the first side surface and exposing the surface of the channel layer; a second side surface that is connected to the terrace, exposes the channel layer, and is inclined with respect to the main surface of the substrate, the inclination angle of which is smaller than that of the first side surface; death, The width of the terrace is 100 nm or more. It is found in semiconductor elements. Another aspect of the present invention is A semiconductor device having a substrate, a channel layer formed on the substrate and made of a Group III nitride semiconductor, and a barrier layer formed on and in contact with the channel layer and made of a Group III nitride semiconductor having a higher Al composition than the channel layer, a recess provided in a partial region of the surface of the barrier layer, the recess having a depth reaching the channel layer; an electrode provided so as to cover the recess, The recess is a first side surface that is an exposed surface of the barrier layer and that is angled with respect to the main surface of the substrate; a terrace connected to the first side surface and exposing the surface of the channel layer; a second side surface that is connected to the terrace, exposes the channel layer, and is inclined with respect to the main surface of the substrate, the inclination angle of which is smaller than that of the first side surface; The first side is in a semiconductor device, the m-plane of the barrier layer.

[0011] Another aspect of the present invention is A method for manufacturing a semiconductor device having a substrate, a channel layer formed on the substrate and made of a Group III nitride semiconductor, and a barrier layer formed on and in contact with the channel layer and made of a Group III nitride semiconductor having a higher Al composition than the channel layer, a first recess forming step of dry-etching a predetermined region of the surface of the barrier layer to form a first recess having a side surface inclined with respect to the main surface of the substrate and a bottom surface deeper than the surface of the channel layer; a second recess forming step of wet-etching a side surface of the first recess with an alkaline solution to form a second recess; an electrode forming step of forming an electrode on the barrier layer so as to cover the second recess, In the method for manufacturing a semiconductor element, the second recess formation step is a step of wet-etching the barrier layer to form a first side surface that is angled with respect to the main surface of the substrate, exposing the surface of the channel layer to form a terrace, and wet-etching the channel layer to form a second side surface that is inclined with respect to the main surface of the substrate and has an angle smaller than that of the first side surface. [Effects of the Invention]

[0012] According to the present invention, the electrode has high coverage over the recess, preventing the electrode from being broken, thereby reducing the contact resistance of the electrode. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view showing the configuration of a semiconductor element according to Embodiment 1, the cross-section being perpendicular to the main surface of the substrate. [Figure 2] FIG. 3 is an enlarged cross-sectional view showing a recess portion of the semiconductor element according to the first embodiment. [Figure 3] FIG. 2 is a diagram showing a planar pattern of an electrode. [Figure 4] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 5] 2A to 2C are diagrams illustrating a manufacturing process of a semiconductor element according to the first embodiment. [Figure 6] 3A to 3C are views showing a manufacturing process of a recessed portion of a semiconductor element according to the first embodiment. [Figure 7] Graph comparing contact resistivity. [Figure 8] 10 is a graph showing the distribution of on-resistance of each semiconductor element. [Figure 9] Cross-sectional SEM image of the recess. DETAILED DESCRIPTION OF THE INVENTION

[0014] The semiconductor device includes a substrate, a channel layer formed on the substrate and made of a Group III nitride semiconductor, and a barrier layer formed on and in contact with the channel layer and made of a Group III nitride semiconductor having a higher Al composition than the channel layer, the semiconductor device having a recess formed in a partial region of the surface of the barrier layer and having a depth reaching the channel layer, and an electrode provided so as to cover the recess, the recess having a first side surface which is a surface where the barrier layer is exposed and which is angled with respect to the main surface of the substrate, a terrace connected to the first side surface which is a surface where the surface of the channel layer is exposed, and a second side surface connected to the terrace which is a surface where the channel layer is exposed and which is inclined with respect to the main surface of the substrate at an angle smaller than that of the first side surface.

[0015] The width of the terrace may be 100 nm or more, which can improve the electrode coverage and better prevent the electrode from being broken.

[0016] The first side surface may be a surface that has an angle of 80 degrees or more and 90 degrees or less with respect to the main surface of the substrate. The first side surface may also be an m-plane of the barrier layer. This can prevent the 2DEG concentration of the 2DEG layer from decreasing near the recess side surface.

[0017] A method for manufacturing a semiconductor device includes a substrate, a channel layer formed on the substrate and made of a Group III nitride semiconductor, and a barrier layer formed on and in contact with the channel layer and made of a Group III nitride semiconductor having a higher Al composition than the channel layer, the method comprising the steps of: a first recess formation step of dry-etching a predetermined region of the surface of the barrier layer to form a first recess whose side is inclined with respect to the main surface of the substrate and whose bottom is deeper than the surface of the channel layer; a second recess formation step of wet-etching the side of the first recess with an alkaline solution to form a second recess; and an electrode formation step of forming an electrode on the barrier layer so as to cover the second recess. The second recess formation step includes wet-etching the barrier layer to form a first side that is angled with respect to the main surface of the substrate, exposing the surface of the channel layer to form a terrace, and wet-etching the channel layer to form a second side that is inclined with respect to the main surface of the substrate at an angle smaller than that of the first side.

[0018] The second recess forming step may be a step of forming a terrace so that the terrace has a width of 100 nm or more, which can improve the electrode coverage and more effectively prevent the electrode from being disconnected.

[0019] The second recess forming step may be performed so that the first side surface is at an angle of 80 degrees or more and 90 degrees or less with respect to the main surface of the substrate. The second recess forming step may also be performed so that the first side surface is an m-plane. This can prevent the 2DEG concentration of the 2DEG layer from decreasing near the recess side surface. The alkaline solution may be a TMAH aqueous solution.

[0020] (Embodiment 1) 1. Structure of semiconductor elements FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to embodiment 1, showing a cross section perpendicular to the main surface of a substrate. The semiconductor device according to embodiment 1 is a polarization super junction (PSJ) FET, and as shown in FIG. 1, includes a substrate 10, a buffer layer 11, a channel layer 12, a barrier layer 13, an undoped layer 14, a p-layer 15, a gate electrode 16, a source electrode 17, and a drain electrode 18. FIG. 2 is an enlarged cross-sectional view of a recess portion of the semiconductor device according to embodiment 1. FIG. 3 is a top view showing an electrode pattern. The AA cross section in FIG. 3 corresponds to FIG. 1.

[0021] The substrate 10 is made of sapphire with the c-plane or a-plane as the principal surface, and has a thickness of, for example, 50 to 500 μm.

[0022] The channel layer 12 is located on the substrate 10 via a buffer layer 11. The channel layer 12 is made of undoped GaN. The buffer layer 11 is, for example, low-temperature grown AlN or GaN. The thickness of the channel layer 12 is, for example, 300 to 5000 nm.

[0023] The barrier layer 13 is located on the channel layer 12. The barrier layer 13 is made of undoped AlGaN. The Al composition is 10 to 50%. The channel layer 12 and the barrier layer 13 form a heterojunction, and a two-dimensional electron gas (2DEG) layer 19 is generated in the channel layer 12 near the interface. The semiconductor device in embodiment 1 operates using this 2DEG layer 19 as a channel. The thickness of the barrier layer 13 is, for example, 20 to 150 nm.

[0024] The undoped layer 14 is located in a partial region on the barrier layer 13 (a region excluding the regions where the source electrode 17 and the drain electrode 18 are formed). The undoped layer 14 is undoped GaN. The barrier layer 13 and the undoped layer 14 form a heterojunction, and a two-dimensional hole gas (2DHG) layer 22 is generated in the undoped layer 14 near the interface. This 2DHG layer 22 does not function as a channel, but flattens the electric field distribution and improves the breakdown voltage. The thickness of the undoped layer 14 is, for example, 10 to 1000 nm.

[0025] The p-layer 15 is located in a partial region on the undoped layer 14, closer to the source electrode 17. The p-layer 15 is made of p-GaN. The Mg concentration is, for example, 1×10 17 cm -3 3x10 or more 20 cm -3 The thickness of p-layer 15 is, for example, 20 to 150 nm. P-layer 15 may be made up of two layers: a low-concentration p-type layer and a high-concentration p-type layer.

[0026] The gate electrode 16 is located on the p-layer 15. The material of the gate electrode 16 is, for example, Ni / Au.

[0027] The recess 20 is a groove provided in a region of the surface of the barrier layer 13 where the source electrode 17 and the drain electrode 18 are to be provided, and has a depth that reaches the channel layer 12. The recess 20 has a two-stepped side surface, and has a shape including a side surface 20a where the barrier layer 13 is exposed, a terrace 20b that is continuous with the lower end of the side surface 20a and where the surface of the channel layer 12 is exposed, a side surface 20c that is continuous with one end of the terrace 20b and where the channel layer 12 is exposed, and a bottom surface 20d that is continuous with the lower end of the side surface 20c and is the surface where the channel layer 12 is exposed and is located deeper than the surface of the channel layer 12.

[0028] The side surface 20a is a surface perpendicular to the major surface of the barrier layer 13, and is, for example, the m-plane of AlGaN. It may also be a surface other than the m-plane, such as the a-plane. It does not have to be a perpendicular surface, as long as its inclination angle with respect to the major surface of the substrate 10 is larger than that of the side surface 20c. However, it is preferable that it is as close to perpendicular as possible, and for example, it is preferable that it has an angle of 80 degrees or more and 90 degrees or less with respect to the major surface of the substrate 10, and most preferably is perpendicular. The side surface 20a is a surface exposed by wet etching and is a surface that is not damaged by etching.

[0029] The terrace 20b is the surface of the channel layer 12, which is the c-plane of GaN. The terrace 20b is a surface exposed by wet etching and is free from etching damage. The terrace 20b is perpendicular to and continuous with the side surface 20a.

[0030] The width of the terrace 20b is preferably 100 nm or more. Here, the width of the terrace 20b refers to the width of the terrace 20b that can be placed in the direction of the shortest straight line connecting the source electrode 17 and the drain electrode 18 in a plan view. 3 In this case, the width is the width in the direction perpendicular to the stripe. By making the width of the terrace 20b 100 nm or more, and making the width of the terrace 20b sufficiently wide, the coverage of the source electrode 17 and the drain electrode 18 with the recess 20 can be further improved, and the source electrode 17 and the drain electrode 18 can be prevented from being cut off by the step of the recess 20. The width is more preferably 140 nm or more.

[0031] Furthermore, the width of the terrace 20b is preferably 1000 nm or less, because the area of ​​the 2DEG layer 19 decreases when the width of the terrace 20b increases.

[0032] The side surface 20c is angled with respect to the major surface of the channel layer 12. This angle is smaller than the angle of the side surface 20a, and is, for example, 40 to 80 degrees with respect to the major surface of the substrate 10. Because the side surface 20c is inclined, the coverage of the source electrode 17 and the drain electrode 18 on the recess 20 can be further improved. The side surface 20c is a surface exposed by wet etching and is not damaged by etching. The side surface 20c is connected to the terrace 20b at an angle. The side surface 20c is, for example, a surface obtained by inclining an m-plane.

[0033] The bottom surface 20d is a surface parallel to the major surface of the channel layer 12 and is the c-plane of GaN. The bottom surface 20d is a surface located deeper than the surface of the channel layer 12 (on the substrate 10 side) and is a surface exposed by dry etching of the channel layer 12. The bottom surface 20d is connected to the side surface 20c at an angle. The height from the bottom surface 20d to the surface of the channel layer 12 can be any height greater than 0 nm, but is, for example, 10 nm or greater.

[0034] The source electrode 17 and the drain electrode 18 are provided in predetermined regions on the barrier layer 13, spaced apart from each other. The source electrode 17 and the drain electrode 18 are provided so as to cover the recess 20. That is, the source electrode 17 and the drain electrode 18 are provided so as to contact the side surface 20a, the terrace 20b, the side surface 20c, and the bottom surface 20d of the recess 20. Therefore, the source electrode 17 and the drain electrode 18 are in contact with the 2DEG layer 19 near the corner formed by the side surface 20a and the terrace 20b of the recess 20. This reduces the contact resistance of the source electrode 17 and the drain electrode 18. The material of the source electrode 17 and the drain electrode is, for example, Ti / Al / Ti or V / Al / Ti.

[0035] Next, the planar pattern of the recess 20 and the electrodes will be described. The source electrode 17 and the drain electrode 18 are provided at a predetermined interval in a planar view, and are patterned so that the gate electrode 16 is sandwiched between the source electrode 17 and the drain electrode 18.

[0036] figure 3As shown in Fig. 1, the source electrode 17 and the drain electrode 18 have a comb-like planar pattern. That is, they have stripe-like portions where long, thin linear patterns are arranged in parallel at a predetermined interval, and portions where the linear patterns connect to each other. The stripe portions of the source electrode 17 and the stripe portions of the drain electrode 18 are arranged so as to interdigitate with each other.

[0037] The gate electrodes 16 are provided in ring-shaped patterns surrounding the respective elongated linear patterns of the source electrodes 17 .

[0038] Also, 3 As shown in the figure, a plurality of recesses 20 are arranged at predetermined intervals along the linear patterns of the source electrode 17 and the drain electrode 18 inside the respective lines. The planar shape of the recesses 20 is, for example, a regular hexagon. This is because the side surfaces 20a of the recesses 20 are m-planes. Of course, the planar shape of the recesses is not limited to a regular hexagon. For example, it may be an equilateral triangle, a square, a rectangle, a circle, or the like.

[0039] The diameter of the recess 20 may be large enough so that it is included in the patterns of the source electrode 17 and the drain electrode 18 in a plan view. 3 In this case, it is sufficient that the width is smaller than the width of the linear patterns of the source electrode 17 and the drain electrode 18. For example, the width of the linear patterns is 20 μm, and the diameter of the recess 20 is 5 μm.

[0040] The planar patterns of the gate electrode 16, the source electrode 17, and the drain electrode 18 are merely examples, and are not limited to the patterns shown in FIG.

[0041] 2. Operation of semiconductor elements The semiconductor device in the first embodiment is a normally-on device in which current flows from the drain electrode 18 to the source electrode 17 via the 2DEG layer 19 when no voltage is applied to the gate electrode 16. When a voltage (negative voltage) equal to or lower than the threshold voltage is applied to the gate electrode 16, the current from the drain electrode 18 to the source electrode 17 is turned off.

[0042] When a voltage (negative voltage) equal to or lower than the threshold voltage is applied to the gate electrode 16, holes are extracted from the 2DHG layer 22 and disappear, and electrons disappear from the 2DEG layer 19 below the undoped layer 14. As a result, the entire region below the undoped layer 14 is depleted, and the electric field strength becomes constant. This allows the electric field applied from the drain electrode 18 to the gate electrode 16 to be evenly distributed, and there is no area where the electric field concentrates. As a result, a very high breakdown voltage can be achieved.

[0043] Furthermore, when a voltage higher than the threshold voltage is applied to gate electrode 16, a current flows from drain electrode 18 to source electrode 17, resulting in an ON operation. At this time, a current flows from drain electrode 18 to 2DEG layer 19 via the surface of barrier layer 13 and side surface 20a of recess 20. Then, a current flows from 2DEG layer 19 to source electrode 17 via the surface of barrier layer 13 and side surface 20a of recess 20.

[0044] 2, the source electrode 17 and the drain electrode 18 can make good contact with the 2DEG layer 19. The details are as follows.

[0045] Because the side surface 20a of the recess 20 is perpendicular to the major surface of the substrate 10, there is no substantial reduction in the thickness of the barrier layer 13. When the side surface 20a is inclined, strain is relaxed, and the substantial thickness of the barrier layer 13 is reduced. Because there is no substantial reduction in the thickness of the barrier layer 13, it is possible to prevent a reduction in the 2DEG concentration of the 2DEG layer 19 near the side surface of the recess 20. As a result, the source electrode 17 and the drain electrode 18 can make good contact with the 2DEG layer 19.

[0046] The side surface of the recess 20 has a two-step structure: a side surface 20a perpendicular to the main surface of the substrate 10, a terrace 20b which is the surface of the channel layer 12, and a side surface 20c inclined relative to the main surface of the substrate 10. This step structure improves the coverage of the recess 20 with the source electrode 17 and the drain electrode 18, preventing the source electrode 17 and the drain electrode 18 from being disconnected by the step. As a result, the source electrode 17 and the drain electrode 18 are securely in close contact with the corner formed by the terrace 20b and the side surface 20c, and can make good contact with the 2DEG layer 19 near the corner.

[0047] Furthermore, the side surface 20a, terrace 20b, and side surface 20c of the recess 20 are exposed by wet etching after dry etching, as will be described in detail in the manufacturing method section. Therefore, these surfaces are free from etching damage. The source electrode 17 and the drain electrode 18 are in contact with these surfaces free from etching damage, thereby reducing contact resistance.

[0048] As described above, in the semiconductor element of embodiment 1, the recess 20 has a shape having the side surface 20a, the terrace 20b, the side surface 20c, and the bottom surface 20d as shown in FIG. 2 , and therefore the coverage of the source electrode 17 and the drain electrode 18 is high, the source electrode 17 and the drain electrode 18 can be prevented from being disconnected, and the contact resistance of the source electrode 17 and the drain electrode 18 can be reduced.

[0049] 3. Manufacturing method of semiconductor element Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings.

[0050] First, a channel layer 12, a barrier layer 13, an undoped layer 14, and a p-layer 15 are sequentially stacked on a substrate 10 via a buffer layer 11 by MOCVD (see FIG. 4). For example, TMG (trimethylgallium) is used as a Ga source gas, TMA (trimethyl gallium) is used as an Al source gas, and ammonia is used as a nitrogen source gas. Hydrogen or nitrogen is used as a carrier gas.

[0051] Next, a predetermined region on the surface of the p-layer 15 is dry-etched to expose the undoped layer 14. Furthermore, of the exposed undoped layer 14, regions where the source electrode 17 and the drain electrode 18 are to be formed are dry-etched to expose the barrier layer 13 (see FIG. 5).

[0052] Next, predetermined regions of the barrier layer 13 are dry-etched to form recesses 21 (see FIG. 6(a)). Here, etching conditions are set so that the side surfaces of the recesses 21 are inclined. The inclination angle of the side surfaces of the recesses 21 is, for example, 30 to 70 degrees with respect to the main surface of the substrate 10. Furthermore, the recesses 21 are formed deeper than the surface of the channel layer 12. This dry etching causes etching damage to the side surfaces and bottom surface of the recesses 21.

[0053] Next, the side surfaces of the recess 21 are wet-etched with a TMAH aqueous solution. The concentration of the TMAH aqueous solution is, for example, 15 to 25 wt %. The temperature of the TMAH aqueous solution is, for example, 60 to 90°C. If the concentration and temperature are within these ranges, the difference in etching rate between the barrier layer 13 and the channel layer 12 becomes appropriate, making it easy to form the recess 20.

[0054] The etching time is, for example, 10 to 30 minutes. If the etching time is shorter than 10 minutes, the width of the terrace 20b does not expand sufficiently, which may result in a decrease in coverage or a step discontinuity of the source electrode 17 and the drain electrode 18. If the etching time is longer than 30 minutes, etching of the channel layer 12 progresses, exposing the m-plane and making the side surface 20c vertical, which may result in a decrease in coverage or a step discontinuity of the source electrode 17 and the drain electrode 18.

[0055] In wet etching of a group III nitride semiconductor using a TMAH solution, the side surfaces of the recess 20 are etched because they are surfaces other than the c-plane, but the surfaces of the barrier layer 13, the channel layer 12, and the bottom surface of the recess 20 are not etched because they are c-planes. Also, the etching rate increases as the Al composition increases. Furthermore, as the etching progresses, the m-plane is exposed, and the etching progresses while maintaining the m-plane.

[0056] Therefore, by wet etching the recess 21, a recess 20 having a side surface 20a, a terrace 20b, a side surface 20c, and a bottom surface 20d is formed (see FIG. 6(b)). More details are as follows.

[0057] The region of the side surface of the recess 21 where the barrier layer 13 is exposed is etched quickly in the lateral direction. Channel layer 12 The etching rate is slower in the region where the barrier layer 13 is exposed. This is because the Al composition of the barrier layer 13 is higher than that of the channel layer 12. This etching exposes the surface of the channel layer 12. This exposed surface of the channel layer 12 is not etched because it is the c-plane. This forms a terrace 20b of the recess 20. The terrace 20b is a surface that was not exposed when the recess 21 was formed, and is therefore a surface that is not damaged by etching.

[0058] As the etching of the barrier layer 13 progresses, the m-plane of the barrier layer 13 is exposed, and side surfaces 20a of the recess 20 are formed perpendicular to the main surface of the barrier layer 13. Furthermore, etching damage to the side surfaces 20a is removed by etching the barrier layer 13.

[0059] Furthermore, the region of the side surface of the recess 21 where the channel layer 12 is exposed is made of GaN with a lower Al composition than the barrier layer 13 (Al composition is 0), and therefore has a slower etching rate than the barrier layer 13. As a result, etching does not progress to the point where the side surface becomes vertical, and the side surface remains inclined. This inclined side surface of the channel layer 12 becomes the side surface 20c of the recess 20. The inclination angle of the side surface 20c is equal to or greater than the inclination angle of the side surface of the recess 21. This etching of the channel layer 12 removes etching damage to the side surface 20c.

[0060] The bottom surface of the recess 21 is the c-plane and is not etched, but remains as the bottom surface 20d of the recess 20. In this way, the recess 20 having the side surface 20a, the terrace 20b, the side surface 20c, and the bottom surface 20d is formed.

[0061] In addition to TMAH, the wet etching solution can also be an alkaline solution such as KOH or NaOH, and the solvent is not limited to water.

[0062] Next, a source electrode 17 and a drain electrode 18 are formed in predetermined regions on the barrier layer 13. The source electrode 17 and the drain electrode 18 are formed so as to cover the recess 20. If the source electrode 17 and the drain electrode 18 are made of the same material, they can be formed simultaneously.

[0063] Here, the recess 20 has a terrace 20b where the surface of the channel layer 12 is exposed, and a sloped side surface 20c. Therefore, the source electrode 17 and the drain electrode 18 can be formed with good coverage along the step of the recess 20, preventing step disconnection. In particular, the source electrode 17 and the drain electrode 18 can be reliably adhered to the 2DEG layer 19 exposed near the corner formed by the terrace 20b and the side surface 20c.

[0064] The source electrode 17 and the drain electrode 18 can be formed by vapor deposition, sputtering, or the like. In particular, it is preferable to use vapor deposition, such as EB vapor deposition. Conventionally, sputtering, which provides good coverage, has been used to cover the recesses without causing discontinuities in the source electrode 17 and the drain electrode 18. However, sputtering can sometimes damage the semiconductor layer. In contrast, the shape of the recess 20 in embodiment 1 provides good coverage for the source electrode 17 and the drain electrode 18, preventing discontinuities even when the source electrode 17 and the drain electrode 18 are formed by vapor deposition.

[0065] Furthermore, the source electrode 17 and the drain electrode 18 are in contact with the side surface 20a, the terrace 20b, and the side surface 20c of the recess 20, which are not damaged by etching, and therefore the contact resistance can be reduced.

[0066] Next, heat treatment is carried out to reduce the contact resistance of source electrode 17 and drain electrode 18. The heat treatment conditions are, for example, a nitrogen atmosphere, 500 to 700° C., and 60 to 600 seconds.

[0067] Next, the gate electrode 16 is formed on the p-layer 15 by vapor deposition or the like. The gate electrode 16 may be formed first, followed by the formation of the recess 20, the source electrode 17, and the drain electrode 18. In this manner, the semiconductor device of the first embodiment is manufactured.

[0068] 4. Experimental Results As Sample A, a semiconductor device according to Embodiment 1 was fabricated in which a recess 20 was formed as follows. First, a recess 21 was formed by dry etching to a depth reaching the channel layer 12, and then wet etching was performed at 50°C for 20 minutes using a 2.3 wt% TMAH aqueous solution. This resulted in the formation of a recess 20 with a terrace 20b having a width of 40 nm. Then, electrodes were formed on the top, side, and bottom surfaces of the recess 20. The electrodes were made of Ti / Al / Ti, and the alloy temperature was set to 600°C.

[0069] On the other hand, for sample B, the wet etching after forming the recess 21 was changed as follows to form the recess 20. The rest was the same as sample A. The wet etching was performed using a 22 wt% TMAH aqueous solution at 85°C for 20 minutes. This resulted in the formation of a recess 20 with a terrace 20b width of 140 nm.

[0070] Figure 7 is a graph showing the results of measuring and comparing the contact resistance using TLM patterns for samples A and B. As shown in Figure 7, both the average and median values ​​of contact resistivity were lower for sample B than for sample A.

[0071] Furthermore, a plurality of semiconductor devices according to the first embodiment having the recesses 20 of samples A and B were fabricated, and the on-resistance of each device was measured. FIG. 8 is a graph showing the distribution of the on-resistance of each device. As shown in FIG. 8, sample B has a higher on-resistance than sample A. Mode but 1mΩcm 2 It was found to be low.

[0072] Figure 9 shows cross-sectional SEM images of the recess cross section for samples A and B. As shown in Figure 9(a), sample A showed a step discontinuity. On the other hand, as shown in Figure 9(b), sample B showed no step discontinuity in the electrode.

[0073] 7 to 9, it is found that sufficient widening of the terraces 20b in the recess 20 improves the electrode's coverage of the recess 20 and prevents step disconnection. It is also found that the improved coverage and prevention of step disconnection can reduce the electrode's contact resistivity and therefore the on-resistance.

[0074] 4. Various transformations The present invention is not limited to the semiconductor device shown in Embodiment 1, but can be applied to any semiconductor device having a structure including a channel layer made of a group III nitride semiconductor, a barrier layer made of a group III nitride semiconductor having a higher Al composition than the channel layer, and an electrode in contact with the 2DEG layer by a recess. For example, the present invention can be applied to an HFET or the like. [Explanation of symbols]

[0075] 10: Circuit board 11: Buffer layer 12: Channel layer 13: Barrier layer 14: Undoped layer 15:p layer 16: Gate electrode 17: Source electrode 18: Drain electrode 19:2DEG layer 20: Recess

Claims

1. A semiconductor device having a substrate, a channel layer formed on the substrate and made of a Group III nitride semiconductor, and a barrier layer formed on and in contact with the channel layer and made of a Group III nitride semiconductor having a higher Al composition than the channel layer, a recess provided in a partial region of the surface of the barrier layer, the recess having a depth reaching the channel layer; an electrode provided so as to cover the recess, The recess is a first side surface that is an exposed surface of the barrier layer and that is angled with respect to the main surface of the substrate; a terrace connected to the first side surface and exposing the surface of the channel layer; a second side surface that is connected to the terrace, exposes the channel layer, and is inclined with respect to the main surface of the substrate, the inclination angle of which is smaller than that of the first side surface; A semiconductor device, wherein the terrace has a width of 100 nm or more.

2. A semiconductor device having a substrate, a channel layer formed on the substrate and made of a Group III nitride semiconductor, and a barrier layer formed on and in contact with the channel layer and made of a Group III nitride semiconductor having a higher Al composition than the channel layer, a recess provided in a partial region of the surface of the barrier layer, the recess having a depth reaching the channel layer; an electrode provided so as to cover the recess, The recess is a first side surface that is an exposed surface of the barrier layer and that is angled with respect to the main surface of the substrate; a terrace connected to the first side surface and exposing the surface of the channel layer; a second side surface that is connected to the terrace, exposes the channel layer, and is inclined with respect to the main surface of the substrate, the inclination angle of which is smaller than that of the first side surface; The semiconductor device, wherein the first side is an m-plane of the barrier layer.

3. The semiconductor device according to claim 2 , wherein the terrace has a width of 100 nm or more.

4. 4. The semiconductor element according to claim 1, wherein the first side surface is a surface that has an angle of 80 degrees or more and 90 degrees or less with respect to the main surface of the substrate.

5. A method for manufacturing a semiconductor device having a substrate, a channel layer formed on the substrate and made of a Group III nitride semiconductor, and a barrier layer formed on and in contact with the channel layer and made of a Group III nitride semiconductor having a higher Al composition than the channel layer, comprising: a first recess forming step of dry-etching a predetermined region of the surface of the barrier layer to form a first recess having a side surface inclined with respect to the main surface of the substrate and a bottom surface deeper than the surface of the channel layer; a second recess forming step of wet-etching a side surface of the first recess with an alkaline solution to form a second recess; an electrode forming step of forming an electrode on the barrier layer so as to cover the second recess, a second recess forming step of wet-etching the barrier layer to form a first side surface that is angled with respect to the main surface of the substrate, exposing a surface of the channel layer to form a terrace, and wet-etching the channel layer to form a second side surface that is inclined with respect to the main surface of the substrate, the inclination angle of which is smaller than that of the first side surface.

6. The method of manufacturing a semiconductor device according to claim 5 , wherein the second recess forming step forms the terrace so that the terrace has a width of 100 nm or more.

7. 7. The method for manufacturing a semiconductor element according to claim 5, wherein the second recess forming step forms the first side surface at an angle of 80 degrees or more and 90 degrees or less with respect to the main surface of the substrate.

8. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the second recess forming step forms the first side surface to be an m-plane.

9. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the alkaline solution is a TMAH aqueous solution.

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