Method and apparatus for optimizing program / erase voltages for charge trap memory devices using three-dimensional trap analysis

Abstract

The present invention relates to a method and apparatus for optimizing program / erase voltages of charge trapping memory elements by three-dimensional trap analysis. [Solution] The method is configured to apply different trap control voltages to a memory element, measure the low-frequency noise of the memory element corresponding to each trap control voltage, extract trap distributions in the memory element for each trap control voltage based on the low-frequency noise, analyze the trap distributions according to the depth of the memory element, and detect the trap control voltage having the maximum trap distribution in the charge trap layer of the memory element, thereby detecting at least one of the optimal program voltage or erase voltage for the memory element.

Description

[Technical Field]

[0001] This invention relates generally to memory device optimization, and more particularly to optimizing program / erase voltages for charge trapping memory devices through three-dimensional trap analysis. This patent was supported by the Korea Research Foundation (RS-2023-00280841) funded by the Ministry of Science and ICT. [Background technology]

[0002] CV measurement and charge pumping measurement have been used as traditional methods to extract the amount of charge trapped in the charge trapping layer of a charge trapping memory device. However, CV measurement has the disadvantage that it can only indirectly know the amount of trapped charge, and the charge pumping method cannot measure traps in the charge trapping layer during programming / erasing because the measurable trap depth depends on the gate voltage. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure provides a method and apparatus to check the trap distribution from the interface to the trap layer during program / erase, as the trap depth is frequency dependent.

[0004] The present disclosure provides a method and apparatus for optimizing program / erase voltages for charge trapping memory elements through three-dimensional trap analysis. [Means for solving the problem]

[0005] In the present disclosure, a method for operating a computing device for optimizing program and erase voltages of a charge trapping memory element through three-dimensional trap analysis may include the steps of applying different trap control voltages to the memory element and measuring low-frequency noise of the memory element corresponding to the trap control voltages, extracting trap distributions in the memory element for the trap control voltages based on the low-frequency noise, and analyzing the trap distributions according to the depth of the memory element to detect a trap control voltage having a maximum trap distribution in a charge trapping layer of the memory element.

[0006] In the present disclosure, a computing device for optimizing program and erase voltages of charge trapping memory elements through three-dimensional trap analysis may include a memory and a processor connected to the memory and configured to execute at least one instruction word stored in the memory, wherein the processor may be configured to apply different trap control voltages to the memory elements, measure low-frequency noise of the memory elements corresponding to the trap control voltages, extract trap distributions in the memory elements for the trap control voltages based on the low-frequency noise, and analyze the trap distributions according to the depth of the memory elements to detect a trap control voltage having a maximum trap distribution in a charge trapping layer of the memory elements. [Effects of the Invention]

[0007] The present disclosure can optimize at least one of the program voltage and erase voltage of a charge trap memory element based on frequency analysis and depth analysis. That is, the present disclosure can analyze the trap distribution due to the voltage applied to the charge trap memory element according to depth to detect at least one of the optimal program voltage and erase voltage of the charge trap memory element. As a result, the charge trap memory element can operate based on at least one of the optimal program voltage and erase voltage. This increases the memory window of the charge trap memory element. Furthermore, it can minimize the electrical stress applied to the charge trap memory element during operation, thereby suppressing or preventing degradation of the charge trap memory element. This extends the life of the charge trap memory element and reduces unnecessary power consumption. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram of a computing device according to various embodiments. [Figure 2] FIG. 1 illustrates a schematic diagram of a method of operation of a computing device in accordance with various embodiments. [Figure 3] 3A to 3C are diagrams showing in detail the steps of measuring the low frequency noise in FIG. 2, respectively. [Figure 4] 3 is a diagram showing an example of a three-dimensional graph illustrating the relationship between trap control voltage, trap distribution, and depth, which is expressed in the step of detecting the trap control voltage in FIG. 2. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the present disclosure provides a method and apparatus for optimizing the program / erase voltages of a charge trapping memory device through three-dimensional trap analysis. Generally, a charge trapping memory device includes a substrate having a source electrode, a drain electrode, and a channel region between the source electrode and the drain electrode; a tunnel layer stacked on the channel region to allow charges injected from the channel region to pass; a charge trapping layer stacked on the tunnel layer to trap charges from the tunnel layer; and a gate electrode formed on the charge trapping layer. At least one other component may be added between adjacent components. For example, a blocking layer, e.g., an insulating layer, may be added between the charge trapping layer and the gate electrode. Here, when the tunnel layer and the charge trapping layer or the blocking layer are added, the tunnel layer, the charge trapping layer, and the blocking layer may be referred to as oxide layers. A charge trapping memory device maximizes the memory window by trapping as many charges as possible in the charge trapping layer during a program operation and detrapping as many charges as possible in the charge trapping layer during an erase operation. To maximize the amount of charges trapped in the charge trapping layer, a small trap distribution is required in the interface region between the tunnel layer and the charge trapping layer and in the tunnel layer. However, since the location (depth) of traps in a charge trap memory device varies depending on the applied voltage, this must be strategically analyzed. Therefore, this disclosure proposes a technology for obtaining optimized program / erase voltages through low-frequency noise analysis and depth analysis.

[0010] Various embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0011] FIG. 1 is a schematic diagram of a computing device 100 according to various embodiments.

[0012] 1 , computing device 100 is for optimizing program and erase voltages of charge trapping memory elements through three-dimensional trap analysis and may include at least one of camera module 110, communication module 120, input module 130, output module 140, measurement module 150, memory 160, or processor 170. In some embodiments, at least one of the components of computing device 100 (e.g., camera module 110, communication module 120) may be omitted, and at least one other component may be added. In some embodiments, at least two of the components of computing device 100 may be implemented as a single integrated circuit. In some embodiments, the components of computing device 100 may be distributed across at least two devices, where these devices may be communicatively connected to each other.

[0013] The camera module 110 may capture images in the computing device 100. Here, the camera module 110 may be, but is not limited to, an RGB camera. For example, the camera module 110 may include at least one of a lens, an image sensor, an image signal processor, and a flash.

[0014] The communication module 120 may enable the computing device 100 to communicate with an external device (not shown). The communication module 120 may establish a communication channel between the computing device 100 and the external device and communicate with the external device via the communication channel. For example, the external device may include at least one of an electronic device, a base station, a server, or a satellite. The communication module 120 may include at least one of a wired communication module and a wireless communication module. For example, the wireless communication module may communicate with the external device via at least one of a telecommunications network and a short-range communication network.

[0015] Input module 130 may input instructions for use to at least one component of computing device 100. Input module 130 may include at least one of an input unit configured for a user to directly input instructions or data to computing device 100, or a sensor unit configured to sense the surrounding environment and generate data. For example, the input unit may include at least one of a microphone, a mouse, or a keyboard. In some embodiments, the input unit may include at least one of touch circuitry configured to detect a touch or a sensor circuit configured to measure the intensity of a force generated by a touch.

[0016] Output module 140 may output information external to computing device 100. Output module 140 may include at least one of a display module that visually outputs information or an audio module that audibly outputs information. For example, the display module may include at least one of a display, a holographic device, or a projector. In one embodiment, the display module may be combined with at least one of the touch circuitry or sensor circuitry of input module 130 and implemented as a touch screen. For example, the audio module may include at least one of a speaker or a receiver.

[0017] The measurement module 150 may measure low-frequency noise of the charge trapping memory element, which may include noise generated in the drain current of the charge trapping memory element and noise corresponding to the flat band voltage of the charge trapping memory element.

[0018] Memory 160 may store various data used by at least one component of computing device 100. For example, memory 160 may include volatile memory and / or non-volatile memory. The data may include input data or output data for a program or its associated instructions. The program may be stored in memory 160 as software and may include an operating system, middleware, or / and / or an application.

[0019] The processor 170 may execute programs in the memory 160 and control at least one component of the computing device 100. This allows the processor 170 to process data or perform calculations. In doing so, the processor 170 may execute instructions stored in the memory 160.

[0020] In various embodiments, the processor 170 may determine at least one of an optimal program voltage or an optimal erase voltage for a charge trapping memory element based on a three-dimensional trap analysis. A charge trapping memory element maximizes its memory window by trapping as many charges as possible in the charge trapping layer during a program operation and detrapping as many charges as possible in the charge trapping layer during an erase operation. To maximize the number of charges trapped in the charge trapping layer, the interface between the charge trapping layer and the tunnel layer and the tunnel layer must be thin. Meanwhile, the location (depth) at which traps concentrate within the charge trapping memory element varies depending on the applied voltage. Therefore, the processor 170 may determine at least one of an optimal program voltage or an optimal erase voltage based on a low-frequency noise analysis and a depth analysis.

[0021] Specifically, the processor 170 may apply different trap control voltages to the charge trap memory element via the measurement module 150 to measure the low-frequency noise of the charge trap memory element. The trap control voltages may include different pairs of program and erase voltages, where at least one of the program voltages or the erase voltages may be different from each other. The processor 170 may analyze the low-frequency noise and extract trap distributions in the charge trap memory element for each trap control voltage. The processor 170 may analyze the trap distributions according to the depth of the charge trap memory element and detect a trap control voltage having a maximum trap distribution in the charge trap layer of the charge trap memory element. The detected trap control voltage is optimized for the charge trap memory element and may include at least one of the program voltage or the erase voltage. The charge trap memory element can then operate based on the detected trap control voltage.

[0022] Figure 2 is a diagram that schematically illustrates a method of operation of computing device 100 according to various embodiments. Figure 3 is a diagram that details the step of measuring low-frequency noise (step 220) of Figure 2. Figure 4 is an exemplary diagram that illustrates a three-dimensional graph showing the relationship between trap control voltage, trap distribution, and depth as expressed in the step of detecting trap control voltage (step 240) of Figure 2.

[0023] Referring to FIG. 2 , first, in step 210, the computing device 100 may set parameters for trap analysis of the charge trap memory element. Specifically, the processor 170 may set the parameters based on information input via at least one of the camera module 110, the communication module 120, or the input module 130. In this case, the parameters may include factors extracted from the charge trap memory element and factors applied to the charge trap memory element. Here, the parameters may include temperature conditions and voltage ranges. The voltage range indicates a range between a lower limit and an upper limit to which the trap control voltage belongs, and the voltage range of the program voltage and the voltage range of the erase voltage may be different or the same.

[0024] Next, in step 220, the computing device 100 may apply different trap control voltages to the charge trap memory elements and measure low-frequency noise of the charge trap memory elements corresponding to the trap control voltages. Specifically, the processor 170 may apply different trap control voltages based on set parameters. Here, the processor 170 may determine the trap control voltages within a set voltage range. The trap control voltages may include different pairs of program voltages and erase voltages, and at least one of the program voltages or erase voltages may be different from each other. This allows the processor 170 to measure low-frequency noise of the charge trap memory elements corresponding to the trap control voltages. The low-frequency noise may include noise generated in the drain current of the charge trap memory elements corresponding to the trap control voltages and noise corresponding to the flat band voltage of the charge trap memory elements. This will be described in more detail with reference to FIG. 3.

[0025] 3, first, in step 310, processor 170 may initialize the charge trapping memory device. Specifically, processor 170 may apply an erase voltage to the charge trapping memory device via measurement module 150. The applied erase voltage may detrap charges trapped in the charge trapping memory device. The applied erase voltage may be within or outside the voltage range set in step 210, for example, the upper limit of the voltage range.

[0026] Next, in step 320, processor 170 may select a pair of program voltages and erase voltages. The trap control voltages may include different pairs of program voltages and erase voltages, and at least one of the program voltages or erase voltages may be different from each other. Therefore, processor 170 may select a pair of program voltages and erase voltages by selecting one of the trap control voltages.

[0027] Next, in step 330, processor 170 may apply a selected program voltage to the charge trapping memory element. Specifically, processor 170 may apply the selected program voltage to the charge trapping memory element via measurement module 150. This allows charges to be trapped in the charge trapping memory element by the applied program voltage. Next, in step 340, processor 170 may measure a first low-frequency noise of the charge trapping memory element. Specifically, processor 170 may measure the first low-frequency noise corresponding to the selected program voltage via measurement module 150.

[0028] Next, in step 350, processor 170 may apply a selected erase voltage to the charge trapping memory element. Specifically, processor 170 may apply the selected erase voltage to the charge trapping memory element via measurement module 150. This allows charges to be detrapped in the charge trapping memory element by the applied erase voltage. Next, in step 360, processor 170 may measure a second low-frequency noise of the charge trapping memory element. Specifically, processor 170 may measure the second low-frequency noise corresponding to the selected erase voltage via measurement module 150.

[0029] Next, in step 370, processor 170 may determine whether measurement has been completed for the charge trap memory element. Specifically, processor 170 may determine whether all trap control voltages, i.e., all pairs of program and erase voltages, have been measured. If it is determined in step 370 that measurement has not been completed, processor 170 may select another one of the trap control voltages, i.e., another pair of program and erase voltages, in step 325. Then, processor 170 may return to step 330. In this manner, processor 170 can repeatedly measure the first low-frequency noise and the second low-frequency noise corresponding to all trap control voltages, i.e., all pairs of program and erase voltages. Thus, if it is determined in step 370 that measurement has been completed, processor 170 may proceed to step 230 of FIG. 2.

[0030] 2, in step 230, the computing device 100 may extract trap distributions in the charge trap memory element for each trap control voltage based on the low-frequency noise. Specifically, the processor 170 may extract trap distributions in the trap control memory element for each trap control voltage using normalized power spectrum densities (nPSDs) of the drain current and flat band voltage. In this case, the processor 170 may calculate the trap distributions using the following equation (1):

[0031]

number

[0032] where I D is the drain current, JPEG0007822102000003.jpg77 is the spectral density of noise generated by the drain current, S vfb denotes the noise spectral density corresponding to the flat band voltage, which may be calculated as follows: α denotes the Coulomb scattering coefficient, μ eff is the effective mobility of the charge, Cox is the capacitance of the oxide layer of the charge trapping memory element, and g m may represent the transconductance of the charge trapping memory element.

[0033]

number

[0034] where q is the charge and k B is the Boltzmann constant, T is the absolute temperature, λ is the interface between the charge trapping layer and the tunnel layer and the tunnel distance (depth) of the tunnel layer, and N tmay represent the charge trap density, f the frequency, W the width of the channel region that injects charges into the charge trap layer via the tunnel layer, and L the length of the channel region.

[0035] Finally, in step 240, the computing device 100 may analyze the trap distribution according to the depth of the charge trap memory element and detect a trap control voltage having a maximum trap distribution in the charge trap layer of the charge trap memory element. The detected trap control voltage may be optimized for the charge trap memory element and may include at least one of a program voltage and an erase voltage. Specifically, the processor 170 may analyze the trap distribution according to the depth of the charge trap memory element and determine the depth of the charge trap layer of the charge trap memory element corresponding to each trap control voltage. The processor 170 may calculate the depth of the charge trap memory element using the following equation (3). This allows the processor 170 to determine the relationship between the trap control voltage, trap distribution, and depth. For example, the processor 170 may represent the relationship between the trap control voltage, trap distribution, and depth in a three-dimensional graph, as shown in FIG. 4. This may show the depth of the tunnel layer of the charge trap memory element as a function of the trap control voltage, and the trap distribution at the depth of the charge trap layer. Therefore, the processor 170 can compare the trap distributions at different depths in the charge trapping layer and find the trap control voltage that has the maximum trap distribution in the charge trapping layer.

[0036]

number

[0037] Here, Depth may represent the depth of the charge trapping memory element, λ may represent the interface and tunnel distance between the charge trapping layer and the tunneling layer, f may represent the frequency, and τ may represent the time constant in the interface region between the charge trapping layer and the tunneling layer of the charge trapping memory element.

[0038] More specifically, the processor 170 may extract trap distributions for each program voltage based on the first low-frequency noise. Then, the processor 170 may analyze the trap distributions for each program voltage according to the depth of the charge trapping memory device, and detect a program voltage having a maximum trap distribution in the charge trap layer of the charge trapping memory device. Meanwhile, the processor 170 may extract trap distributions for each erase voltage based on the second low-frequency noise. Then, the processor 170 may analyze the trap distributions for each erase voltage according to the depth of the charge trapping memory device, and detect an erase voltage having a maximum trap distribution in the charge trap layer of the charge trapping memory device.

[0039] According to the present disclosure, the computing device 100 can optimize the program voltage or erase voltage of the charge trapping memory element. That is, the processor 170 can set an optimal program voltage or erase voltage for the charge trapping memory element. This allows the charge trapping memory element to operate based on the optimal program voltage or erase voltage.

[0040] The present disclosure can optimize at least one of the program voltage and erase voltage of a charge trap memory element based on frequency analysis and depth analysis. That is, the present disclosure analyzes the trap distribution due to the voltage applied in the charge trap memory element according to depth and detects at least one of the optimal program voltage and erase voltage of the charge trap memory element. This allows the charge trap memory element to operate based on at least one of the optimal program voltage and erase voltage. This increases the memory window of the charge trap memory element. Furthermore, it can minimize the electrical stress applied to the charge trap memory element during operation, thereby suppressing or preventing degradation of the charge trap memory element. This extends the life of the charge trap memory element and reduces unnecessary power consumption.

[0041] In summary, the present disclosure provides a method of operating a computing device 100 for optimizing program and erase voltages for charge trapping memory elements through three-dimensional trap analysis.

[0042] In the present disclosure, the operating method of the computing device 100 may include the steps of applying different trap control voltages to the charge trap memory elements and measuring the low-frequency noise of the charge trap memory elements corresponding to the trap control voltages (step 220), extracting trap distributions in the charge trap memory elements for the trap control voltages based on the low-frequency noise (step 230), and analyzing the trap distributions according to the depth of the charge trap memory elements to detect the trap control voltage having the maximum trap distribution in the charge trap layer of the charge trap memory element (step 240).

[0043] In the present disclosure, the trap control voltage may include at least one of a program voltage or an erase voltage.

[0044] In the present disclosure, low frequency noise may include noise occurring in the drain current of the charge trapping memory element corresponding to each trap control voltage, and noise corresponding to the flat band voltage of the charge trapping memory element.

[0045] In the present disclosure, the step of detecting the trap control voltage (step 230) may include the steps of analyzing the trap distribution according to the depth of the charge trap memory element, determining the depth of the charge trap layer of the charge trap memory element corresponding to each trap control voltage, and comparing the trap distribution at the depth of the charge trap layer, and detecting the trap control voltage having the maximum trap distribution in the charge trap layer.

[0046] In the present disclosure, the step of extracting the trap distributions (step 230) may extract the trap distributions using the above formulas (1) and (2).

[0047] In the present disclosure, the depth of the charge trapping memory element may be calculated using the above equation (3).

[0048] In the present disclosure, the trap control voltages may include different pairs of program and erase voltages, where at least one of the program or erase voltages is different from each other, and the step of measuring the low frequency noise (step 220) may be performed repeatedly for the pairs.

[0049] In the present disclosure, the step of measuring the low-frequency noise (step 220) includes steps of applying a pair of program voltages to the charge trapping memory element to measure a first low-frequency noise of the charge trapping memory element (steps 330 and 340), and applying a pair of erase voltages to the charge trapping memory element to measure a second low-frequency noise of the charge trapping memory element (steps 350 and 360), where the first low-frequency noise measured from the pair may be used to detect a program voltage having a maximum trap distribution in the charge trapping layer, and the second low-frequency noise measured from the pair may be used to detect an erase voltage having a maximum trap distribution in the charge trapping layer.

[0050] In the present disclosure, the computing device 100 includes a memory 160 and a processor 170 connected to the memory 160 and configured to execute at least one instruction word stored in the memory 160, and the processor 170 may be configured to apply different trap control voltages to the charge trap memory elements, measure low-frequency noise of the charge trap memory elements corresponding to the trap control voltages, extract trap distributions in the charge trap memory elements for the trap control voltages based on the low-frequency noise, analyze the trap distributions according to the depth of the charge trap memory elements, and detect a trap control voltage having a maximum trap distribution in the charge trap layer of the charge trap memory element.

[0051] In the present disclosure, the trap control voltage may include at least one of a program voltage or an erase voltage.

[0052] In the present disclosure, low frequency noise may include noise occurring in the drain current of the charge trapping memory element corresponding to each trap control voltage, and noise corresponding to the flat band voltage of the charge trapping memory element.

[0053] In the present disclosure, the processor 170 may be configured to analyze the trap distribution according to the depth of the charge trapping memory element, determine the depth of the charge trapping layer of the charge trapping memory element corresponding to each trap control voltage, compare the trap distribution at the depth of the charge trapping layer, and detect the trap control voltage having the maximum trap distribution in the charge trapping layer.

[0054] In the present disclosure, the processor 170 may extract the trap distributions using the above equations (1) and (2), respectively.

[0055] In the present disclosure, the processor 170 may use the above equation (3) to calculate the depth of each charge trapping memory element.

[0056] In this disclosure, the trap control voltages may include different pairs of program and erase voltages, where at least one of the program or erase voltages is different from each other, and the processor 170 may be configured to repeatedly measure low frequency noise for the pairs.

[0057] In the present disclosure, the processor 170 may be configured to apply a pair of program voltages to the charge trapping memory element to measure a first low frequency noise of the charge trapping memory element, and apply the pair of erase voltages to the charge trapping memory element to measure a second low frequency noise of the charge trapping memory element, wherein the first low frequency noise measured from the pair may be used to detect a program voltage having a maximum trap distribution in the charge trapping layer, and the second low frequency noise measured from the pair may be used to detect an erase voltage having a maximum trap distribution in the charge trapping layer.

[0058] The above-described devices may be implemented using hardware components, software components, and / or a combination of hardware and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or various devices capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the OS. The processing device may also access, record, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, a single processing device may be described. However, those skilled in the art will understand that a processing device may include multiple processing elements and / or multiple types of processing elements. For example, a processing device may include multiple processors or one processor and one controller. Other processing configurations, such as parallel processors, are also possible.

[0059] Software may include computer programs, codes, instructions, or a combination of one or more of these, which may configure a processing device to operate as desired or may independently or collectively instruct the processing device. The software and / or data may be embodied in any type of machine, component, physical device, computer storage medium, or device to be interpreted by the processing device or to provide instructions or data to the processing device. The software may be distributed and stored and executed in a distributed manner on computer systems connected by a network. The software and data may be stored on one or more computer-readable storage media.

[0060] Methods according to embodiments may be implemented in the form of program instructions executable by various computer means and recorded on a computer-readable medium. In this case, the medium may continuously record a computer-executable program or may temporarily record the program for execution or download. The medium may be various recording or storage means in the form of a single piece of hardware or multiple pieces of hardware combined together. It may be a medium directly connected to a computer system or distributed over a network. Examples of media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and media configured to record program instructions, such as ROMs, RAMs, and flash memories. Other examples of media include recording media or storage media managed by app stores that distribute applications, or by websites or servers that provide or distribute various software.

[0061] The various embodiments described herein and the terminology used therein are not intended to limit the technology described herein to a particular embodiment, but should be understood to encompass various modifications, equivalents, and / or alternatives of the relevant embodiment. In connection with the description of the drawings, like reference numerals are used to refer to like elements. A singular expression may also include a plural expression unless the context clearly dictates otherwise. In this specification, expressions such as "A or B," "at least one of A and / or B," "A, B, or C," or "at least one of A, B, and / or C" may include all possible combinations of the listed items. Expressions such as "first," "second," "first," or "second" modify the corresponding element, regardless of order or importance, and are used merely to distinguish one element from other elements, not to limit the corresponding element. When a (e.g., first) component is described as being "(functionally or communicatively) coupled" or "connected" to another (e.g., second) component, such component may be directly coupled to such other component or may be coupled through another component (e.g., third component).

[0062] According to various embodiments, each of the components described above (e.g., modules or programs) may include one or more entities. According to various embodiments, one or more of the components or steps described above may be omitted, or one or more other components or steps may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in a manner that is the same as or similar to that performed by the corresponding component among the multiple components before integration. According to various embodiments, the steps performed by a module, program, or other component may be performed sequentially, in parallel, iteratively, or heuristically, and one or more of the steps may be performed in a different order, omitted, or one or more other steps may be added. [Explanation of symbols]

[0063] 100 Computing Devices 110 Camera Module 120 Communication Module 130 Input Module 140 Output Module 150 measurement modules 160 memory 170 processors

Claims

1. 1. A method of operating a computing device for optimizing program and erase voltages of charge trapping memory elements through three-dimensional trap analysis, comprising: applying different trap control voltages to the memory elements by a measurement module of a processor of the computing device, and measuring low frequency noises of the memory elements corresponding to the trap control voltages; extracting, by the processor, a trap distribution in the memory element relative to the trap control voltage based on the low frequency noise; analyzing, by the processor, the trap distribution as a function of depth in the memory element to determine a target trap control voltage having a maximum trap distribution in a charge trapping layer of the memory element; Including, the low-frequency noise includes noise generated in a drain current of the memory device and noise corresponding to a flat band voltage of the memory device, each of which corresponds to the trap control voltage; The step of extracting the trap distribution includes: extracting the trap distribution in the memory element for each of the trap control voltages using a noise spectral density generated in the drain current and a noise spectral density corresponding to a flat band voltage; determining the target trap control voltage comprises: determining a trap distribution corresponding to a depth belonging to the charge trap layer for each of the trap control voltages based on a relationship between the trap distribution and a depth belonging to the charge trap layer; determining, as the target trap control voltage, a trap control voltage having the maximum trap distribution among the trap control voltages based on a result of comparing the trap distribution according to the depth belonging to the charge trap layer among the trap control voltages; Including, A method of operating a computing device.

2. the target trap control voltage comprises at least one of a program voltage or an erase voltage; 10. A method of operating a computing device as claimed in claim 1.

3. The step of extracting the trap distribution includes: The trap distribution is extracted using the following formula: 、 Here, I Ｄ is the drain current, is the spectral density of the noise generated in the drain current, S ｖｆｂ is the noise spectral density corresponding to the flatband voltage, α is the Coulomb scattering coefficient, μ ｅｆｆ is the effective mobility of the charge, Cox is the capacitance of the oxide layer of the memory element, g ｍ is the transconductance of the memory element, q is the charge amount, and k Ｂ is the Boltzmann constant, T is the absolute temperature, λ is the interface between the charge trapping layer and the tunnel layer and the tunnel distance of the tunnel layer, and N ｔ represents the charge trap density, f represents the frequency, W represents the width of the channel region into which charges are injected into the charge trap layer, and L represents the length of the channel region.

10. A method of operating a computing device as claimed in claim 1.

4. The depth of the memory element is calculated using the following formula: where Depth is the depth of the memory element, λ is the interface between the charge trapping layer and the tunnel layer and the tunnel distance of the tunnel layer, f is the frequency, and τ ０ denotes a time constant at an interface region between the charge trapping layer and the tunnel layer of the memory element; 10. A method of operating a computing device as claimed in claim 1.

5. the trap control voltages include different pairs of program voltages and erase voltages, and at least one of the program voltages or erase voltages is different from each other; The step of measuring each of the low frequency noises comprises: Iteratively performed on the pairs, 10. A method of operating a computing device as claimed in claim 1.

6. The step of measuring each of the low frequency noises comprises: applying a pair of program voltages to the memory device and measuring a first low frequency noise of the memory device; applying the pair of erase voltages to the memory device and measuring a second low frequency noise of the memory device; Including, a first low frequency noise measured from the pair is utilized to detect a program voltage having a maximum trap distribution in the charge trapping layer; a second low frequency noise measured from the pair is utilized to detect an erase voltage having a maximum trap distribution in the charge trapping layer; 6. A method of operating a computing device as claimed in claim 5.

7. 1. A computing device for optimizing program and erase voltages of charge trapping memory devices by three-dimensional trap analysis, comprising: Memory and a processor coupled to the memory and configured to execute at least one instruction stored in the memory; Including, The processor: A measurement module applies different trap control voltages to the memory device, and measures low-frequency noises of the memory device corresponding to the trap control voltages; extracting a trap distribution in the memory element for each of the trap control voltages based on the low frequency noise; configured to analyze the trap distribution according to depth of the memory element to find a target trap control voltage having a maximum trap distribution in a charge trapping layer of the memory element; the low-frequency noise includes noise generated in a drain current of the memory device and noise corresponding to a flat band voltage of the memory device, each of which corresponds to the trap control voltage; The processor, in extracting the trap distribution, extracting the trap distribution in the memory element for each of the trap control voltages using a noise spectral density generated in the drain current and a noise spectral density corresponding to a flat band voltage; The processor, in determining the target trap control voltage, determining the trap distribution according to the depth belonging to the charge trap layer for each of the trap control voltages based on the relationship between the trap distribution and the depth belonging to the charge trap layer; determining, as the target trap control voltage, a trap control voltage having the maximum trap distribution from among the trap control voltages based on a result of comparing the trap distribution according to the depth belonging to the charge trap layer among the trap control voltages; Computing equipment.

8. the target trap control voltage comprises at least one of a program voltage or an erase voltage; The computing device of claim 7.

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