Power Conversion Device

Abstract

To provide a power conversion device capable of realizing controls that promptly deal with abnormalities even when abnormalities occur in a power conversion circuit.SOLUTION: A power conversion device (100) comprises: a drive circuit (6) that performs switching control of semiconductor switching elements; short circuit control means (7) that performs short circuit control of a power conversion circuit; overcurrent detection means (50) that detects presence or absence of abnormalities caused by an overcurrent of the semiconductor switching elements; and gate drive abnormality detection means (60) that detects presence or absence of abnormalities in gate voltage of the semiconductor switching elements. The short circuit control means (7) is configured to perform the short circuit control by turning ON all semiconductor switching elements of at least one of an upper arm and a lower arm on the basis of abnormality detection results by the overcurrent detection means (50) and abnormality detection results by the gate drive abnormality detection means (60).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present application relates to a power conversion device. [Background technology]

[0002] Electric vehicles using AC motors as drive power sources have been known for some time. When the electric vehicle is traveling, the AC motor operates in power running mode to generate drive torque to drive the electric vehicle, and when the electric vehicle is braking, the AC motor operates in regenerative mode to generate regenerative braking torque. The drive system of such electric vehicles includes a DC power supply using a secondary battery such as a lithium-ion battery, a power conversion device including a capacitor and multiple semiconductor switching elements, and an AC motor as a load connected to the power conversion device.

[0003] When an AC motor is powered, the power conversion device in an electric vehicle operates as an inverter that converts DC power to AC power, and controls the switching of multiple semiconductor switching elements at a predetermined switching frequency to convert the DC power into predetermined AC power and supply it to the AC motor. The AC motor is powered based on the AC power supplied from the inverter, and its torque, rotation speed, etc. are controlled to drive the electric vehicle.

[0004] On the other hand, when the AC motor is operated in regenerative mode, the power conversion device operates as a converter that converts AC power into DC power, and by controlling the switching of multiple semiconductor switching elements of the power conversion device at a predetermined switching frequency, the AC power generated by the regenerative operation of the AC motor is converted into predetermined DC power and supplied to the DC power source.

[0005] The AC motors used in electric vehicles are generally permanent magnet three-phase synchronous motors with good operating efficiency. In the drive system of an electric vehicle using a three-phase synchronous motor, the power conversion device is configured as a three-phase bridge circuit, which includes three series circuits in which upper-arm semiconductor switching elements and lower-arm semiconductor switching elements are connected in series, corresponding to the U-phase, V-phase, and W-phase, and these series circuits are each connected in parallel to a DC power source. The connection points between the upper-arm semiconductor switching elements and the lower-arm semiconductor switching elements, which serve as the midpoints of each of the three series circuits of the power conversion device, are connected to the armature windings of the U-phase, V-phase, and W-phase of the three-phase synchronous motor.

[0006] In the power conversion device configured as described above, the upper arm semiconductor switching elements and lower arm semiconductor switching elements provided corresponding to the U phase, V phase, and W phase are switched and controlled at predetermined timing, thereby supplying AC power having a phase difference of 120 electrical degrees to the armature windings of the U phase, V phase, and W phase of the three-phase synchronous motor, thereby driving the three-phase synchronous motor.

[0007] In the drive system of an electric vehicle, a switching device is provided to disconnect the battery, which is a DC power source, from the power conversion device as needed to protect the battery from overvoltage and overcurrent. The conditions for opening the switching device include when the battery voltage exceeds a predetermined value during regenerative operation of the AC motor, when the battery voltage falls below a predetermined value due to battery depletion, or when the current flowing through the battery exceeds a predetermined value. The switching device may also be opened due to a vehicle malfunction or collision.

[0008] However, in the case of the above-mentioned conventional technology, when all of the semiconductor switching elements of the upper arms or lower arms of the U phase, V phase, and W phase of the power conversion device are turned on to perform fail-safe operation by three-phase short-circuit control, if an abnormality such as a stuck short circuit or stuck open occurs in the semiconductor switching element of the arm opposite to the arm whose semiconductor switching element is turned on, there is a problem in that three-phase short-circuit control cannot be performed.

[0009] That is, in an inverter serving as a power conversion device, when three-phase short-circuit control is performed by turning on the semiconductor switching elements of the upper or lower arms of all phases, if an abnormality such as a stuck short or stuck open occurs in the semiconductor switching element of the arm opposite to the arm of the semiconductor switching element that is turned on, a short circuit between the upper arm and the lower arm may occur, leading to a secondary failure. Therefore, from the viewpoint of protecting the driver particularly in an emergency such as a vehicle collision, it is necessary to reliably perform three-phase short-circuit control even if a failure occurs in the semiconductor switching element of any arm of the power conversion device.

[0010] In the drive system of an electric vehicle as described above, the switching device may be opened during regenerative operation of the AC motor, disconnecting the DC power supply from the power conversion device. Even in a system that does not include a switching device, the power conversion device may be disconnected from the DC power supply due to a break in the power line between the DC power supply and the power conversion device. Furthermore, in an electric vehicle drive system, if the rotor of the AC motor is forcibly driven by an external factor, the regenerative power flowing from the AC motor to the inverter cannot be used to charge the battery, which could result in the AC motor spinning, unwanted torque, and other problems that could disrupt vehicle behavior.

[0011] In the past, in order to protect the driver by preventing disturbances in vehicle behavior due to the AC motor's freewheeling, generation of unnecessary torque, etc., a so-called fail-safe operation has been performed by performing three-phase short-circuit control of the power conversion device, reducing the rotation speed of the AC motor and reducing the voltage of the DC power supply connected to the power conversion device to a normal value. However, in order to perform the fail-safe operation by three-phase short-circuit control, it is necessary to determine whether the semiconductor switching elements are stuck short-circuited or stuck open, as described above.

[0012] Conventionally, power conversion devices have provided DESAT, OC, and the like in drive circuits that drive semiconductor switching elements as overcurrent detection or overcurrent protection means. DESAT detects overcurrents, such as short circuits in semiconductor switching elements, and protects the semiconductor switching elements by cutting off the gate voltage, while OC detects overcurrents and cuts off the circuit. However, because overcurrent detection means such as DESAT and OC instantaneously detect overcurrents, such as short circuits, and cut off the gate voltage of the semiconductor switching elements, they are unable to determine whether the semiconductor switching elements are stuck shorted or stuck open.

[0013] For this reason, in the case of anomaly detection functions such as DESAT and OC, it is possible to identify the leg (series circuit of upper arm and lower arm) in which the abnormality occurred, but it is not possible to identify whether the abnormality occurred in the upper arm or the lower arm, nor is it possible to determine whether the abnormality is transient or persistent, such as a semiconductor switching element being stuck short or stuck open.

[0014] Furthermore, other abnormality detection functions in the drive circuit of the semiconductor switching element, such as the function of monitoring abnormalities in the gate voltage using gate drive abnormality detection means, can detect whether the gate voltage is abnormal or normal, but cannot determine whether the semiconductor switching element of the target arm is fixed short-circuited or fixed open.

[0015] Therefore, in the drive system for a permanent magnet synchronous motor disclosed in Patent Document 1, it is proposed that the control device that generates drive signals for driving the semiconductor switching elements that make up the inverter be equipped with a first function for detecting an abnormality in the inverter, a second function for detecting the output current of each phase of the inverter, and a third function for generating drive signals that perform short-circuit control by turning on the semiconductor switching elements of the upper arms or lower arms of all phases while avoiding short-circuiting the upper and lower arms of the inverter, depending on the balance state of the output current of each phase detected by the second function, in order to short-circuit the stator windings of the permanent magnet synchronous motor when an abnormality is detected by the first function.

[0016] According to Patent Document 1, as shown in FIG. 3 thereof, in order to prevent secondary failures such as a short circuit between the upper arm and the lower arm during short circuit control, the presence or absence of an abnormality due to a fixed short circuit or a fixed open circuit in the semiconductor switching elements of the upper arm and the semiconductor switching elements of the lower arm is checked sequentially based on the balance state of the output current of each phase, and while identifying the location where an abnormality such as a short circuit failure or an open circuit failure has occurred in the semiconductor switching elements that make up the inverter, short circuit control is performed on the windings of the synchronous motor, and a fail-safe operation is performed to perform evacuation operations.

[0017] According to the conventional technology disclosed in Patent Document 1, software processing by a microcomputer or the like is required to determine an abnormality such as a stuck short circuit or stuck open circuit as shown in Fig. 3. However, in order to quickly transition the vehicle to an evacuation driving state, it is necessary to quickly transition to a fail-safe state while avoiding secondary failures such as a short circuit between the upper and lower arms of the inverter as a power conversion device, and when three-phase short-circuit control is performed using software processing by a microcomputer as in the technology disclosed in Patent Document 1, there is an issue in that there is a delay in transitioning to the fail-safe state after the detection of the occurrence of an abnormality.

[0018] In particular, according to the conventional technology disclosed in Patent Document 1, it is not possible to determine whether an abnormality such as a short circuit or an open circuit is present unless the current of each phase is observed for a while, which poses the problem that it takes time to control the inverter to transition the vehicle into an evacuation driving state.

[0019] Furthermore, according to the conventional technology disclosed in Patent Document 1, the transition time from the detection of an abnormality to transitioning the vehicle to an evacuation driving state must be factored into the system design, resulting in a trade-off between cost and responsiveness. For example, during three-phase short-circuit control, the phase currents gradually offset, so the busbar shape must be designed to be larger to take into account the phase current offset. Alternatively, to improve responsiveness, a dedicated microcomputer for three-phase short-circuit control must be added, which increases the cost of the product.

[0020] Furthermore, from the viewpoint of product performance, according to the conventional technology disclosed in Patent Document 1, the response time from identifying the location of a semiconductor switching element in the upper arm or lower arm that is stuck short-circuited or stuck open to fail-safe operation is long, so the current sensor observation range must be widened to take into account offsets due to phase current imbalance, which could result in a decrease in sensor resolution or deterioration in accuracy. [Prior art documents] [Patent documents]

[0021] [Patent Document 1] Japanese Patent Publication No. 2020-65341 Summary of the Invention [Problem to be solved by the invention]

[0022] The present application discloses a technique for solving the above-mentioned problems, and aims to provide a power conversion device that realizes control that quickly responds to an abnormality even if an abnormality occurs in a power conversion circuit. [Means for solving the problem]

[0023] The power conversion device disclosed in the present application comprises: a power conversion circuit in which a plurality of series circuits, each of which connects upper arm semiconductor switching elements and lower arm semiconductor switching elements in series, are connected in parallel to one another, a parallel connection portion of the plurality of series circuits is connected to a DC power source, a series connection portion of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits is connected to an armature winding of an AC motor, and which performs power conversion between the DC power source and the AC motor by switching control of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits; a drive circuit that applies gate drive signals to the upper arm semiconductor switching elements and the lower arm semiconductor switching elements to perform the switching control; a short-circuit control means for turning on all of the semiconductor switching elements of either the upper arm or the lower arm in the plurality of series circuits to perform short-circuit control of the power conversion circuit; an overcurrent detection means for detecting whether or not there is an abnormality due to an overcurrent in the semiconductor switching elements of the upper arm and the lower arm; a gate drive abnormality detection means for detecting whether or not there is an abnormality in the gate voltage of the semiconductor switching element of the upper arm and the semiconductor switching element of the lower arm; Equipped with The short circuit control means The short-circuit control is performed by turning on all of the semiconductor switching elements of either the upper arm or the lower arm based on the detection result of the abnormality by the overcurrent detection means and the detection result of the abnormality by the gate drive abnormality detection means. A power conversion device comprising: When the detection result by the overcurrent detection means indicates an abnormality in one or both of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements, and the detection result by the gate drive abnormality detection means indicates an abnormality in one of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements, the short circuit control means is configured to perform the short circuit control by a semiconductor switching element of an arm on which an abnormality is detected by the gate drive abnormality detection means. It is characterized by: Further, the power conversion device disclosed in the present application is a power conversion circuit in which a plurality of series circuits, each of which connects upper arm semiconductor switching elements and lower arm semiconductor switching elements in series, are connected in parallel to one another, a parallel connection portion of the plurality of series circuits is connected to a DC power source, a series connection portion of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits is connected to an armature winding of an AC motor, and which performs power conversion between the DC power source and the AC motor by switching control of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits; a drive circuit that applies gate drive signals to the upper arm semiconductor switching elements and the lower arm semiconductor switching elements to perform the switching control; a short-circuit control means for turning on all of the semiconductor switching elements of either the upper arm or the lower arm in the plurality of series circuits to perform short-circuit control of the power conversion circuit; an overcurrent detection means for detecting whether or not there is an abnormality due to an overcurrent in the semiconductor switching elements of the upper arm and the lower arm; a gate drive abnormality detection means for detecting whether or not there is an abnormality in the gate voltage of the semiconductor switching element of the upper arm and the semiconductor switching element of the lower arm; Equipped with The short circuit control means a power conversion device configured to perform the short-circuit control by turning on all semiconductor switching elements of either the upper arm or the lower arm based on a detection result of the abnormality by the overcurrent detection means and a detection result of the abnormality by the gate drive abnormality detection means, When only the detection result by the gate drive abnormality detection means is abnormal, the short circuit control means is configured to perform the short circuit control by a semiconductor switching element of an arm opposite to the arm on which the gate drive abnormality detection means detects the abnormality. It is characterized by: Furthermore, the power conversion device disclosed in the present application is a power conversion circuit in which a plurality of series circuits, each of which connects upper arm semiconductor switching elements and lower arm semiconductor switching elements in series, are connected in parallel to one another, a parallel connection portion of the plurality of series circuits is connected to a DC power source, a series connection portion of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits is connected to an armature winding of an AC motor, and which performs power conversion between the DC power source and the AC motor by switching control of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits; a drive circuit that applies gate drive signals to the upper arm semiconductor switching elements and the lower arm semiconductor switching elements to perform the switching control; a short-circuit control means for turning on all of the semiconductor switching elements of either the upper arm or the lower arm in the plurality of series circuits to perform short-circuit control of the power conversion circuit; an overcurrent detection means for detecting whether or not there is an abnormality due to an overcurrent in the semiconductor switching elements of the upper arm and the lower arm; a gate drive abnormality detection means for detecting whether or not there is an abnormality in the gate voltage of the semiconductor switching element of the upper arm and the semiconductor switching element of the lower arm; Equipped with The short circuit control means a power conversion device configured to perform the short-circuit control by turning on all semiconductor switching elements of either the upper arm or the lower arm based on a detection result of the abnormality by the overcurrent detection means and a detection result of the abnormality by the gate drive abnormality detection means, When only the detection result by the overcurrent detection means is abnormal, The short circuit control means is configured to perform the short circuit control by a semiconductor switching element of an arm opposite to the arm on which the overcurrent detection means detects the abnormality. Characterized by . [Effects of the Invention]

[0024] According to the power conversion device disclosed in the present application, even if an abnormality occurs in the power conversion circuit, a power conversion device can be obtained that realizes control to quickly deal with the abnormality. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a configuration diagram showing the overall configuration of a power conversion device according to a first embodiment. [Figure 2] 1 is a configuration diagram showing the configuration of a part of a power conversion device according to a first embodiment. [Figure 3] 2 is a configuration diagram showing the configuration of the relationship between the semiconductor switching elements and drive circuits of the U-phase upper arm and the U-phase lower arm in the power conversion device according to the first embodiment. FIG. [Figure 4] 3 is an explanatory diagram showing the relationship between an output signal of a logic circuit unit, a gate voltage, and gate control in the power conversion device according to the first embodiment. FIG. [Figure 5] 4 is a waveform diagram showing the operation of the power conversion device according to the first embodiment when a Hi lock occurs in the U-phase lower arm. FIG. [Figure 6] 4 is a waveform diagram showing the operation of the power conversion device according to the first embodiment when a Lo lock occurs in the U-phase lower arm. FIG. [Figure 7] 4 is a waveform diagram showing the operation of the power conversion device according to the first embodiment when a short-circuit fault occurs in the U-phase lower arm. FIG. [Figure 8] 4 is a waveform diagram showing the operation of the power conversion device according to the first embodiment when an open fault occurs in the U-phase lower arm. FIG. [Figure 9] 3 is an explanatory diagram showing the relationship between input signals, output signals, and gate control of a logic circuit unit in the power conversion device according to the first embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0026] A power conversion device according to a first embodiment will be described below with reference to the drawings. In the following description, identical or corresponding parts are designated by the same reference numerals. The power conversion device according to the first embodiment is configured to drive, by a power conversion circuit, an AC motor for driving an electric vehicle, such as a permanent magnet three-phase synchronous motor, but in the following description, the permanent magnet three-phase synchronous motor will be simply referred to as an AC motor.

[0027] Embodiment 1 Fig. 1 is a configuration diagram showing the overall configuration of a power conversion device according to embodiment 1. In Fig. 1, a power conversion device 100 includes a power conversion circuit 3, a drive circuit 6, short-circuit control means 7, overcurrent detection means 50, gate drive abnormality detection means 60, a microprocessor (hereinafter referred to as a microcomputer) 9, and a smoothing capacitor 8 as a power storage circuit.

[0028] Smoothing capacitor 8 is composed of a film capacitor or the like. Its purpose is to store the power supplied from DC power supply 1 and smooth the voltage and current by suppressing ripples caused by the inverter operation of power conversion circuit 3. Smoothing capacitor 8 also temporarily stores the regenerative energy generated by AC motor 2 and regenerates it to DC power supply 1.

[0029] The power conversion circuit 3 is connected between the DC power supply 1 and the AC motor 2. The power conversion circuit 3 is configured as a three-phase bridge circuit, and includes a semiconductor switching element Qup of a U-phase upper arm, a semiconductor switching element Qun of a U-phase lower arm, a semiconductor switching element Qvp of a V-phase upper arm, a semiconductor switching element Qvn of a V-phase lower arm, a semiconductor switching element Qwp of a W-phase upper arm, and a semiconductor switching element Qwn of a W-phase lower arm.

[0030] Here, the semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn are composed of wide-gap semiconductors such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), or SiC-MOSFETs (Silicon Carbide MOSFETs) and GaN (Gallium Nitride).

[0031] The semiconductor switching element Qup of the U-phase upper arm and the semiconductor switching element Qun of the U-phase lower arm are connected in series to each other by a series connection part 31 to form a U-phase series circuit, the semiconductor switching element Qvp of the V-phase upper arm and the semiconductor switching element Qvn of the V-phase lower arm are connected in series to each other by a series connection part 32 to form a V-phase series circuit, and the semiconductor switching element Qwp of the W-phase upper arm and the semiconductor switching element Qwn of the W-phase lower arm are connected in series to each other by a series connection part 33 to form a W-phase series circuit.

[0032] The U-phase series circuit, V-phase series circuit, and W-phase series circuit are connected in parallel with one another, with a positive terminal 3P of the power conversion circuit 3 connected to one parallel connection 34 and a negative terminal 3N of the power conversion circuit 3 connected to the other parallel connection 35. The positive terminal 3P is connected to the positive electrode of the DC power supply 1, and the negative terminal 3N is connected to the negative electrode of the DC power supply 1. A smoothing capacitor 8 serving as a storage circuit is connected between the positive terminal 3P and the negative terminal 3N of the power conversion circuit 3. The DC power supply 1 is formed by a high-voltage lithium-ion battery or the like mounted on an electric vehicle, and applies a DC voltage of approximately 200 V to 800 V between the positive terminal 3P and the negative terminal 3N.

[0033] In the power conversion circuit 3, a series connection 31 between the semiconductor switching element Qup of the U-phase upper arm and the semiconductor switching element Qun of the U-phase lower arm is connected to the U-phase armature winding 2U of the AC motor 2, a series connection 32 between the semiconductor switching element Qvp of the V-phase upper arm and the semiconductor switching element Qvn of the V-phase lower arm is connected to the V-phase armature winding 2V of the AC motor 2, and a series connection 33 between the semiconductor switching element Qwp of the W-phase upper arm and the semiconductor switching element Qwn of the W-phase lower arm is connected to the W-phase armature winding 2W of the AC motor 2.

[0034] The driver circuit unit 17 provided in the drive circuit 6 generates a gate drive signal 171 based on the PWM control signal 10 input from the microcomputer 9, and supplies the signal to the gates of the semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn of the power conversion circuit 3, thereby controlling the switching of these semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn.

[0035] Here, the driver circuit unit 17 in the drive circuit 6 has an insulating function, and turns on or off the semiconductor switching element of the target arm depending on the H level (high level) or L level (low level) state of a PWM control signal 10 as an input signal to the drive circuit 6 from the low-voltage side, which is the side of a 12V low-voltage power supply generated by a step-down converter from a low-voltage lead battery or a high-voltage battery as a second power supply (not shown) and the reference potential of the microcomputer 9. In other words, the drive circuit 6 turns on the semiconductor switching element when the PWM control signal 10 is H level, and turns off the semiconductor switching element when the PWM control signal 10 is Lo.

[0036] The semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn are switched by PWM control based on the gate drive signal 171, and perform power conversion between the DC power supply 1 and the armature windings 2U, 2V, and 2W of each phase of the AC motor 2.

[0037] When AC motor 2 is in power running mode, power conversion circuit 3 is operated as an inverter to supply AC power with a phase difference of 120° electrical angle to U-phase, V-phase, and W-phase armature windings 2U, 2V, and 2W of AC motor 2. When AC motor 2 is in regenerative running mode, power conversion circuit 3 is operated as a converter to convert the AC power with a phase difference of 120° electrical angle generated in U-phase, V-phase, and W-phase armature windings 2U, 2V, and 2W of AC motor 2 into DC power and supply it to DC power source 1 via smoothing capacitor 8.

[0038] The drive circuit 6 also includes an overcurrent detection means 50 and a gate drive abnormality detection means 60. The overcurrent detection means 50 uses a DESAT (non-saturation) detection unit, and the output of the DESAT detection unit will be referred to as a DESAT signal in the following description. The overcurrent detection means 50 detects whether or not an abnormality due to an overcurrent has occurred in each of the semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn, based on the DESAT signal 36 from each of the semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn.

[0039] That is, when the overcurrent detection means 50 detects an abnormality due to an overcurrent in the semiconductor switching element Qup of the U-phase upper arm based on the DESAT signal 36, it outputs a U-phase upper arm overcurrent abnormality detection signal 50up; when it detects an abnormality due to an overcurrent in the semiconductor switching element Qvp of the V-phase upper arm, it outputs a V-phase upper arm overcurrent abnormality detection signal 50vp; and when it detects an abnormality due to an overcurrent in the semiconductor switching element Qwp of the W-phase upper arm, it outputs a W-phase upper arm overcurrent abnormality detection signal 50wp.

[0040] Furthermore, when the overcurrent detection means 50 detects an abnormality due to an overcurrent in the semiconductor switching element Qun of the U-phase lower arm based on the DESAT signal 36, it outputs a U-phase lower arm overcurrent abnormality detection signal 50un; when it detects an abnormality due to an overcurrent in the semiconductor switching element Qvn of the V-phase lower arm, it outputs a V-phase lower arm overcurrent abnormality detection signal 50vn; and when it detects an abnormality due to an overcurrent in the semiconductor switching element Qwn of the W-phase lower arm, it outputs a W-phase lower arm overcurrent abnormality detection signal 50wn.

[0041] The gate drive abnormality detection means 60 detects whether or not there is an abnormality in the gate voltage applied to each of the semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn, based on a gate voltage detection signal 37 from a gate voltage monitoring unit (described later) that monitors the gate voltage of each of the semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn.

[0042] When gate drive abnormality detection means 60 detects an abnormality in the gate voltage applied to semiconductor switching element Qup of the U-phase upper arm based on gate voltage detection signal 37, it outputs U-phase upper arm gate drive abnormality detection signal 60up; when it detects an abnormality in the gate voltage applied to semiconductor switching element Qvp of the V-phase upper arm, it outputs V-phase upper arm gate drive abnormality detection signal 60vp; and when it detects an abnormality in the gate voltage applied to semiconductor switching element Qwp of the W-phase upper arm, it outputs W-phase upper arm gate drive abnormality detection signal 60wp.

[0043] Furthermore, when gate drive abnormality detection means 60 detects an abnormality in the gate voltage to semiconductor switching element Qun of the U-phase lower arm based on gate voltage detection signal 37, it outputs U-phase lower arm gate drive abnormality detection signal 60un; when it detects an abnormality in the gate voltage to semiconductor switching element Qvn of the V-phase lower arm, it outputs V-phase lower arm gate drive abnormality detection signal 60vn; and when it detects an abnormality in the gate voltage to semiconductor switching element Qwn of the W-phase lower arm, it outputs W-phase lower arm gate drive abnormality detection signal 60wn.

[0044] In the first embodiment, the short circuit control means 7 is configured by an ASC (Active Short Circuit), and receives as inputs from the overcurrent detection means 50 a U-phase upper arm overcurrent abnormality detection signal 50up, a V-phase upper arm overcurrent abnormality detection signal 50vp, a W-phase upper arm overcurrent abnormality detection signal 50wp, a U-phase lower arm overcurrent abnormality detection signal 50un, a V-phase lower arm overcurrent abnormality detection signal 50vn, and a W-phase lower arm overcurrent abnormality detection signal 50wn.

[0045] In addition, the short-circuit control means 7 receives as inputs from the gate drive abnormality detection means 60 a U-phase upper arm gate drive abnormality detection signal 60up, a V-phase upper arm gate drive abnormality detection signal 60vp, a W-phase upper arm gate drive abnormality detection signal 60wp, a U-phase lower arm gate drive abnormality detection signal 60un, a V-phase lower arm gate drive abnormality detection signal 60vn, and a W-phase lower arm gate drive abnormality detection signal 60wn.

[0046] As will be described later, the short circuit control means 7 is configured to determine which of the upper and lower arms in the power conversion circuit 3 the semiconductor switching elements of which arm should be turned on to perform short circuit control, based on the overcurrent abnormality detection signal from the overcurrent detection means 50 and the gate drive abnormality detection signal from the gate drive abnormality detection means 60, and to perform short circuit control of the power conversion circuit 3 based on the determination.

[0047] Next, a detailed description will be given of the configuration of the drive circuit 6 and the short-circuit control means 7. Fig. 2 is a configuration diagram showing the configuration of a part of the power conversion device according to the first embodiment, and shows the configuration details of the drive circuit 6 and the short-circuit control means 7.

[0048] In FIG. 2, the DESAT signal 36 is a general term that includes a U-phase upper-arm DESAT signal 36up, a U-phase lower-arm DESAT signal 36un, a V-phase upper-arm DESAT signal 36vp, a V-phase lower-arm DESAT signal 36vn, a W-phase upper-arm DESAT signal 36wp, and a W-phase lower-arm DESAT signal 36wn.

[0049] Gate voltage detection signal 37 is a general term that includes U-phase upper arm gate voltage detection signal 37up, U-phase lower arm gate voltage detection signal 37un, V-phase upper arm gate voltage detection signal 37vp, V-phase lower arm gate voltage detection signal 37vn, W-phase upper arm gate voltage detection signal 37wp, and W-phase lower arm gate voltage detection signal 37wn.

[0050] Furthermore, gate drive signal 171 is a general term that encompasses U-phase upper arm gate drive signal 171up, U-phase lower arm gate drive signal 171un, V-phase upper arm gate drive signal 171vp, V-phase lower arm gate drive signal 171vn, W-phase upper arm gate drive signal 171wp, and W-phase lower arm gate drive signal 171wn.

[0051] Furthermore, PWM control signal 10 is a collective term that includes the U-phase upper arm PWM control signal PWM-up, the U-phase lower arm PWM control signal PWM-un, the V-phase upper arm PWM control signal PWM-vp, the V-phase lower arm PWM control signal PWM-vn, the W-phase upper arm PWM control signal PWM-wp, and the W-phase lower arm PWM control signal PWM-wn.

[0052] Drive circuit 6 is composed of a U-phase upper arm drive circuit 61, a U-phase lower arm drive circuit 62, a V-phase upper arm drive circuit 63, a V-phase lower arm drive circuit 64, a W-phase upper arm drive circuit 65, and a W-phase lower arm drive circuit 66, and each drive circuit is provided with the above-mentioned driver circuit unit 17, overcurrent detection means 50, and gate drive abnormality detection means 60.

[0053] The U-phase upper arm drive circuit 61, the U-phase lower arm drive circuit 62, the V-phase upper arm drive circuit 63, the V-phase lower arm drive circuit 64, the W-phase upper arm drive circuit 65 and the W-phase lower arm drive circuit 66 each include a PWM input unit to which a PWM control signal 10 is input, an ASC1 input unit to which a first ASC signal ASC1 described below from the short-circuit control means 7 is input, and an ASC2 input unit to which a second ASC signal ASC2 described below from the short-circuit control means 7 is input.

[0054] U-phase upper arm drive circuit 61 generates U-phase upper arm gate drive signal 171up based on U-phase upper arm PWM control signal PWM-up from microcomputer 9 input to its PWM input section, and provides this signal to the gate of semiconductor switching element Qup in the U-phase upper arm of power conversion circuit 3. U-phase lower arm drive circuit 62 generates U-phase lower arm gate drive signal 171un based on U-phase lower arm PWM control signal PWM-un from microcomputer 9 input to its PWM input section, and provides this signal to the gate of semiconductor switching element Qun in the U-phase lower arm of power conversion circuit 3.

[0055] U-phase upper arm drive circuit 61 outputs U-phase upper arm overcurrent abnormality detection signal 50up based on input U-phase upper arm DESAT signal 36up, and outputs U-phase upper arm gate drive abnormality detection signal 60up based on input U-phase upper arm gate voltage detection signal 37up. U-phase lower arm drive circuit 62 outputs U-phase lower arm overcurrent abnormality detection signal 50un based on input U-phase lower arm DESAT signal 36un, and outputs U-phase lower arm gate drive abnormality detection signal 60un based on input U-phase lower arm gate voltage detection signal 37un.

[0056] V-phase upper arm drive circuit 63 generates V-phase upper arm gate drive signal 171vp based on V-phase upper arm PWM control signal PWM-vp from microcomputer 9 input to its PWM input section, and provides this signal to the gate of semiconductor switching element Qvp of the V-phase upper arm of power conversion circuit 3. V-phase lower arm drive circuit 64 generates V-phase lower arm gate drive signal 171vn based on V-phase lower arm PWM control signal PWM-vn from microcomputer 9 input to its PWM input section, and provides this signal to the gate of semiconductor switching element Qvn of the V-phase lower arm of power conversion circuit 3.

[0057] V-phase upper arm drive circuit 63 outputs V-phase upper arm overcurrent abnormality detection signal 50vp based on input V-phase upper arm DESAT signal 36vp, and outputs V-phase upper arm gate drive abnormality detection signal 60vp based on input V-phase upper arm gate voltage detection signal 37vp. V-phase lower arm drive circuit 64 outputs V-phase lower arm overcurrent abnormality detection signal 50vn based on input V-phase lower arm DESAT signal 36vn, and outputs V-phase lower arm gate drive abnormality detection signal 60vn based on input V-phase lower arm gate voltage detection signal 37vn.

[0058] W-phase upper arm drive circuit 65 generates W-phase upper arm gate drive signal 171wp based on W-phase upper arm PWM control signal PWM-wp from microcomputer 9 input to its PWM input section, and provides this signal to the gate of semiconductor switching element Qwp of the W-phase upper arm of power conversion circuit 3. W-phase lower arm drive circuit 66 generates W-phase lower arm gate drive signal 171wn based on W-phase lower arm PWM control signal PWM-wn from microcomputer 9 input to its PWM input section, and provides this signal to the gate of semiconductor switching element Qwn of the W-phase lower arm of power conversion circuit 3.

[0059] W-phase upper arm drive circuit 65 outputs W-phase upper arm overcurrent abnormality detection signal 50wp based on input W-phase upper arm DESAT signal 36wp, and outputs W-phase upper arm gate drive abnormality detection signal 60wp based on input W-phase upper arm gate voltage detection signal 37wp. W-phase lower arm drive circuit 66 outputs W-phase lower arm overcurrent abnormality detection signal 50wn based on input W-phase lower arm DESAT signal 36wn, and outputs W-phase lower arm gate drive abnormality detection signal 60wn based on input W-phase lower arm gate voltage detection signal 37wn.

[0060] Here, the U-phase upper arm overcurrent abnormality detection signal 50up, the U-phase lower arm overcurrent abnormality detection signal 50un, the V-phase upper arm overcurrent abnormality detection signal 50vp, the V-phase lower arm overcurrent abnormality detection signal 50vn, the W-phase upper arm overcurrent abnormality detection signal 50wp, and the W-phase lower arm overcurrent abnormality detection signal 50wn are at H level if the current of the semiconductor switching element to be detected is normal, and are at L level if the current of the semiconductor switching element to be detected is abnormal due to an overcurrent.

[0061] In addition, U-phase upper arm gate drive abnormality detection signal 60up, U-phase lower arm gate drive abnormality detection signal 60un, V-phase upper arm gate drive abnormality detection signal 60vp, V-phase lower arm gate drive abnormality detection signal 60vn, W-phase upper arm gate drive abnormality detection signal 60wp, and W-phase lower arm gate drive abnormality detection signal 60wn are at H level if the gate voltage of the semiconductor switching element being detected is normal, and are at L level if the gate voltage of the semiconductor switching element being detected is abnormal.

[0062] Next, we will explain the short-circuit control means 7. The short-circuit control means 7, which is configured by ASC, includes a first AND circuit 71, a second AND circuit 72, a third AND circuit 73, a fourth AND circuit 74, and a logic circuit unit 11.

[0063] The first AND circuit 71 receives as input the U-phase upper arm overcurrent abnormality detection signal 50up, the V-phase upper arm overcurrent abnormality detection signal 50vp, and the W-phase upper arm overcurrent abnormality detection signal 50wp. If at least one of these input signals is at L level indicating an abnormality, the first AND circuit 71 outputs an L-level upper arm overcurrent abnormality detection signal 71p indicating an overcurrent abnormality in the upper arm semiconductor switching element. If all of the above input signals are at H level indicating normality, the first AND circuit 71 outputs an H-level upper arm overcurrent abnormality detection signal 71p indicating that the current in the upper arm semiconductor switching element is normal.

[0064] The second AND circuit 72 receives as input U-phase upper arm gate drive abnormality detection signal 60up, V-phase upper arm gate drive abnormality detection signal 60vp, and W-phase upper arm gate drive abnormality detection signal 60wp, and if at least one of these input signals is at L level indicating an abnormality, outputs an L-level upper arm gate drive abnormality detection signal 72p indicating an abnormality in the gate voltage of the upper arm semiconductor switching element, and if all of the above input signals are at H level indicating normality, outputs an H-level upper arm gate drive abnormality detection signal 72p indicating that the gate voltage of the upper arm semiconductor switching element is normal.

[0065] The third AND circuit 73 receives as input the U-phase lower arm overcurrent abnormality detection signal 50un, the V-phase lower arm overcurrent abnormality detection signal 50vn, and the W-phase lower arm overcurrent abnormality detection signal 50wn. If at least one of these input signals is at an L level indicating an abnormality, the third AND circuit 73 outputs a L-level lower arm overcurrent abnormality detection signal 73n indicating an overcurrent abnormality in the lower arm semiconductor switching element. If all of the above input signals are at an H level indicating normality, the third AND circuit 73 outputs a H-level lower arm overcurrent abnormality detection signal 73n indicating that the current in the lower arm semiconductor switching element is normal.

[0066] The fourth AND circuit 74 receives as input U-phase lower arm gate drive abnormality detection signal 60un, V-phase lower arm gate drive abnormality detection signal 60vn, and W-phase lower arm gate drive abnormality detection signal 60wn, and if at least one of these input signals is at L level indicating an abnormality, outputs a lower arm gate drive abnormality detection signal 74n of L level indicating an abnormality in the gate voltage of the lower arm semiconductor switching element, and if all of the above input signals are at H level indicating normality, outputs a lower arm gate drive abnormality detection signal 74n of H level indicating that the gate voltage of the lower arm semiconductor switching element is normal.

[0067] As described above, the short-circuit control means 7 configured with ASCs monitors the DESAT signal 36 and the gate voltage detection signal 37 from the drive circuit 6 collectively for each upper arm and each lower arm, respectively. When monitoring the DESAT signal 36 and the gate voltage detection signal 37, the generation of each signal varies, so a filter time constant is provided in the logic circuit unit 11, and the generation point of each signal is adjusted, for example, within a range of half the switching period of each phase or less, using the settling time or latency of the ASC1 input unit and the ASC2 input unit of the drive circuit 6.

[0068] The logic circuit unit 11 is composed of hardware such as general-purpose logic circuits such as AND circuits, OR circuits, and NOT circuits, as well as resistors, diodes, and transistors, and outputs a first ASC signal ASC1 of either an H level indicating normality or an L level indicating abnormality from a first output unit A1 based on an upper arm overcurrent abnormality detection signal 71p input to input unit a, an upper arm gate drive abnormality detection signal 72p input to input unit b, a lower arm overcurrent abnormality detection signal 73n input to input unit c, and a lower arm gate drive abnormality detection signal 74n input to input unit d, and outputs a second ASC signal ASC2 of either an H level indicating normality or an L level indicating abnormality from a second output unit A2.

[0069] Next, the relationship between the above-mentioned signals input to the logic circuit section 11 of the short-circuit control means 7 and the first ASC signal ASC1 and second ASC signal ASC2 output from the logic circuit section 11 will be described.

[0070] 9 is an explanatory diagram showing the relationship between input signals, output signals, and gate control of the logic circuit unit in the power conversion device according to Embodiment 1. Here, upper-arm overcurrent abnormality detection signal 71p input to an input unit of logic circuit unit 11, upper-arm gate drive abnormality detection signal 72p input to input unit b, lower-arm overcurrent abnormality detection signal 73n input to input unit c, and lower-arm gate drive abnormality detection signal 74n input to input unit d are each simply referred to as input signals.

[0071] As shown in Figure 9, if the combination of input signals input to input parts a, b, c, and d of the logic circuit unit 11 is combination (1), the first ASC signal ASC1 and the second ASC signal ASC2 output from the logic circuit unit 11 will both be at H level, and all semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn will be driven normally based on the PWM control signal.

[0072] On the other hand, if the combination of input signals input to input units a, b, c, and d is one of the six combinations shown in combination (2) in Fig. 9, the first ASC signal ASC1 output from the logic circuit unit 11 goes low and the second ASC signal ASC2 goes high. As a result, as a fail-safe operation, the semiconductor switching elements Qun, Qvn, and Qwn in the lower arms of all three phases are forcibly turned on, and short-circuit control is performed by the lower arms of all phases.

[0073] Furthermore, if the combination of input signals input to input units a, b, c, and d is one of the five combinations shown in combination (3) in Fig. 9, the first ASC signal ASC1 output from the logic circuit unit 11 becomes H level and the second ASC signal ASC2 becomes L level. As a result, as a fail-safe operation, the semiconductor switching elements Qup, Qvp, and Qwp in the upper arms of all three phases are forcibly turned on, and short-circuit control is performed by the upper arms of all phases.

[0074] Furthermore, if the combination of input signals input to input sections a, b, c, and d is any one of the four combinations shown in combination (4) of Figure 9, the first ASC signal ASC1 and the second ASC signal ASC2 output from the logic circuit section 11 will both be at L level, and as a fail-safe operation, all semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn will be turned off, or the power conversion circuit 3 will be disconnected from the DC power supply 1, and so-called shutdown control will be performed.

[0075] Returning to Figure 2, the ASC1 input sections of U-phase upper arm drive circuit 61, U-phase lower arm drive circuit 62, V-phase upper arm drive circuit 63, V-phase lower arm drive circuit 64, W-phase upper arm drive circuit 65 and W-phase lower arm drive circuit 66 receive the above-mentioned first ASC signal ASC1 output from short circuit control means 7, and the second ASC signal ASC2 receives the ASC2 input sections.

[0076] The U-phase upper arm drive circuit 61, U-phase lower arm drive circuit 62, V-phase upper arm drive circuit 63, V-phase lower arm drive circuit 64, W-phase upper arm drive circuit 65 and W-phase lower arm drive circuit 66 perform the above-mentioned fail-safe operation depending on the levels of the input first ASC signal ASC1 and second ASC signal ASC2.

[0077] Next, the configuration of the semiconductor switching elements and drive circuits in the upper and lower arms will be described. Here, we will explain the U-phase leg consisting of a series circuit of the U-phase upper arm and U-phase lower arm. The V-phase leg consisting of a series circuit of the V-phase upper arm and V-phase lower arm, and the W-phase leg consisting of a series circuit of the W-phase upper arm and W-phase lower arm, both have the same configuration as the U-phase leg.

[0078] Fig. 3 is a configuration diagram showing the relative configuration of the semiconductor switching elements and drive circuits of the U-phase upper arm and U-phase lower arm in the power conversion device according to embodiment 1. In Fig. 3, overcurrent detection means 50 in U-phase upper arm drive circuit 61 and U-phase lower arm drive circuit 62 is composed of a DESAT detection unit as described above, but is represented as overcurrent detection means in Fig. 3.

[0079] DESAT detection by the DESAT detection unit serving as overcurrent detection means 50 in U-phase upper arm drive circuit 61 and U-phase lower arm drive circuit 62 is a method for protecting semiconductor switching elements Qup and Qun, which are made up of IGBT, Si, SiC-MOSFET, GaN-FET, etc., from excessive currents such as load short-circuit currents that could cause damage.

[0080] As shown in FIG. 3, the DESAT detection unit serving as overcurrent detection means 50 in U-phase upper arm drive circuit 61 and U-phase lower arm drive circuit 62 detects DESAT voltage Vdesat by flowing a constant current from current source 15 through semiconductor switching elements Qup, Qun, and by monitoring this DESAT voltage Vdesat, detects the saturation voltage of semiconductor switching element Qup in the event of a short circuit and protects semiconductor switching elements Qup, Qun of the U-phase upper arm.

[0081] The inputs of the DESAT detection units serving as overcurrent detection means 50 in U-phase upper arm drive circuit 61 and U-phase lower arm drive circuit 62 are connected to the parallel connection point between capacitor 14 and the series circuit of resistor 121 and diode 13.

[0082] The cathodes of diodes 13 in the U-phase upper arm and U-phase lower arm are connected to the drain terminals of semiconductor switching elements Qup and Qun, and the cathodes of diodes 13 are connected to the drain terminals of semiconductor switching elements Qup and Qun.

[0083] U-phase upper arm semiconductor switching element Qup receives, via resistor 122, a U-phase upper arm gate drive signal 171up from driver circuit 17 to its gate, and when U-phase upper arm gate drive signal 171up is at H level, a Hi-level gate-source voltage is applied to semiconductor switching element Qup. In the DESAT detection section of U-phase upper arm drive circuit 61, a charge current flows from current source 15 to semiconductor switching element Qup after a predetermined mask time has elapsed before and after the rising edge of the gate-source voltage.

[0084] Similarly, U-phase lower arm gate drive signal 171un is applied to the gate of semiconductor switching element Qun of the U-phase lower arm from driver circuit 17 via resistor 122, and when U-phase lower arm gate drive signal 171un is at H level, a Hi-level gate-source voltage is applied to semiconductor switching element Qun. In the DESAT detection section in U-phase lower arm drive circuit 62, a charge current flows from current source 15 to semiconductor switching element Qup after a predetermined mask time has elapsed before and after the rising edge of the gate-source voltage.

[0085] In the U-phase upper arm and the U-phase lower arm, during normal operation, the saturation voltage between the drain and source of the semiconductor switching elements Qup and Qun due to the load current is low, so the current path is divided into the forward path through resistor 121 and diode 13, and capacitor 14.

[0086] On the other hand, when the load current to semiconductor switching element Qup of the U-phase upper arm and U-phase lower arm is excessively large, the saturation voltage between the drain and source of semiconductor switching elements Qup and Qun becomes higher than the voltage on the cathode side of diode 13, so the current path is limited to the capacitor 14 side, and the current flows only to capacitor 14 without being branched to semiconductor switching elements Qup and Qup.

[0087] Therefore, the DESAT detection unit serving as overcurrent detection means 50 for the U-phase upper arm and U-phase lower arm detects the DESAT voltage by inputting the voltage across capacitor 14 as U-phase upper arm DESAT signals 36up, 36un, and when the detected DESAT voltage Vdesat exceeds a threshold value, outputs a U-phase upper arm overcurrent abnormality detection signal 50up and a U-phase lower arm overcurrent abnormality detection signal 50un.

[0088] The threshold value of the DESAT voltage Vdesat in the U-phase upper arm and the U-phase lower arm and the resistance value of resistor 121 are set to appropriate values ​​in advance. In addition, the blanking time, which is the mask time before and after the rise of the gate-source voltage of the semiconductor switching elements Qup and Qun, is set to an appropriate value in advance.

[0089] When U-phase upper arm gate drive signal 171up goes low and the gate voltage goes low, MOSFET 18 in the DESAT detection section serving as overcurrent detection means 50 turns on and the charge in capacitor 14 is extracted.

[0090] Similarly, when U-phase lower arm gate drive signal 171un goes to Lo level, ie, L level, MOSFET 18 in the DESAT detection section serving as overcurrent detection means 50 turns on, and the charge in capacitor 14 is extracted.

[0091] As described above, the DESAT detection units serving as overcurrent detection means 50 in the U-phase upper arm and U-phase lower arm detect the DESAT voltage Vdesat when the semiconductor switching elements Qup, Qun of the corresponding arm are turned on. Therefore, when the gate voltages of the semiconductor switching elements Qup, Qun are at the Hi level, the DESAT detection units detect whether the current flowing through the semiconductor switching elements Qup, Qun is normal or abnormal.

[0092] When the DESAT detection section in the U-phase upper arm detects an abnormality in DESAT voltage Vdesat, even if the U-phase upper arm PWM control signal PWM-up input from microcomputer 9 is at a signal level that turns on semiconductor switching element Qup, driver circuit section 17 of U-phase upper arm drive circuit 61 switches the gate voltage as U-phase upper arm gate drive signal 171up from Hi level to Lo level, detects the abnormality in U-phase upper arm DESAT signal 36up, and notifies the subsequent short-circuit control means 7 of the abnormality as U-phase upper arm overcurrent abnormality detection signal 50up.

[0093] Similarly, when the DESAT detection section in the U-phase lower arm detects an abnormality in DESAT voltage Vdesat, even if the U-phase lower arm PWM control signal PWM-un input from microcomputer 9 is at a signal level that turns on semiconductor switching element Qun, driver circuit section 17 of U-phase lower arm drive circuit 62 switches the gate voltage as U-phase lower arm gate drive signal 171un from Hi level to Lo level, detects the abnormality in U-phase lower arm DESAT signal 36un, and notifies the subsequent short-circuit control means 7 of the abnormality as U-phase lower arm overcurrent abnormality detection signal 50un.

[0094] In this way, the DESAT detection unit can detect an overcurrent in the target arm and stop the gate drive of the target arm, but because it detects the overcurrent instantaneously and shuts off the gate of the semiconductor switching element when an overcurrent occurs, it cannot determine whether the semiconductor switching element has a short-circuit failure or an open-circuit failure.

[0095] Furthermore, the DESAT method cannot identify whether the fault is in the upper or lower arm, and it is also impossible to determine whether the fault is transient or persistent due to a short-circuit or open-circuit failure in a semiconductor switching element. Therefore, in conventional technology such as that disclosed in Patent Document 1, the DESAT signal is used as a trigger to check the phase current using a current sensor or the like, identify the faulty arm, and determine whether it is a short-circuit or open-circuit failure, thereby performing three-phase short-circuit control.

[0096] According to the power conversion device of the first embodiment of the present application, as described above and below, the short circuit control means is configured to turn on all of the semiconductor switching elements in either the upper arm or the lower arm to perform short circuit control based on the abnormality detection result by the overcurrent detection means and the abnormality detection result by the gate drive abnormality detection means.

[0097] Next, we will explain gate drive abnormality detection means 60 in U-phase upper arm drive circuit 61 and U-phase lower arm drive circuit 62. As shown in Figure 3, U-phase upper arm drive circuit 61 includes gate drive abnormality detection means 60 that monitors the gate-source voltage of semiconductor switching element Qup in the U-phase upper arm, and determines whether the gate-source voltage of semiconductor switching element Qup has reached a predetermined voltage.

[0098] For example, gate drive abnormality detection means 60 in U-phase upper arm drive circuit 61 has a determination threshold voltage for detecting whether the gate voltage of semiconductor switching element Qup is stuck at High or Low, and detects whether the gate voltage of semiconductor switching element Qup is stuck at High or Low using a comparator or the like, depending on whether U-phase upper arm PWM control signal PWM-up from microcomputer 9 is at High or Low level. This detection result is output as U-phase upper arm gate drive abnormality detection signal 60up.

[0099] Similarly, the U-phase lower arm drive circuit 62 includes a gate drive abnormality detection means 60 that monitors the gate-source voltage of the semiconductor switching element Qun of the U-phase lower arm, and determines whether the gate-source voltage of the semiconductor switching element Qun has reached a predetermined voltage.

[0100] For example, gate drive abnormality detection means 60 in U-phase lower arm drive circuit 62 has a determination threshold voltage for detecting whether the gate voltage of semiconductor switching element Qun is fixed at High or Low, and detects whether the gate voltage of semiconductor switching element Qun is fixed at High or Low using a comparator or the like, depending on whether the U-phase lower arm PWM control signal PWM-un from microcomputer 9 is at High or Low level. This detection result is output as U-phase lower arm gate drive abnormality detection signal 60un.

[0101] Driver circuit units 17 in U-phase upper arm drive circuit 61 and U-phase lower arm drive circuit 62 control the gates of target semiconductor switching elements Qup, Qun as shown in FIG. 4 in response to first ASC signal ASC1 and second ASC signal ASC2 from logic circuit unit 11 of short-circuit control means 7.

[0102] That is, Figure 4 is an explanatory diagram showing the relationship between the output signal of the logic circuit unit, the gate voltage, and the gate control in the power conversion device according to embodiment 1, and shows the gate voltage as the gate drive signal 171 output from the driver circuit unit 17 in each drive circuit 6 and the gate control corresponding to the first ASC signal ASC1 and the second ASC signal ASC2 from the logic circuit unit 11 in the short circuit control means 7 configured by the ASC.

[0103] As shown in FIG. 4, when the first ASC signal ASC1 and the second ASC signal ASC2 from the logic circuit unit 11 of the short circuit control means 7 are both at L level, the gate voltages of the driver circuit units 17 of the upper and lower arms of all phases are all at Lo level, and all semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn are cut off, resulting in all phases being cut off.

[0104] Furthermore, when the first ASC signal ASC1 from the logic circuit unit 11 is at L level and the second ASC signal ASC2 is at H level, the gate voltages of the driver circuit units 17 of the lower arms of all phases become Hi level, and the semiconductor switching elements Qun, Qvn, and Qwn of the lower arms are subjected to three-phase short-circuit control.

[0105] Furthermore, when the first ASC signal ASC1 from the logic circuit unit 11 is at H level and the second ASC signal ASC2 is at L level, the gate voltages of the driver circuit units 17 of the upper arms of all phases become Hi level, and three-phase short-circuit control is performed on the semiconductor switching elements Qup, Qvp, and Qwp of the upper arms.

[0106] Furthermore, when the first ASC signal ASC1 and the second ASC signal ASC2 from the logic circuit unit 11 are both at H level, the PWM control signal 10 from the microcomputer 9 for all the drive circuits becomes valid, and based on the PWM control signal 10 output from the microcomputer 9, all the semiconductor switching elements Qup, Qun, Qvp, Qvn, Qwp, and Qwn are PWM controlled, and the power conversion circuit 3 is driven as an inverter or a converter.

[0107] In the above description, the overcurrent detection means 50 and the gate drive abnormality detection means 60 are provided inside the drive circuits 6 of the upper and lower arms of all phases, respectively. However, the overcurrent detection means 50 and the gate drive abnormality detection means 60 may be provided outside the drive circuits 6, and these means may be configured not only as hardware but also as software.

[0108] Next, a method for determining which arm, the upper arm or the lower arm, to use for the three-phase short circuit control will be described. Specifically, the gate drive abnormality signal for the upper arm or the lower arm is combined with an overcurrent abnormality detection signal based on the DESAT signal for the upper arm or the lower arm to determine which arm, the upper arm or the lower arm, to use for the three-phase short circuit control, and the control is then executed.

[0109] In the following explanation, the U phase will be taken as an example. Note that the V phase and W phase are similar to the U phase, and therefore their explanation will be omitted. (1) When the lower arm gate voltage detection signal is abnormal and the lower arm DESAT signal is abnormal In this case, the gate voltage of the U-phase lower arm is at Hi level, and both the U-phase lower arm gate voltage detection signal 37un and the U-phase lower arm overcurrent abnormality detection signal 50un are abnormal, which allows us to determine that the semiconductor switching element Qun of the U-phase lower arm is stuck at Hi.

[0110] Figure 5 is a waveform diagram showing the operation of the power conversion device according to embodiment 1 when a Hi lock occurs in the U-phase lower arm. In Figure 5, the horizontal axis represents time, and the vertical axis represents the following: A) on the vertical axis in Figure 5, A) represents U-phase upper arm PWM control signal PWM-up input to U-phase upper arm drive circuit 61, B) represents U-phase lower arm PWM control signal PWM-un input to U-phase lower arm drive circuit 62, C) represents the gate voltage applied to the gate of semiconductor switching element Qup in the U-phase upper arm, and D) represents the gate voltage applied to the gate of semiconductor switching element Qun in the U-phase lower arm.

[0111] Furthermore, E) indicates the gate-source voltage Vgsp [V] of semiconductor switching element Qup in the U-phase upper arm, F) indicates the gate-source voltage Vgsn [V] of semiconductor switching element Qun in the U-phase lower arm, G) indicates the drain-source voltage Vdsp [V] of semiconductor switching element Qup in the U-phase upper arm, H) indicates the drain-source voltage Vdsn [V] of semiconductor switching element Qun in the U-phase lower arm, I) indicates U-phase upper arm DESAT signal 36up, J) indicates U-phase lower arm DESAT signal 36un, K) indicates U-phase upper arm overcurrent abnormality detection signal 50up, and L) indicates U-phase lower arm overcurrent abnormality detection signal 50un.

[0112] 5, U-phase upper arm PWM control signal PWM-up shown in A) rises from L level to H level at time T51, and in response thereto, the gate voltage of U-phase upper arm drive circuit 61 shown in C) rises from L level to H level at time T51. Meanwhile, U-phase lower arm PWM control signal PWM-un shown in B) falls from H level to L level at time T52, but the gate voltage of U-phase lower arm drive circuit 62 shown in D) is fixed at Hi and therefore remains at H level after time T52.

[0113] The U-phase upper arm DESAT voltage Vdesat shown in I) gradually increases from time T53 when the master period M51 shown in C) ends, and reaches the Vdesat threshold value at time T54. As a result, the U-phase upper arm DESAT signal 36up changes from normal to abnormal at time T54, and the U-phase upper arm overcurrent abnormality detection signal 50up goes to the L level indicating an abnormality at time T54.

[0114] Meanwhile, the DESAT voltage Vdesat of the U-phase lower arm shown in J) gradually increases from time T55 when the master period M52 shown in D) ends, and at time T56 when the drain-source voltage Vdsn [V] of the semiconductor switching element Qun in the U-phase lower arm rises shown in H), it continues to increase gradually and reaches the Vdesat threshold value at time T57. As a result, the U-phase lower arm DESAT signal 36un shown in J) changes from normal to abnormal at time T57.

[0115] At time T52 when U-phase lower arm PWM control signal PWM-un shown in B) transitions from H level to L level, U-phase lower arm DESAT voltage Vdesat shown in J) is not 0 V, so U-phase lower arm gate drive abnormality detection signal 60un shown in L) changes from H level, indicating normality, to L level, indicating abnormality, at time T52 when U-phase lower arm PWM control signal PWM-un shown in B) falls from H level to L level, and an abnormality in the gate drive voltage of the U-phase lower arm is detected. U-phase upper arm gate drive abnormality detection signal 60up shown in K) remains at H level, indicating normality.

[0116] After U-phase upper arm PWM control signal PWM-up rises to H level at time T51, the gate-source voltage of semiconductor switching element Qup in the U-phase upper arm shown in E) rises, and the drain-source voltage of semiconductor switching element Qup in the U-phase upper arm shown in G) falls, reaching Vdsp / 2 [V] at time T57. At the same time, the drain-source voltage of semiconductor switching element Qun in the U-phase lower arm shown in H) reaches Vdsn / 2 [V] at this time T57.

[0117] As described above, when the semiconductor switching element Qun of the U-phase lower arm is stuck at Hi, an abnormality in the gate drive of the lower arm is detected at time T52 when the U-phase lower arm PWM control signal PWM-un transitions from H level to L level, and after the U-phase upper arm PWM control signal PWM-up transitions from L level to H level at time T51, the DESAT signal of the U-phase lower arm becomes abnormal at time T57, and an overcurrent abnormality in the U-phase lower arm is detected.

[0118] The above explanation applies to the case where the semiconductor switching element of the U-phase lower arm is stuck at Hi, but the same operation applies when the semiconductor switching element of the U-phase upper arm is stuck at Hi, and when the V-phase or W-phase is stuck at Hi.

[0119] As described above, when the gate drive abnormality signal is abnormal and the DESAT signal is also abnormal, a secondary failure due to a short circuit between the upper arm and the lower arm can be avoided by performing three-phase short-circuit control using the arm on the side where the gate drive abnormality signal is abnormal.

[0120] (2) When the gate drive abnormality signal of either the upper arm or the lower arm is abnormal In this case, the DESAT signals are normal in the upper and lower arms, so there are no open or short circuit faults in the semiconductor switching elements of the upper and lower arms. Also, since there is only an abnormality in the gate drive abnormality detection signal and no abnormality occurs in the DESAT signal, it can be determined that the target arm is stuck at Lo.

[0121] 6 is a waveform diagram showing the operation of the power conversion device according to embodiment 1 when a Lo lock occurs in the U-phase lower arm. In Fig. 6, the horizontal axis represents time, and A) to L) on the vertical axis represent voltage or signal waveforms corresponding to A) to L) in Fig. 5, respectively.

[0122] 6, U-phase upper arm PWM control signal PWM-up shown in A) rises from L level to H level at time point T61, and in response thereto, the gate voltage of U-phase upper arm drive circuit 61 shown in C) rises from L level to H level at time point T61. Meanwhile, U-phase lower arm PWM control signal PWM-un shown in B) rises from L level to H level at time point T62, and in response thereto, the gate voltage of U-phase lower arm drive circuit 62 shown in D) rises at time point T62.

[0123] The gate voltage of U-phase lower arm drive circuit 62 shown in D) rises to H level at time T62, but falls to L level at time T63 because semiconductor switching element Qun of the U-phase lower arm is fixed at Lo. At the same time that the gate voltage of U-phase lower arm drive circuit 62 falls to L level at time T63, it is blocked by mask period M63, and thereafter mask period M63 continues.

[0124] The U-phase upper arm DESAT voltage Vdesat shown in I) gradually increases from time T64 when the master period M61 shown in C) ends, and thereafter remains at a value that does not reach the Vdesat threshold. As a result, the U-phase upper arm DESAT signal 36up continues to indicate normal operation.

[0125] On the other hand, the U-phase lower arm DESAT voltage Vdesat shown in J) gradually increases from time T65 when the master period M62 shown in D) ends, but immediately falls back to the level before the gradual increase at time T63 when the gate voltage of the U-phase lower arm goes low, and continues thereafter without reaching the Vdesat threshold. Therefore, the U-phase lower arm DESAT signal 36un continues to indicate normality.

[0126] As a result of the above operation, U-phase upper arm gate drive abnormality detection signal 60up shown in K) continues to indicate normality, while U-phase lower arm gate drive abnormality detection signal 60un shown in L) transitions from normal to abnormal at time T63 and continues to indicate abnormality thereafter.

[0127] After U-phase upper arm PWM control signal PWM-up rises to H level at time T61, the gate-source voltage of semiconductor switching element Qup in the U-phase upper arm shown in E) rises, and the drain-source voltage of semiconductor switching element Qup in the U-phase upper arm shown in G) drops, reaching 0 V at time T66. At the same time, the drain-source voltage of semiconductor switching element Qun in the U-phase lower arm shown in H) reaches Vdsn V at this time T66.

[0128] As described above, when semiconductor switching element Qun of the U-phase lower arm is stuck at Low, even if the U-phase lower arm PWM control signal PWM-un input from microcomputer 9 goes to H level, the gate voltage of drive circuit 62 for the U-phase lower arm is at L level, and the abnormality can be detected by U-phase lower arm gate drive abnormality detection signal 60un.

[0129] Furthermore, because the U-phase upper arm DESAT signal 36up and the U-phase lower arm DESAT signal 36un are normal, there is no open circuit or short circuit failure in the semiconductor switching elements Qup and Qun of the U-phase upper arm and U-phase lower arm. Furthermore, the DESAT method as an overcurrent detection means detects DESAT when the semiconductor switching elements are turned on, making it possible to determine whether the gate drive is stuck at Lo.

[0130] The above explanation is for the case where the semiconductor switching element of the U-phase lower arm is stuck at Lo, but the same operation will occur if the semiconductor switching element of the U-phase upper arm is stuck at Lo, or if the V-phase or W-phase are stuck at Lo.

[0131] Therefore, if the gate drive abnormality signal of either the upper arm or the lower arm is abnormal, a secondary failure due to a short circuit between the upper arm and the lower arm can be avoided by performing three-phase short circuit control on the arm opposite the arm with the abnormal gate drive abnormality signal.

[0132] (3) When the DESAT signal of either the upper arm or the lower arm is abnormal If only the DESAT signal is abnormal, it can be determined that the gate drive of the upper and lower arms is normal. The DESAT method detects DESAT when the semiconductor switching element is turned on. Therefore, if the semiconductor switching element of one of the upper and lower arms has a short-circuit fault, an abnormality in the DESAT signal of the arm that is turned on can be detected when the semiconductor switching element of the other arm is turned on.

[0133] Furthermore, if the semiconductor switching element of one of the upper and lower arms has an open fault, turning on the semiconductor switching element of the other arm will not cause a short-circuit current to flow, and the DESAT signal will remain normal. Therefore, when the semiconductor switching element of the arm with the open fault is turned on, current from the current source of the DESAT detection unit flows to the capacitor without being diverted to the semiconductor switching element, making it possible to detect an abnormality in the DESAT signal of the arm with the open fault.

[0134] Next, a case where a short-circuit fault occurs in one of the semiconductor switching elements of the upper arm and the lower arm will be described. Fig. 7 is a waveform diagram showing the operation of the power conversion device according to embodiment 1 when a short-circuit fault occurs in the U-phase lower arm. In Fig. 7, the horizontal axis represents time, and A) to L) on the vertical axis represent voltage or signal waveforms corresponding to A) to L) in Fig. 5, respectively.

[0135] 7, U-phase upper arm PWM control signal PWM-up shown in A) rises from L level to H level at time point T71, and in response thereto, the gate voltage of U-phase upper arm drive circuit 61 shown in C) rises from L level to H level at time point T71. Meanwhile, U-phase lower arm PWM control signal PWM-un shown in B) rises from L level to H level at time point T72, and in response thereto, the gate voltage of U-phase lower arm drive circuit 62 shown in D) rises at time point T72.

[0136] The gate voltage of U-phase lower arm drive circuit 62 shown in D) rises at time T72 and falls at time T73 in synchronization with the behavior of U-phase lower arm PWM control signal PWM-un shown in B). If a short-circuit failure occurs in semiconductor switching element Qun of the U-phase lower arm at time T74 as shown in H), the drain-source voltage of semiconductor switching element Qun of the U-phase lower arm shown in H) will remain at 0 V even though the gate voltage of the U-phase lower arm shown in D) goes low at time T73, and will remain at 0 V until time T75 when the gate-source voltage of semiconductor switching element Qun of the U-phase lower arm shown in F) reaches 0 V.

[0137] The drain-source voltage of semiconductor switching element Qun in the U-phase lower arm shown in H) gradually increases from 0 V at time T75 and reaches the drain-source voltage Vds / 2 V at time T79. The DESAT voltage Vdesat of the U-phase lower arm shown in J) gradually increases from time T76 when mask period M72 blocking the gate voltage of the U-phase lower arm shown in D) ends, but does not reach the Vdesat threshold value and returns to its original voltage value at time T73 when the U-phase lower arm PWM control signal PWM-un transitions to the L level shown in B). Therefore, the U-phase lower arm DESAT signal 36un shown in J) does not become abnormal and remains normal.

[0138] On the other hand, the gate voltage of U-phase upper arm drive circuit 61 shown in C) rises to H level at time T71, and then at time T77 when mask period M71 ends, upper arm semiconductor switching element Qup transitions to ON, causing a short-circuit current to flow due to a short-circuit fault in lower arm semiconductor switching element Qun. As a result, U-phase upper arm DESAT voltage Vdesat shown in I) gradually increases from time T77 and reaches the Vdesat threshold value at time T78, and U-phase upper arm DESAT signal 36up becomes abnormal.

[0139] Neither the gate-source voltage of U-phase upper arm drive circuit 61 shown in E) nor the gate-source voltage of U-phase lower arm drive circuit 62 shown in F) is abnormal, and therefore U-phase upper arm gate drive abnormality detection signal 60up shown in K) and U-phase lower arm gate drive abnormality detection signal 60un shown in L) continue to indicate normality.

[0140] After U-phase upper arm PWM control signal PWM-up rises to H level at time T71, the gate-source voltage of semiconductor switching element Qup in the U-phase upper arm shown in E) rises and the drain-source voltage of semiconductor switching element Qup in the U-phase upper arm shown in G) falls, reaching Vdsn / 2 [V] at time T79. At the same time, the drain-source voltage of semiconductor switching element Qun in the U-phase lower arm shown in H) reaches Vdsn / 2 [V] at this time T79.

[0141] The above explanation applies to the case where the semiconductor switching element of the U-phase lower arm fails short-circuited, but the same operation also applies to the case where the semiconductor switching element of the U-phase upper arm fails short-circuited, and to the case where the V-phase or W-phase fails short-circuited.

[0142] As described above, if the lower arm semiconductor switching element experiences a short-circuit failure, while the lower arm semiconductor switching element is on, its drain-source voltage will be in a short-circuit state and almost no voltage will be generated. However, when the upper arm semiconductor switching element is turned on, a short-circuit current will flow through the upper and lower arms of that phase, and the power supply voltage will be divided by the upper and lower arm semiconductor switching elements. As mentioned above, the DESAT method detects the DESAT voltage when the semiconductor switching element is turned on, so it is possible to detect DESAT voltage abnormalities, that is, abnormalities caused by overcurrent, using the DESAT signal on the upper arm side.

[0143] Next, a case where a short-circuit fault occurs in the semiconductor switching element of one of the upper and lower arms will be described. Fig. 8 is a waveform diagram showing the operation of the power conversion device according to embodiment 1 when an open circuit fault occurs in the U-phase lower arm. In Fig. 8, the horizontal axis represents time, and A) to L) on the vertical axis represent voltage or signal waveforms corresponding to A) to L) in Fig. 5, respectively.

[0144] 8, U-phase upper arm PWM control signal PWM-up shown in A) rises from L level to H level at time point T81, and in response thereto, the gate voltage of U-phase upper arm drive circuit 61 shown in C) rises from L level to H level at time point T81. Meanwhile, U-phase lower arm PWM control signal PWM-un shown in B) rises from L level to H level at time point T82, and in response thereto, the gate voltage of U-phase lower arm drive circuit 62 shown in D) rises at time point T82.

[0145] If an open circuit fault occurs in semiconductor switching element Qun of the U-phase lower arm at time T83, as shown in H), the drain-source voltage of semiconductor switching element Qun of the U-phase lower arm increases from time T83 and then reaches a value of Vds / 2 [V]. Because an open circuit fault has occurred in semiconductor switching element Qun of the U-phase lower arm, the DESAT detection unit serving as overcurrent detection means 50 for the U-phase lower arm charges only capacitor 14. Here, DESAT voltage Vdesat of U-phase lower arm drive circuit 62 reaches the Vdesat threshold value at time T84.

[0146] As a result, the U-phase lower arm DESAT signal 36un shown in J) transitions from normal to abnormal at time T84.

[0147] On the other hand, DESAT voltage Vdesat of U-phase upper arm drive circuit 61 shown in I), the gate-source voltage of U-phase upper arm drive circuit 61 shown in E), and the gate-source voltage of U-phase lower arm drive circuit 62 shown in F) do not become abnormal, and therefore U-phase upper arm gate drive abnormality detection signal 60up shown in K) and U-phase lower arm gate drive abnormality detection signal 60un shown in L) both continue to indicate normality.

[0148] The above explanation applies to the case where an open circuit fault occurs in the semiconductor switching element of the U-phase lower arm, but the same operation will also occur if an open circuit fault occurs in the semiconductor switching element of the U-phase upper arm, or in the V-phase or W-phase.

[0149] As described above, when a short-circuit fault occurs in the semiconductor switching element of either the upper arm or the lower arm, the DESAT signal becomes abnormal in the arm opposite the arm with the short-circuit fault, and when an open-circuit fault occurs in the semiconductor switching element of either the upper arm or the lower arm, an abnormal DESAT signal occurs in the arm on the side where the open-circuit fault occurred.

[0150] Therefore, if the DESAT signal of either the upper arm or the lower arm indicates an abnormality, it can be determined that the semiconductor switching elements of the upper arm and the lower arm have a short-circuit failure or an open-circuit failure. If three-phase short-circuit control is performed using the arm opposite the arm that receives the DESAT signal indicating an abnormality, it is possible to avoid a secondary failure due to a short circuit between the upper arm and the lower arm.

[0151] According to the above (1), (2), and (3), it is possible to logically determine which arm, the upper arm or the lower arm, should be subjected to three-phase short-circuit control from the combination of the gate drive abnormality detection signal of the upper arm or the lower arm and the DESAT signal of the upper arm or the lower arm, so that three-phase short-circuit control can be realized even in hardware.

[0152] In addition, in the case of a combination of the gate drive abnormality detection signal and the DESAT signal other than those described above in (1), (2), and (3), if the gate drive abnormality detection signal indicates an abnormality in both the upper arm and the lower arm, it can be determined that the gates of both the upper arm and the lower arm of each of the three-phase legs consisting of the upper arm and the lower arm cannot be driven, and three-phase short circuit control cannot be performed. In this case, all-phase shutoff control is performed.

[0153] Furthermore, if the DESAT signal for both the upper arm and the lower arm indicates an abnormality, it can be determined that the gate drive of the upper arm and the lower arm is normal with respect to the PWM control signal that is the input signal to the drive circuit, and that the Hi fixation has occurred due to the PWM control signal 10 between the drive circuit and the microcomputer. In such a case, it can be assumed that the semiconductor switching elements are normal, and although the lower arm is subjected to three-phase short-circuit control in the first embodiment, three-phase short-circuit control may be performed by either the upper arm or the lower arm.

[0154] According to the power conversion device of the first embodiment, a combination of the gate drive abnormality determination and the DESAT signal makes it possible to determine whether a short-circuit fault or an open-circuit fault has occurred in either the upper arm or the lower arm, eliminating the need to observe phase currents through software processing by a microcomputer, as in conventional technology. As a result, even if a fault occurs in the power conversion circuit, three-phase short-circuit control can be achieved through a hardware configuration, thereby shortening the time it takes for the power conversion device to transition to a state in which it operates to put the vehicle into an evacuation driving state.

[0155] Therefore, it is no longer necessary to observe phase current imbalance using current sensors as in conventional technology, and three-phase short circuit control is possible using a hardware configuration while avoiding secondary failures such as short circuits between the upper and lower arms, allowing the vehicle to quickly transition to an evacuation driving state.

[0156] In addition, there is no need to add a dedicated microcomputer to improve the responsiveness of three-phase short-circuit control, or to design (increase the size) the busbar shape to take into account the phase current offset, which helps avoid increases in costs.

[0157] Furthermore, there is no need to consider offsets due to phase current imbalances, and there is no need to widen the observation range of the current sensor, which improves the resolution and accuracy of the sensor.

[0158] Furthermore, three-phase short circuit control can be achieved by a hardware configuration without software intervention, using inexpensive circuit configurations such as general-purpose logic circuits, resistors, diodes, and transistors.

[0159] In the first embodiment, the overcurrent detection means is described as being of the DESAT detection type, but the same effect can be expected from a current sense (OC) type.

[0160] Although the present application describes an exemplary embodiment 1, the various features, aspects, and functions described in embodiment 1 are not limited to application to a specific embodiment, but can be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are anticipated within the scope of the technology disclosed in the present application. For example, this includes modifying, adding, or omitting at least one component.

[0161] Next, aspects of the power conversion device disclosed in the present application will be described below as supplementary notes. (Appendix 1) a power conversion circuit in which a plurality of series circuits, each of which connects upper arm semiconductor switching elements and lower arm semiconductor switching elements in series, are connected in parallel to one another, a parallel connection portion of the plurality of series circuits is connected to a DC power source, a series connection portion of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits is connected to an armature winding of an AC motor, and which performs power conversion between the DC power source and the AC motor by switching control of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits; a drive circuit that applies gate drive signals to the upper arm semiconductor switching elements and the lower arm semiconductor switching elements to perform the switching control; a short-circuit control means for turning on all of the semiconductor switching elements of either the upper arm or the lower arm in the plurality of series circuits to perform short-circuit control of the power conversion circuit; an overcurrent detection means for detecting whether or not there is an abnormality due to an overcurrent in the semiconductor switching elements of the upper arm and the lower arm; a gate drive abnormality detection means for detecting whether or not there is an abnormality in the gate voltage of the semiconductor switching element of the upper arm and the semiconductor switching element of the lower arm; Equipped with The short circuit control means and performing the short-circuit control by turning on all of the semiconductor switching elements of either the upper arm or the lower arm based on the detection result of the abnormality by the overcurrent detection means and the detection result of the abnormality by the gate drive abnormality detection means. A power conversion device characterized by: (Appendix 2) When the detection result by the overcurrent detection means indicates an abnormality in one or both of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements, and the detection result by the gate drive abnormality detection means indicates an abnormality in one of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements, the short circuit control means is configured to perform the short circuit control by a semiconductor switching element of an arm on which an abnormality is detected by the gate drive abnormality detection means. 2. The power conversion device according to claim 1, (Appendix 3) When only the detection result by the gate drive abnormality detection means is abnormal, the short circuit control means is configured to perform the short circuit control by a semiconductor switching element of an arm opposite to the arm on which the gate drive abnormality detection means detects the abnormality. 2. The power conversion device according to claim 1, (Appendix 4) When only the detection result by the overcurrent detection means is abnormal, The short circuit control means is configured to perform the short circuit control by a semiconductor switching element of an arm opposite to the arm on which the overcurrent detection means detects the abnormality. 2. The power conversion device according to claim 1, (Appendix 5) The short circuit control means is configured by hardware. 5. The power conversion device according to claim 1, wherein: (Appendix 6) The drive circuit includes at least one of the gate drive abnormality detection means and the overcurrent detection means. 6. The power conversion device according to any one of claims 1 to 5, [Explanation of symbols]

[0162] 100 power conversion device, 1 DC power supply, 2 AC motor, 2U, 2V, 2W armature winding, 3 power conversion circuit, 3P positive terminal, 3N negative terminal, 6 drive circuit, 61 U phase upper arm drive circuit, 62 U phase lower arm drive circuit, 63 V phase upper arm drive circuit, 64 V phase lower arm drive circuit, 65 W phase upper arm drive circuit, 66 W phase lower arm drive circuit, 7 short circuit control means, 8 smoothing capacitor, 9 microcomputer, 10 PWM control signal, 11 logic circuit unit, 13 diode, 14 capacitor, 15 current source, 18 MOSFET, 17 driver circuit unit, 171 gate drive signal, 171up U phase upper arm gate drive signal, 171vp V phase upper arm gate drive signal, 171wp W phase upper arm gate drive signal, 171un U phase lower arm gate drive signal, 171vn V-phase lower arm gate drive signal, 171wn W-phase lower arm gate drive signal, 31, 32, 33 series connection part, 34,35 parallel connection section, 36 DESAT signal, 36up U-phase upper arm DESAT signal, 36un U-phase lower arm DESAT signal, 36vp V-phase upper arm DESAT signal, 36vn V-phase lower arm DESAT signal, 36wp W-phase upper arm DESAT signal, 36wn W-phase lower arm DESAT signal, 37 gate voltage detection signal, 37up U-phase upper arm gate voltage detection signal, 37un U-phase lower arm gate voltage detection signal, 37vp V-phase upper arm gate voltage detection signal, 37vn V-phase lower arm gate voltage detection signal, 37wp W-phase upper arm gate voltage detection signal, 37wn W-phase lower arm gate voltage detection signal, 50 overcurrent detection means, 50up U-phase upper arm overcurrent abnormality detection signal, 50vp V-phase upper arm overcurrent abnormality detection signal, 50wp W-phase upper arm overcurrent abnormality detection signal, 50un U-phase lower arm overcurrent abnormality detection signal, 50vn V-phase lower arm overcurrent abnormality detection signal, 50wn W-phase lower arm overcurrent abnormality detection signal, 60 gate drive abnormality detection means, 60up U-phase upper arm gate drive abnormality detection signal, 60vp V-phase upper arm gate drive abnormality detection signal, 60wp W-phase upper arm gate drive abnormality detection signal, 60un U-phase lower arm gate drive abnormality detection signal, 60vn V-phase lower arm gate drive abnormality detection signal, 60wn W-phase lower arm gate drive abnormality detection signal, 71 first AND circuit, 72 second AND circuit, 73 third AND circuit, 74 fourth AND circuit, 71p upper arm overcurrent abnormality detection signal, 72p upper arm gate drive abnormality detection signal, 73n lower arm overcurrent abnormality detection signal, 74n lower arm gate drive abnormality detection signal, 121, 122 resistors, Qup, Qun, Qvp, Qvn, Qwp, Qwn semiconductor switching element, PWM-up U-phase upper arm PWM control signal, PWM-un U-phase lower arm PWM control signal, PWM-vp V-phase upper arm PWM control signal, PWM-vn V-phase lower arm PWM control signal, PWM-wp W-phase upper arm PWM control signal, PWM-wn W-phase lower arm PWM control signal, A1 first output unit, A2 second output unit, ASC1 first ASC signal, ASC2 second ASC signal

Claims

1. a power conversion circuit in which a plurality of series circuits, each of which connects upper arm semiconductor switching elements and lower arm semiconductor switching elements in series, are connected in parallel to one another, a parallel connection portion of the plurality of series circuits is connected to a DC power source, a series connection portion of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits is connected to an armature winding of an AC motor, and which performs power conversion between the DC power source and the AC motor by switching control of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits; a drive circuit that applies gate drive signals to the upper arm semiconductor switching elements and the lower arm semiconductor switching elements to perform the switching control; a short-circuit control means for turning on all of the semiconductor switching elements of either the upper arm or the lower arm in the plurality of series circuits to perform short-circuit control of the power conversion circuit; an overcurrent detection means for detecting whether or not there is an abnormality due to an overcurrent in the semiconductor switching elements of the upper arm and the lower arm; a gate drive abnormality detection means for detecting whether or not there is an abnormality in the gate voltage of the semiconductor switching element of the upper arm and the semiconductor switching element of the lower arm; Equipped with The short circuit control means a power conversion device configured to perform the short-circuit control by turning on all semiconductor switching elements of either the upper arm or the lower arm based on a detection result of the abnormality by the overcurrent detection means and a detection result of the abnormality by the gate drive abnormality detection means, When the detection result by the overcurrent detection means indicates an abnormality in one or both of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements, and the detection result by the gate drive abnormality detection means indicates an abnormality in one of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements, the short circuit control means is configured to perform the short circuit control by a semiconductor switching element of an arm on which an abnormality is detected by the gate drive abnormality detection means. A power conversion device characterized by:

2. A power conversion circuit in which a plurality of series circuits, each having an upper arm semiconductor switching element and a lower arm semiconductor switching element connected in series, are connected in parallel to one another, the parallel connection portions of the plurality of series circuits are connected to a DC power source, and the series connection portions of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits are connected to the armature windings of an AC motor, and which performs power conversion between the DC power source and the AC motor by switching control of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits; a drive circuit that applies gate drive signals to the upper arm semiconductor switching elements and the lower arm semiconductor switching elements to perform the switching control; a short-circuit control means for turning on all of the semiconductor switching elements of either the upper arm or the lower arm in the plurality of series circuits to perform short-circuit control of the power conversion circuit; an overcurrent detection means for detecting whether or not there is an abnormality due to an overcurrent in the semiconductor switching elements of the upper arm and the lower arm; a gate drive abnormality detection means for detecting whether or not there is an abnormality in the gate voltage of the semiconductor switching element of the upper arm and the semiconductor switching element of the lower arm; Equipped with The short circuit control means a power conversion device configured to perform the short-circuit control by turning on all semiconductor switching elements of either the upper arm or the lower arm based on a detection result of the abnormality by the overcurrent detection means and a detection result of the abnormality by the gate drive abnormality detection means, When only the detection result by the gate drive abnormality detection means is abnormal, the short circuit control means is configured to perform the short circuit control by a semiconductor switching element of an arm opposite to the arm on which the gate drive abnormality detection means detects the abnormality. A power conversion device characterized by:

3. A power conversion circuit in which a plurality of series circuits, each having an upper arm semiconductor switching element and a lower arm semiconductor switching element connected in series, are connected in parallel to one another, the parallel connection portions of the plurality of series circuits are connected to a DC power source, and the series connection portions of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits are connected to the armature windings of an AC motor, and which performs power conversion between the DC power source and the AC motor by switching control of the upper arm semiconductor switching elements and the lower arm semiconductor switching elements in the plurality of series circuits; a drive circuit that applies gate drive signals to the upper arm semiconductor switching elements and the lower arm semiconductor switching elements to perform the switching control; a short-circuit control means for turning on all of the semiconductor switching elements of either the upper arm or the lower arm in the plurality of series circuits to perform short-circuit control of the power conversion circuit; an overcurrent detection means for detecting whether or not there is an abnormality due to an overcurrent in the semiconductor switching elements of the upper arm and the lower arm; a gate drive abnormality detection means for detecting whether or not there is an abnormality in the gate voltage of the semiconductor switching element of the upper arm and the semiconductor switching element of the lower arm; Equipped with The short circuit control means a power conversion device configured to perform the short-circuit control by turning on all semiconductor switching elements of either the upper arm or the lower arm based on a detection result of the abnormality by the overcurrent detection means and a detection result of the abnormality by the gate drive abnormality detection means, When only the detection result by the overcurrent detection means is abnormal, The short circuit control means is configured to perform the short circuit control by a semiconductor switching element of an arm opposite to the arm on which the overcurrent detection means detects the abnormality. A power conversion device characterized by:

4. The short circuit control means is configured by hardware.

4. The power conversion device according to claim 1, wherein the power conversion device comprises: a power converter;

5. The drive circuit includes at least one of the gate drive abnormality detection means and the overcurrent detection means.

4. The power conversion device according to claim 1, wherein the power conversion device comprises: a power converter;

6. The drive circuit includes at least one of the gate drive abnormality detection means and the overcurrent detection means.

5. The power conversion device according to claim 4.

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