Signal processing device and communication device

Abstract

The present application provides a signal processing apparatus and a communication device for improving the cancellation accuracy of a nonlinear distortion signal, and relates to the field of communication technology. The apparatus includes a first splitter module, a first combiner module, a delay, and a filter circuit. The first splitter module is coupled to a signal source of the signal processing apparatus, and an output end of the first splitter module is separately coupled to an input end of the delay and an input end of the filter circuit. The output end of the delay is coupled to a first input end of the first combiner module. The output end of the filter circuit is coupled to a second input end of the first combiner module. The filter circuit includes a plurality of filter sub-circuits and an accumulation circuit, and the output ends of the plurality of filter sub-circuits are coupled to an input end of the accumulation circuit.

Description

[Technical Field]

[0001] The present application relates to the field of communications technology, and in particular to signal processing apparatus and communications devices. [Background technology]

[0002] When a desired signal (i.e., a service signal) passes through a nonlinear system, nonlinear distortion occurs. For example, after the power of the desired signal is amplified by a power amplifier (PA), the output signal includes the desired signal and a nonlinear distortion signal.

[0003] Currently, feedforward cancellation techniques are usually used to cancel the nonlinear distortion components of the output signal of a nonlinear system. However, the processing precision of existing feedforward cancellation techniques is low, resulting in low cancellation effect on the nonlinear distortion components, and further resulting in poor performance of the communication system. Summary of the Invention

[0004] The present application provides a signal processing apparatus and a communication device for improving the accuracy of cancellation of nonlinearly distorted signals. [Means for solving the problem]

[0005] To achieve the aforementioned objectives, the following technical solutions are used in the embodiments of this application.

[0006] According to a first aspect, a signal processing device is provided, including a first splitter module, a delay, a first combiner module, and a filter circuit. The first splitter module may be a component such as a combiner or a splitter, and for the purposes of explanation, the first combiner is used as an example of the first splitter module. The first combiner module may be a component such as a combiner or a combiner, and for the purposes of explanation, the second combiner is used as an example of the first combiner module. In other words, the signal processing device includes a first combiner, a second combiner, a delay, and a filter circuit. The first combiner is coupled to a signal source of the signal processing device, and an output end of the first combiner is separately coupled to an input end of the delay and an input end of the filter circuit. The output end of the delay is coupled to a first input end of the second combiner. The output end of the filter circuit is coupled to a second input end of the second combiner. The filter circuit includes a plurality of filter subcircuits and a storage circuit, with outputs of the plurality of filter subcircuits coupled to an input of the storage circuit.

[0007] The first combiner is configured to output a first sub-signal and a second sub-signal based on an input signal of the first combiner, where the power of the first sub-signal may be greater than the power of the second sub-signal. The delayer is configured to delay the first sub-signal to output a delayed signal. The filter circuit includes multiple filter sub-circuits and an accumulation circuit. The multiple filter sub-circuits are separately configured to sample the second sub-signal at different sampling times and perform filtering on the sampled signals obtained by the sampling to output sampled and filtered signals. In other words, the multiple filter sub-circuits may be separately configured to adjust the amplitude of the second sub-signal at different phases. The accumulation circuit is configured to accumulate the sampled and filtered signals output by the multiple filter sub-circuits to obtain an intermodulation cancellation signal. The second combiner is configured to output a target signal based on the intermodulation cancellation signal and the delayed signal, for example, by subtracting the intermodulation cancellation signal from the delayed signal to cancel the intermodulation signal in the delayed signal.

[0008] In the above technical solution, the apparatus uses a filter circuit to perform equalization processing on the second sub-signal. The filter circuit includes a plurality of filter sub-circuits and an accumulation circuit. The plurality of filter sub-circuits and the accumulation circuit can perform high-precision amplitude adjustment on the second sub-signal of different phases in the analog signal domain, so that the equalization processing on the intermodulation signal can be performed when the delay device provides a very small delay, thereby reducing the processing delay and improving the processing precision.

[0009] In a possible implementation of the first aspect, the apparatus further includes a second combiner module. For the purposes of explanation, a third combiner is used as an example of the second combiner module. A first input of the third combiner is coupled to an output of the first combiner, a second input of the third combiner is coupled to a signal source, and an output of the third combiner is coupled to an input of a filter circuit. The third combiner is configured to obtain a first intermodulation signal from the second sub-signal by combining. The third combiner may be replaced by an equalizer and output the first intermodulation signal. In this case, the multiple filter sub-circuits are separately configured to sample the first intermodulation signal in the second sub-signal at different sampling times and perform filtering on the sampled signal to output a sampled and filtered signal. In other words, the multiple filter sub-circuits may be separately configured to adjust the amplitude of the first intermodulation signal at different phases. By introducing a third combiner (second combiner module) or an equalizer, the first intermodulation signal in the second sub-signal can be extracted, allowing the filter circuit to perform high-precision amplitude and phase adjustment on the first intermodulation signal as intended, and reducing the service signal component in the intermodulation cancellation signal output by the filter circuit. Therefore, the adverse effect of the intermodulation cancellation signal on the desired signal component in the delayed signal can be reduced, and the cancellation performance of the intermodulation signal can be further improved.

[0010] It can be understood that when the apparatus does not include a combiner module, the first intermodulation signal processed by the filter circuit and the filter sub-circuit is replaced with the second sub-signal.

[0011] In a possible implementation of the first aspect, each of the plurality of filter subcircuits includes a sample-and-hold circuit and an amplitude adjustment circuit. An output terminal of the sample-and-hold circuit is coupled to a first input terminal of the amplitude adjustment circuit. The sample-and-hold circuit is configured to sample and hold the first intermodulation signal at a sampling time to output a sampled signal. The amplitude adjustment circuit is configured to perform a filtering process on the sampled signal to output a sampled and filtered signal. In the above possible implementation, the plurality of filter subcircuits can separately adjust the amplitude of the first intermodulation signal at different phases to ensure that the equalization process on the intermodulation signal has relatively high processing accuracy.

[0012] In a possible implementation of the first aspect, the sample-and-hold circuit includes a switch, a capacitor, and a buffer, and the amplitude adjustment circuit includes a multiplier. A first end of the switch is an input end of the filter subcircuit, and a second end of the switch, a first end of the capacitor, and a first end of the buffer are coupled together. A second end of the capacitor is grounded. A second end of the buffer is coupled to a first input end of the multiplier. A second input end of the multiplier is configured to receive a filtering coefficient, and an output end of the multiplier is configured to output a sampled and filtered signal. In the above possible implementation, the provided sample-and-hold circuit and the provided amplitude adjustment circuit are simple, effective, and low-cost. In addition, when the sample-and-hold circuit and the amplitude adjustment circuit sample and hold the first intermodulation signal and perform filtering processing on it, highly accurate amplitude and phase adjustment of the first intermodulation signal in the intermodulation signal can be performed with very little delay, resulting in reduced processing delay and improved processing accuracy.

[0013] In a possible implementation of the first aspect, the amplitude adjustment circuit further includes a transconductance amplifier coupled to the output of the multiplier, the transconductance amplifier being configured to amplify the sampled and filtered signal, and / or the filter circuit further includes a variable gain amplifier coupled to the output of the accumulation circuit. In the above possible implementation, it can be ensured that the amplitude of the intermodulation cancellation signal matches the amplitude of the intermodulation signal in the delayed signal, resulting in an improved cancellation effect for the intermodulation signal in the delayed signal.

[0014] In a possible implementation of the first aspect, the apparatus further includes an attenuator coupled between the first coupler and the third coupler, the attenuator configured to attenuate the second sub-signal such that an amplitude of the second sub-signal matches an amplitude of the service signal input to the third coupler.

[0015] In a possible implementation of the first aspect, a first input of the third combiner is coupled to an output of the filter circuit, a second input of the third combiner is coupled to the signal source, and an output of the third combiner is coupled to the second combiner. Optionally, the apparatus further includes an amplifier coupled between the signal source and the third combiner.

[0016] In a possible implementation of the first aspect, the apparatus further includes a post-distortion circuit coupled to the third combiner and the signal source. The post-distortion circuit is configured to inject a second intermodulation signal into the signal output by the signal source (which may be understood as the first service signal) to obtain a second service signal. The second service signal and the second sub-signal are used to obtain the first intermodulation signal by combination, and the frequency of the second intermodulation signal is different from the frequency of the first intermodulation signal. Optionally, the difference between the frequency of the second intermodulation signal and the frequency of the first service signal is greater than a preset threshold. In the above-mentioned possible implementation, the post-distortion circuit injects a second intermodulation signal into the first service signal to obtain a second service signal, whereby the third combiner uses the second service signal to obtain a first intermodulation signal from the second sub-signal by combining, thereby ensuring that the first intermodulation signal obtained by combining is an intermodulation signal within a specific frequency band range, reducing the complexity of processing the first intermodulation signal by the filter circuit and reducing costs.

[0017] In a possible implementation of the first aspect, the apparatus further includes a pre-distortion circuit configured to inject a third intermodulation signal into the first service signal. A difference between the frequency of the third intermodulation signal and the frequency of the first service signal is less than a first threshold. The third intermodulation signal may be referred to as a near-end intermodulation signal, and the third intermodulation signal is used to reduce the first intermodulation signal in the input signal of the first coupler. In the above possible implementation, the third intermodulation signal is injected into the first service signal, and the first intermodulation signal in the input signal of the first coupler is reduced using the third intermodulation signal, thereby reducing the processing difficulty of processing the first intermodulation signal by a filter circuit and reducing costs.

[0018] In a possible implementation of the first aspect, the apparatus further includes a filtering coefficient calculation circuit. An output end of the filtering coefficient calculation circuit is coupled to a second input end of the amplitude adjustment circuit. The filtering coefficient calculation circuit is configured to output a plurality of filtering coefficients based on the first intermodulation signal and the target signal, the plurality of filtering coefficients being filtering coefficients of a plurality of filter subcircuits. Optionally, the filtering coefficient calculation circuit includes a second splitter module and a calculation circuit. For example, the second splitter module is a fourth combiner. The filtering calculation circuit includes a fourth combiner and a calculation circuit. An input end of the fourth combiner is coupled to an output end of the second combiner, a first output end of the fourth combiner is coupled to a first input end of the calculation circuit, and a second input end of the calculation circuit is configured to receive the first intermodulation signal. In the above-mentioned possible implementation, the filtering coefficient calculation circuit is configured to output a plurality of filtering coefficients of a plurality of filter sub-circuits based on the first intermodulation signal and the target signal, thereby improving the processing accuracy of the filter circuit when a filtering process is performed on the first intermodulation signal based on the plurality of filtering coefficients.

[0019] In a possible implementation of the first aspect, the filtering coefficient calculation circuit further includes a first switch circuit and a second switch circuit coupled between the fourth combiner and the calculation circuit, and the first switch circuit and the second switch circuit are configured to disconnect or connect the fourth combiner and the calculation circuit. In the above possible implementation, the hardware link between the first switch circuit and the second switch circuit may implement time division multiplexing, and specifically, multiple fourth combiners share one calculation circuit by disconnecting and connecting the first switch circuit and the second switch circuit to improve utilization of the hardware link and reduce costs.

[0020] In a possible implementation of the first aspect, the apparatus further includes a parameter calibration circuit coupled to the filter circuit. The parameter calibration circuit is configured to determine mismatch parameters of the filter circuit based on the first intermodulation signal and the intermodulation cancellation signal, and the mismatch parameters are used to calibrate the filter circuit. Optionally, the mismatch parameters include at least one of the following: a sampling instant mismatch value, a gain mismatch value, or a DC current mismatch value. In the aforementioned possible implementation, the parameter calibration circuit is used to calibrate the filter circuit based on the mismatch parameters output based on the first intermodulation signal and the intermodulation cancellation signal, thereby avoiding filtering efficiency differences between multiple filter subcircuits in the filter circuit due to manufacturing differences between components, and thereby improving the processing accuracy of the filter circuit.

[0021] In a possible implementation of the first aspect, the filter circuit is integrated on one chip together with at least one of the following: a filtering coefficient calculation circuit, a parameter calibration circuit, or a post-distortion circuit. In said possible implementation, said circuits are integrated on a chip, which can reduce the size and cost of the system.

[0022] In a possible implementation of the first aspect, the apparatus further includes a power amplifier coupled between the input end of the first combiner and the signal source, and a duplexer coupled to the output end of the second combiner. The power amplifier is configured to output the input signal of the first combiner, and the duplexer is configured to receive a target signal and perform transmit filtering on the target signal. In this possible implementation, an effect of the target signal on the duplexed received signal when the target signal passes through the duplexer can be avoided.

[0023] According to a second aspect, a chip is provided. The chip includes a filter circuit. The filter circuit includes a plurality of filter subcircuits and an accumulation circuit. The plurality of filter subcircuits are separately configured to sample a first intermodulation signal at different sampling times and perform filtering on the sampled signals obtained by sampling to output sampled and filtered signals. The accumulation circuit is configured to accumulate the sampled and filtered signals output by the plurality of filter subcircuits to obtain an intermodulation cancellation signal.

[0024] In a possible implementation of the second aspect, each of the plurality of filter sub-circuits includes a sample-and-hold circuit configured to sample and hold the first intermodulation signal at a sampling time to output a sampled signal, and an amplitude adjustment circuit configured to perform a filtering process on the sampled signal to output a sampled and filtered signal.

[0025] In a possible implementation of the second aspect, the sample-and-hold circuit includes a switch, a capacitor, and a buffer, and the amplitude adjustment circuit includes a multiplier. A first end of the switch is an input end of the filter subcircuit, and a second end of the switch, a first end of the capacitor, and a first end of the buffer are coupled together. A second end of the capacitor is grounded. A second end of the buffer is coupled to a first input end of the multiplier. A second input end of the multiplier is configured to receive a filtering coefficient, and an output end of the multiplier is configured to output a sampled and filtered signal.

[0026] In a possible implementation of the second aspect, the amplitude adjustment circuit further includes a transconductance amplifier coupled to the output of the multiplier, the transconductance amplifier configured to amplify the sampled and filtered signal.

[0027] In a possible implementation of the second aspect, the filter circuit further comprises a gain amplifier coupled to the output of the storage circuit.

[0028] In a possible implementation of the second aspect, the chip further includes a post-distortion circuit configured to inject a second intermodulation signal into the first service signal to obtain a second service signal, the second service signal and the second transmit sub-signal being used to output the first intermodulation signal, and the frequency of the second intermodulation signal being different from the frequency of the first intermodulation signal.

[0029] In a possible implementation of the second aspect, the difference between the frequency of the second intermodulation signal and the frequency of the first service signal is greater than a preset threshold.

[0030] In a possible implementation of the second aspect, the chip further includes a filtering coefficient calculation circuit configured to output a plurality of filtering coefficients based on the first intermodulation signal and the target signal, the plurality of filtering coefficients being filtering coefficients of a plurality of filter sub-circuits.

[0031] In a possible implementation of the second aspect, the chip further includes a parameter calibration circuit coupled to the filter circuit, the parameter calibration circuit configured to determine a mismatch parameter of the filter circuit based on the first intermodulation signal and the intermodulation cancellation signal, the mismatch parameter being used to calibrate the filter circuit.

[0032] In a possible implementation of the second aspect, the mismatch parameters include at least one of the following: a sampling instant mismatch value, a gain mismatch value, or a DC current mismatch value.

[0033] According to a third aspect, there is provided a filtering coefficient calculation circuit for use in the signal processing device provided in the first aspect. A first input end of the filtering coefficient calculation circuit is coupled to the output end of the second combiner, and a second input end of the filtering coefficient calculation circuit is configured to receive a first intermodulation signal. The first intermodulation signal is an input signal of the filter circuit. An output end of the filtering coefficient calculation circuit is configured to output a filtering coefficient of the filter circuit.

[0034] In a possible implementation of the third aspect, the filtering coefficient calculation circuit includes a third combiner and a calculation circuit, an input end of the third combiner is coupled to an output end of the second combiner, a first output end of the third combiner is coupled to a first input end of the calculation circuit, a second input end of the calculation circuit is configured to receive the first intermodulation signal, and an output end of the calculation circuit is configured to output the filtering coefficients of the filter circuit.

[0035] In a possible implementation of the third aspect, the filtering coefficient calculation circuit further includes a first switch circuit and a second switch circuit coupled between the third combiner and the calculation circuit, the first switch circuit and the second switch circuit being configured to disconnect or connect the third combiner and the calculation circuit. In the above possible implementation, the hardware link between the first switch circuit and the second switch circuit may implement time division multiplexing, and specifically, the hardware link is switched by disconnecting and connecting the first switch circuit and the second switch circuit to improve utilization of the hardware link and reduce costs.

[0036] According to a fourth aspect, there is provided a communications device, the communications device comprising a baseband circuit and a signal processing apparatus provided in the first aspect or any possible implementation thereof.

[0037] It can be understood that any one of the chip, filtering coefficient calculation circuit, and communication device provided above includes at least part of the content of the signal processing device provided above. Therefore, for the beneficial effects that can be achieved by any one of the chip, filtering coefficient calculation circuit, and communication device, please refer to the beneficial effects of the signal processing device provided above. Details will not be described again here. [Brief explanation of the drawings]

[0038] [Figure 1] 1 is a schematic diagram of the structure of a wireless communication device according to an embodiment of the present application; [Figure 2] FIG. 1 is a schematic diagram of the structure of a feedforward cancellation system according to an embodiment of the present application; [Figure 3a] 1 is a schematic diagram of the structure of a signal processing device according to an embodiment of the present application; [Figure 3b] 1 is a schematic diagram of the structure of a signal processing device according to an embodiment of the present application; [Figure 3c] 1 is a schematic diagram of the structure of a signal processing device according to an embodiment of the present application; [Figure 3d] 1 is a schematic diagram of the structure of a signal processing device according to an embodiment of the present application; [Figure 4] FIG. 1 is a schematic diagram of the structure of a filter circuit according to an embodiment of the present application; [Figure 5] FIG. 10 is a schematic diagram of the structure of another filter circuit according to an embodiment of the present application. [Figure 6] 1 is an operational timeline diagram of a filter circuit according to an embodiment of the present application; [Figure 7] FIG. 2 is a schematic diagram of the structure of another signal processing device according to an embodiment of the present application; [Figure 8] FIG. 10 is a schematic diagram of the structure of yet another signal processing device according to an embodiment of the present application; [Figure 9] FIG. 2 is a schematic diagram of the structure of another signal processing device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0039] Hereinafter, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0040] In this application, "at least one" means one or more, "multiple" means two or more, and "and / or" describes an association relationship between associated objects and indicates that a three-way relationship may exist. For example, A and / or B may represent the following cases: only A is present, both A and B are present, and only B is present, where A and B may be singular or plural. The symbol " / " generally indicates an "or" relationship between associated objects. "At least one of" or similar expressions means a singular element or any combination of these, including any combination of plural elements. For example, at least one of a, b, or c may represent a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c may be singular or plural.

[0041] In the embodiments of the present application, terms such as "first" and "second" do not limit the number and order. The term "coupled" is used to represent an electrical connection, including a direct connection via an electric wire or a connecting end or an indirect connection via another component. Therefore, "coupled" should be considered as a generalized electronic communication connection.

[0042] It should be noted that in this application, terms such as "example" or "for example" are used to denote providing an example, illustration, or explanation. Any embodiment or design scheme described in this application as an "example" or "for example" is not described as more preferred or having more advantages than another embodiment or design scheme. Rather, the use of words such as "example" or "for example" is intended to present relative concepts in a concrete manner.

[0043] 1 is a schematic diagram of the structure of a wireless communication device according to one embodiment of the present application. The wireless communication device may be deployed indoors, outdoors, handheld, or on land, including on a vehicle. Alternatively, the wireless communication device may be deployed on water (e.g., a ship). Alternatively, the wireless communication device may be deployed in the air (e.g., an airplane, a balloon, or a satellite). For example, the wireless communication device may be a terminal or a base station. For example, the terminals include, but are not limited to, mobile phones, tablet computers, notebook computers, palmtop computers, mobile internet devices (MIDs), wearable devices (such as smart watches, smart bands, or pedometers), vehicle-mounted devices (such as automobiles, bicycles, electric vehicles, airplanes, ships, trains, or high-speed trains), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals for industrial control, smart home devices (such as refrigerators, televisions, air conditioners, or electricity meters), intelligent robots, workshop devices, wireless terminals for self-driving, wireless terminals for remote medical surgery, wireless terminals for smart grids, wireless terminals for transportation safety, wireless terminals for smart cities, wireless terminals for smart homes, and flying devices (such as intelligent robots, hot air balloons, unmanned aerial vehicles, or airplanes). In the following, with reference to FIG. 1, the structure of the wireless communication device will be described in detail.

[0044] The wireless communication device shown in FIG. 1 includes a baseband circuit, a radio frequency (RF) circuit, and an antenna, which are coupled in sequence.

[0045] The baseband circuitry may have baseband processing functionality and be configured to process baseband signals. The radio frequency circuitry may be configured to provide functionality such as power amplification or filtering. For example, the radio frequency circuitry may be configured to perform power amplification or filtering on baseband signals to convert them to radio frequency signals. The antenna may be configured to receive or transmit radio frequency signals, i.e., to convert energy between radio frequency signals and electromagnetic waves.

[0046] The radio frequency circuit may include one or more transmit (Tx) channels and one or more receive (Rx) channels. Each transmit channel includes a power amplifier (PA). The transmit channel may further include a transmit filter (Tx filter), which may be an isolator. Each receive channel includes a low noise amplifier (LNA). The receive channel may further include a receive filter (Rx filter), which may be a surface acoustic wave filter (SAW filter).

[0047] Furthermore, the radio frequency circuit may be configured to perform modulation or demodulation between a baseband signal and a radio frequency signal. For example, the radio frequency circuit may further include a modulation circuit corresponding to a transmission channel and a demodulation circuit corresponding to a reception channel. The modulation circuit corresponding to the transmission channel may include a digital-to-analog converter (DAC), a low-pass filter (LPF), an up-converter, and a driver amplifier (DA). The demodulation circuit corresponding to the reception channel may include an analog-to-digital converter (ADC), a low-pass filter (LPF), a down-converter, etc.

[0048] When the communication device shown in FIG. 1 supports frequency division duplexing (FDD) to separate transmit signals from receive signals and ensure that receive and transmit functions can function simultaneously, the communication device further includes a duplexer. As shown in FIG. 1, the duplexer may be disposed between the radio frequency circuit and the antenna. The duplexer is a special two-way three-ended filter and includes a transmit filter and a receive filter that can perform filtering on the transmit signal and the receive signal, respectively, to separate the transmit signal from the receive signal and ensure that receive and transmit functions can function simultaneously. Multiple transmit channels and multiple receive channels in the radio frequency circuit may share one duplexer.

[0049] The duplexer's transmit filter has two requirements: first, to ensure that interference signals within the receive frequency band, which are filtered out by the transmit filter, do not affect the receiver sensitivity at the receiving end; and second, to ensure that interference signals outside the receive frequency band, which are filtered out by the transmit filter, meet a specified spurious transmission index. The aforementioned requirements can be implemented by improving the filter's rejection. However, this also leads to larger size and higher cost of the transmit filter.

[0050] To reduce the rejection of the duplexer's transmit filter, a feedforward cancellation system can be used to cancel nonlinear distortion signals in the transmit signal input to the duplexer, reducing the impact of the nonlinear distortion signals on the receive sensitivity and spurious transmission index. The nonlinear distortion signals are generated due to the nonlinear operation of components on the transmit channel, and are primarily generated due to the nonlinear operation of the PA on the transmit channel. The nonlinear distortion signals primarily include intermodulation signals, which are signals generated by intermodulation between an interference signal or noise signal and a desired signal (also referred to as a service signal). The nonlinear distortion signals may also include harmonic signals. For ease of explanation, the term "intermodulation signal" will be used hereinafter to refer to the nonlinear distortion signals.

[0051] Below, the feedforward cancellation system is described in detail.

[0052] FIG. 2 is a schematic diagram of the structure of a feedforward cancellation system according to an embodiment of the present application. This system may be disposed between a PA and a duplexer on a transmit channel. As shown in FIG. 2, the feedforward cancellation system includes a first combiner, a delay, an equalizer, an amplifier, and a second combiner. The input end of the first combiner is coupled to the PA, and the output end of the second combiner is coupled to the transmit filter of the duplexer. Specifically, the first combiner is configured to output two transmit sub-signals based on the transmit signal output by the PA. The equalizer is configured to adjust the amplitude and phase of an intermodulation signal in one of the transmit sub-signals to output a cancellation signal. The amplifier is configured to amplify the cancellation signal to match the power of the intermodulation signal in the other transmit sub-signal. The delay is configured to delay the other transmit sub-signal to output a transmit delayed signal, the delay being used to match the processing delay of the equalizer and the processing delay of the amplifier. The second combiner is configured to cancel the intermodulation signal in the transmit delayed signal based on the amplified cancellation signal. The equalizer may be implemented using a limiter, a band-stop filter, and a phase shifter coupled in sequence. The limiter may be configured to adjust the amplitude of the input signal, the band-stop filter may be configured to extract the intermodulation signal, and the phase shifter may be configured to adjust the phase of the intermodulation signal. Alternatively, the equalizer may be implemented using an ADC, a digital filter, a digital equalizer, and a DAC coupled in sequence. The digital filter is configured to extract the intermodulation signal, and the digital filter is configured to perform amplitude-phase equalization processing on the intermodulation signal. Alternatively, the equalizer may be specifically implemented in another manner. However, existing feedforward cancellation techniques have low processing accuracy, resulting in low cancellation effectiveness for nonlinear distortion components, and further resulting in poor performance of the communication system.

[0053] Based on this, one embodiment of the present application provides a signal processing device shown in Figures 3a to 3d (the signal processing device may also be called a feedforward cancellation system). Multiple filter sub-circuits are used to separately perform sampling and filtering processes on the intermodulation signal at different sampling times, and an accumulation circuit accumulates the sampled and filtered signals output by the multiple filter sub-circuits to obtain an intermodulation cancellation signal. Therefore, high-precision amplitude and phase adjustment of the intermodulation signal is performed in the analog signal domain, resulting in reduced processing delay and improved processing accuracy.

[0054] The signal processing device may be applied to the aforementioned communication device supporting FDD, or may also be applied to communication devices supporting other duplex communication, or communication devices that do not support or use duplex communication, in order to reduce the effects of nonlinear distortion signals on the communication device. The other duplex communication may include a time division duplexing (TDD) communication scenario and an FDD+TDD communication scenario.

[0055] It may be understood that the signal processing device may be disposed between the PA on the transmit channel and the transmit filter of the duplexer, or between the PA on the transmit channel and the transmit filter on the transmit channel. Furthermore, a component with nonlinear distortion in a communication device may be directly or indirectly connected to the input of the signal processing device to cancel the nonlinear distortion introduced by the component using the signal processing device.

[0056] In the following, a signal processing device is described.

[0057] 3a to 3d are schematic diagrams of the structure of a signal processing device according to an embodiment of the present application. The signal processing device includes a splitter module #11, a delay 20, a combiner module #21, and a filter circuit 30. The splitter module #11 may be a component such as a coupler or splitter, and an example in which the first coupler 10 is the splitter module #1 will be used for the following description. The combiner module #21 may be a component such as a coupler or combiner, and an example in which the second coupler 40 is the combiner module #21 will be used for the following description. It can be understood that the splitter module #11 and the combiner module #21 may alternatively be implemented in other ways, which is not a limitation of the present application.

[0058] Based on the above description, the signal processing device shown in FIG. 3 a includes a first combiner 10 , a delay 20 , a second combiner 40 and a filter circuit 30 .

[0059] An input end of the first combiner 10 is coupled to a signal source of the signal processing device, an output end of the first combiner 10 is separately coupled to an input end of a delay unit 20 and an input end of a filter circuit 30, an output end of the delay unit 20 is coupled to a first input end of a second combiner 40, and an output end of the filter circuit 30 is coupled to a second input end of the second combiner 40. The filter circuit 30 includes a plurality of filter subcircuits 31 and an accumulation circuit 32, and output ends of the plurality of filter subcircuits 31 are coupled to an input end of the accumulation circuit 32. The signal source may be a baseband circuit and may output a baseband signal.

[0060] The first combiner 10 is configured to output a first sub-signal and a second sub-signal based on an input signal. The first sub-signal is output to the delay circuit 20, and the second sub-signal is output to the filter circuit 30. The first combiner 10 may be configured to split the input signal into the first sub-signal and the second sub-signal. The input signal is an analog signal. Specifically, the input signal is a signal obtained after nonlinear distortion is introduced into a signal output by a signal source. For example, the input signal may be a signal directly output by a component with nonlinear distortion introduced therein, or a signal obtained after the directly output signal passes through another component. For example, the input signal may be the output signal of a PA on a transmission channel. The input signal includes a desired signal (hereinafter referred to as a service signal) and an intermodulation signal. Both the first sub-signal and the second sub-signal include the intermodulation signal and the service signal. The signal processing device is configured to filter out the intermodulation signal to obtain the service signal. The power of the first sub-signal may be different from the power of the second sub-signal. For example, the power of the first sub-signal is greater than the power of the second sub-signal.

[0061] The delay 20 is configured to delay the first sub-signal to output the delayed signal to the second combiner 40. The delay amount of the delay 20 may be preset, and the delay amount may be used to match the processing delay of the filter circuit 30.

[0062] The filter circuit 30 includes a plurality of filter subcircuits 31 and an accumulation circuit 32. The plurality of filter subcircuits 31 are separately configured to sample the second sub-signal at different sampling times and perform filtering on the sampled signal obtained by the sampling to output a sampled and filtered signal. The accumulation circuit 32 is configured to accumulate the sampled and filtered signals output by the plurality of filter subcircuits 31 to obtain an intermodulation cancellation signal. In other words, the plurality of filter subcircuits 31 may be separately configured to perform amplitude and phase adjustment on the second sub-signal, and the accumulation circuit 32 is configured to obtain an intermodulation cancellation signal obtained after the second sub-signal is adjusted.

[0063] The second combiner 40 is configured to perform cancellation on the delayed signal based on the intermodulation cancellation signal and output the target signal. The second combiner 40 may subtract the intermodulation cancellation signal from the delayed signal to cancel the intermodulation signal in the delayed signal to obtain the target signal.

[0064] Furthermore, the signal processing device may further include an amplifier 50a, which is coupled between the filter circuit 30 and the second combiner 40. The amplifier 50a is configured to amplify the intermodulation cancellation signal output by the filter circuit 30 so that the amplitude of the intermodulation cancellation signal can match the amplitude of the intermodulation signal in the delayed signal.

[0065] Optionally, the signal processing device further includes a combiner module #22. As an example for the following description, the combiner module #22 is a third combiner 60. As shown in FIG. 3b, a first input end of the third combiner 60 is coupled to an output end of the first combiner 10 to obtain a second sub-signal, a second input end of the third combiner 60 is coupled to a signal source, and an output end of the third combiner 60 is coupled to an input end of the filter circuit 30.

[0066] The third combiner 60 is configured to extract the first intermodulation signal from the second sub-signal. Optionally, the signal output by the signal source and the second sub-signal are separately input to the third combiner 60, and the third combiner 60 outputs the first intermodulation signal after cancellation. In other words, with respect to the signals input to the third combiner 60, one is the second sub-signal and the other is a signal having the same source as the second sub-signal. The signal is used to extract the first intermodulation signal.

[0067] Optionally, the third combiner 60 may be replaced by the aforementioned equalizer, in which case the signal output by the equalizer is the first intermodulation signal. In other words, the combiner module #2 may be replaced by the aforementioned equalizer.

[0068] It can be understood that the third combiner 60 may alternatively be coupled between the filter circuit 30 and the second combiner 40. Alternatively, as shown in FIG. 3c, the third combiner 60 may be coupled between the filter circuit 30 and the amplifier 50a. Alternatively, as shown in FIG. 3d, the third combiner 60 may be coupled between the amplifier 50a and the second combiner 40. In other words, the first input end of the third combiner 60 may alternatively be coupled to the output end of the filter circuit 30 or the output end of the amplifier 50a, and the output end of the third combiner 60 may alternatively be coupled to the input end of the second combiner 40 or the input end of the amplifier 50a. It can be understood that in FIG. 3d, the second input end of the third combiner 60 may alternatively be coupled to the amplifier 50b, and the input end of the amplifier 50b is coupled to a signal source. By introducing the amplifier 50b, the signal of the signal source input to the third combiner 60 can match the power of the second sub-signal or the service signal within the second sub-signal.

[0069] The introduction of the third combiner 60 allows the service signal to be reduced to some extent before the signal enters the second combiner 40, thereby reducing the adverse effect on the service signal component in the delayed signal when the intermodulation cancellation signal is used to cancel the intermodulation signal in the delayed signal.

[0070] As an example for the following description, the apparatus includes a third combiner 60, which is coupled between the first combiner 10 and the filter circuit 30, i.e., as shown in Fig. 3b. It can be understood that when the filter circuit 30 is directly coupled to the first combiner 10, the first intermodulation signal in the filter circuit 30 in the following description is replaced by the second sub-signal.

[0071] Optionally, the signal processing device may further include an attenuator coupled between the first combiner 10 and the third combiner 60. The attenuator is configured to attenuate the second sub-signal so that the amplitude of the second sub-signal matches the amplitude of the service signal input to the third combiner 60.

[0072] 4, each of the plurality of filter subcircuits 31 includes a sample-and-hold circuit 311 and an amplitude adjustment circuit 312. The sample-and-hold circuit 311 is configured to sample and hold the first intermodulation signal at a sampling time point corresponding to the filter subcircuit 31 to output a sampled signal. The amplitude adjustment circuit 312 is configured to perform a filtering process on the sampled signal to adjust the amplitude and phase of the sampled signal and output the sampled and filtered signal. Sampling and holding may be understood as holding a sampled value for a period for a subsequent procedure after a sampled value is obtained at a sampling time point, and also as holding a new sampled value for a subsequent period for a subsequent procedure after a new sampled value is obtained at the next sampling time point. Holding may also be understood as sustaining, maintaining, or saving.

[0073] In a possible embodiment, the filter circuit 30 may be a switched capacitor analog filter, which may be in the form of multiple phases, with each phase of the multiple phases corresponding to one filter subcircuit 31. As shown in Figure 5, for each filter subcircuit 31, the sample and hold circuit 311 may include a switch SW, a capacitor C, and a buffer BF, and the amplitude adjustment circuit 312 includes a multiplier MUL. Optionally, the amplitude adjustment circuit 312 may further include a transconductance amplifier GM. The first end of the switch SW is the input end of the filter subcircuit 31, the second end of the switch SW, the first end of the capacitor C, and the first end of the buffer BF are coupled together, the second end of the capacitor C is grounded, the second end of the buffer BF is coupled to the first input end of the multiplier MUL, the second input end of the multiplier MUL is configured to receive the filtering coefficient c, the output end of the multiplier MUL is coupled to the input end of the transconductance amplifier GM, and the output end of the transconductance amplifier GM is the output end of the filter subcircuit 31.

[0074] It should be noted that FIG. 5 is illustrated using an example in which the plurality of filter subcircuits 31 includes nine filter subcircuits 31, and the switches, capacitors, buffers, multipliers, and transconductance amplifiers in the ith filter subcircuit 31 among the nine filter subcircuits 31, as well as the filtering coefficients corresponding to the multipliers, are represented as SWi, Ci, BFi, MULi, GMi, and ci, respectively, where the value of i ranges from 0 to 8.

[0075] Specifically, in the ith filter subcircuit 31, the switch SWi and the capacitor Ci may be configured to sample the first intermodulation signal at a sampling time corresponding to the filter subcircuit 31, the buffer BFi may be configured to hold the sampled signal, the multiplier MULi may be configured to adjust the amplitude of the sampled signal based on the filtering coefficient ci, and the transconductance amplifier GMi may be configured to amplify the power of the adjusted sampled signal. The filtering coefficient c corresponding to the multiplier MUL in different filter subcircuits 31 may be different. The amplification factors of the transconductance amplifiers GM in different filter subcircuits 31 may also be different. The buffers BF in different filter subcircuits 31 hold the sampled signals for the same length of time.

[0076] Optionally, the opening and closing of the switch SW may be controlled by a controller. The filtering coefficients c of the multipliers MUL in the different filter sub-circuits 31 may be set by the controller. The amplification factors of the transconductance amplifiers GM in the different filter sub-circuits 31 may be set by the controller. The controller may be a controller of a device to which the signal processing device is applied. For example, the controller may be a processor or a system on chip (SoC).

[0077] For example, in the signal processing device, it is assumed that the first intermodulation signal is represented as X, the intermodulation cancellation signal output by the filter circuit 30 is represented as Y, the signal output by the delay circuit is represented as Y', the signal output by the amplifier 50 after amplifying the intermodulation cancellation signal Y is represented as Gain×Y, the target signal output by the second combiner 40 is Error, and the sequence including multiple filtering coefficients is represented as Cn. In this case, Error must satisfy the following equation (1), where

number

number

[0078] FIG. 6 is a timeline diagram of the operation of the filter circuit 30 corresponding to FIG. 5. The operating principle of the filter circuit 30 will be described in detail below with reference to FIG. 6. In FIG. 6, X represents the first intermodulation signal, x1 to x17 represent data streams of the first intermodulation signal X at different times, and p0 to p8 represent drive signals for the sample-and-hold circuits 311 in the nine filter subcircuits 31, respectively. The sample-and-hold circuits 311 temporarily sample and hold the corresponding drive signal at the rising edge, and then temporarily sample and hold again until the next rising edge of the drive signal arrives. For example, when the first rising edge of p0 arrives, SW0, C0, and BF0 sample to obtain the value of X at this time, record this value as x0, and hold this value until the next rising edge of p0 arrives. It can be seen that during the period between the sampled value x0 being obtained and the next rising edge of p0 arriving and the new sampled value x9 being obtained, the value output from BF0 to MUL0 is always x0. It can be understood that the rising edges of p0 to p8 are used to trigger sampling, and the falling edges may not have any function in the filter subcircuit. In a specific implementation, it can be understood that the rising edge of the drive signal does not have to appear as an instantaneous jump. In this case, performing sample and hold temporarily on the rising edge of the drive signal may be performing sample and hold when the change in the drive signal reaches a specified threshold.

[0079] The sampling signals obtained after the nine filter sub-circuits 31 perform sampling and holding based on the aforementioned process are respectively represented as d0 to d8, in other words, d0 to d8 are respectively the sampling signals output by the sample-and-hold circuits 311 in the nine filter sub-circuits 31. Assuming that the time point corresponding to x8 is the output time point of the filter circuit 30, and the filtering coefficients corresponding to p0 to p8 are respectively c0 to c8, the signals correspondingly output by the filter circuit 30 at different time points satisfy the following equation (2): y(8)=c0×x0+c1×x1+c2×x2+c3×x3+c4×x4+c5×x5+c6×x6+c7×x7+c8×x8 y(9)=c0×x9+c1×x1+c2×x2+c3×x3+c4×x4+c5×x5+c6×x6+c7×x7+c8×x8 y(10)=c0×x9+c1×x10+c2×x2+c3×x3+c4×x4+c5×x5+c6×x6+c7×x7+c8×x8 y(11)=c0×x9+c1×x10+c2×x11+c3×x3+c4×x4+c5×x5+c6×x6+c7×x7+c8×x8 y(12)=c0×x9+c1×x10+c2×x11+c3×x12+c4×x4+c5×x5+c6×x6+c7×x7+c8×x8 ……(2)

[0080] The controller may directly configure or input filtering coefficients or inputs corresponding to each filter subcircuit 31, or the calculation circuit 82 may obtain filtering coefficients corresponding to each filter subcircuit 31 through calculation and input the filtering coefficients to each filter subcircuit. The filtering coefficients corresponding to the filter subcircuits 31 may have different values ​​at different times. The values ​​of the filtering coefficients and the changes to the filtering coefficients may be controlled by the controller. For example, at a time corresponding to x8, the filtering coefficient corresponding to the first filter subcircuit may be c0 and the filtering coefficient corresponding to the second filter subcircuit may be c1; at a time corresponding to x9, the filtering coefficient corresponding to the first filter subcircuit may be changed to c0' and the filtering coefficient corresponding to the second filter subcircuit may be changed to c1'.

[0081] Optionally, as shown in Figure 5, filter circuit 30 may further include a variable-gain amplifier (VGA) 33 coupled to the output of storage circuit 32. VGA 33 may be configured to amplify the gain of the intermodulation cancellation signal output by filter circuit 30 so that the gain of the intermodulation cancellation signal can match the gain of the intermodulation signal in the transmit delayed signal.

[0082] In a possible embodiment, as shown in FIG. 7 , the apparatus further includes a post-distortion circuit 70a coupled to the third combiner 60. The input of the post-distortion circuit 70a is configured to receive a first service signal, which is a signal output by a signal source of the signal processing device. The first service signal may be a signal used to input to a nonlinear distortion component. For example, the first service signal may be a baseband signal generated by a baseband circuit, and the signal obtained after the power of the first service signal is amplified is the aforementioned input signal of the signal processing device. Optionally, the post-distortion circuit 70a includes a primary carrier cancellation circuit configured to provide the first service signal. The primary carrier cancellation circuit may be implemented using a digital adaptive filter to compensate for the amplitude and phase plane of the hardware link. Optionally, the post-distortion circuit 70a further includes a nonlinear post-distortion circuit and a summing circuit. The nonlinear post-distortion circuit is configured to inject a second intermodulation signal into the first service signal. The adder circuit is configured to add the first service signal and the second intermodulation signal to obtain a second service signal and output the second service signal to the third combiner 60. After receiving the second service signal, the third combiner 60 may subtract the second service signal from the second sub-signal to obtain a first intermodulation signal. When the difference between the frequency of the second intermodulation signal and the frequency of the first service signal is equal to or greater than a first threshold, the second intermodulation signal may be referred to as a far-end intermodulation signal. When the difference between the frequency of the first intermodulation signal and the frequency of the first service signal is less than a first threshold, the first intermodulation signal may be referred to as a near-end intermodulation signal. In other words, a nonlinear post-distortion circuit and an adding circuit are further introduced, which allows the third combiner 60 to further filter out intermodulation signals that are not within the receiving frequency band from the first sub-signal, so that the processing of the filter circuit 30 focuses on intermodulation signals within the receiving frequency band, which in turn helps to improve the cancellation effect of intermodulation signals within the receiving frequency band.Intermodulation signals that are not within the receiving frequency band can be filtered out by a filter at a subsequent stage in the communication device. It can be understood that the third combiner 60 can be further coupled to the position shown in Figure 3c or 3d. In this case, the post-distortion circuit 70a can also be coupled to the third combiner 60. When the third combiner 60 is coupled to the position shown in Figure 3d, the amplifier 50b can be coupled between the post-distortion circuit 70a and the third combiner 60.

[0083] In another possible embodiment, as shown in FIG. 7, the apparatus further includes a predistortion circuit 70b. The predistortion circuit 70b is disposed before the nonlinear distortion component. For example, the predistortion circuit is coupled to the input end of the PA. The predistortion circuit 70b may also be referred to as a nonlinear predistortion circuit and is configured to inject a third intermodulation signal into the first service signal to obtain a predistortion signal. After the predistortion passes through the nonlinear distortion component, the distortion caused by the nonlinear component can be canceled to a certain extent, thereby reducing the intermodulation signal in the output signal of the nonlinear component. The third intermodulation signal is a near-end intermodulation signal. The predistortion circuit 70b may be implemented using a digital adaptive filter.

[0084] 7 , the apparatus further includes a filtering coefficient calculation circuit 80. The filtering coefficient calculation circuit 80 has two input terminals, which are used to receive the first intermodulation signal and the target signal, respectively. The filtering coefficient calculation circuit 80 is configured to output a plurality of filtering coefficients based on the first intermodulation signal and the target signal, where the plurality of filtering coefficients are filtering coefficients of the plurality of filter subcircuits 31. Optionally, the filtering coefficient calculation circuit 80 may output the plurality of filtering coefficients to a controller, and the controller assigns the plurality of filtering coefficients to different filter subcircuits 31 of the plurality of filter subcircuits 31.

[0085] In a possible embodiment, the filtering coefficient calculation circuit 80 includes a splitter module #12 and a calculation circuit 82. As described above, the splitter module may be a component such as a combiner or a splitter. For the purposes of explanation below, the fourth combiner 81 is used as an example of the splitter module #12. An input end of the fourth combiner 81 is coupled to the output end of the second combiner 40, a first output end of the fourth combiner 81 is coupled to a first input end of the calculation circuit 82, and a second input end of the calculation circuit 82 is configured to receive the first intermodulation signal. The fourth combiner 81 is configured to obtain a target sub-signal from the target signal by combining. For example, the fourth combiner 81 may be a splitter and configured to obtain a target sub-signal from the target signal by splitting. The power of the target sub-signal may be smaller than the power of the target signal. The calculation circuit 82 is configured to output a plurality of filtering coefficients based on the first intermodulation signal and the target sub-signal. When the target transmission sub-signal is represented as Error, the first intermodulation signal is represented as X, and the plurality of filtering coefficients is represented as C(n) (n represents the number of iterations), the solution formula for the plurality of filtering coefficients can be expressed as the following Equation (3): where mu represents the iteration step of each iteration, and conj represents the conjugate operation.

number

[0086] 7 , the apparatus further includes a parameter calibration circuit 90 coupled to the filter circuit 30. The parameter calibration circuit 90 has two inputs configured to receive the first intermodulation signal and the intermodulation cancellation signal, respectively. The parameter calibration circuit 90 is configured to determine mismatch parameters of the filter circuit 30 based on the first intermodulation signal and the intermodulation cancellation signal. The mismatch parameters are used to calibrate the filter circuit 30 so that performance of the filter subcircuits is adjusted. Optionally, the mismatch parameters include at least one of the following: a sampling instant mismatch value, a gain mismatch value, or a DC current mismatch value.

[0087] The filter circuit 30 is essentially a filter with a multi-phase architecture. Since the filter circuit 30 is implemented by an analog circuit, parameter mismatches, such as sampling time mismatches, gain mismatches, or DC current mismatches, may exist between multiple phases in the actual application process. Assuming that the filter circuit 30 includes M filter subcircuits 31 (i.e., M phases), parameter adaptation can be performed by applying f to the spectrum of the output signal of the filter circuit 30. s / M±f in This generates spurious signals of f in represents the frequency of the first intermodulation signal. The spurious energy generated by the parameter mismatch satisfies the following equation (4), where X represents the first intermodulation signal, Y represents the intermodulation cancellation signal, and C represents the filtering coefficient:

number

number

[0088] The aforementioned mismatch parameter is assumed to be denoted as S. The value of the mismatch parameter can be determined by injecting a known dither signal into X. If the known dither signal is denoted as Δ, then after the known dither signals (Δ1 and Δ2) are injected, two corresponding spurious energies P Δ1 and P Δ2 can be obtained, and the mismatch value (also called the correction value) of the mismatch parameter satisfies the following equation (5): where mu is the step of each iterative correction.

number

[0089] The aforementioned parameter mismatch is corrected using the parameter calibration circuit 90, so that the spurious energy can be reduced and the cancellation performance can be improved. Optionally, the parameter calibration circuit 90 may further send the determined mismatch parameters to the controller, so that the controller corrects the filter circuit 30 based on the corresponding mismatch parameters, thereby ensuring that the cancellation performance of the device is not affected by the spurious energy.

[0090] 7, the apparatus further includes a power amplifier PA and a duplexer DUX. Before the power amplifier PA is coupled to the input end of the first coupler 10, the power amplifier PA is configured to amplify the output signal of the predistortion circuit 70b, or is configured to amplify the first service signal and output the signal to the first coupler 10. The duplexer DUX is coupled between the second output end of the fourth coupler 81 or the output end of the second coupler 40 and the antenna. The duplexer DUX is configured to receive a target signal, perform transmit filtering on the target signal, and transmit the processed signal via the antenna.

[0091] It should be noted that the signal processing device may alternatively not include the power amplifier PA or the duplexer DUX. For example, the power amplifier PA and the duplexer DUX may be located independently of the device. The signal processing device may also be referred to as a feedforward cancellation system. This is not specifically limited in this embodiment of the present application.

[0092] The signal processing device provided in this embodiment of the present application can be applied to a multi-antenna scenario. In this case, the number of signal processing devices can be the same as the number of power amplifiers PA. There may be no binding relationship between the number of signal processing devices and the number of antennas, that is, one or more antennas may correspond to one signal processing device.

[0093] Optionally, the filter circuit 30 may be further integrated with one or more of the post-distortion circuit 70a, the filtering coefficient calculation circuit 80, or the parameter calibration circuit 90 on one chip.

[0094] In one example, as shown in Figure 8, the filter circuit 30 is integrated on a single chip with the calculation circuit 81 in the filtering coefficient calculation circuit 80 and the parameter calibration circuit 90. In another example, as shown in Figure 9, the filter circuit 30 is integrated on a single chip with the post-distortion circuit 70a, the calculation circuit 81 in the filtering coefficient calculation circuit 80, and the parameter calibration circuit 90.

[0095] Optionally, when the calculation circuit 81 and the filter circuit 30 are integrated on one chip, the filtering coefficient calculation circuit 80 may further include a first switch circuit 83 and a second switch circuit 84 coupled between the fourth combiner 82 and the calculation circuit 81. The first switch circuit 83 may be disposed off-chip, and the second switch circuit 84 may be integrated on-chip. In this manner, the hardware link between the first switch circuit 83 and the second switch circuit 84 may further implement time division multiplexing; in other words, by opening and closing the first switch circuit 83 and the second switch circuit 84, multiple fourth combiners 81 can share one calculation circuit 82 to improve the utilization of the hardware link and reduce the cost of the device.

[0096] In this embodiment of the present application, the first combiner 10 is configured to output a first sub-signal and a second sub-signal based on an input signal, the delay 20 is configured to delay the first sub-signal to output a delayed signal, the third combiner 60 is configured to extract the first intermodulation signal from the second sub-signal, the filter circuit 30 includes a plurality of filter sub-circuits 31 and an accumulation circuit 32, each of the plurality of filter sub-circuits 31 is configured to perform analog domain sampling and filtering on the first intermodulation signal at a different sampling time, the accumulation circuit 32 is configured to accumulate the sampled and filtered signals output by the plurality of filter sub-circuits 31 to obtain an intermodulation cancellation signal, and the second combiner 40 is configured to output a target signal based on the intermodulation cancellation signal and the delayed signal. In other words, the plurality of filter sub-circuits 31 and the accumulation circuit 32 included in the filter circuit 30 can perform high-precision analog domain sampling and amplitude phase adjustment of the first intermodulation signal in the analog signal domain using a polyphase sample-and-hold circuit and amplitude phase adjustment. It can be seen that a larger number of phases in the multi-phase filter, i.e., a larger number of filter subcircuits 31, indicates more sampling data of the first intermodulation signal at a given time and higher accuracy of amplitude and phase adjustment. In addition, because the filter circuit 30 performs analog-domain processing, additional analog-to-digital conversion is unnecessary, effectively reducing delay. Therefore, when the delay circuit 20 provides a very small delay, equalization processing of the intermodulation signal can be performed, thereby improving processing accuracy while reducing processing delay. In addition, the predistortion circuit 70b and the postdistortion circuit 70a can further improve the cancellation effect on the intermodulation signal within the reception frequency band, thereby reducing system costs. Using the filtering coefficient calculation circuit 80 and the parameter calibration circuit 90, high performance of the filter circuit 30 can be further ensured.

[0097] Based on this, an embodiment of the present application further provides a chip, which includes a filter circuit 30. For a specific description of the filter circuit, please refer to the above description of the filter circuit 30. In this embodiment of the present application, details will not be described again here.

[0098] In another aspect, an embodiment of the present application further provides a communication device. The communication device may be a base station or a terminal. The communication device includes a baseband circuit and a signal processing device provided in any one of Figures 3a to 9. For a specific description of the signal processing device, please refer to the above description. In this embodiment of the present application, details will not be described again here.

[0099] It should be understood that in some embodiments provided in the present application, the different devices disclosed may be implemented in other ways. For example, the device embodiments described are merely examples. For example, the division into modules or units is merely a logical division of functions, and other divisions may be used in actual implementation. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not implemented.

[0100] The units described as separate parts may or may not be physically separate, and the parts shown as units may be one or more physical units, located in one place, or distributed in different places. Some or all of the units may be selected based on actual requirements to achieve the objectives of the solutions of the embodiments.

[0101] In addition, the functional units in the embodiments of the present application may be integrated into one processing unit, each unit may exist physically alone, or two or more units may be integrated into one unit. The integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0102] In conclusion, the above description is merely a specific embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications or replacements within the technical scope disclosed in the present application shall fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims. [Explanation of symbols]

[0103] 10 First Coupler 20 Delay Device 30 Filter Circuit 31 Filter Subcircuit 32 Storage circuit 33 Variable Gain Amplifier 40 Second Coupler 50a amplifier 50b amplifier 60 Third Coupler 70a Post-Distortion Circuit 70b Predistortion Circuit 80 Filtering coefficient calculation circuit 81 Fourth Coupler 82 Calculation circuit 83 First switch circuit 84 First switch circuit 90 Parameter Calibration Circuit 311 Sample and hold circuit 312 Amplitude adjustment circuit

Claims

1. A signal processing device comprising a first splitter module, a first combiner module, a delay device, and a filter circuit, the first splitter module is coupled to a signal source of the signal processing device, and an output end of the first splitter module is coupled to an input end of the delay device and an input end of the filter circuit separately; an output of the delay unit coupled to a first input of the first combiner module; an output terminal of the filter circuit coupled to a second input terminal of the first combiner module, the filter circuit comprising a plurality of filter subcircuits and a storage circuit, the output terminals of the plurality of filter subcircuits coupled to an input terminal of the storage circuit; Signal processing device.

2. Each of the plurality of filter subcircuits comprises:

10. The apparatus of claim 1, comprising a sample and hold circuit and an amplitude adjustment circuit, an output of the sample and hold circuit coupled to a first input of the amplitude adjustment circuit.

3. the sample-and-hold circuit includes a switch, a capacitor, and a buffer; the amplitude adjustment circuit includes a multiplier; a first end of the switch is an input of the filter subcircuit, a second end of the switch, a first end of the capacitor, and a first end of the buffer are coupled together, a second end of the capacitor is grounded, and a second end of the buffer is coupled to a first input of the multiplier; 3. The apparatus of claim 2.

4. The apparatus of claim 3 , wherein the amplitude adjustment circuit further comprises a transconductance amplifier coupled to an output of the multiplier.

5. The apparatus of claim 1 , wherein the filter circuit further comprises a variable gain amplifier coupled to an output of the storage circuit.

6. the apparatus further comprises a filtering coefficient calculation circuit; an output terminal of the filtering coefficient calculation circuit is coupled to a second input terminal of the amplitude adjustment circuit; 3. The apparatus of claim 2.

7. the filtering coefficient calculation circuit comprises a second splitter module and a calculation circuit; an input end of the second splitter module is coupled to the output end of the first combiner module, a first output end of the second splitter module is coupled to a first input end of the calculation circuit, and a second input end of the calculation circuit is coupled to an output end of the second combiner module; 7. The apparatus of claim 6.

8. The apparatus of claim 1 , further comprising a parameter calibration circuit coupled to the filter circuit.

9. 10. The apparatus of claim 1, further comprising: a second combiner module, wherein a first input end of the second combiner module is coupled to the output end of the first splitter module, a second input end of the second combiner module is coupled to the signal source, and an output end of the second combiner module is coupled to the input end of the filter circuit.

10. 10. The apparatus of claim 9, further comprising an attenuator, the attenuator coupled between the first splitter module and the second combiner module.

11. 10. The apparatus of claim 1, further comprising: a second combiner module, wherein a first input of the second combiner module is coupled to the output of the filter circuit, a second input of the second combiner module is coupled to the signal source, and an output of the second combiner module is coupled to the second input of the first combiner module.

12. The apparatus of claim 11 , further comprising an amplifier coupled to the second input of the second combiner module.

13. 10. The apparatus of claim 9, further comprising a post-distortion circuit, the post-distortion circuit coupled between the signal source and the second combiner module.

14. The apparatus of claim 13 , wherein the post-distortion circuit comprises a digital adaptive filter.

15. Further comprising an equalizer, 2. The apparatus of claim 1, wherein a first input of the equalizer is connected to the output of the first splitter module, a second input of the equalizer is connected to the signal source, and an output of the equalizer is connected to the input of the filter circuit.

16. The device of claim 1 , wherein the filter circuit is integrated on a chip.

17. 17. The apparatus of claim 16, wherein the filter circuit is integrated on the chip with at least one of the following: a filtering coefficient calculation circuit, a parameter calibration circuit, or a post-distortion circuit.

18. 10. The apparatus of claim 1, further comprising: a power amplifier coupled between an input of the first splitter module and the signal source; and a duplexer coupled to the output of the first combiner module.

19. A communication device, said communication device comprising a baseband circuit and a signal processing apparatus according to any one of claims 1 to 18.

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