Photoelectric front-end amplification circuit and photoelectric imaging equipment

Abstract

The invention provides a photoelectric front-end amplifying circuit and photoelectric imaging equipment, the photoelectric front-end amplifying circuit comprises an amplifying module and a T-shaped feedback module, differential input signals are amplified through the amplifying module, and differential output signals are output outwards; the T-type feedback module is connected in series between the input end and the output end of the amplification module, the gain of the amplification module is adjusted through a pseudo resistor in the T-type feedback module, and the linear dynamic range of the whole circuit is expanded through a quasi floating gate structure in the T-type feedback module. The T-type feedback module is arranged between the input end and the output end of the amplification module, the wide-range adjustable feedback resistance value is achieved through a pseudo resistor of a gated PMOS tube, and the output current requirements of various detectors are met; through the quasi-floating gate and quasi-floating N-Well technology, high-frequency noise introduced by high-order distortion and junction capacitance is remarkably suppressed, and the linear dynamic range is widened; the T-type feedback module is low in noise, wide in bandwidth and low in power consumption; the circuit integration level is high and the silicon wafer area is compact.

Description

A photoelectric front-end amplifier circuit and a photoelectric imaging device Technical Field

[0001] This invention relates to the field of analog front-end circuit technology, and more particularly to an optoelectronic front-end amplifier circuit and an optoelectronic imaging device. Background Technology

[0002] In photoelectric detection systems, the front-end amplifier circuit is a crucial component determining system performance. Its main function is to convert the weak photocurrent signal output by the photodetector into a voltage signal suitable for subsequent processing, while maximizing the signal-to-noise ratio in the process. The transimpedance amplifier, as the most commonly used front-end architecture, firstly achieves precise current-to-voltage conversion through a feedback resistor; secondly, by adjusting the parameters of this feedback network, the circuit's gain, bandwidth, and noise characteristics can be simultaneously set, thereby optimizing the system's ability to detect weak light signals.

[0003] In existing technologies, transimpedance amplifiers are mainly implemented through the following aspects: 1) Using a simple architecture of operational amplifiers and passive resistors, the current-to-voltage conversion of the photodiode is completed through a single large-value metal thin film or polysilicon resistor. However, once the resistance reaches a certain level, the resistor area increases and the parasitic capacitance rises significantly, leading to a sharp drop in the -3dB bandwidth. For example, when achieving a 1000x gain using this method, the bandwidth remains at a low level, and the resistor noise density is high. 2) Splitting the large resistor into a T-type feedback network combining capacitors and resistors, the bandwidth extension is improved through capacitor compensation at intermediate nodes, achieving a -3dB bandwidth extension, but the overall thermal noise is higher than that of a single resistor. 3) Using two PMOS transistors in parallel to form a pseudo-resistor, the gain can be adjusted within a range of 100,000 times. However, this parallel structure suffers from distortion and limited dynamic range when the input voltage swing is limited. 4) The gain and bandwidth pressure are distributed by using a multi-stage cascaded amplifier structure. High gain and low bandwidth are obtained based on the first-stage feedback, and high bandwidth is achieved by the second-stage feedback, keeping the noise density at a low level. However, the overall power consumption of the cascaded structure increases and the circuit layout becomes larger. Summary of the Invention

[0004] This invention provides an optoelectronic front-end amplifier circuit and an optoelectronic imaging device to solve the technical problems of the above-mentioned transimpedance amplifier, such as large feedback impedance, narrow bandwidth, high noise, and poor linearity.

[0005] In a first aspect, the present invention provides an optoelectronic front-end amplifier circuit, comprising: an amplification module having an input terminal connected to a differential input signal, amplifying the differential input signal, and outputting a differential output signal; and a T-type feedback module connected between the input and output terminals of the amplification module, adjusting the gain of the amplification module based on a pseudo-resistance in the T-type feedback module, and improving the linear dynamic range of the optoelectronic front-end amplifier circuit through a quasi-floating gate structure in the T-type feedback module.

[0006] In one embodiment of the present invention, the optoelectronic front-end amplification circuit further includes a common-mode feedback module. The input terminal of the common-mode feedback module is connected to the output terminal of the amplification module, which monitors the average voltage of the two outputs of the amplification module in real time, compares the average voltage with a reference voltage, and adjusts the common-mode voltage input to the amplification module to a preset voltage threshold based on the comparison result.

[0007] In one embodiment of the present invention, the optoelectronic front-end amplifier circuit further includes a current mirror module, which replicates a reference current under the control of two current control signals to provide a bias current to the amplification module and the common-mode feedback module.

[0008] In one embodiment of the present invention, the amplification module includes a first-stage amplification unit and a second-stage amplification unit. The first-stage amplification unit performs current-to-voltage conversion and first-stage amplification on the differential input signal to obtain an intermediate signal. The second-stage amplification unit performs second-stage amplification on the intermediate signal and adjusts the signal swing of the intermediate signal to obtain the differential output signal.

[0009] In one embodiment of the present invention, the first-stage amplification unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the source of the first PMOS transistor is also connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is connected to a power supply voltage. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the first NMOS transistor is connected to the gate of the second PMOS transistor, and the source of the first NMOS transistor is connected to the source of the second NMOS transistor. The source of the second NMOS transistor is grounded. The gates of the first and second PMOS transistors are the input terminals of the first-stage amplification unit, and the drains of the first and second NMOS transistors are the output terminals of the second-stage amplification unit. The gate of the third PMOS transistor is connected to a bias current.

[0010] In one embodiment of the present invention, the second-stage amplification unit includes a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The source of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, and the source of the fourth PMOS transistor is also connected to a power supply voltage. The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor. The gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor via the first resistor and the first capacitor. The drain of the fourth PMOS transistor is also connected to the drain of the third NMOS transistor. The gate of the fifth PMOS transistor is connected to the drain of the third NMOS transistor via the second resistor and the fifth NMOS transistor via the second resistor and the fifth NMOS transistor. The second capacitor is connected to the drain of the fifth PMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor, the drain of the third NMOS transistor is connected to the first terminal of the third resistor via the third capacitor, the drain of the fourth NMOS transistor is connected to the first terminal of the fourth capacitor via the fourth capacitor, the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor via the fifth resistor and the sixth resistor, the source of the third NMOS transistor is connected to the source of the fourth NMOS transistor, and the source of the third NMOS transistor is grounded. The second terminals of the third resistor and the fourth resistor are the input terminals of the second-stage amplification unit, and the common terminal of the fifth resistor and the sixth resistor is the driving terminal of the second-stage amplification unit.

[0011] In one embodiment of the present invention, the T-type feedback module includes two T-type feedback units. Each T-type feedback unit includes a pseudo resistor, a sixth PMOS transistor, a seventh resistor, an eighth resistor, a ninth resistor, and a fifth capacitor. The first end of the pseudo resistor is connected to the gate of the sixth PMOS transistor. The first end of the pseudo resistor is also connected to the source of the sixth PMOS transistor via the fifth capacitor. The source of the sixth PMOS transistor is grounded via the seventh resistor. The source of the sixth PMOS transistor is connected to the first end of the eighth resistor. The N-well of the sixth PMOS transistor is connected to the source of the sixth PMOS transistor via the ninth resistor. The drain of the sixth PMOS transistor is the input terminal of the T-type feedback unit. The second end of the pseudo resistor is the control terminal of the T-type feedback unit. The second end of the eighth resistor is the output terminal of the T-type feedback unit.

[0012] In one embodiment of the present invention, the common-mode feedback module includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a tenth resistor, an eleventh resistor, a sixth capacitor, and a seventh capacitor. The source of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, and the source of the seventh PMOS transistor is also connected to a power supply voltage. The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, and the gate of the eighth PMOS transistor is also connected to the drain of the eighth PMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the fifth NMOS transistor is connected to... The source of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, which is also connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor is grounded. The gate of the sixth NMOS transistor is connected to the first terminal of the tenth resistor. The gate of the sixth NMOS transistor is also connected to the first terminal of the eleventh resistor. The sixth capacitor is connected in parallel with the tenth resistor, and the seventh capacitor is connected in parallel with the eleventh resistor. The gate of the fifth NMOS transistor is connected to the reference voltage, and the gate of the seventh NMOS transistor is connected to the bias current. The second terminals of the tenth and eleventh resistors are the two differential input terminals of the common-mode feedback module. The drain of the seventh PMOS transistor is the output terminal of the common-mode feedback module.

[0013] Secondly, this application provides an optoelectronic imaging device, which includes the optoelectronic front-end amplifier circuit as described above.

[0014] The beneficial effects of this invention are as follows: This invention provides a photoelectric front-end amplifier circuit and a photoelectric imaging device. The photoelectric front-end amplifier circuit includes an amplification module and a T-type feedback module. The amplification module amplifies the differential input signal and outputs a differential output signal. The T-type feedback module is connected in series between the input and output terminals of the amplification module. The gain of the amplification module is adjusted by a pseudo-resistor in the T-type feedback module, and the linear dynamic range of the overall circuit is improved by a quasi-floating gate structure in the T-type feedback module. This invention sets up a T-type feedback module between the input and output terminals of the amplification module, and uses the pseudo-resistance of a gated PMOS transistor to achieve a wide-range adjustable feedback resistance value to meet the output current requirements of various detectors. Furthermore, through quasi-floating gate and quasi-floating N-Well technology, it significantly suppresses high-order distortion and high-frequency noise introduced by junction capacitance, thereby improving the linear dynamic range. The T-type feedback module balances low noise, wide bandwidth, and low power consumption; the circuit has high integration and a compact silicon wafer area. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0016] In the accompanying drawings: Figure 1 is a block diagram of the optoelectronic front-end amplifier circuit provided in an embodiment of the present invention; Figure 2 is a block diagram of the optoelectronic front-end amplifier circuit provided in an embodiment of the present invention, including a common-mode feedback module and a current mirror module; Figure 3 is a detailed structural diagram of the amplification module, common-mode feedback module, and current mirror module provided in an embodiment of the present invention; Figure 4 is a detailed structural diagram of the T-type feedback module provided in an embodiment of the present invention; Figure 5 is a curve showing the relationship between transimpedance gain and control voltage change provided in an embodiment of the present invention; Figure 6 is a curve showing the input reference thermal noise current of the existing single-resistor feedback structure and the T-type feedback module provided in an embodiment of the present invention.

[0017] Figure reference numerals: 110 - Amplification module; 120 - T-type feedback module; 130 - Common-mode feedback module; 140 - Current mirror module; Vin, Vip - Differential input signals; Von, Vop - Differential output signals; Vocm - Reference voltage; VS1 - First current control signal; VS2 - Second current control signal. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0021] To address the aforementioned problems, as shown in Figure 1, this application provides a photoelectric front-end amplifier circuit, comprising: an amplification module 110, whose input terminal is connected to differential input signals (Vin, Vip), amplifying the differential input signals (Vin, Vip), and outputting differential output signals (Von, Vop); and a T-type feedback module 120, which is connected between the input and output terminals of the amplification module 110, adjusting the gain of the amplification module 110 based on the pseudo-resistance in the T-type feedback module 120, and improving the linear dynamic range of the photoelectric front-end amplifier circuit through the quasi-floating gate structure in the T-type feedback module 120.

[0022] As shown in Figure 2, the optoelectronic front-end amplifier circuit also includes a common-mode feedback module 130. The input terminal of the common-mode feedback module 130 is connected to the output terminal of the amplifier module 110. It monitors the average voltage of the two differential output terminals of the amplifier module 110 in real time, compares the average voltage with the reference voltage Vocm, and adjusts the common-mode voltage input to the amplifier module 110 to a preset voltage threshold based on the comparison result.

[0023] In detail, as shown in Figure 2, the optoelectronic front-end amplifier circuit also includes a current mirror module 140, which replicates the reference current under the control of two current control signals (VS1, VS2) to provide bias current to the amplifier module 110 and the common-mode feedback module 130.

[0024] In detail, the amplification module 110 includes a first-stage amplification unit and a second-stage amplification unit. The first-stage amplification unit performs current-to-voltage conversion and first-stage amplification on the differential input signals (Vin, Vip) to obtain an intermediate signal. The second-stage amplification unit performs second-stage amplification on the intermediate signal and adjusts the signal swing of the intermediate signal to obtain a differential output signal (Von, Vop).

[0025] More specifically, as shown in Figure 3, the first-stage amplification unit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, and a second NMOS transistor NM2. The source of the first PMOS transistor PM1 is connected to the source of the second PMOS transistor PM2, and the source of the first PMOS transistor PM1 is also connected to the drain of the third PMOS transistor PM3. The source of the third PMOS transistor PM3 is connected to the power supply voltage VDD. The drain of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor NM1, and the drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2. The gate of transistor 1 is connected to the gate of the second PMOS transistor PM2. The source of the first NMOS transistor NM1 is connected to the source of the second NMOS transistor NM2. The source of the second NMOS transistor NM2 is grounded. The gates of the first PMOS transistor PM1 and the second PMOS transistor PM2 are the input terminals of the first stage amplifier unit. The gate of the first PMOS transistor PM1 is connected to one end of the differential input signal Vin, and the gate of the second PMOS transistor PM2 is connected to the other end of the differential input signal Vip. The drains of the first NMOS transistor NM1 and the second NMOS transistor NM2 are the output terminals of the second stage amplifier unit. The gate of the third PMOS transistor PM3 is connected to the bias current.

[0026] In detail, as shown in Figure 3, the second-stage amplification unit includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The source of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5, and the source of the fourth PMOS transistor PM4 is also connected to the power supply voltage VDD. The gate of the fourth PMOS transistor PM4 is connected to the gate of the fifth PMOS transistor PM5. The gate of the fourth PMOS transistor PM4 is connected to the drain of the fourth PMOS transistor PM4 after passing through the first resistor R1 and the first capacitor C1. The drain of the fourth PMOS transistor PM4 is also connected to the drain of the third NMOS transistor NM3. The gate of the fifth PMOS transistor PM5 is connected to the fifth PMOS transistor PM5 after passing through the second resistor R2 and the second capacitor C2. The drain of the fifth PMOS transistor PM5 is connected to the drain of the fourth NMOS transistor NM4. The drain of the third NMOS transistor NM3 is connected to the first terminal of the third resistor R3 via the third capacitor C3. The drain of the fourth NMOS transistor NM4 is connected to the first terminal of the fourth capacitor C4 via the fourth capacitor C4. The gate of the third NMOS transistor NM3 is connected to the gate of the fourth NMOS transistor NM4 via the fifth resistor R5 and the sixth resistor R6. The source of the third NMOS transistor NM3 is connected to the source of the fourth NMOS transistor NM4. The source of the third NMOS transistor NM3 is grounded. The second terminals of the third resistor R3 and the fourth resistor R4 are the input terminals of the second-stage amplifier unit. The second terminal of the third resistor R3 is connected to the drain of the first PMOS transistor. The second terminal of the fourth resistor R4 is connected to the drain of the second PMOS transistor. The common terminal of the fifth resistor R5 and the sixth resistor R6 is the driving terminal of the second-stage amplifier unit. The driving terminal of the second-stage amplifier unit is connected to the gate of the first NMOS transistor NM1.

[0027] More specifically, as shown in Figure 4, the T-type feedback module 120 includes two T-type feedback units. Each T-type feedback unit includes a pseudo-resistor RL, a sixth PMOS transistor PM6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a fifth capacitor C5. The first end of the pseudo-resistor RL is connected to the gate of the sixth PMOS transistor PM6. The first end of the pseudo-resistor RL is also connected to the source of the sixth PMOS transistor PM6 via the fifth capacitor C5. The source of the sixth PMOS transistor PM6 is grounded via the seventh resistor R7. The source of the sixth PMOS transistor PM6 is connected to the first end of the eighth resistor R8. The N-well of the sixth PMOS transistor PM6 is connected to the source of the sixth PMOS transistor PM6 via the ninth resistor R9. The drain of the sixth PMOS transistor PM6 is the input terminal of the T-type feedback unit. The second end of the pseudo-resistor RL is the control terminal of the T-type feedback unit, and the second end of the eighth resistor R8 is the output terminal of the T-type feedback unit.

[0028] It should be noted that the input terminal of the first T-type feedback unit is connected to the gate of the first PMOS transistor PM1, the output terminal of the first T-type feedback unit is connected to the drain of the fourth PMOS transistor PM4, and the control terminal of the first T-type feedback unit is connected to the control voltage Vctrl; the input terminal of the second T-type feedback unit is connected to the gate of the second PMOS transistor PM2, the output terminal of the second T-type feedback unit is connected to the drain of the fifth PMOS transistor PM5, and the control terminal of the second T-type feedback unit is connected to the control voltage Vctrl.

[0029] More specifically, as shown in Figure 3, the common-mode feedback module 130 includes a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a tenth resistor R10, an eleventh resistor R11, a sixth capacitor C6, and a seventh capacitor C7. The source of the seventh PMOS transistor PM7 is connected to the source of the eighth PMOS transistor PM8, and the source of the seventh PMOS transistor PM7 is also connected to the power supply voltage VDD. The gate of the seventh PMOS transistor PM7 is connected to the gate of the eighth PMOS transistor PM8, and the gate of the eighth PMOS transistor PM8 is also connected to the drain of the eighth PMOS transistor PM8. The drain of the seventh PMOS transistor PM7 is connected to the drain of the fifth NMOS transistor NM5, and the drain of the eighth PMOS transistor PM8 is connected to the drain of the sixth NMOS transistor NM6. The source of the fifth NMOS transistor NM5 is connected to the source of the sixth NMOS transistor NM6, and the source of the fifth NMOS transistor NM5 is also connected to... The drain of the seventh NMOS transistor NM7 is connected to the ground, the source of the seventh NMOS transistor NM7 is connected to the ground, the gate of the sixth NMOS transistor NM6 is connected to the first terminal of the tenth resistor R10, the gate of the sixth NMOS transistor NM6 is also connected to the first terminal of the eleventh resistor R11, the sixth capacitor C6 is connected in parallel with the tenth resistor R10, the seventh capacitor C7 is connected in parallel with the eleventh resistor R11, the gate of the fifth NMOS transistor NM5 is connected to the reference voltage Vocm, the gate of the seventh NMOS transistor NM7 is connected to the bias current, the second terminals of the tenth resistor R10 and the eleventh resistor R11 are the two differential input terminals of the common-mode feedback module 130, the second terminal of the tenth resistor R10 is connected to the drain of the fourth PMOS transistor PM4, the second terminal of the eleventh resistor R11 is connected to the drain of the fifth PMOS transistor PM5, the drain of the seventh PMOS transistor PM7 is the output terminal of the common-mode feedback module 130, and the output terminal of the common-mode feedback module 130 is connected to the gate of the fourth PMOS transistor PM4.

[0030] More specifically, as shown in Figure 3, the current mirror module 140 includes a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a twelfth PMOS transistor PM12, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, and a tenth NMOS transistor NM10. The source of the ninth PMOS transistor PM9 is connected to the source of the tenth PMOS transistor PM10, and the source of the ninth PMOS transistor PM9 is also connected to the power supply voltage VDD. The gate of the ninth PMOS transistor PM9 is connected to the gate of the tenth PMOS transistor PM10, and the gate of the tenth PMOS transistor PM10 is connected to the drain of the tenth PMOS transistor PM10. The drain of the ninth PMOS transistor PM9 is connected to the source of the eleventh PMOS transistor PM11, and the drain of the tenth PMOS transistor PM10 is connected to the source of the twelfth PMOS transistor PM12. The gate of the eleventh PMOS transistor PM11 is connected to the gate of the twelfth PMOS transistor PM12, and the gate of the twelfth PMOS transistor PM12 is connected to the gate of the twelfth PMOS transistor PM12. The drain of the eleventh PMOS transistor PM11 is connected to the drain of the tenth NMOS transistor NM10, the gate of the tenth NMOS transistor NM10 is connected to the drain of the tenth NMOS transistor NM10, and the source of the tenth NMOS transistor NM10 is grounded. The drain of the twelfth PMOS transistor PM12 is connected to the drain of the eighth NMOS transistor NM8, the source of the eighth NMOS transistor NM8 is connected to the drain of the ninth NMOS transistor NM9, and the source of the ninth NMOS transistor NM9 is connected to the source of the tenth NMOS transistor NM10. The gate of the ninth PMOS transistor PM9 is the first output terminal of the current mirror module 140, which is connected to the gate of the third PMOS transistor. The gate of the tenth NMOS transistor NM10 is the second output terminal of the current mirror module 140, which is connected to the gate of the seventh NMOS transistor. The gate of the eighth NMOS transistor NM8 is connected to the first current control signal VS1, and the gate of the ninth PMOS transistor PM9 is connected to the second current control signal VS2.

[0031] Please refer to Figures 1 to 6. The working principle of the optoelectronic front-end amplifier circuit provided by this invention is as follows: As shown in Figure 1, the amplification module 110 amplifies the input differential input signals (Vin, Vip) to obtain the output differential output signals (Von, Vop); the T-type feedback module 120 is disposed between the input and output terminals of the amplification module 110, as shown in Figure 4. By adjusting the ratio of the seventh resistor R7 to the eighth resistor R8 in the T-type feedback module 120, the overall gain can be flexibly controlled without requiring a large-value physical resistor; RL is a pseudo-resistor, which can be adjusted by adjusting the control voltage. Vctrl adjusts the feedback coefficient: In each T-type feedback unit, the main feedback branch uses a symmetrical gated sixth PMOS transistor PM6 operating in the deep voltage threshold region. The sixth PMOS transistor PM6 exhibits an exponentially changing equivalent resistance under gate control. The value of the pseudo-resistance RL depends on the manufacturing process and can be adjusted by appropriately changing the size of the sixth PMOS transistor PM6 and by changing the control voltage Vctrl, as shown in Figure 5. The horizontal axis represents the frequency value, and the vertical axis represents the reverse impedance gain. The reverse impedance gain of the amplifier circuit increases with the increase of the control voltage Vctrl. As shown in Figure 4, an AC feedback path is formed between the gate and source of the sixth PMOS transistor PM6 through the fifth capacitor C5, allowing the AC signal component to be fed back to the gate, thus achieving "negative feedback" nonlinear cancellation. A typical value pseudo-5kΩ (kiloohm) ninth resistor R9 is placed between the source and N-well of the sixth PMOS transistor PM6, so that the N-well terminal of the sixth PMOS transistor PM6 is in a "floating" state at high frequencies, coupled only by parasitic capacitance and resistance, cutting off the noise conduction path. As shown in Figure 6, the horizontal axis represents the frequency value, and the vertical axis represents the equivalent input noise current. in_RTeq is the equivalent input noise current under normal conditions, and in_RF is the equivalent input noise current of the sixth PMOS transistor PM6 after it is in a "floating" state at high frequency, which is significantly smaller than the normal noise current.

[0032] Because the amplifier can only suppress common-mode signals and cannot determine the common-mode level of the output, without common-mode feedback, the differential output signals (Von, Vop) of the amplifier module 110 may drift to the positive or negative terminal of the power supply due to process deviations and current source mismatch, causing the circuit to malfunction. As shown in Figure 3, the common-mode feedback module 130 stabilizes the DC operating point. The common-mode feedback module 130 detects the average voltage of the two differential outputs of the amplifier module 110 and compares the average voltage with the reference voltage Vocm, fixing the common-mode voltage output by the amplifier module 110 at half of the power supply voltage.

[0033] As shown in Figures 2 and 3, the current mirror module 140 generates a reference current by inputting the power supply voltage VCC. Under the control of the first current control signal VS1 and the second current control signal VS2, the reference current is copied to each branch, thereby ensuring that all transistors operate in the saturation region.

[0034] The optoelectronic front-end amplifier circuit provided by the present invention sets up a transconductance compensation network of capacitors and resistors at the two-stage amplification end of the amplification module 110, and configures three sets of compensation paths of resistors and capacitors (T-type feedback unit + differential input path of common mode feedback module 130) to enhance the system loop stability; the common mode feedback module 130 adopts voltage divider detection and comparison method to ensure the stability of common mode level.

[0035] The present invention also provides an optoelectronic imaging device, which includes an optoelectronic front-end amplification circuit as described above, to improve the imaging performance of the optoelectronic imaging device.

[0036] This invention provides a photoelectric front-end amplifier circuit and a photoelectric imaging device. The photoelectric front-end amplifier circuit includes an amplification module and a T-type feedback module. The amplification module amplifies the differential input signal and outputs a differential output signal. The T-type feedback module is connected in series between the input and output terminals of the amplification module. The gain of the amplification module is adjusted by a pseudo-resistor in the T-type feedback module, and the linear dynamic range of the overall circuit is improved by a quasi-floating gate structure in the T-type feedback module. This invention sets up a T-type feedback module between the input and output terminals of the amplification module, and uses the pseudo-resistance of a gated PMOS transistor to achieve a wide-range adjustable feedback resistance value to meet the output current requirements of various detectors. Furthermore, through quasi-floating gate and quasi-floating N-Well technology, high-order distortion and high-frequency noise introduced by junction capacitance are significantly suppressed, improving the linear dynamic range. The T-type feedback module balances low noise, wide bandwidth, and low power consumption; the circuit has high integration and a compact silicon wafer area.

[0037] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A photoelectric front-end amplifier circuit, characterized in that, include: An amplification module is connected to a differential input signal at its input terminal, amplifies the differential input signal, and outputs a differential output signal to the outside. The T-type feedback module is connected between the input and output terminals of the amplification module. It adjusts the gain of the amplification module based on the pseudo-resistance in the T-type feedback module and improves the linear dynamic range of the optoelectronic front-end amplification circuit through the quasi-floating gate structure in the T-type feedback module.

2. The optoelectronic front-end amplifier circuit according to claim 1, characterized in that, The optoelectronic front-end amplifier circuit also includes a common-mode feedback module. The input terminal of the common-mode feedback module is connected to the output terminal of the amplifier module. It monitors the average voltage of the two outputs of the amplifier module in real time, compares the average voltage with a reference voltage, and adjusts the common-mode voltage input to the amplifier module to a preset voltage threshold based on the comparison result.

3. The optoelectronic front-end amplifier circuit according to claim 2, characterized in that, The optoelectronic front-end amplifier circuit also includes a current mirror module, which replicates the reference current under the control of two current control signals to provide bias current to the amplification module and the common-mode feedback module.

4. The optoelectronic front-end amplifier circuit according to claim 1, characterized in that, The amplification module includes a first-stage amplification unit and a second-stage amplification unit. The first-stage amplification unit performs current-to-voltage conversion and first-stage amplification on the differential input signal to obtain an intermediate signal. The second-stage amplification unit performs second-stage amplification on the intermediate signal and adjusts the signal swing of the intermediate signal to obtain the differential output signal.

5. The optoelectronic front-end amplifier circuit according to claim 4, characterized in that, The first-stage amplification unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor is connected to the source of the second PMOS transistor, and the source of the first PMOS transistor is also connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is connected to the power supply voltage. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the first NMOS transistor is connected to the gate of the second PMOS transistor, and the source of the first NMOS transistor is connected to the source of the second NMOS transistor. The source of the second NMOS transistor is grounded. The gates of the first and second PMOS transistors are the input terminals of the first-stage amplification unit, and the drains of the first and second NMOS transistors are the output terminals of the second-stage amplification unit. The gate of the third PMOS transistor is connected to the bias current.

6. The optoelectronic front-end amplifier circuit according to claim 4, characterized in that, The second-stage amplification unit includes a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The source of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, and the source of the fourth PMOS transistor is also connected to the power supply voltage. The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor. The gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor via the first resistor and the first capacitor. The drain of the fourth PMOS transistor is also connected to the drain of the third NMOS transistor. The gate of the fifth PMOS transistor is connected to the drain of the third NMOS transistor via the second resistor and the second capacitor. The drain of the fifth PMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the third NMOS transistor is connected to the first terminal of the third resistor via the third capacitor. The drain of the fourth NMOS transistor is connected to the first terminal of the fourth capacitor via the fourth capacitor. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor via the fifth resistor and the sixth resistor. The source of the third NMOS transistor is connected to the source of the fourth NMOS transistor. The source of the third NMOS transistor is grounded. The second terminals of the third resistor and the fourth resistor are the input terminals of the second-stage amplification unit. The common terminal of the fifth resistor and the sixth resistor is the driving terminal of the second-stage amplification unit.

7. The optoelectronic front-end amplifier circuit according to claim 1, characterized in that, The T-type feedback module includes two T-type feedback units. Each T-type feedback unit includes a pseudo resistor, a sixth PMOS transistor, a seventh resistor, an eighth resistor, a ninth resistor, and a fifth capacitor. The first end of the pseudo resistor is connected to the gate of the sixth PMOS transistor. The first end of the pseudo resistor is also connected to the source of the sixth PMOS transistor via the fifth capacitor. The source of the sixth PMOS transistor is grounded via the seventh resistor. The source of the sixth PMOS transistor is connected to the first end of the eighth resistor. The N-well of the sixth PMOS transistor is connected to the source of the sixth PMOS transistor via the ninth resistor. The drain of the sixth PMOS transistor is the input terminal of the T-type feedback unit. The second end of the pseudo resistor is the control terminal of the T-type feedback unit. The second end of the eighth resistor is the output terminal of the T-type feedback unit.

8. The optoelectronic front-end amplifier circuit according to claim 2, characterized in that, The common-mode feedback module includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a tenth resistor, an eleventh resistor, a sixth capacitor, and a seventh capacitor. The source of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, and the source of the seventh PMOS transistor is also connected to the power supply voltage. The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, and the gate of the eighth PMOS transistor is also connected to the drain of the eighth PMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the fifth NMOS transistor, the drain of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the fifth NMOS transistor is connected to the sixth NMOS transistor. The source of the fifth NMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the seventh NMOS transistor is grounded, the gate of the sixth NMOS transistor is connected to the first terminal of the tenth resistor, the gate of the sixth NMOS transistor is also connected to the first terminal of the eleventh resistor, the sixth capacitor is connected in parallel with the tenth resistor, the seventh capacitor is connected in parallel with the eleventh resistor, wherein the gate of the fifth NMOS transistor is connected to the reference voltage, the gate of the seventh NMOS transistor is connected to the bias current, the second terminals of the tenth resistor and the second terminals of the eleventh resistor are the two differential input terminals of the common-mode feedback module, and the drain of the seventh PMOS transistor is the output terminal of the common-mode feedback module.

9. The optoelectronic front-end amplifier circuit according to claim 3, characterized in that, The current mirror module includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. The source of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor, and the source of the ninth PMOS transistor is also connected to a power supply voltage. The gate of the ninth PMOS transistor is connected to the gate of the tenth PMOS transistor, and the gate of the tenth PMOS transistor is connected to its drain. The drain of the ninth PMOS transistor is connected to the source of the eleventh PMOS transistor, and the drain of the tenth PMOS transistor is connected to the source of the twelfth PMOS transistor. The gate of the eleventh PMOS transistor is connected to the gate of the twelfth PMOS transistor, and the gate of the twelfth PMOS transistor is connected to the tenth PMOS transistor. The drains of two PMOS transistors are connected as follows: the drain of the eleventh PMOS transistor is connected to the drain of the tenth NMOS transistor; the gate of the tenth NMOS transistor is connected to the drain of the tenth NMOS transistor; the source of the tenth NMOS transistor is grounded; the drain of the twelfth PMOS transistor is connected to the drain of the eighth NMOS transistor; the source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; and the source of the ninth NMOS transistor is connected to the source of the tenth NMOS transistor. The gate of the ninth PMOS transistor is the first output terminal of the current mirror module, the gate of the tenth NMOS transistor is the second output terminal of the current mirror module, the gate of the eighth NMOS transistor is connected to the first current control signal, and the gate of the ninth PMOS transistor is connected to the second current control signal.

10. A photoelectric imaging device, characterized in that, Includes the photoelectric front-end amplifier circuit as described in any one of claims 1-9.

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