wiring board

Abstract

To provide a wiring board in which the adhesion between a wiring layer and an insulation layer is improved.SOLUTION: A wiring board 1 includes: an insulation layer 17 containing a filler 171 that coats a first wiring layer 16; an open part 17x exposing an upper surface of the first wiring layer 16; and a second wiring layer 18 that is electrically connected to the first wiring layer 16 while filling the open part 17x, and is extended to an upper surface of the insulation layer 17 from the inside of the open part 17x. A concave part 17y as a mark obtained by removing the filler 171 is formed in an inner wall surface of the open part 17x. The second wiring layer 18 has a construction that an electrolyte plating layer 182 is laminated onto a seed layer 181. The electrolyte plating layer 182 fills the inside of the open part 17x including an inner part of the concave part 17y. The seed layer 181 is formed on the inner wall surface of at least the open part 17x, the inner wall surface of the concave part 17y, and the upper surface of the first wiring layer 16 exposed to the open part 17x.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] A wiring board is known that has an insulating layer that covers a first wiring layer, an opening formed in the insulating layer that exposes the upper surface of the first wiring layer, and a second wiring layer that fills the opening and extends onto the upper surface of the insulating layer.

[0003] The second wiring layer is formed, for example, as follows. First, an opening is formed in the insulating layer to expose the top surface of the first wiring layer. Then, the entire surface of the insulating layer, including the inside of the opening, is pre-treated for plating, and then a seed layer is formed. Next, electrolytic plating is selectively performed using the seed layer as a base to form an electrolytic plated layer. After that, unnecessary portions of the seed layer are removed by etching using the electrolytic plated layer as a mask, and a second wiring layer consisting of the seed layer and the electrolytic plated layer is formed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-103878 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the insulating layer may contain filler. In this case, the filler exposed on the inner wall surface of the opening may fall off during pre-plating. When the filler falls off, the recess formed in the trace of the fallen filler is left with an unattached portion of the seed layer because the pre-plating has not been performed there. The unattached portion of the seed layer inhibits the growth of electrolytic plating, reducing the adhesion between the second wiring layer and the insulating layer.

[0006] The present invention has been made in view of the above points, and an object of the present invention is to provide a wiring board in which the adhesion between the wiring layer and the insulating layer is improved. [Means for solving the problem]

[0007] This wiring board has an insulating layer containing a filler that covers a first wiring layer, an opening formed in the insulating layer to expose an upper surface of the first wiring layer, and a second wiring layer that fills the opening, is electrically connected to the first wiring layer, and extends from within the opening to an upper surface of the insulating layer, and the second wiring layer includes via wiring that fills the opening, and is electrically connected to the first wiring layer, and a wiring pattern and / or pad formed on the via wiring, The particle size of the filler is 0.1 μm or more and 10 μm or less, A recess is formed on the inner wall surface of the opening, which is a mark left by removing the filler, and the second wiring layer is Thickness is between 0.3 μm and 1 μm The structure is one in which an electroplated layer is laminated on a seed layer. 、 At least the inner wall surface of the opening The surface of the filler exposed from the inner wall surface of the opening A catalyst is adsorbed on the inner wall surface of the recess and the upper surface of the first wiring layer exposed in the opening, and the seed layer is formed on at least the inner wall surface of the opening. The surface of the filler exposed from the inner wall surface of the opening , an inner wall surface of the recess and an upper surface of the first wiring layer exposed in the opening Continuously along formed on the catalyst The electrolytic plating layer is formed on the seed layer continuously along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed in the opening, and fills the inside of the opening including the inside of the recess. are. [Effects of the Invention]

[0008] According to the disclosed technique, it is possible to provide a wiring board with improved adhesion between the wiring layer and the insulating layer. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view illustrating a wiring board according to a first embodiment. [Figure 2] 1A to 1C are views (part 1) illustrating a manufacturing process of a wiring board according to the first embodiment. [Figure 3] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 4]10A to 10C are views (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment. [Figure 5] 10A to 10C are views (part 4) illustrating the manufacturing process of the wiring board according to the first embodiment. [Figure 6] 1A and 1B are diagrams (part 1) illustrating a method for manufacturing a wiring board according to a comparative example. [Figure 7] 10A and 10B are diagrams (part 2) illustrating a method for manufacturing a wiring board according to a comparative example. [Figure 8] FIG. 10 is a cross-sectional view illustrating a wiring board according to a second embodiment. [Figure 9] 10A to 10C are views (part 1) illustrating a manufacturing process of a wiring board according to a second embodiment. [Figure 10] 10A to 10C are diagrams (part 2) illustrating the manufacturing process of the wiring board according to the second embodiment. [Figure 11] FIG. 2 is a cross-sectional view illustrating a semiconductor package according to an application example of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0011] First Embodiment [Structure of wiring board according to first embodiment] 1A and 1B are cross-sectional views illustrating a wiring board according to a first embodiment, where FIG. 1A is an overall view and FIG. 1B is a partially enlarged view of part A in FIG. 1A.

[0012] Referring to FIG. 1, a wiring board 1 is a wiring board in which wiring layers and insulating layers are laminated on both sides of a core layer 10.

[0013] Specifically, in the wiring board 1, a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, a solder resist layer 17, and a wiring layer 18 are sequentially stacked on one surface 10a of the core layer 10. Also, a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, and a solder resist layer 27 are sequentially stacked on the other surface 10b of the core layer 10.

[0014] In the first embodiment, for convenience, the solder resist layer 17 side of the wiring board 1 is referred to as the upper side or one side, and the solder resist layer 27 side is referred to as the lower side or the other side. Furthermore, the surface of each part facing the solder resist layer 17 is referred to as one side or the upper side, and the surface facing the solder resist layer 27 is referred to as the other side or the lower side. However, the wiring board 1 can be used upside down or positioned at any angle. Furthermore, a planar view refers to viewing an object from the normal direction of one surface 10a of the core layer 10, and a planar shape refers to the shape of the object viewed from the normal direction of one surface 10a of the core layer 10.

[0015] The core layer 10 may be, for example, a so-called glass epoxy substrate obtained by impregnating a glass cloth with an insulating resin such as an epoxy resin. Alternatively, the core layer 10 may be a substrate obtained by impregnating a woven or nonwoven fabric such as glass fiber, carbon fiber, or aramid fiber with an epoxy resin. The core layer 10 has a thickness of, for example, about 60 to 1000 μm. The core layer 10 has through holes 10x that penetrate the core layer 10 in the thickness direction. The planar shape of the through holes 10x is, for example, a circle.

[0016] The wiring layer 12 is formed on one surface 10a of the core layer 10. The wiring layer 22 is formed on the other surface 10b of the core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by through-wires 11 formed in the through-holes 10x. The wiring layers 12 and 22 are each patterned into a predetermined planar shape. The wiring layers 12 and 22 and the through-wires 11 may be made of, for example, copper (Cu). The thickness of the wiring layers 12 and 22 is, for example, about 10 to 40 μm. The wiring layer 12, the wiring layer 22, and the through-wires 11 may be formed integrally.

[0017] The insulating layer 13 is an interlayer insulating layer formed on one surface 10a of the core layer 10 so as to cover the wiring layer 12. The insulating layer 13 may be made of, for example, a non-photosensitive thermosetting resin containing an epoxy resin as a main component. The insulating layer 13 has a thickness of, for example, about 25 to 40 μm. The insulating layer 13 contains a filler such as silicon dioxide (SiO2). The particle size of the filler is, for example, about 0.1 to 10 μm. The filler content is, for example, about 30 to 80 wt %.

[0018] The insulating layer 13 has a via hole 13x, which is an opening. The via hole 13x penetrates the insulating layer 13 and exposes the upper surface of the wiring layer 12. The wiring layer 14 fills the via hole 13x, is electrically connected to the wiring layer 12, and extends from the via hole 13x to the upper surface of the insulating layer 13. In detail, the wiring layer 14 includes a via wiring filled in the via hole 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 through the via wiring. The via hole 13x is, for example, an inverted truncated cone-shaped recess in which the diameter of the opening opening on the insulating layer 15 side is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 12. The material of the wiring layer 14 and the thickness of the wiring pattern are, for example, similar to those of the wiring layer 12.

[0019] The insulating layer 15 is an interlayer insulating layer formed on the upper surface of the insulating layer 13 so as to cover the wiring layer 14. The material and thickness of the insulating layer 15 are, for example, the same as those of the insulating layer 13. The insulating layer 15 contains, for example, the same filler as that of the insulating layer 13.

[0020] The insulating layer 15 has via holes 15x, which are openings. The via holes 15x penetrate the insulating layer 15 and expose the upper surface of the wiring layer 14. The wiring layer 16 fills the via holes 15x, is electrically connected to the wiring layer 14, and extends from the via holes 15x to the upper surface of the insulating layer 15. Specifically, the wiring layer 16 includes via wiring filled in the via holes 15x and a wiring pattern formed on the upper surface of the insulating layer 15. The wiring pattern of the wiring layer 16 is electrically connected to the wiring layer 14 through the via wiring. The via holes 15x are, for example, recesses in the shape of an inverted truncated cone, with the diameter of the opening on the solder resist layer 17 side being larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 14. The material of the wiring layer 16 and the thickness of the wiring pattern are, for example, similar to those of the wiring layer 12.

[0021] The solder resist layer 17 is a protective insulating layer located at the outermost side of one side of the wiring board 1, and is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The solder resist layer 17 can be formed from, for example, a photosensitive resin whose main component is an epoxy resin or the like. The thickness of the solder resist layer 17 is, for example, about 15 to 35 μm.

[0022] The solder resist layer 17 contains filler 171 such as silicon dioxide (SiO2) or barium sulfate (BaSO4). The particle size of the filler 171 is, for example, about 0.3 to 4 μm. The content of the filler 171 is, for example, about 30 to 60 wt %.

[0023] The solder resist layer 17 has openings 17x. The openings 17x penetrate the solder resist layer 17 and expose the upper surface of the wiring layer 16. The wiring layer 18 fills the openings 17x, is electrically connected to the wiring layer 16, and extends from the openings 17x to the upper surface of the solder resist layer 17. More specifically, the wiring layer 18 includes via wirings filled in the openings 17x and pads formed on the upper surface of the solder resist layer 17. The pads constituting the wiring layer 18 are electrically connected to the wiring layer 16 through the via wirings. The openings 17x are, for example, recesses in the shape of an inverted truncated cone, with the diameter of the openings opened on the surface side of the solder resist layer 17 being larger than the diameter of the bottom of the openings formed by the upper surface of the wiring layer 16.

[0024] The planar shape of the pads that make up the wiring layer 18 is, for example, a circle with a diameter of about 35 to 85 μm. The pitch of the pads that make up the wiring layer 18 is, for example, about 40 to 100 μm. The thickness of the pads that make up the wiring layer 18 is, for example, about 10 to 30 μm. The pads that make up the wiring layer 18 function as electronic component mounting pads for electrically connecting to electronic components such as semiconductor chips.

[0025] The wiring layer 18 has a seed layer 181 and an electroplated layer 182, and has a structure in which the electroplated layer 182 is laminated on the seed layer 181. The seed layer 181 is continuously formed on the region around the opening 17x on the upper surface of the solder resist layer 17, on the inner wall surface of the opening 17x, and on the upper surface of the wiring layer 16 exposed in the opening 17x. The seed layer 181 is made of, for example, copper. The seed layer 181 has a thickness of, for example, about 0.3 to 1 μm. The electroplated layer 182 is made of, for example, copper. The material of the electroplated layer 182 may be nickel or tin other than copper.

[0026] 1(b), filler 171 contained in solder resist layer 17 may partially protrude from the inner wall of opening 17x, or depressions 17y may be formed on the inner wall surface of opening 17x as traces of fallen filler 171 contained in solder resist layer 17. In such cases, seed layer 181 is formed on the surface of filler 171 exposed from the inner wall surface of opening 17x and also on the inner wall surface of depression 17y.

[0027] That is, the seed layer 181 is formed with a substantially uniform thickness on the region around the opening 17x on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed in the opening 17x. The reason for this will be explained in the section on the manufacturing method of the wiring board 1.

[0028] Electrolytic plated layer 182 is formed on seed layer 181. Electrolytic plated layer 182 is formed to fill opening 17x and extend above the upper surface of seed layer 181 located around opening 17x. Here, the portion of wiring layer 18 filled in opening 17x is referred to as a via wiring, and the portion protruding from the upper surface of solder resist layer 17 is referred to as a pad.

[0029] Note that a metal layer may be formed on the surface of the pads that make up the wiring layer 18, or an organic coating may be formed by performing an anti-oxidation treatment such as an OSP (Organic Solderability Preservative) treatment. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer formed by laminating an Ni layer and an Au layer in this order), a Ni / Pd / Au layer (a metal layer formed by laminating an Ni layer, a Pd layer, and an Au layer in this order), and a Sn layer.

[0030] The insulating layer 23 is an interlayer insulating layer formed on the other surface 10b of the core layer 10 so as to cover the wiring layer 22. The material and thickness of the insulating layer 23 are, for example, the same as those of the insulating layer 13. The insulating layer 23 contains, for example, the same filler as the insulating layer 13.

[0031] The insulating layer 23 has via holes 23x which are openings. The via holes 23x penetrate the insulating layer 23 and expose the lower surface of the wiring layer 22. The wiring layer 24 fills the via holes 23x, is electrically connected to the wiring layer 22, and extends from the via holes 23x to the lower surface of the insulating layer 23. In detail, the wiring layer 24 includes via wirings filled in the via holes 23x and a wiring pattern formed on the lower surface of the insulating layer 23. The wiring pattern of the wiring layer 24 is electrically connected to the wiring layer 22 through the via wirings. The via holes 23x are, for example, truncated cone-shaped recesses whose diameter at the opening on the insulating layer 25 side is larger than the diameter of the bottom of the opening formed by the lower surface of the wiring layer 22. The material of the wiring layer 24 and the thickness of the wiring pattern are, for example, similar to those of the wiring layer 12.

[0032] The insulating layer 25 is an interlayer insulating layer formed on the lower surface of the insulating layer 23 so as to cover the wiring layer 24. The material and thickness of the insulating layer 25 are, for example, the same as those of the insulating layer 13. The insulating layer 25 contains, for example, the same filler as that of the insulating layer 13.

[0033] The insulating layer 25 has via holes 25x, which are openings. The via holes 25x penetrate the insulating layer 25 and expose the lower surface of the wiring layer 24. The wiring layer 26 fills the via holes 25x, is electrically connected to the wiring layer 24, and extends from the via holes 25x to the lower surface of the insulating layer 25. In detail, the wiring layer 26 includes via wiring filled in the via holes 25x and a wiring pattern formed on the lower surface of the insulating layer 25. The wiring pattern of the wiring layer 26 is electrically connected to the wiring layer 24 through the via wiring. The via holes 25x are, for example, truncated cone-shaped recesses whose openings on the solder resist layer 27 side have a diameter larger than the diameter of the bottom of the opening formed by the lower surface of the wiring layer 24. The material of the wiring layer 26 and the thickness of the wiring pattern are, for example, similar to those of the wiring layer 12.

[0034] The solder resist layer 27 is a protective insulating layer located at the outermost position on the other side of the wiring board 1, and is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The material and thickness of the solder resist layer 27 are, for example, the same as those of the solder resist layer 17. The solder resist layer 27 contains, for example, the same filler as that of the solder resist layer 17.

[0035] The solder resist layer 27 has openings 27x, in which a portion of the lower surface of the wiring layer 26 is exposed. The planar shape of the openings 27x is, for example, circular. The wiring layer 26 exposed in the openings 27x can be used as a pad for electrical connection to a mounting substrate (not shown) such as a motherboard. If necessary, the above-mentioned metal layer may be formed on the lower surface of the wiring layer 26 exposed in the openings 27x, or an organic coating may be formed by performing an anti-oxidation treatment such as OSP treatment.

[0036] [Method for manufacturing a wiring board according to the first embodiment] 2 to 5 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment. Fig. 2, Fig. 4(a), Fig. 4(c), and Fig. 5 are cross-sectional views corresponding to Fig. 1(a), and Fig. 3 and Fig. 4(b) are cross-sectional views corresponding to Fig. 1(b). Note that, although an example of the process for manufacturing one wiring board is shown here, it is also possible to manufacture a plurality of parts that will become the wiring board and then separate them into individual wiring boards.

[0037] 2(a), through wiring 11 and wiring layers 12 and 22 are formed in a core layer 10. Specifically, a laminate is prepared in which unpatterned plain copper foil is formed on one surface 10a and the other surface 10b of the core layer 10, which may be a so-called glass epoxy substrate, for example. Then, in the prepared laminate, the copper foil on each surface is thinned as necessary, and then through holes 10x are formed through the core layer 10 and the copper foil on each surface by laser processing using a CO2 laser or the like.

[0038] Next, a desmear process is performed as needed to remove resin residue from the core layer 10 that is attached to the inner wall surfaces of the through holes 10x. Then, a seed layer (copper, etc.) is formed by, for example, electroless plating or sputtering to cover the copper foil on each surface and the inner wall surfaces of the through holes 10x, and an electrolytic plating layer (copper, etc.) is formed on the seed layer by electrolytic plating using the seed layer as a power supply layer. As a result, the through holes 10x are filled with the electrolytic plating layer formed on the seed layer, and wiring layers 12 and 22, each composed of a copper foil, a seed layer, and an electrolytic plating layer stacked on one surface 10a and the other surface 10b of the core layer 10, are formed. Next, the wiring layers 12 and 22 are patterned into a predetermined planar shape by, for example, a subtractive process.

[0039] 2(b), a semi-cured film-like non-photosensitive thermosetting resin, primarily composed of an epoxy resin, is laminated on one surface 10a of the core layer 10 so as to cover the wiring layer 12, and then cured to form the insulating layer 13. A semi-cured film-like non-photosensitive thermosetting resin, primarily composed of an epoxy resin, is laminated on the other surface 10b of the core layer 10 so as to cover the wiring layer 22, and then cured to form the insulating layer 23. Alternatively, instead of laminating a film-like epoxy resin, a liquid or paste-like epoxy resin may be applied and then cured to form the insulating layers 13 and 23. The thickness of each of the insulating layers 13 and 23 is, for example, approximately 25 to 40 μm.

[0040] Each of the insulating layers 13 and 23 contains a filler such as silicon dioxide (SiO2). The particle size of the filler is, for example, about 0.1 to 10 μm. The filler content is, for example, about 30 to 80 wt %.

[0041] Next, via holes 13x are formed in the insulating layer 13, which are openings that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 12. Also, via holes 23x are formed in the insulating layer 23, which are openings that penetrate the insulating layer 23 and expose the lower surface of the wiring layer 22. The via holes 13x and 23x can be formed by, for example, a laser processing method using a CO2 laser or the like. After the via holes 13x and 23x are formed, it is preferable to perform a desmear process to remove resin residues adhering to the surfaces of the wiring layers 12 and 22 that are exposed at the bottoms of the via holes 13x and 23x.

[0042] Next, the via holes 13x are filled to form a wiring layer 14 that is electrically connected to the wiring layer 12 and extends from the via holes 13x to the upper surface of the insulating layer 13. The wiring layer 14 includes via wirings filled in the via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The material of the wiring layer 14 and the thickness of the wiring pattern are, for example, the same as those of the wiring layer 12. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the via holes 13x.

[0043] Furthermore, the via holes 23x are filled with a material to form a wiring layer 24 that is electrically connected to the wiring layer 22 and extends from within the via holes 23x to the underside of the insulating layer 23. The wiring layer 24 includes via wirings filled within the via holes 23x and a wiring pattern formed on the underside of the insulating layer 23. The material of the wiring layer 24 and the thickness of the wiring pattern are, for example, the same as those of the wiring layer 12. The wiring layer 24 is electrically connected to the wiring layer 22 exposed at the bottom of the via holes 23x. The wiring layers 14 and 24 can be formed using various wiring formation methods, such as a semi-additive method or a subtractive method.

[0044] Next, insulating layer 15 is formed on the upper surface of insulating layer 13 so as to cover wiring layer 14 using the same method as for insulating layer 13. The material and thickness of insulating layer 15 are, for example, the same as for insulating layer 13. Then, via hole 15x is formed using the same method as for via hole 13x. Furthermore, insulating layer 25 is formed on the lower surface of insulating layer 23 so as to cover wiring layer 24 using the same method as for insulating layer 13. The material and thickness of insulating layer 25 are, for example, the same as for insulating layer 13. Then, via hole 25x is formed using the same method as for via hole 13x. Each of insulating layers 15 and 25 contains, for example, the same filler as for insulating layer 13.

[0045] After the via holes 15x and 25x are formed, it is preferable to perform a desmear treatment to remove resin residues adhering to the surfaces of the wiring layers 14 and 24 exposed at the bottoms of the via holes 15x and 25x, respectively.

[0046] Next, the via holes 15x are filled to form a wiring layer 16 that is electrically connected to the wiring layer 14 and extends from the via holes 15x to the upper surface of the insulating layer 15. The wiring layer 16 includes via wirings filled in the via holes 15x and a wiring pattern formed on the upper surface of the insulating layer 15. The material of the wiring layer 16 and the thickness of the wiring pattern are, for example, the same as those of the wiring layer 12. The wiring pattern of the wiring layer 16 is electrically connected to the wiring layer 14 exposed at the bottom of the via holes 15x.

[0047] Furthermore, the via holes 25x are filled with a material to form a wiring layer 26 that is electrically connected to the wiring layer 24 and extends from within the via holes 25x to the underside of the insulating layer 25. The wiring layer 26 includes via wirings filled within the via holes 25x and a wiring pattern formed on the underside of the insulating layer 25. The material of the wiring layer 26 and the thickness of the wiring pattern are, for example, the same as those of the wiring layer 12. The wiring layer 26 is electrically connected to the wiring layer 24 exposed at the bottom of the via holes 25x. The wiring layers 16 and 26 can be formed using various wiring formation methods, such as a semi-additive method or a subtractive method.

[0048] 2(c), a solder resist layer 17 is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. In addition, a solder resist layer 27 is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The solder resist layer 17 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin to the upper surface of the insulating layer 15 so as to cover the wiring layer 16 by screen printing, roll coating, spin coating, or the like. Alternatively, the solder resist layer 17 may be formed, for example, by laminating a film-like photosensitive epoxy insulating resin on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The method for forming the solder resist layer 27 is the same as that for the solder resist layer 17.

[0049] The solder resist layers 17 and 27 contain filler 171 such as silicon dioxide (SiO2) or barium sulfate (BaSO4). The particle size of the filler 171 is, for example, about 0.3 to 4 μm. The content of the filler 171 is, for example, about 30 to 60 wt %.

[0050] 2(d), the solder resist layers 17 and 27 are exposed and developed to form openings 17x in the solder resist layer 17 that expose a portion of the upper surface of the wiring layer 16 (photolithography). Also, openings 27x are formed in the solder resist layer 27 that expose a portion of the lower surface of the wiring layer 26 (photolithography). The planar shape of each of the openings 17x and 27x is, for example, circular. The diameter of each of the openings 17x and 27x can be arbitrarily designed to suit the connection target (such as a semiconductor chip).

[0051] Fig. 3(a) is an enlarged view of part B in Fig. 2(d). As shown in Fig. 3(a), when openings 17x are formed in solder resist layer 17, filler 171 is exposed, for example, on the inner wall surface of openings 17x. Furthermore, although not shown, when openings 27x are formed in solder resist layer 27, filler is exposed, for example, on the inner wall surface of openings 27x.

[0052] 3(b), a first alkaline treatment is performed as a pretreatment for electroless plating. Specifically, for example, the upper surface of the solder resist layer 17, the inner wall surfaces of the openings 17x, the surfaces of the fillers 171 exposed from the inner wall surfaces of the openings 17x, and the upper surface of the wiring layer 16 exposed within the openings 17x are treated with a treatment solution containing 1.5 to 2% sodium hydroxide and an appropriate amount of surfactant for about 4 to 5 minutes in a temperature environment of about 50 to 60°C. Examples of surfactants include octylphenol ethoxylate (an ether compound).

[0053] The first alkaline treatment cleans and conditions the upper surface of the solder resist layer 17, the inner wall surfaces of the openings 17x, the surfaces of the fillers 171 exposed from the inner wall surfaces of the openings 17x, and the upper surface of the wiring layer 16 exposed in the openings 17x. Note that in Figure 3(b), the cleaned and conditioned surfaces are indicated by dashed lines for convenience.

[0054] Here, cleaning is a process of washing the surface of the solder resist layer 17 in order to form a seed layer (electroless plating layer) on the surface of the solder resist layer 17. Moreover, conditioning is a process of adjusting the surface condition of the solder resist layer 17.

[0055] In this embodiment, a seed layer is formed on the surface of the solder resist layer 17 by electroless plating. Cleaning and conditioning make it easier for a catalyst (such as palladium) for depositing electroless plating to be adsorbed on the surface of the solder resist layer 17. The presence of the catalyst allows an electroless plating layer to be formed satisfactorily on the surface of the solder resist layer 17. In other words, a seed layer for forming an electrolytic plating layer can be formed satisfactorily on the surface of the solder resist layer 17.

[0056] Furthermore, the first alkali treatment wets and swells the resin that constitutes the solder resist layer 17. This treatment reduces the force with which the solder resist layer 17 fixes the filler 171 in the openings 17x, making the filler 171 more likely to fall off from the solder resist layer 17.

[0057] Next, in the step shown in FIG. 3(c), an ultrasonic cleaning process is performed. The ultrasonic cleaning process is, for example, ultrasonic water washing in which ultrasonic vibrations of a frequency of 35 to 50 kHz are applied, and the processing time is approximately 3 to 10 minutes. The ultrasonic cleaning process removes the filler 171 that was in a state where it was likely to fall off in the step shown in FIG. 3(b). After removal, a recess 17y, which is a mark left by the removed filler 171, is formed on the inner wall surface of the opening 17x by the ultrasonic cleaning process. The removed filler 171 is removed from the opening 17x by the ultrasonic cleaning process. Note that even if there is filler 171 that has fallen off before the ultrasonic cleaning process, the fallen filler 171 is also removed from the opening 17x by the ultrasonic cleaning process. The recess 17y is in a state where it has not been cleaned or conditioned. Note that in FIG. 3(c), the surface that has been cleaned and conditioned is indicated by a dashed line for convenience.

[0058] 3(d), a second alkali treatment is performed under conditions that make it less likely for the filler 171 to fall off from the solder resist layer 17 than the first alkali treatment.

[0059] The second alkaline treatment can be carried out, for example, using the same type of treatment liquid as the first alkaline treatment. In this case, the second alkaline treatment can be carried out under the following conditions: (1) the treatment temperature of the first alkaline treatment > the treatment temperature of the second alkaline treatment, (2) the treatment time of the first alkaline treatment > the treatment time of the second alkaline treatment, and (3) the concentration of the treatment liquid of the first alkaline treatment > the concentration of the treatment liquid of the second alkaline treatment.

[0060] In other words, when the second alkaline treatment is carried out using the same type of treatment liquid as the first alkaline treatment, the second alkaline treatment is carried out so as to satisfy one of the conditions (1), (2), and (3), (1) and (2), (1) and (3), (2) and (3), or (1), (2), and (3).

[0061] Specifically, for example, the upper surface of the solder resist layer 17, the inner wall surfaces of the openings 17x, the surface of the filler 171 exposed from the inner wall surfaces of the openings 17x, the inner wall surfaces of the recesses 17y, and the upper surface of the wiring layer 16 exposed within the openings 17x are treated with a solution of 1 to 1.5% sodium hydroxide with an appropriate amount of surfactant for about 3 to 4 minutes in a temperature environment of about 40 to 50° C. This is an example of the second alkali treatment that satisfies all of the conditions (1), (2), and (3).

[0062] The second alkaline treatment cleans and conditions the upper surface of the solder resist layer 17, the inner wall surfaces of the openings 17x, the surfaces of the fillers 171 exposed from the inner wall surfaces of the openings 17x, the inner wall surfaces of the recesses 17y, and the upper surface of the wiring layer 16 exposed within the openings 17x. Note that in Figure 3(d), the cleaned and conditioned surfaces are indicated by dashed lines for convenience.

[0063] The second alkali treatment is performed under conditions that make it less likely for the filler 171 to fall off from the solder resist layer 17 than the first alkali treatment, and therefore the resin that makes up the solder resist layer 17 is less likely to become wet. Therefore, no new filler 171 falls off during the second alkali treatment. In other words, the conditions for the second alkali treatment can be determined so that no new filler 171 falls off during the second alkali treatment.

[0064] 4(a), a seed layer 181 is continuously formed on the upper surface of the solder resist layer 17, the inner wall surfaces of the openings 17x, and the upper surface of the wiring layer 16 exposed in the openings 17x. A seed layer 281 is also continuously formed on the lower surface of the solder resist layer 27, the inner wall surfaces of the openings 27x, and the lower surface of the wiring layer 26 exposed in the openings 27x. The seed layers 181 and 281 are made of copper, for example. The seed layers 181 and 281 have a thickness of, for example, about 0.3 to 1 μm. The seed layers 181 and 281 can be formed by, for example, electroless plating.

[0065] Fig. 4(b) is an enlarged view of part B in Fig. 4(a). As shown in Fig. 4(b), the seed layer 181 is also formed on the surface of the filler 171 exposed from the inner wall surface of the opening 17x and on the inner wall surface of the recess 17y. That is, the seed layer 181 is formed with a substantially uniform thickness on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed in the opening 17x. The same applies to the seed layer 281.

[0066] 4(c), a resist layer 310 is formed on the upper surface of the seed layer 181. A resist layer 320 is formed on the lower surface of the seed layer 281. The resist layers 310 and 320 can be formed by laminating a photosensitive dry film resist, for example.

[0067] 5(a), the resist layer 310 is exposed and developed to form an opening 310x in the resist layer 310, exposing a portion of the seed layer 181. The opening 310x is opened to match the shape of the electroplated layer to be formed on the seed layer 181.

[0068] 5(b), copper or the like is deposited on the seed layer 181 exposed in the opening 310x by electrolytic plating using a power supply from the seed layer 181, selectively forming an electrolytic plated layer 182. The electrolytic plated layer 182 fills the opening 17x and is formed to extend above the upper surface of the seed layer 181 around the opening 17x.

[0069] 5(c), the resist layers 310 and 320 are removed. The resist layers 310 and 320 can be removed using, for example, a stripping solution. After the resist layers 310 and 320 are removed, etching is performed using the electroplated layer 182 as a mask to remove the seed layer 181 exposed from the electroplated layer 182, and the wiring layer 18 is formed.

[0070] When seed layer 181 and electroplated layer 182 are made of copper, for example, a hydrogen peroxide / sulfuric acid based aqueous solution, a sodium persulfate aqueous solution, an ammonium persulfate aqueous solution, etc. can be used as the etching solution. Seed layer 281 is also removed at the same time as seed layer 181 is removed. In this way, wiring substrate 1 is obtained.

[0071] 6 and 7 are diagrams illustrating a method for manufacturing a wiring board according to a comparative example. In the method for manufacturing a wiring board according to the comparative example, in the step shown in FIG. 6(a), openings 17x are formed in the solder resist layer 17, similar to the step shown in FIG. 3(a). In the step shown in FIG. 6(b), an alkali treatment is performed as a pretreatment for electroless plating, similar to the step shown in FIG. 3(a). However, in the method for manufacturing a wiring board according to the comparative example, the alkali treatment is performed only once, which corresponds to the first alkali treatment in the method for manufacturing a wiring board according to the first embodiment, and there is no second alkali treatment step. There is also no ultrasonic cleaning step.

[0072] 6(b), the alkali treatment wets and swells the resin that constitutes the solder resist layer 17. As a result, the force with which the solder resist layer 17 fixes the filler 171 in the openings 17x is reduced, causing the filler 171 to fall off from the solder resist layer 17, as shown in FIG.

[0073] In the method for manufacturing a wiring board according to the comparative example, the ultrasonic cleaning process is not performed, so the filler 171 that has fallen off the solder resist layer 17 is not removed from the openings 17x. In addition, in the method for manufacturing a wiring board according to the comparative example, the second alkali process is not performed, so the inner wall surfaces of the recesses 17y and part of the surface of the filler 171 that has fallen off into the openings 17x are in an uncleaned and unconditioned state. Note that in FIG. 6(c), the cleaned and conditioned surfaces are indicated by dashed lines for convenience.

[0074] Next, as shown in FIG. 6(d), a seed layer 181a is formed by electroless plating or the like on the upper surface of the solder resist layer 17, the inner wall surfaces of the openings 17x, and the upper surface of the wiring layer 16 exposed in the openings 17x. The catalyst is not adsorbed to the inner wall surfaces of the recesses 17y that have not been cleaned or conditioned, and electroless plating is not deposited thereon. Similarly, the catalyst is not adsorbed to a portion of the surface of the fallen filler 171 that has not been cleaned or conditioned, and electroless plating is not deposited thereon. As a result, the seed layer 181a is not formed continuously, but has discontinuous portions.

[0075] 4(c) to 5(c) in the method for manufacturing a wiring board according to the first embodiment are then performed. As a result, as shown in FIG. 7(a), a wiring layer 18a is formed in which an electroplated layer 182a is formed on a seed layer 181a, completing a wiring board 1X according to the comparative example. In the wiring board 1X, the electroplated layer 182a is not deposited near the portion where the seed layer 181a is not formed, and therefore, voids B1 to B4 are formed, for example, within the opening 17x.

[0076] Next, as shown in FIG. 7(b), consider a case where the wiring layer 18a of the wiring substrate 1X is electrically connected to the electrode pads 120 of the semiconductor chip 110 via bumps 130, such as solder bumps. As shown in FIG. 7(a), voids B1 to B4 are formed within the opening 17x, and the locations where the voids B1 to B4 exist are likely to become the starting points for cracks C1 and C2 when an electrical or thermal load is applied. The occurrence of cracks C1 and C2 may cause poor electrical conductivity between the wiring layer 18a and the electrode pads 120, reducing the reliability of the connection between the wiring substrate 1X and the semiconductor chip 110.

[0077] In contrast, the method for manufacturing a wiring board according to the first embodiment includes, between the step of forming the opening 17x and the step of forming the wiring layer 18, steps of sequentially performing a first alkaline treatment, an ultrasonic cleaning treatment, and a second alkaline treatment on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed in the opening 17x, as described above.

[0078] Therefore, no areas are left uncleaned and conditioned, and the seed layer 181a is continuously formed without any undeposited portions. As a result, no areas are left where the electroplated layer 182 is not deposited, and therefore no voids are formed within the openings 17x, and no cracks originating from the voids occur.

[0079] As a result, the adhesion between the solder resist layer 17 and the wiring layer 18 is improved, and good adhesion is obtained between them, thereby avoiding problems such as swelling of the wiring layer 18 due to poor adhesion between the solder resist layer 17 and the wiring layer 18.

[0080] Furthermore, since the wiring substrate 1 is subjected to ultrasonic cleaning, there is no residue of the filler 171 at the bottom of the opening 17x, which ensures the connection strength at the connection between the wiring layer 16 and the wiring layer 18 in the opening 17x, improving the connection reliability between the wiring layer 16 and the wiring layer 18.

[0081] Furthermore, when the wiring layer 18 of the wiring substrate 1 is electrically connected to the electrode pads 120 of the semiconductor chip 110 via the bumps 130, there is no risk of poor electrical conductivity occurring between the wiring layer 18 and the electrode pads 120. This improves the connection reliability between the wiring substrate 1 and the semiconductor chip 110.

[0082] Second Embodiment In the second embodiment, an example is shown in which the method for manufacturing a wiring board according to the present invention is applied to internal wiring of a wiring board. Note that in the second embodiment, descriptions of components that are the same as those in the previously described embodiments may be omitted.

[0083] [Structure of wiring board according to second embodiment] First, the structure of the wiring board according to the second embodiment will be described. Figure 8 is a cross-sectional view illustrating the wiring board according to the second embodiment, where Figure 8(a) is an overall view and Figure 8(b) is a partially enlarged view of part C in Figure 8(a).

[0084] 8, in wiring board 1A, wiring layer 14 has the same structure as wiring layer 18 of the first embodiment. That is, wiring layer 14 has a seed layer 141 and an electrolytic plated layer 142, and has a structure in which electrolytic plated layer 142 is laminated on seed layer 141. Wiring layers 16, 24, and 26 may also have the same structure as wiring layer 14.

[0085] The seed layer 141 is continuously formed on the region around the via hole 13x on the upper surface of the insulating layer 13, on the inner wall surface of the via hole 13x, and on the upper surface of the wiring layer 12 exposed in the via hole 13x. The seed layer 141 is made of, for example, copper. The thickness of the seed layer 141 is, for example, about 0.3 to 1 μm.

[0086] 8(b), the filler 173 contained in the insulating layer 13 may partially protrude from the inner wall of the via hole 13x, or a recess 13y may be formed on the inner wall surface of the via hole 13x as a trace left by the fallen filler 173 contained in the insulating layer 13. In such cases, the seed layer 141 is also formed on the surface of the filler 173 exposed from the inner wall surface of the via hole 13x and on the inner wall surface of the recess 13y.

[0087] That is, the seed layer 141 is formed with a substantially uniform thickness on the region around the via hole 13x on the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, the inner wall surface of the recess 13y, and the upper surface of the wiring layer 12 exposed in the via hole 13x. The reason for this will be explained in the section on the manufacturing method of the wiring board 1A.

[0088] The electrolytic plated layer 142 is formed on the seed layer 141. The electrolytic plated layer 142 is formed to fill the via hole 13x and to extend above the upper surface of the seed layer 141 located around the via hole 13x. Here, the portion of the wiring layer 14 filled in the via hole 13x is referred to as a via wiring, and the portion protruding from the upper surface of the insulating layer 13 is referred to as a wiring pattern.

[0089] The wiring pattern constituting the wiring layer 14 may be routed from above the via hole 13x to any position on the upper surface of the insulating layer 13. In other words, the seed layer 141 may be routed from above the via hole 13x to any position on the upper surface of the insulating layer 13, and in this case too, the electroplated layer 142 is laminated on the seed layer 141.

[0090] [Method for manufacturing a wiring board according to the second embodiment] Next, a method for manufacturing a wiring board according to the second embodiment will be described. Figures 9 and 10 are diagrams illustrating the manufacturing process of a wiring board according to the second embodiment. Figures 9 and 10 are cross-sectional views corresponding to Figure 8(b). Note that, although an example of the process for manufacturing one wiring board is shown here, a process may also be used in which multiple parts that will become wiring boards are manufactured and then separated into individual wiring boards.

[0091] First, after performing the same process as in FIG. 2(a) of the first embodiment, a semi-cured film-like non-photosensitive thermosetting resin, mainly composed of an epoxy-based resin, is laminated on one surface 10a of the core layer 10 so as to cover the wiring layer 12, and then cured to form the insulating layer 13. A semi-cured film-like non-photosensitive thermosetting resin, mainly composed of an epoxy-based resin, is laminated on the other surface 10b of the core layer 10 so as to cover the wiring layer 22, and then cured to form the insulating layer 23. Alternatively, instead of laminating a film-like epoxy-based resin, a liquid or paste-like epoxy-based resin may be applied and then cured to form the insulating layers 13 and 23. The thickness of each of the insulating layers 13 and 23 is, for example, approximately 25 to 40 μm.

[0092] Each of the insulating layers 13 and 23 contains filler 173 such as silicon dioxide (SiO2). The particle size of the filler 173 is, for example, about 0.1 to 10 μm. The content of the filler 173 is, for example, about 30 to 80 wt %.

[0093] Although only one surface 10a of the core layer 10 will be illustrated and explained below, the other surface 10b of the core layer 10 undergoes the same process.

[0094] 9(a), a via hole 13x is formed in the insulating layer 13 as an opening that penetrates the insulating layer 13 and exposes the upper surface of the wiring layer 12. Also, a via hole 23x is formed in the insulating layer 23 as an opening that penetrates the insulating layer 23 and exposes the lower surface of the wiring layer 22. A filler 173 is exposed on the inner wall surfaces of the via holes 13x and 23x. The via holes 13x and 23x can be formed by, for example, a laser processing method using a CO2 laser or the like. After the via holes 13x and 23x are formed, a desmear process is preferably performed to remove resin residue adhering to the surfaces of the wiring layers 12 and 22 that are exposed at the bottoms of the via holes 13x and 23x.

[0095] Next, in the step shown in Fig. 9(b), a first alkaline treatment is performed as a pretreatment for electroless plating. Details of the first alkaline treatment are as described in the step shown in Fig. 3(b).

[0096] The first alkaline treatment cleans and conditions the upper surface of the insulating layer 13, the inner wall surfaces of the via holes 13x, the surfaces of the fillers 173 exposed from the inner wall surfaces of the via holes 13x, and the upper surface of the wiring layer 12 exposed in the via holes 13x. Note that in Figure 9(b), the cleaned and conditioned surfaces are indicated by dashed lines for convenience.

[0097] Here, cleaning is a process for washing the surface of insulating layer 13 in order to form a seed layer (electroless plating layer) on the surface of insulating layer 13. Moreover, conditioning is a process for adjusting the surface state of insulating layer 13.

[0098] In this embodiment, a seed layer is formed on the surface of insulating layer 13 by electroless plating. Cleaning and conditioning make it easier for a catalyst (such as palladium) for depositing electroless plating to be adsorbed on the surface of insulating layer 13. The presence of the catalyst allows for the successful formation of an electroless plated layer on the surface of insulating layer 13. In other words, a seed layer for forming an electrolytic plated layer can be successfully formed on the surface of insulating layer 13.

[0099] In addition, the first alkaline treatment cleans and conditions the lower surface of the insulating layer 23, the inner wall surface of the via hole 23x, the surface of the filler 173 exposed from the inner wall surface of the via hole 23x, and the lower surface of the wiring layer 22 exposed in the via hole 23x.

[0100] Furthermore, the first alkali treatment causes the resin constituting the insulating layer 13 to wet and swell. This treatment reduces the force with which the insulating layer 13 fixes the filler 173 in the via holes 13x, making the filler 173 more likely to fall off from the insulating layer 13. Furthermore, the first alkali treatment causes the resin constituting the insulating layer 23 to wet and swell. This treatment reduces the force with which the insulating layer 23 fixes the filler 173 in the via holes 23x, making the filler 173 more likely to fall off from the insulating layer 23.

[0101] Next, in the step shown in Fig. 9(c), an ultrasonic cleaning process is performed. Details of the ultrasonic cleaning process are as explained in the step shown in Fig. 3(c).

[0102] The ultrasonic cleaning process removes filler 173 that was prone to falling off in the process shown in FIG. 9(b). After removal, a recess 13y is formed on the inner wall surface of via hole 13x, representing the trace of the removed filler 173. The removed filler 173 is removed from within via hole 13x by the ultrasonic cleaning process. Note that even if there is filler 173 that has fallen off before the ultrasonic cleaning process, the fallen filler 173 is also removed from within via hole 13x by the ultrasonic cleaning process. The recess 13y formed on the inner wall surface of via hole 13x is in a state that has not been cleaned or conditioned. Note that in FIG. 9(c), the surface that has been cleaned and conditioned is indicated by a dashed line for convenience.

[0103] Next, in the step shown in Fig. 9(d), a second alkali treatment is performed. Details of the second alkali treatment are as described in the step shown in Fig. 3(d).

[0104] The second alkali treatment cleans and conditions the upper surface of the insulating layer 13, the inner wall surfaces of the via holes 13x, the surfaces of the fillers 173 exposed from the inner wall surfaces of the via holes 13x, the inner wall surfaces of the recesses 13y, and the upper surface of the wiring layer 12 exposed in the via holes 13x. Note that in Figure 9(d), the cleaned and conditioned surfaces are indicated by dashed lines for convenience.

[0105] In addition, the second alkaline treatment cleans and conditions the lower surface of the insulating layer 23, the inner wall surface of the via hole 23x, the surface of the filler 173 exposed from the inner wall surface of the via hole 23x, the inner wall surface of the recess formed in the inner wall surface of the via hole 23x, and the lower surface of the wiring layer 22 exposed in the via hole 23x.

[0106] 10(a), a seed layer 141 is continuously formed on the upper surface of the insulating layer 13, the inner wall surfaces of the via holes 13x, and the upper surface of the wiring layer 12 exposed in the via holes 13x. A seed layer is also continuously formed on the lower surface of the insulating layer 23, the inner wall surfaces of the via holes 23x, and the lower surface of the wiring layer 22 exposed in the via holes 23x. The seed layer 141 is made of, for example, copper. The seed layer 141 has a thickness of, for example, about 0.3 to 1 μm. The seed layer 141 can be formed by, for example, electroless plating. The material, thickness, and manufacturing method of the seed layer formed on the lower surface of the wiring layer 22 are the same as those of the seed layer 141.

[0107] The seed layer 141 is also formed on the surface of the filler 173 exposed from the inner wall surface of the via hole 13x and on the inner wall surface of the recess 13y. That is, the seed layer 141 is formed with a substantially uniform thickness on the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, the inner wall surface of the recess 13y, and the upper surface of the wiring layer 12 exposed in the via hole 13x. The same applies to the seed layer formed on the lower surface of the wiring layer 22.

[0108] 10(b), wiring layers 14 and 24 are formed. Specifically, for example, a resist layer having openings corresponding to the shape of wiring layer 14 is formed on seed layer 141. Then, by electrolytic plating using power supplied from seed layer 141, copper or the like is deposited on the seed layer 141 exposed in the openings of the resist layer, selectively forming electrolytic plated layer 142. Next, after removing the resist layer, etching is performed using electrolytic plated layer 142 as a mask, and the seed layer 141 exposed from electrolytic plated layer 142 is removed, thereby forming wiring layer 14 in which electrolytic plated layer 142 is laminated on seed layer 141. Wiring layer 24 can be formed by a similar method.

[0109] After the step shown in FIG. 10(b), an insulating layer 15 is formed on the upper surface of the insulating layer 13 to cover the wiring layer 14 using the same method as for the insulating layer 13. The material and thickness of the insulating layer 15 are, for example, the same as for the insulating layer 13. Furthermore, an insulating layer 25 is formed on the lower surface of the insulating layer 23 to cover the wiring layer 24 using the same method as for the insulating layer 13. The material and thickness of the insulating layer 25 are, for example, the same as for the insulating layer 13. Then, steps similar to those shown in FIGS. 9(a) to 10(b) are performed to form a wiring layer 16 on one side of the insulating layer 15, in which an electrolytic plating layer is formed on a seed layer. Furthermore, a wiring layer 26 on the other side of the insulating layer 25, in which an electrolytic plating layer is formed on a seed layer.

[0110] Next, the same steps as those shown in FIGS. 2(c) to 5(c) of the first embodiment are carried out to complete the wiring board 1A.

[0111] In this way, the method for manufacturing a wiring board according to the present invention may be applied to the internal wiring (wiring layers 14, 16, 24, and 26) of wiring board 1A, thereby achieving the same effects as in the first embodiment.

[0112] <Application example of the first embodiment> In the application example of the first embodiment, an example of a semiconductor package in which a semiconductor chip is mounted on the wiring substrate according to the first embodiment is shown. Note that in the application example of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0113] 11 is a cross-sectional view illustrating a semiconductor package according to an application example of the first embodiment. Referring to FIG. 11, the semiconductor package 100 includes the wiring substrate 1 shown in FIG. 1, a semiconductor chip 110, electrode pads 120, bumps 130, underfill resin 140, and bumps 150.

[0114] The semiconductor chip 110 is, for example, a semiconductor integrated circuit (not shown) formed on a thin semiconductor substrate (not shown) made of silicon, etc. Electrode pads 120 electrically connected to the semiconductor integrated circuit (not shown) are formed on the semiconductor substrate (not shown).

[0115] The bumps 130 are formed on the electrode pads 120 of the semiconductor chip 110 and are electrically connected to the wiring layer 18 of the wiring substrate 1. An underfill resin 140 is filled between the semiconductor chip 110 and the upper surface of the wiring substrate 1. The bumps 150 are formed on the lower surface of the wiring layer 26 exposed at the bottom of the openings 27x of the solder resist layer 27. The bumps 150 are connected to, for example, a motherboard. The bumps 130 and 150 are, for example, solder bumps. Examples of materials that can be used for the solder bumps include an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu.

[0116] In this way, a semiconductor package 100 can be realized in which a semiconductor chip 110 is mounted on the wiring substrate 1 according to the first embodiment. As described above, in the wiring substrate 1, no voids are formed within the openings 17x, and no cracks originating from the voids occur. Therefore, there is no risk of poor electrical conductivity between the wiring layer 18 and the electrode pads 120, and the connection reliability between the wiring substrate 1 and the semiconductor chip 110 can be improved.

[0117] In semiconductor package 100, wiring board 1 may be replaced with wiring board 1A.

[0118] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0119] For example, in the above embodiment, the present invention is applied to a wiring board having a core layer manufactured by a build-up method, but the present invention may also be applied to a coreless wiring board manufactured by a build-up method. Furthermore, the present invention is not limited to these, and can be applied to various wiring boards. [Explanation of symbols]

[0120] 1. 1A wiring board 10 Core Layer 10a One side 10b The other side 10x through holes 11 Through wiring 12, 14, 16, 18, 22, 24, 26 wiring layer 13, 15, 23, 25 Insulation layers 13x, 15x, 23x, 25x via holes 13y, 17y recess 17, 27 Solder resist layer 17x, 27x opening 100 Semiconductor Packages 110 Semiconductor Chips 120 electrode pads 130, 150 bump 140 Underfill resin 141, 181 seed layer 142, 182 Electroplated layer 171, 173 Filler

Claims

1. an insulating layer containing a filler that covers the first wiring layer; an opening formed in the insulating layer to expose an upper surface of the first wiring layer; a second wiring layer that fills the opening, is electrically connected to the first wiring layer, and extends from within the opening to an upper surface of the insulating layer; the second wiring layer includes a via wiring that fills the opening and is electrically connected to the first wiring layer, and a wiring pattern and / or a pad formed on the via wiring; The particle size of the filler is 0.1 μm or more and 10 μm or less, a recessed portion, which is a mark left by removing the filler, is formed on an inner wall surface of the opening; the second wiring layer has a structure in which an electroplated layer is laminated on a seed layer having a thickness of 0.3 μm or more and 1 μm or less, a catalyst is adsorbed on at least an inner wall surface of the opening, a surface of the filler exposed from the inner wall surface of the opening, an inner wall surface of the recess, and an upper surface of the first wiring layer exposed in the opening; the seed layer is formed on the catalyst continuously along at least an inner wall surface of the opening, a surface of the filler exposed from the inner wall surface of the opening, an inner wall surface of the recess, and an upper surface of the first wiring layer exposed in the opening; The electroplating layer is formed continuously on the seed layer along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed in the opening, filling the inside of the opening including the inside of the recess.

2. 2. The wiring substrate of claim 1, wherein the seed layer is formed continuously on the catalyst with a substantially uniform thickness along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed in the opening.

3. 3. The wiring board according to claim 1, wherein the content of the filler is 30 to 80% by weight.

4. the insulating layer is an outermost insulating layer, The wiring board according to claim 1 , wherein the second wiring layer includes a pad formed on the via wiring.

5. 5. The wiring board according to claim 4, wherein the pads are electronic component mounting pads for electrically connecting to electronic components.

6. the insulating layer is an interlayer insulating layer, The wiring board according to claim 1 , wherein the second wiring layer includes a wiring pattern formed on the via wiring.

Images