Active control of light-emitting diodes and light-emitting diode displays

Abstract

To provide an improved LED array device with small pixel pitches.SOLUTION: The invention provides an LED package 26 at a particular state of fabrication where a plurality of LEDs 28-1 to 28-3 and an active electrical element 30 are mounted on a submount 32. A controller may be included that is configured to transmit communication signals to one or more strings of LED pixels. An active electrical element in each LED pixel may be configured to receive the communication signals, generate corresponding synchronization signals, and make a response harmoniously with all other LED pixels in a particular LED display. Fault mitigation of LED pixel faults in an LED string is provided when the controller is configured with bidirectional communication ports for communication with the LED string. In a fault mitigation process, the bidirectional communication ports may switch directions to provide the communication signals to both sides of the LED string.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001]

[0002] The present invention relates to solid state lighting devices, including light emitting diode devices and light emitting diode displays. [Background technology]

[0002]

[0003] Light-emitting diodes (LEDs) are solid-state devices that convert electrical energy into light and generally include one or more active layers of semiconductor material (or active region) disposed between oppositely doped n-type and p-type layers. When a bias is applied across the doped layers, holes and electrons are injected into the active layer(s), where they recombine to generate emission, such as visible or ultraviolet emission. LED chips typically include an active region that may be fabricated from epitaxial layers of, for example, silicon carbide, gallium nitride, aluminum gallium nitride, indium nitride, gallium phosphide, aluminum nitride, gallium arsenide-based materials, and / or from organic semiconductor materials.

[0003]

[0004] LEDs have been widely adopted in a variety of lighting environments for backlighting liquid crystal display (LCD) systems (e.g., as a replacement for cold cathode fluorescent tubes) and for direct-view LED displays. Applications utilizing LED arrays include vehicle headlamps, roadway lighting, luminaires, and a variety of indoor, outdoor, and professional environments. Desirable properties of LED devices include high luminous efficacy, long lifetime, and wide color gamut.

[0004]

[0005] Conventional LCD systems require polarizers and color filters (e.g., red, green, and blue), which inherently reduce light utilization efficiency. Direct-view LED displays, which utilize self-emitting LEDs and eliminate the need for backlighting, polarizers, and color filters, offer increased light utilization efficiency.

[0005]

[0006] Large, multicolor, direct-view LED displays (including full-color LED video screens) typically include many individual LED panels, packages, and / or components that provide image resolution determined by the distance between adjacent pixels, or “pixel pitch.” Direct-view LED displays include tri-color displays with arrayed red, green, and blue (RGB) LEDs and bi-color displays with arrayed red and green (RG) LEDs. Other colors or color combinations may also be used. Large displays intended to be viewed from a distance (e.g., digital signage and stadium displays) typically have a relatively large pixel pitch and usually include separate LED arrays with multicolor (e.g., red, green, and blue) LEDs that may be independently operated to form what appear to the viewer to be full-color pixels. Medium-sized displays with relatively smaller viewing distances require a smaller pixel pitch (e.g., 3 mm or less) and may include panels in which arrayed red, green, and blue LED components are mounted on a single electronic device attached to a driver printed circuit board that controls the LEDs. Driver printed circuit boards are typically densely populated with electronic devices, including capacitors, field effect transistors (FETs), decoders, microcontrollers, and the like, for driving the display's pixels. As pixel pitch continues to decrease for higher resolution displays, the density of such electronic devices becomes greater, corresponding to the increased number of pixels in a given panel area. This tends to add greater complexity and cost to LED panels for display applications, as well as increase thermal congestion in areas where the driver electronics are spaced closer together. Summary of the Invention [Problem to be solved by the invention]

[0006]

[0007] The art continues to seek improved LED array devices with small pixel pitches while overcoming the limitations associated with conventional devices and production methods. [Means for solving the problem]

[0007]

[0008] The present disclosure relates to light-emitting diodes (LEDs), LED packages, and related LED displays, and more particularly to active control of LEDs within an LED display. An LED display may include rows and columns of LED diodes forming an array of LED pixels. A particular LED pixel may include a collection of LED chips of the same color or multiple colors; an exemplary LED pixel includes a red LED chip, a green LED chip, and a blue LED chip. In certain embodiments, an LED package may include multiple LED chips forming at least one LED pixel, and multiple such LED packages may be arranged to form an array of LED pixels for an LED display. Each LED package may include active electrical elements configured to receive control signals and actively maintain an operating state, such as a brightness or gray level or color selection signal, for the LED chips of the LED package while other LED packages are addressed. In certain embodiments, the active electrical elements may include active circuitry including one or more of a driver device, a signal conditioning or conversion device, a memory device, a decoder device, an electrostatic discharge (ESD) protection device, a thermal management device, and a detection device, among others. In this regard, each LED pixel of the LED display may be configured for operation using active matrix addressing. The active electrical elements may be configured to receive one or more of analog control signals, coded analog control signals, digital control signals, and coded digital control signals. A display panel is disclosed that includes an array of such LED pixels on a first side of the panel and control circuitry on a back side of the panel that is configured to communicate with each active electrical element of the LED pixels.

[0008]

[0009] According to aspects of the present disclosure, synchronization of LED pixels within an LED display is provided so that one or more actions of all LED pixels can be initiated at the same time or within milliseconds. The LED display and corresponding system may include a controller configured to send communication signals to one or more strings of LED pixels. Active electrical elements within each LED pixel may be configured to receive the communication signals, generate corresponding synchronization signals, and respond in a coordinated manner with all other LED pixels within the particular LED display. A further aspect of the present disclosure includes fault mitigation of an LED pixel failure within an LED string, in which the controller is configured with a bidirectional communication port for the LED string. During the fault mitigation process, the bidirectional communication port may switch direction to provide communication signals to both sides of the LED string.

[0009]

[0010] In one aspect, an LED package includes at least one LED chip and an active electrical element electrically connected to the at least one LED chip, the active electrical element configured to receive serial communications from a data stream and determine a synchronization signal correlated to a repeating pattern of data in the data stream. In certain embodiments, the active electrical element includes a counter configured to count the synchronization signals. In certain embodiments, the counter is configured to count down from a counter start value corresponding to a location of the active electrical element. In certain embodiments, the active electrical element is configured to initiate an event signal when the counter reaches a first predetermined value. In certain embodiments, the first predetermined value is determined based on a location of the active electrical element, and the event signal initiated in the active electrical element is synchronized with other active elements arranged to receive the data stream. Certain embodiments In the embodiment, the event signal includes one or more of turning on at least one LED chip, turning off at least one LED chip, and maintaining at least one LED chip in an activated state. In certain embodiments, the active electrical element is configured to initiate a second event signal when the counter reaches a second predetermined value. In certain embodiments, the second event signal includes one or more of turning on at least one LED chip, turning off at least one LED chip, and maintaining at least one LED chip in an activated state. In certain embodiments, an output of the counter is provided to a processing unit of the active electrical element. In certain embodiments, the active electrical element includes an overflow register configured to provide an overflow bit to the processing unit. In certain embodiments, the counter is configured to be reset when one or more predetermined commands from the data stream are received by the active electrical element. In certain embodiments, the one or more predetermined commands include an end of frame command.

[0010]

[0011] Another aspect of controlling an LED display includes providing a first LED string including a plurality of first LED pixels, each of the plurality of first LED pixels including at least one LED chip and an active electrical element; loading different counter values ​​into the active electrical element of each of the first LED pixels based on a location of each of the first LED pixels in the first LED string; and synchronizing operational states of each of the first LED pixels based on the different counter values. In certain embodiments, the loading of the different counter values ​​is performed by a controller connected to the first LED string. In certain embodiments, the method further includes providing a second LED string including a plurality of second LED pixels, each of the plurality of second LED pixels including at least one LED chip and an active electrical element; loading different counter values ​​into the active electrical element of each of the second LED pixels based on a location of each of the second LED pixels in the second LED string; and synchronizing operational states of the plurality of first LED pixels and the plurality of second LED pixels based on the counter values. In certain embodiments, synchronizing the operational states of the plurality of first LED pixels and the plurality of second LED pixels includes turning the plurality of first LED pixels and the plurality of second LED pixels on or off. In certain embodiments, synchronizing the operational states of each first LED pixel provides a time frame during which the plurality of first LED pixels are all turned off. In certain embodiments, the LED display is a three-dimensional (3D) LED display requiring 3D shutter glasses for a viewer, and the time frame is determined to allow the 3D shutter glasses to transition from one viewing condition to another viewing condition while the plurality of first LED pixels are off.

[0011]

[0012] In one aspect, an LED package comprises at least one LED chip and an active electrical element electrically connected to the at least one LED chip, the active electrical element configured to provide a pulse-width modulation (PWM) signal to the at least one LED chip, the PWM signal including a PWM period and a PWM duty cycle, interrupt the PWM signal for a portion of the PWM period, and resume the PWM signal from the interrupted portion of the PWM period. In a specific embodiment, the active electrical element is configured to receive serial communication from a data stream, determine a synchronization signal correlated to a repetitive pattern of data in the data stream, count down the synchronization signal from a counter start value corresponding to the location of the at least one LED chip, and initiate a first event signal to interrupt the PWM signal when the count reaches a predetermined value. In a specific embodiment, the active electrical element is configured to initiate a second event signal to resume the PWM signal when the count reaches a second predetermined value. The method is further configured to:

[0012]

[0013] In another aspect, an LED package comprises at least one LED chip and an active electrical element electrically connected to the at least one LED chip, the active electrical element configured to receive data from a data stream in a communication direction and respond to a command in the data stream by reversing the communication direction of the data stream. In certain embodiments, the active electrical element is configured to transmit a command in the communication direction before reversing the communication direction. In certain embodiments, the active electrical element is configured to provide return data to the data stream after reversing the communication direction. In certain embodiments, the return data comprises pulses configured to be counted by a controller for the LED package. The LED package may further comprise at least one bidirectional communication port configured to receive a command and then respond to the command by reversing the direction of the at least one bidirectional communication port.

[0013]

[0014] In another aspect, an LED display includes at least one LED string including a plurality of LED pixels, each LED pixel including at least one LED chip and an active electrical element; and a controller connected to the at least one LED string, the controller configured to provide a fault mitigation process that identifies one or more operable LED pixels of the LED string and at least one inoperable LED pixel of the LED string, the fault mitigation process including sending a communication to the at least one LED string, the active electrical elements of the one or more operable LED pixels sending a return communication to the controller, and the at least one inoperable LED pixel not responding to the communication. In certain embodiments, the communication is a polling communication, and the return communication is a return polling communication. In certain embodiments, the return communication includes a ping or pulse from each of the one or more operable LED pixels. In certain embodiments, the controller is configured to count each ping or pulse to determine the number of the one or more operable LED pixels. In certain embodiments, the controller includes a first bidirectional communication port and a second bidirectional communication port coupled to opposite ends of the at least one LED string. In certain embodiments, the communication direction of one of the first and second bidirectional communication ports is reversed to receive the return polling communication. The LED display may further include a data line tap connected between at least one adjacent pair of LED pixels of the plurality of LED pixels in the at least one LED string. In certain embodiments, communication through the data line tap is initiated during a fault mitigation process. In certain embodiments, each LED pixel of the plurality of LED pixels includes at least one bidirectional communication port configured to receive the polling communication and then reverse the communication direction of the at least one bidirectional communication port to send the return polling communication to the controller.In certain embodiments, in the range of 10 to 100 LED pixels of the plurality of LED pixels in at least one LED string are arranged along the periphery of the LED display.

[0014]

[0015] In other embodiments, any of the foregoing embodiments and / or various separate embodiments and features as described herein may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein.

[0015]

[0016] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures.

[0017] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief explanation of the drawings]

[0016] [Figure 1A]

[0018] 1 is a top view of the front of a representative display panel for a light-emitting diode (LED) display including a plurality of active LED pixels. [Figure 1B]

[0019] 1B is a bottom view of the rear surface of the exemplary display panel of FIG. 1A. [Figure 2A]

[0020] 1 is a bottom view of an LED package in a particular state of manufacture, with multiple LEDs and active electrical elements mounted on a submount. [Figure 2B]

[0021] 2B is a cross-sectional view taken along section line AA of FIG. 2A. [Figure 2C]

[0022] 2B is a bottom view of the LED package of FIG. 2A at a later stage of manufacture, in which an encapsulation layer and a plurality of conductive traces have been formed. [Figure 2D]

[0023] 2D is a cross-sectional view taken along section line BB in FIG. 2C. [Figure 2E]

[0024] 2D is a bottom view of the LED package of FIG. 2C in a subsequent state of manufacture, in which an additional encapsulation layer and multiple package bond pads have been formed. [Figure 2F]

[0025] FIG. 2B is a cross-sectional view taken along section line CC of FIG. 2E. [Figure 2G]

[0026] FIG. 2B is a cross-sectional view taken along section line DD in FIG. 2E. [Figure 2H]

[0027] FIG. 2F is a simplified top view of the LED package of FIG. 2E. [Figure 2I]

[0028] FIG. 2F is a simplified bottom view of the LED package of FIG. 2E. [Figure 3A]

[0029] 1 is a bottom view of a representative LED package including multiple conductive traces, portions of certain of the conductive traces forming package bond pads for the LED package. [Figure 3B]

[0030] 3B is a cross-sectional view taken along section line EE of FIG. 3A. [Figure 4]

[0031] 1 is a cross-sectional view of an LED package illustrating a configuration in which one or more LED chips and active electrical elements are mounted along the same horizontal plane. [Figure 5]

[0032] 1 is a cross-sectional view of an LED package illustrating a configuration in which one or more LED chips are mounted along a first horizontal plane and an active electrical element is mounted along a second horizontal plane different from the first horizontal plane. [Figure 6]

[0033] 1 is a cross-sectional view of an LED package illustrating a configuration in which one or more LED chips and an active electrical element are mounted on opposite sides of a submount. [Figure 7]

[0034] 1 is a bottom view of an LED package including a plurality of LED pixels according to an embodiment disclosed herein. [Figure 8]

[0035] FIG. 2 is a block schematic diagram illustrating components of an active electrical element according to embodiments disclosed herein. [Figure 9]

[0036] FIG. 2 is a block schematic diagram illustrating components of an active electrical element according to embodiments disclosed herein. [Figure 10]

[0037] 1 is a schematic diagram illustrating an example structure of a volatile memory element that may be included within an active electrical element according to embodiments disclosed herein. [Figure 11A]

[0038] FIG. 1 is a schematic diagram illustrating a driver element including a voltage-controlled current source circuit. [Figure 11B]

[0039] FIG. 1 is a schematic diagram illustrating a driver element including transconductance amplifiers arranged in an active cascode configuration. [Figure 11C]

[0040] FIG. 11C is a schematic diagram illustrating a driver element including an input amplifier added to the driver element of FIG. 11B. [Figure 11D]

[0041] FIG. 11D is a schematic diagram illustrating a driver element similar to that of FIG. 11C, but with reversed polarity connections. [Figure 11E]

[0042] FIG. 1 is a schematic diagram illustrating a driver element including a Howland current pump. [Figure 11F]

[0043] FIG. 11F is a schematic diagram illustrating a driver element similar to that of FIG. 11E, adding a voltage divider and an additional operational amplifier. [Figure 12A]

[0044] FIG. 1 is a block schematic diagram illustrating an embodiment of an active electrical element including a detector element. [Figure 12B]

[0045] FIG. 2 is a bottom view of an LED package including a photodiode according to an embodiment disclosed herein. [Figure 13]

[0046] FIG. 2 is a block schematic diagram illustrating various components that may be included in a system level control scheme for an LED display panel according to embodiments disclosed herein. [Figure 14]

[0047] FIG. 1 is a schematic diagram illustrating a configuration in which an active electrical element corresponding to a particular LED pixel is configured to receive a row select signal line and separate control signals for each red, green, and blue LED chip included within the LED pixel. [Figure 15]

[0048] FIG. 10 is a schematic diagram illustrating a configuration in which an active electrical element associated with a particular LED pixel is configured to receive a separate row select signal line for each LED chip of the LED pixel, and a single color level signal line for all of the LED chips within the LED pixel. [Figure 16]

[0049] FIG. 10 is a schematic diagram illustrating a configuration in which an active electrical element corresponding to a particular LED pixel is configured to receive coded row select signals for each LED chip of the LED pixel, and a single color level signal line for all of the LED chips within the LED pixel. [Figure 17]

[0050] FIG. 1 is a schematic diagram illustrating a configuration in which the active electrical elements of a particular LED package are configured to receive a row select signal, a color level signal, and one or more color select signals for the red, green, and blue LED chips contained within the LED package. [Figure 18]

[0051] FIG. 18 is a schematic diagram illustrating an independent notation configuration that is similar to the configurations of both FIGS. 16 and 17. [Figure 19]

[0052] FIG. 10 is a schematic diagram illustrating a configuration in which an active electrical element associated with a particular LED pixel is configured to receive a single row select signal line and a single color level signal line for all LED chips of the LED pixel. [Figure 20]

[0053] FIG. 10 is a schematic diagram illustrating a configuration in which an active electrical element associated with a particular LED pixel is configured to receive a single row select signal line and a single color level signal line for all LED chips of the LED pixel. [Figure 21]

[0054] 21 is a block schematic diagram illustrating a system level control scheme for an LED display panel in which each active electrical element of an LED pixel array is configured to receive a signal line according to the embodiment of FIG. 20. [Figure 22]

[0055] 22 is a partial plan view illustrating a routing configuration for an LED display panel configured for operation according to the configurations of FIGS. 20 and 21. FIG. [Figure 23]

[0056] FIG. 1 is a schematic diagram illustrating a configuration in which active electrical elements corresponding to particular LED pixels are configured to receive all-digital communications for row, column, and / or color selection signals. [Figure 24]

[0057] FIG. 24 is a block schematic diagram illustrating a system level control scheme for an LED display panel in which each active electrical element of an LED pixel array is configured to receive a signal line according to the embodiment of FIG. 23. [Figure 25]

[0058] 24 is a partial plan view illustrating a routing configuration for an LED display panel configured for operation according to the configuration of FIG. 23. [Figure 26A]

[0059] 1 is a schematic diagram illustrating an exemplary data packet arrangement according to an embodiment disclosed herein. [Figure 26B] 1 is a schematic diagram illustrating an exemplary data packet arrangement according to an embodiment disclosed herein. [Figure 27]

[0060] 10 is a schematic diagram illustrating a cascaded flow of data packets from a control element to multiple LED packages according to embodiments disclosed herein. [Figure 28]

[0061] 1 is a schematic diagram illustrating a cascaded flow of data packets from a control element to a plurality of LED packages, and a flow of one or more talkback data packets to the control element, according to an embodiment disclosed herein. [Figure 29]

[0062] FIG. 10 is a schematic diagram illustrating a cascaded flow of data packets from a control element, additionally including a data packet configured to provide information to all LED packages, according to an embodiment disclosed herein. [Figure 30]

[0063] FIG. 10 is a schematic diagram illustrating a cascaded flow of data packets from a control element that additionally includes one or more subsequent data packets configured to provide additional information to at least one LED package, according to an embodiment disclosed herein. [Figure 31]

[0064] 1 is a partial plan view illustrating a routing configuration for an LED panel configured for operation according to embodiments disclosed herein. [Figure 32]

[0065] 10A-10C are partial plan views illustrating routing configurations for LED panels including LED packages with selectively assignable communication ports according to embodiments disclosed herein. [Figure 33]

[0066] 10 is a partial plan view illustrating another routing configuration for an LED panel including LED packages with selectively assignable communication ports according to embodiments disclosed herein. [Figure 34]

[0067] 34 is a partial plan view illustrating a routing configuration for the LED panel of FIG. 33 with the addition of voltage and ground wires according to embodiments disclosed herein. [Figure 35]

[0068] 1 is a schematic diagram illustrating various inputs and corresponding actions for an active electrical element according to embodiments disclosed herein. [Figure 36]

[0069] 1 is a schematic diagram illustrating an active electrical element comprising a finite state machine according to an embodiment disclosed herein. [Figure 37]

[0070] 1 is a schematic diagram illustrating an embodiment in which an active electrical element is configured to detect normal or adverse operating conditions of at least one LED, according to embodiments disclosed herein. [Figure 38]

[0071] 1 is a schematic diagram illustrating an embodiment in which an active electrical element is configured to provide both a forward bias state and a reverse bias state to at least one LED according to embodiments disclosed herein. [Figure 39]

[0072] FIG. 39 is a schematic diagram illustrating an embodiment in which the resistor network and corresponding select switches of FIG. 38 are replaced with current sources according to embodiments disclosed herein. [Figure 40]

[0073] FIG. 40 is a schematic diagram illustrating a multiple LED embodiment similar to that of FIG. 39. [Figure 41]

[0074] 41 is a schematic diagram illustrating the active electrical element of FIG. 40 configured with multiple ports including a supply voltage, ground, and a bidirectional communication port according to an embodiment disclosed herein. [Figure 42]

[0075] FIG. 42 is a schematic diagram illustrating the active electrical element of FIG. 41 configured with polarity-independent input capability according to an embodiment disclosed herein. [Figure 43]

[0076] FIG. 43 is a schematic diagram illustrating a four-input rectifier that may be used to provide initial power to the switching network of FIG. 42. [Figure 44A]

[0077] FIG. 1 is a schematic diagram illustrating an embodiment in which an active electrical element is configured to partition a duty cycle for pulse width modulation (PWM) control of one or more LEDs. [Figure 44B]

[0078] 10 is a schematic diagram illustrating an embodiment in which a counter conversion device is configured to be shared among multiple LEDs to partition corresponding duty cycles for the LEDs. FIG. [Figure 45]

[0079] FIG. 10 is a table diagram for providing a sequentially ordered counter for PWM control of one or more LEDs. [Figure 46]

[0080] FIG. 10 is a table diagram for providing a non-sequentially ordered counter following a bit-reversed sequence for PWM control of one or more LEDs. [Figure 47]

[0081] FIG. 10 is a table diagram for providing a non-sequentially ordered counter following a partial bit-reversal sequence for PWM control of one or more LEDs. [Figure 48]

[0082] FIG. 10 is a table diagram for providing a non-sequentially ordered counter following two-segment sequencing for PWM control of one or more LEDs. [Figure 49]

[0083] FIG. 10 is a table diagram for providing a non-sequentially ordered counter following four-segment sequencing for PWM control of one or more LEDs. [Figure 50]

[0084] FIG. 10 is a table diagram for providing a non-sequentially ordered counter following 8-segment sequencing for PWM control of one or more LEDs. [Figure 51A]

[0085] FIG. 1 illustrates a data stream in return-to-zero (RZ) format that may be provided to an active electrical element. [Figure 51B]

[0086] FIG. 10 illustrates a data stream in RZ format that includes a reset signal that may be provided to an active electrical element. [Figure 52]

[0087] FIG. 1 is a block schematic diagram illustrating a system level control scheme for an LED display panel in accordance with the synchronization principles of the present disclosure. [Figure 53]

[0088] 53 is a schematic process flow for the sub-controllers of FIG. 52 in accordance with the synchronization principles of the present disclosure. [Figure 54]

[0089] 54 is a schematic process flow for an exemplary process for counter logic within the active electrical elements of each LED pixel connected to the sub-controller of FIG. 53. [Figure 55]

[0090] 55 is a schematic process flow for an exemplary process of a processing unit in the active electrical element of FIG. 54. [Figure 56]

[0091] FIG. 1 is a block schematic diagram illustrating a system level control scheme for an LED display panel in accordance with the fault mitigation principles of the present disclosure. [Figure 57]

[0092] 1 is a top layout view of a portion of an LED display for an embodiment in which data line taps are provided along one or more LED strings of the LED display. DETAILED DESCRIPTION OF THE INVENTION

[0017]

[0093] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the present embodiments and to illustrate the best mode of practicing the present embodiments. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and recognize applications of these concepts not specifically addressed herein. It is understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0018]

[0094] While terms such as first, second, etc. may be used herein to describe various elements, it should be understood that these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019]

[0095] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it is understood that it can be directly on or extending directly onto the other element, or that intervening elements may be present. Conversely, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "over" or extending "over" another element, it can be directly on or extending directly onto the other element. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0020]

[0096] Relative terms such as "bottom" or "top" or "upper" or "lower" or "horizontal" or "vertical" or "top" or "bottom" or "row" or "column" may be used herein to describe the relationship of one element, layer, surface, or region to another element, layer, surface, or region, as illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in a particular figure is turned over, an element, layer, surface, or region described as "top" would hereafter be oriented as "bottom."

[0021]

[0097] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It is further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0022]

[0098] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this specification and related art, and should not be interpreted in an idealized or overly formal sense, unless expressly defined as such within this specification.

[0023]

[0099] The present disclosure relates to light-emitting diodes (LEDs), LED packages, and related LED displays, and more particularly to active control of LEDs within an LED display. An LED display may include rows and columns of LEDs forming an array of LED pixels. A particular LED pixel may include a collection of LED chips of the same color or multiple colors; an exemplary LED pixel includes a red LED chip, a green LED chip, and a blue LED chip. In certain embodiments, an LED package may include multiple LED chips forming at least one LED pixel, and multiple such LED packages may be arranged to form an array of LED pixels for an LED display. Each LED package may include active electrical elements configured to receive control signals and actively maintain an operating state, such as a brightness or gray level or color selection signal, for the LED chips of the LED package while other LED packages are addressed. In certain embodiments, the active electrical elements may include active circuitry including one or more of a driver device, a signal conditioning or conversion device, a memory device, a decoder device, an electrostatic discharge (ESD) protection device, a thermal management device, and a detection device, among others. In this regard, the LED display may include a plurality of LED chips that form at least one LED pixel, and a plurality of such LED packages may be arranged to form an array of LED pixels for an LED display. Each LED pixel may be configured for operation using active matrix addressing. The active electrical elements may be configured to receive one or more of an analog control signal, a coded analog control signal, a digital control signal, and a coded digital control signal. A display panel is disclosed that includes an array of such LED pixels on a first side of the panel and control circuitry on a back side of the panel that is configured to communicate with each active electrical element of the LED pixels.

[0024]

[0100] The present disclosure relates to LEDs, LED packages, and The present invention relates to active control of related LED displays. In certain embodiments, the effective PWM frequency for LEDs is increased by segmenting the duty cycle at which the LEDs are electrically activated within each PWM period. Segmenting the duty cycle within a PWM period may be achieved by modifying or reordering the sequence in which a comparator outputs control signals to a driver that operates the LEDs. In this manner, the duty cycle within each PWM period may be segmented over a series of pulses that electrically activate and deactivate each LED multiple times within each PWM period, rather than continuously holding the LEDs in an electrically activated state for the duration of the duty cycle. In certain embodiments, active electrical elements incorporated within one or more LED packages of an LED display can segment the duty cycle for one or more LEDs. In certain embodiments, an active electrical element is disclosed that can receive a reset signal from a data stream to either initiate a reset action or pass the reset signal along to other active electrical elements of the display.

[0025]

[0101] According to an aspect of the present disclosure, the synchronization of LED pixels in an LED display is The LED display and corresponding system may include a controller configured to send communication signals to one or more strings of LED pixels. Active electrical elements within each LED pixel may be configured to receive the communication signals, generate corresponding synchronization signals, and respond in a coordinated manner with all other LED pixels within the particular LED display. A further aspect of the present disclosure includes fault mitigation of an LED pixel failure within an LED string, in which the controller is configured with a bidirectional communication port for the LED string. In fault mitigation mode, the bidirectional communication port may switch direction to provide communication signals to both sides of the LED string.

[0026]

[0102] An LED chip typically consists of many different semiconductor layers arranged in different ways. The active LED structure comprises an active LED structure or region that may have a number of different layers, each of which may have a number of different structures. The fabrication and operation of LEDs and their active structures are generally known in the art and will only be briefly described herein. The layers of the active LED structure can be fabricated using known processes, with metalorganic chemical vapor deposition being a preferred process. The layers of the active LED structure can comprise many different layers, typically comprising an active layer sandwiched between n-type and p-type oppositely doped epitaxial layers, all of which are formed in sequence on a growth substrate. It should be understood that additional layers and elements can also be included within the active LED structure, including, but not limited to, buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, current spreading layers, and light extraction layers and elements. The active layer can comprise a single quantum well, multiple quantum wells, a double heterostructure, or a superlattice structure.

[0027]

[0103] The active LED structure can be fabricated from different material systems, some of which The material system is a group III nitride-based material system. Group III nitrides are composed of nitrogen and periodic This term refers to semiconductor compounds formed between elements within Group III of the table, typically aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. Group III nitrides also refer to ternary and quaternary compounds such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). In Group III nitrides, silicon (Si) is a common n-type dopant, and magnesium (Mg) is a common p-type dopant. Thus, for Group III nitride-based material systems, the active, n-type, and p-type layers may include one or more layers of GaN, AlGaN, InGaN, and AlInGaN, either undoped or doped with Si or Mg. Other material systems include silicon carbide (SiC), organic semiconductor materials, and other III-V systems such as gallium phosphide (GaP), gallium arsenide (GaAs), and related compounds.

[0028]

[0104] The active LED structure is made of sapphire, SiC, and aluminum nitride (AlN They may be grown on growth substrates that can include many materials, such as GaN, GaN, and the like. The preferred substrate is the 4H polytype of SiC, but other SiC polytypes, including the 3C, 6H, and 15R polytypes, can also be used. SiC has certain advantages, such as a closer crystal lattice match to III-nitrides than other substrates, resulting in high-quality III-nitride films. SiC also has very high thermal conductivity, and as a result, the total output power of III-nitride devices on SiC is not limited by the heat dissipation of the substrate. Sapphire is another common substrate for III-nitrides, and it also has certain advantages, including lower cost, an established manufacturing process, and good translucent optical properties.

[0029]

[0105] Different embodiments of the active LED structure include the active layer and the n-type and n-type The LED chip can emit different wavelengths of light depending on the hybridization of the p-type and p-type layers. For example, active LED structures for various LEDs may emit blue light with a peak wavelength range of approximately 430 nanometers (nm) to 480 nm, green light with a peak wavelength range of 500 nm to 570 nm, and red light with a peak wavelength range of 600 nm to 650 nm. The LED chip can also be coated with one or more lumiphor or other conversion materials, such as phosphors, so that at least a portion of the light from the LED chip is absorbed by the one or more phosphors and converted to one or more different wavelength spectrums according to the characteristic emission from the one or more phosphors. In some embodiments, the combination of the LED chip and one or more phosphors emits a generally white light combination. The one or more phosphors may be yellow (e.g., YAG:Ce), green (e.g., LuAg:Ce), and red (e.g., Ca i-x-y Sr x EU y AlSiN3) luminescent phosphors, and combinations thereof. The lumiphore material as described herein may be or include one or more of a phosphor, a scintillator, a lumiphore ink, a quantum dot material, a daylight tape, and the like. The lumiphore material may be provided by any suitable means, such as directly coated on one or more surfaces of the LED, dispersed in an encapsulant material configured to cover one or more LEDs, and / or coated on one or more optical or support elements (e.g., by powder coating, inkjet printing, or the like). In certain embodiments, the lumiphore material may be downconverting or upconverting, and both downconverting and upconverting materials may be provided. In certain embodiments, multiple different (e.g., compositionally different) lumiphore materials arranged to produce different peak wavelengths may be arranged to receive the emitted light from one or more LED chips.

[0030]

[0106] The light emitted from the active layer or region of the LED chip is typically The mirror has a Conversian emission pattern. For directional applications, an internal mirror or external reflective surface may be employed to redirect as much light as possible toward the desired emission direction. The internal mirror may include a single or multiple layers. Some multilayer mirrors include a metallic reflector layer and a dielectric reflector layer, with the dielectric reflector layer disposed between the metallic reflector layer and the multiple semiconductor layers. A passivation layer may be disposed between the metallic reflector layer and first and second electrical contacts, with the first electrical contact disposed in conductive electrical communication with the first semiconductor layer and the second electrical contact disposed in conductive electrical communication with the second semiconductor layer. In some embodiments, the first and second electrical contacts may themselves be configured as mirror layers. For single-layer or multilayer mirrors that include surfaces exhibiting less than 100% reflectivity, some light may be absorbed by the mirror. Additionally, light redirected through the active LED structure may be absorbed by other layers or elements within the LED chip.

[0031]

[0107] As used herein, a layer or region of a light-emitting device refers to that layer or region. A layer or region may be considered "transparent" when at least 80% of the luminescent radiation incident on that layer or region emerges through that layer or region. Furthermore, as used herein, a layer or region of an LED is considered to be "reflective" or embody a "mirror" or "reflector" when at least 80% of the luminescent radiation incident on that layer or region is reflected. In some embodiments, the luminescent radiation includes visible light, such as blue and / or green LEDs, with or without lumiphor materials. In other embodiments, the luminescent radiation may include non-visible light. For example, in the context of GaN-based blue and / or green LEDs, silver (e.g., at least 80% reflective) may be considered a reflective material. For ultraviolet (UV) LEDs, appropriate materials may be selected to provide desired reflectivity, and in some embodiments, high reflectivity, and / or desired absorption, and in some embodiments, low absorption. In certain embodiments, a "transparent" material may be configured to transmit at least 50% of the luminescent radiation of a desired wavelength. In certain embodiments, an initially "light-transmitting" material may be modified to become a "light-absorbing material" that transmits less than 50% of the emitted radiation of a desired wavelength by the addition of one or more light-absorbing materials, such as opaque or non-reflective materials that contain gray, dark, or black particles or materials.

[0032]

[0108] The present disclosure provides LEs with various geometries, such as vertical or horizontal geometries. Vertical geometry LED chips can be useful for vertically aligned LED chips. Vertical geometry LED chips typically include anode and cathode connections on opposite sides of the LED chip. Lateral geometry LED chips typically include both anode and cathode connections on the same side of the LED chip facing away from a substrate, such as a growth substrate. Certain embodiments disclosed herein relate to the use of flip-chip LED devices in which a light-transmitting substrate represents the exposed light-emitting surface.

[0033]

[0109] An LED chip or LED package containing one or more LED chips LEDs can be arranged in many different applications to provide illumination of an object, surface, or area. In certain applications, a collection of different colored LED chips or LED packages may be arranged as pixels for LED display applications, including video displays. For example, individual collections of red, green, and blue LED chips may form LED pixels of a larger LED display. In certain applications, the red, green, and blue LED chips of each pixel may be packaged together as a multi-LED package, and an LED display is formed when an array of such multi-LED packages is arranged together. In this regard, each pixel may include a single LED package that includes a red LED chip, a green LED chip, and a blue LED chip. In other embodiments, the red, green, and blue LED chips may be packaged separately or arranged in a chip-on-board configuration. In certain LED display applications, an array of LED pixels may also be referred to as a tile or LED module. The LED display panels are arranged on a panel, and an array of such panels is arranged together to form a larger LED display. Depending on the application, each panel of the LED display may include a different number of LED pixels. In certain applications, each panel of the LED display may include an array formed by 64 rows and 64 columns or more of LED pixels. In certain embodiments, each panel of the LED display may be configured with a horizontal display resolution of approximately 4,000 LED pixels, or 4K resolution. For applications where a higher screen resolution is desired for the LED display, each panel may include even more rows and columns of LED pixels that are more closely spaced together. Depending on the desired screen resolution, the pixel pitch may be approximately 3 millimeters (mm), or approximately 2.5 mm, or approximately 1.6 mm, or within a range of approximately 1.5 mm to approximately 3 mm, or within a range of approximately 1.6 mm to approximately 3 mm, or within a range of approximately 1.5 mm to approximately 2.5 mm. Additionally, for fine pitch LED displays with even higher screen resolution, the pixel pitch may be configured to be less than 1 mm, or less than 0.8 mm, or within the range of about 0.5 mm to about 1 mm, or in certain embodiments, about 0.7 mm.

[0034]

[0110] In conventional video display applications, LED pixels are typically passive In this regard, the LED pixels may be arranged for coupling to passive interface elements that provide electrical connections to a separate driver or controller. For example, orthogonally arranged (e.g., vertical and horizontal) conductors form rows and columns in a grid pattern, whereby the individual LED chips of each LED pixel are defined by each intersection of the row and column. Multiplexing sequencing may be used to allow individual control of each LED chip in the array while employing fewer conductors than the number of LED chips in the array by utilizing either a common-row anode or common-row cathode matrix arrangement, and brightness control may be provided by pulse-width modulation. In this manner, the conductors for a row or column are shared among many LED pixels, and time-division multiplexing is employed to address each individual LED pixel. Due to their passive configuration, each LED pixel only emits light during its respective communication time. Separate drivers for controlling the display are typically located away from the display's pixels, such as on a separate board or module, or on a printed circuit board (PCB) mounted or otherwise attached to the backside of each panel, or on the backside of a common PCB that includes the array of pixels on its front side. As previously discussed, PCBs are densely populated with electrical devices, including capacitors, field-effect transistors (FETs), decoders, microcontrollers, and the like, for driving each of the pixels on a particular panel. In higher-resolution displays, the density of such electrical devices increases correspondingly to the increased number of pixels on each panel. As previously discussed, this adds greater complexity and expense to LED panels for display applications and can increase thermal congestion in areas where the driver electronics are more closely spaced. In passive matrix addressing, LED pixels are typically driven by a pulsed signal sequence. In this regard, the LED pixels may be rapidly pulsed at a particular frequency, such as 60 hertz (Hz) or 120 Hz, depending on the display scan rate.A video display may not appear to be rapidly pulsing to the human eye, but it may be detectable by image capture equipment, and in some cases, interferometric beating may exist between the video display and other pulsating displays or light sources near the video display.

[0035]

[0111] According to the embodiments disclosed herein, each LED pixel of the LED display may be configured for operation using active matrix addressing, in which each LED pixel is assigned an operational or drive state, such as brightness or gray level, or color selection, while other LED pixels are addressed. active, thereby allowing each LED pixel to maintain its drive state with either reduced or no pulsing, depending on the drive configuration. Thus, each LED pixel may be configured to maintain its respective operating state with a continuous drive signal rather than with the pulsed signals associated with passive matrix addressing. In this regard, each LED pixel may include an active electrical chip or active electrical element that may include a memory device and the ability to change the driving condition or drive conditions of the LED pixel based on memory from the memory device. In certain embodiments, the continuous drive signal is a constant analog drive current; in other embodiments, the brightness level may be controlled by a pulse method such as pulse-width modulation (PWM), a continuous drive signal may refer to a PWM signal that is not disturbed by the scanning of other LED pixels within the array or sub-array. In certain embodiments, the active electrical chip may include active circuitry including one or more of a driver device, a signal conditioning or conversion device, a memory device, a decoder device, an ESD protection device, a thermal management device, and a detection device, among others. As used herein, the terms “active electrical chip,” “active electrical element,” or “active electrical component” include any chip or component that can change the drive conditions of an LED based on memory or other information that may be stored within the chip or component. As used herein, the term “active LED pixel” includes one or more LED devices that form a pixel and active electrical chip as described above. In certain embodiments, each LED pixel may comprise a single LED package configured as an active LED package that includes multiple LED chips and active electrical elements as described above. In this way, the number of separate electrical devices required for an LED display, such as separate electrical devices located behind the LED panel of an LED display as previously described, may be reduced.Additionally, the overall operating power required to run the LED panel may be reduced.

[0036]

[0112] FIG. 1A illustrates a schematic diagram of an LED display including a plurality of active LED pixels 12. FIG. 1B is a top view of the front side of a representative display panel 10 of FIG. 1A. As illustrated, a plurality of active LED pixels 12 may be arranged in rows and columns to form an array of active LED pixels 12 across the front side of the display panel 10. In certain embodiments, each of the active LED pixels 12 is configured with active electrical elements that include the ability to receive an input signal, store a memory based on the input signal, change the drive conditions of the LEDs in each active LED pixel 12 based on the stored memory, and update the drive conditions each time the memory is updated with an input signal. In certain embodiments, each active LED pixel 12 comprises an LED package that includes multiple LED chips that form the LED pixel and the active electrical elements. FIG. 1B is a bottom view of the rear side of the representative display panel of FIG. 1A. Although all are illustrated, the display panel 10 may include additional passive or active elements configured to receive, process, and deliver signals to the active LED pixels (12 in FIG. 1A). For example, display panel 10 may include input signal connectors 14 and output signal connectors 16, each of which may be configured as a video source connector, including a Video Graphics Array (VGA) connector, a Digital Visual Interface (DVI) connector, a High-Definition Multimedia Interface (HDMI) connector, or a DisplayPort connector, among others. Display panel 10 may also include a control element 18 including control circuitry, such as a semiconductor control element. Control element 18 may be configured to receive input signals via input signal connector 14 and output control signals for active LED pixels. As will be described in more detail below, the active electrical elements of each LED pixel independently change the drive conditions of each LED chip within the LED pixel in response to the control signals output from control element 18. In certain embodiments, the control elements 18 comprise an integrated circuit such as one or more of an application specific integrated circuit (ASIC), a microcontroller, a programmable control element, and a field programmable gate array (FPGA). In certain embodiments, multiple control elements 18 may be configured on or registered with each display panel 10. The decoder elements 20 may be configured to receive control signals from the control elements 18 and route them to multiple signal lines for the active LED pixels (12 in FIG. 1A). In certain embodiments, one or more digital-to-analog converters (DACs) 22 may be provided to convert digital signals from the control elements 18 and the decoder elements 20 before reaching the active LED pixels (12 in FIG. 1A). The display panel 10 may also include other passive or active elements 24, which may include additional decoders, resistors, capacitors, or other electrical elements or circuits for video display. In this manner, the signal connectors 14 and 16, the control elements 18, the decoder elements 20, the DACs 22, and the other passive or active elements 24 are registered with the display panel 10. In alternative embodiments, the back surface of display panel 10 may include another plurality of LED packages forming another array of LED pixels. In this regard, display panel 10 may be configured for a dual-sided display application. In such embodiments, at least some of signal connectors 14 and 16, control elements 18, decoder elements 20, DAC 22, and other passive or active elements 24 may be registered to display panel 10 at a location other than the back surface in a configuration for providing control signals from one or more edges of display panel 10.

[0037]

[0113] 2A-2I illustrate a plurality of LEDs 28 according to embodiments disclosed herein. 2A illustrates various states of manufacture of an LED package 26 including LEDs 28-1 through 28-3 and an active electrical element 30. In certain embodiments, separate LED packages 26 may be configured to form each of the active LED pixels (12 in FIG. 1A) in a display panel (10 in FIG. 1A). The active electrical element 30 may also be referred to as an active electrical chip or active electrical component. FIG. 2A is a bottom view of the LED package 26 in a particular state of manufacture, in which the plurality of LEDs 28-1 through 28-3 and the active electrical element 30 are mounted to a submount 32. In particular, the plurality of LEDs 28-1 through 28-3 and the active electrical element 30 may be mounted to a first surface 32′ of the submount 32. A light-transmitting die-attach material may be disposed between the plurality of LEDs 28-1 through 28-3 and the submount 32 to facilitate mounting. Each of the plurality of LEDs 28-1 to 28-3 may include a corresponding cathode contact 34-1 to 34-3 (e.g., an n-type contact pad) and a corresponding anode contact 36-1 to 36-3 (e.g., a p-type contact pad). In certain embodiments, the plurality of LEDs 28-1 to 28-3 comprises individual LED chips that produce different dominant wavelengths of light. For example, LED 28-1 may be configured to produce primarily green light emission, LED 28-2 may be configured to produce primarily blue light emission, and LED 28-3 may be configured to produce primarily red light emission. Thus, the plurality of LEDs 28-1 to 28-3 may comprise a green LED chip, a blue LED chip, and a red LED chip. In other embodiments, different color combinations and numbers of LEDs are possible. In still further embodiments, each of the plurality of LEDs 28-1 to 28-3 may be configured to produce light emission that is primarily the same as one another. In other embodiments, the plurality of LEDs 28-1 to 28-3 may comprise a micro LED structure in which a common active LED structure is divided into multiple active LED structure portions to form the plurality of LEDs 28-1 to 28-3, which may be addressable independently of each other.

[0038]

[0114] In certain embodiments, the active electrical element 30 may be a signal or multiple signals. and drives each of the plurality of LEDs 28-1 to 28-3 independently. In certain embodiments, the active electrical element 30 includes a memory element, chip, or component configured to store one or more operating states for the plurality of LEDs 28-1-28-3 received from an external source, such as a control element (18 in FIG. 1B). The active electrical element 30 may be further configured to change one or more drive conditions of the plurality of LEDs 28-1-28-3 based on the one or more stored operating states. In certain embodiments, the active electrical element 30 is configured to independently change the drive conditions of each of the plurality of LEDs 28-1-28-3 based on the plurality of operating states stored by the memory element. In this regard, the active electrical element 30 may be configured to receive and store one or more operating states and independently drive each of the plurality of LEDs 28-1-28-3 according to the one or more operating states. The active electrical element 30 may continue to drive and maintain the operating state of each of the plurality of LEDs 28-1-28-3 until the active electrical element 30 receives a refresh or updated signal corresponding to the updated operating state. In this manner, the active electrical element 30 may be configured to change the drive conditions of the plurality of LEDs 28-1-28-3 according to the temporarily stored operating state of the memory element. Accordingly, the plurality of LEDs 28-1-28-3 may be configured for active matrix addressing, as previously described. To quickly receive one or more operating states of the plurality of LEDs 28-1-28-3, the active electrical element 30 may include a plurality of contact pads 38. In certain embodiments, certain contact pads of the plurality of contact pads 38 are configured to receive one or more signals, and other contact pads of the plurality of contact pads 38 are configured to transmit signals to independently drive or address the plurality of LEDs 28-1-28-3. In certain embodiments, the active electrical element 30 comprises one or more of an integrated circuit chip, an ASIC, a microcontroller, or an FPGA.In certain embodiments, active electrical element 30 may be configured to be programmable or reprogrammable after it is manufactured through various memory elements and logic that are incorporated within active electrical element 30. In this regard, active electrical element 30 may be considered programmable in embodiments in which active electrical element 30 does not include a full FPGA.

[0039]

[0115] The submount 32 can be made of many different materials, with the preferred material being The material is electrically insulating. Suitable materials include, but are not limited to, ceramic materials such as aluminum oxide or alumina, AlN, or organic insulators such as polyimide (PI) and polyphthalamide (PPA). In other embodiments, the submount 32 can comprise PCB, sapphire, Si, or any other suitable material. For PCB embodiments, different PCB types can be used, such as standard FR-4 PCB, bismaleimide triazine (BT) or related materials, metal-core PCB, or any other type of PCB. In certain embodiments, the submount 32 comprises an optically transmissive material to allow light emitted from the plurality of LEDs 28-1 through 28-3 to pass through the submount 32. In this regard, the light-emitting surface of each of the plurality of LEDs 28-1 through 28-3 may be mounted to the submount 32. Suitable optically transmissive materials for the submount 32 include glass, sapphire, epoxy, and silicone. In certain embodiments in which the submount 32 is an optically transmissive submount, the submount 32 may be referred to as a superstrate. The term "superstrate" is used herein in part to avoid confusion with other substrates that may be part of a semiconductor light emitting device, such as a growth or carrier substrate for an LED chip or a different submount for LED package 26. The term "superstrate" is not intended to limit the orientation, location, and / or composition of the structure it describes. In certain embodiments, submount 32 may comprise an optically transmissive superstrate, and LED package 26 may be devoid of a separate submount. In other embodiments, submount 32 may comprise an optically transmissive superstrate, and LED package 26 may be devoid of an additional submount. The LEDs 28-1 to 28-3 are disposed between the submount 32 and the additional submount.

[0040]

[0116] FIG. 2B is a cross-sectional view taken along section line AA of FIG. 2A. First, LED 28-1 is mounted on first surface 32' of submount 32. Light emission from LED 28-1 may therefore be configured to pass through submount 32 such that second surface 32'' of submount 32 is configured as the primary light-emitting surface of LED package 26. Notably, anode contact 36-1 and cathode contact (34-1) of LED 28-1 are disposed on opposite sides of submount 32 from LED 28-1. In this regard, light emission from LED 28-1 may pass through the submount and exit from opposite surface 32'' without interacting with each other or being absorbed by anode contact 36-1 and cathode contact (34-1). While the orientation of the cross-sectional view in FIG. 2B is intended to illustrate that second surface 32'' of submount 32 is configured as the primary light-emitting surface, during intermediate manufacturing steps, the orientation of FIG. 2B and subsequent cross-sectional manufacturing views may be rotated 180 degrees as LED 28-1 is sequentially assembled onto submount 32.

[0041]

[0117] FIG. 2C shows a cross-sectional view of a substrate having an encapsulation layer 40 and a plurality of conductive traces 42-1 through 42-7 formed thereon. 2A is a bottom view of the LED package 26 of FIG. 2A in a subsequent state of manufacture, in which the LED package 26 has been fabricated. FIG. 2D is a cross-sectional view taken along section line BB of FIG. 2C, in which the electrical connector 44 is visible. Prior to the formation of the encapsulation layer 40 and the conductive traces 42-1 through 42-7, the electrical connectors 44 may be formed on the cathode contacts 34-1 through 34-3 and anode contacts 36-1 through 36-3 of each of the LEDs 28-1 through 28-3. The electrical connectors 44 may also be formed on the contact pads 38 of the active electrical element 30. In certain embodiments, the electrical connectors 44 may include at least one of metal bump bonds, metal pads, metal wires, metal interconnects, and metal pedestals, among others. The electrical connectors 44 may be formed by various methods, including, but not limited to, wire bump bonding, solder bumping, plating, laser drilling of vias that are later filled with metal, or other metallization formation techniques. The electrical connectors 44 may be formed at the wafer level before component assembly, after die attachment of the LEDs 28-1-28-3, or in other manufacturing steps depending on various process configurations. After the formation of the electrical connectors 44, the encapsulation layer 40 may be blanket deposited to cover the LEDs 28-1-28-3 and the active electrical elements 30. In certain embodiments, the encapsulation layer 40 may further cover the electrical connectors 44. The encapsulation layer 40 may be configured to surround the outer periphery or side edges of each of the LEDs 28-1-28-3. As illustrated in FIG. 2D , the encapsulation layer 40 may cover at least a portion of the bottom surface of each of the LEDs 28-1-28-3. The encapsulation layer 40 may also be configured to surround the outer periphery or side edges of the active electrical elements 30. In such embodiments, a removal step may then be applied to the encapsulation layer 40 such that portions of the encapsulation layer 40 are removed to form exposed surfaces of the electrical connectors 44. The removal step may include a planarization process, such as grinding, lapping, or polishing the encapsulation layer 40 to expose the plurality of electrical connectors 44 .In embodiments in which the plurality of electrical connectors 44 comprise laser-drilled vias or microvias, the removal step may not be required.

[0042]

[0118] The encapsulation layer 40 may be applied or deposited by a coating or dispensing process. In certain embodiments, the encapsulation layer 40 may include one or more of silicone, epoxy, and thermoplastic materials such as polycarbonate, aliphatic urethane, or polyester, among others. The encapsulation layer 40 may be configured to modify or control the light output from the plurality of LEDs 28-1-28-3. For example, the encapsulation layer 40 may be configured to modify or control the light output from the plurality of LEDs 28-1-28-3. The encapsulation layer 40 may include an opaque or non-reflective material, such as a gray, dark, or black material, that may absorb some of the light traveling between the LEDs 28-1-28-3, thereby improving the contrast between the light emitted by the LEDs 28-1-28-3 passing through the submount 32. In certain embodiments, the encapsulation layer 40 may include light-absorbing particles suspended in a binder, such as silicone or epoxy. The light-absorbing particles may include at least one of carbon, silicon, or metal particles or nanoparticles. In certain embodiments, the light-absorbing particles include a predominantly black color that, when suspended in the binder, provides the predominantly black or dark color of the encapsulation layer 40. Depending on the desired application, the encapsulation layer 40 may be configured as transparent or translucent, or the encapsulation layer 40 may include a light-reflecting or light-redirecting material, such as fused silica, fumed silica, or titanium dioxide (TiO) particles, that form the predominantly white color of the encapsulation layer 40. Other particles or filters may be used to enhance the mechanical, thermal, optical, or electrical properties of encapsulation layer 40. In certain embodiments, encapsulation layer 40 may include multiple layers with different mechanical, thermal, optical, or electrical properties.

[0043]

[0119] After the surface of the electrical connector 44 is exposed through the encapsulation layer 40, a plurality of conductive traces are Conductive traces 42-1 through 42-7 are formed on the encapsulation layer 40 (e.g., on the bottom surface of the encapsulation layer 40 in the orientation illustrated in FIG. 2D ), with certain ones of the conductive traces 42-4 through 42-7 electrically connected to the plurality of LEDs 28-1 through 28-3 by the exposed surfaces of certain electrical connectors 44. Certain ones of the plurality of conductive traces 42-1 through 42-7 may be configured to provide conductive paths between the plurality of contact pads 38 of the active electrical element 30 and the cathode contacts 34-1 through 34-3 and anode contacts 36-1 through 36-3 of each LED 28-1 through 28-3. As illustrated in FIG. 2C , the conductive traces 42-1, 42-2, and 42-3 are electrically connected to the active electrical element 30 but are not electrically connected to any of the plurality of LEDs 28-1 through 28-3. In this regard, the conductive traces 42-1, 42-2, and 42-3 may be configured to provide a signal from an external source (such as the control element 18 of FIG. 1B) to the active electrical element 30. In particular, the conductive trace 42-7 in FIG. 2C is configured to provide a conductive path between the active electrical element 30 and the anode contacts 36-1 through 36-3 of each of the plurality of LEDs 28-1 through 28-3. In this regard, the plurality of LEDs 28-1 through 28-3 may be configured for common anode control. In other embodiments, the plurality of conductive traces 42-1 through 42-7 and the plurality of LEDs 28-1 through 28-3 may be configured for common cathode control.

[0044]

[0120] FIG. 2E shows an additional encapsulation layer 46 and multiple package bond pads 48-1 to 2C is a bottom view of the LED package 26 of FIG. 2C at a later stage of manufacture, in which conductive traces 42-1, 42-2, 42-3, and 42-7 have been formed. FIG. 2F is a cross-sectional view taken along section line CC of FIG. 2E. FIG. 2G is a cross-sectional view taken along section line DD of FIG. 2E, in which an additional electrical connector 50 is visible. Prior to the formation of the additional encapsulation layer 46 and the plurality of package bond pads 48-1 through 48-4, the plurality of additional electrical connectors 50 may be formed over and in electrical communication with the conductive traces 42-1, 42-2, 42-3, and 42-7. The additional electrical connectors 50 may be configured and formed in a manner similar to the previously described electrical connector 44. In certain embodiments, the additional electrical connectors 50 may be formed on the electrical connector 44 without any intervening conductive traces. Alternatively, the additional encapsulation layer 46 may be applied first, and vias or openings for the additional electrical connectors 50 may subsequently be formed by a selective removal step, such as laser drilling. In a similar manner, a selective removal step may also be used to form openings for the previously described electrical connectors 44. An additional encapsulation layer 46 may then be blanket deposited to cover the bottom surfaces of the plurality of conductive traces 42-1 through 42-7 as well as the additional electrical connector 50. The additional encapsulation layer 46 may be constructed and formed in a manner similar to the previously described encapsulation layer 40. Notably, the additional encapsulation layer 46 may also be formed on portions of the encapsulation layer 40 that are not covered by the plurality of conductive traces 42-1 through 42-7. In this regard, the encapsulation layer 40 and the additional encapsulation layer 46 may together form a continuous encapsulation layer 40, 46 such that at least some portions of the plurality of conductive traces 42-1 through 42-7 are embedded within the encapsulation layers 40, 46. After formation of the additional encapsulation layer 46, a removal step (e.g., planarization) as previously described may be applied to form exposed surfaces of the plurality of additional electrical connectors 50. A plurality of package bond pads 48-1 through 48-4 may then be formed on a bottom surface of the additional encapsulation layer 46 and be in electrical communication with the additional electrical connectors 50. In this regard, the package bond pads 48-1 through 48-4 are configured to receive signals that are external to the LED package 26. In certain embodiments, package bond pads 48-1 through 48-4 are configured to be mounted and bonded to another surface (e.g., a mounting surface of an LED panel including electrical traces or other types of signal lines) to receive external signals (e.g., from control element 18 of FIG. 1B ). As illustrated, package bond pad 48-4 is electrically connected to active electrical element 30 by an electrical pathway including a particular additional electrical connector 50 and conductive trace 42-1. Similarly, package bond pad 48-3 is electrically connected to active electrical element 30 by a different electrical pathway including a different additional electrical connector 50 and conductive trace 42-2. Package bond pad 48-2 is electrically connected to active electrical element 30 by a different electrical pathway including a different additional electrical connector 50 and conductive trace 42-3. Notably, package bond pad 48-1 is electrically connected to anode contacts 36-1 through 36-3 of each of LEDs 28-1 through 28-3 by a different additional electrical connector 50 and conductive trace 42-7 in a configuration for common anode control. As previously described, the LED package 26 can be configured such that the common cathode control rearranges the routing of the plurality of conductive traces 42-1 through 42-7.Additional layers, such as solder mask or other insulating layers or materials, may be applied to the additional encapsulation layer 46 and selected areas of the package bond pads 48-1-48-4 to further delineate the footprint of the package bond pads 48-1-48-4 and prevent shorting of the solder material when assembled or mounted on a PCB. In certain embodiments, multiple additional encapsulation layers 46 and at least one additional electrical trace may be similarly formed before the package bond pads 48-1-48-4 are formed. In this manner, additional layers of electrical trace may be stacked or alternated with multiple additional encapsulation layers 46 to provide more conductive paths and connections for the LED packages 26.

[0045]

[0121] FIG. 2H is a simplified top view of the LED package 26 of FIG. 2E. The diagram illustrated by H represents the primary light-emitting surface 52 of the LED package 26. The plurality of LEDs 28-1 through 28-3 are therefore configured below the submount 32 (e.g., an optically transmissive submount or optically transmissive superstrate) to provide light emission that passes through the submount 32. The active electrical element 30 is also configured below the submount 32, and all electrical connections and conductive pathways, as previously described, are therefore disposed below the active electrical element 30 and below the plurality of LEDs 28-1 through 28-3 relative to the primary light-emitting surface 52. Light generated from the plurality of LEDs 28-1 through 28-3 may therefore pass through the submount 32 and exit the primary light-emitting surface 52 with reduced loss or absorption to electrical connections, conductive pathways, or other elements within the LED package 26. In certain embodiments, the plurality of LEDs 28-1 through 28-3 form LED pixels for the LED package 26, which can be combined with other LED packages to form an LED pixel array for video display applications.

[0046]

[0122] FIG. 2I is a simplified bottom view of the LED package 26 of FIG. 2E. The bottom view illustrated by I shows the main mounting surface 54 of the LED package 26. With respect to the LED package 26, the LED package 26 is configured to be mounted to an exterior surface (e.g., a video display panel or PCB) such that the package bond pads 48-1 through 48-4 are glued or soldered to electrical communication lines provided on the exterior surface. In certain embodiments, at least one package bond pad 48-1 may include an identifier 56, such as a notch, a different shape, or other form of identifier, configured to communicate the polarity and mounting position of the LED package 26 relative to the exterior surface.

[0047]

[0123] FIG. 3A shows the conductive traces 60-1 to 60-4 of the LED package 5 3B is a bottom view of an exemplary LED package 58 including a plurality of conductive traces 60-1 through 60-7 forming package bond pads 62-1 through 62-4 for LEDs 28-1 through 28-3. FIG. 3B is a cross-sectional view taken along section line E-E of FIG. 3A. The LED package 58 may include a submount 32, an encapsulation layer 40, a plurality of LEDs 28-1 through 28-3 with cathode contacts 34-1 through 34-3 and anode contacts 36-1 through 36-3, and an active electrical element 30 with contact pads 38, as previously described. After planarizing the encapsulation layer 40 to expose the cathode contacts 34-1 through 34-3, anode contacts 36-1 through 36-3, and contact pads 38, as previously described, the plurality of conductive traces 60-1 through 60-7 are formed on the encapsulation layer 40 in a manner similar to the plurality of conductive traces 42-1 through 42-7 of FIG. 2C. 3A , portions of certain conductive traces 60-1 through 60-4 are configured with a larger area across the LED package 58. An insulating material 64, such as a solder mask, is then formed over portions of the conductive traces 60-1 through 60-7. Notably, the insulating material 64 does not extend entirely across all of the conductive traces 60-1 through 60-7. Notably, portions of the conductive traces 60-1 through 60-4 are not covered by the insulating material 64 to form the package bond pads 62-1 through 62-4 of the LED package 58. In this regard, the package bond pads 62-1 through 62-4 may be glued or soldered to another surface, and the insulating material 64 may prevent electrical shorting between different ones of the conductive traces 60-1 through 60-7.

[0048]

[0124] FIG. 4 shows one or more LEDs 28-1 and an active electrical element 30. FIG. 4 is a cross-sectional view of an LED package 66 illustrating a mounting configuration along a first horizontal plane P1 of the LED package 66. While only the LED 28-1 is illustrated in FIG. 4, it should be understood that the LED package 66 may include multiple LEDs mounted in a manner similar to the LED 28-1 of FIG. 4. As illustrated, the LED 28-1 and the active electrical element 30 are mounted or adhered along the first horizontal plane P1 defined by the mounting surface of the submount 32. In some embodiments, the LED 28-1 and the active electrical element 30 may include different dimensions, such as different thicknesses or heights, relative to the submount 32. Additionally, adhesive layers of different thicknesses may be provided to adhere the LED 28-1 and the active electrical element 30 to the submount 32, respectively. After bonding the LED 28-1 and the active electrical element 30 along the first horizontal plane P1, the electrical connector 44, the encapsulation layer 40, the additional electrical connector 50, the conductive traces 42-1 to 42-3, the additional encapsulation layer 46, and the package bond pad 48-1 may be formed as previously described.

[0049]

[0125] FIG. 5 shows one or more LEDs 28-1 mounted along a first horizontal plane P1. 5 is a cross-sectional view of an LED package 68 illustrating a configuration in which the LED 28-1 is mounted on a first horizontal plane P1 of the LED package 68, and the active electrical element 30 is mounted along a second horizontal plane P2 different from the first horizontal plane P1 of the LED package 68. While only the LED 28-1 is illustrated in FIG. 5, it should be understood that the LED package 68 may include multiple LEDs mounted in a manner similar to the LED 28-1 of FIG. 5. As illustrated, the LED 28-1 is mounted or bonded along the first horizontal plane P1 defined by the mounting surface of the submount 32. The electrical connector 44, the encapsulation layer 40, and the multiple conductive traces 42-1 through 42-3 are then formed as previously described. The active electrical element 30 is then mounted along a second horizontal plane P2 defined by the sides of the plurality of conductive traces 42-1 to 42-3 opposite the LED 28-1. In this manner, the plurality of conductive traces 42-1 to 42-2 are thereby disposed between the LED 28-1 and the active electrical element 30. An additional electrical connector 50, an additional encapsulation layer 46, and a package bond pad 48-1 may subsequently be formed as previously described. Notably, the active electrical element 30 may be at least partially embedded in the additional encapsulation layer 46 in this configuration. Accordingly, at least one of the additional encapsulation layer 46 and the additional electrical connector 50 may include a thickness greater than that of previously described embodiments. In certain embodiments, the additional encapsulation layer 46 may comprise a second submount, and the active electrical element 30 is either embedded within or mounted to the second submount. Such an arrangement may be referred to as a chip-scale configuration.

[0050]

[0126] FIG. 6 shows a circuit diagram of a device supported by one or more LEDs 28-1 and an active electrical element 30. 6 is a cross-sectional view of an LED package 70 illustrating a configuration in which the LED 28-1 is mounted on opposing sides of the submount 32. While only the LED 28-1 is illustrated in FIG. 6, it should be understood that the LED package 70 may include multiple LEDs mounted in a manner similar to the LED 28-1 of FIG. 6. As illustrated, multiple conductive traces 42-1, 42-2 are formed on the second side 32″ of the submount 32, and additional electrical traces 71-1, 71-2 are formed on the first side 32′ of the submount 32. The LED 28-1 is mounted or bonded to the conductive traces 42-1, 42-2 by an electrical connector 44, and the active electrical element 30 is mounted or bonded to the additional electrical traces 71-1, 71-2 by an additional electrical connector 50. An encapsulation layer 40 is formed over the LED 28-1 and the second side 32″ of the submount 32. In certain embodiments, a portion of the encapsulation layer 40 forms the primary light-emitting surface 52 of the LED package 70. As previously described, the encapsulation layer 40 may include a black material to provide enhanced contrast between the LED 28-1 and other LEDs that may be mounted in the LED package 70. In certain embodiments, another layer or extension of the encapsulation layer 40 may extend over the LED 28-1 to provide encapsulation of the LED 28-1. In such embodiments, the other layer or extension of the encapsulation layer 40 over the LED 28-1 may include a light-transmitting material, an additional layer, or a texture. An additional encapsulation layer 46 may be formed on the first surface 32′ of the submount 32 to provide encapsulation for the active electrical element 30. In this regard, the additional encapsulation layer 46 may or may not extend across the entire first surface 32′ of the submount 32. Notably, the portions of the additional conductive traces 71-2 not covered by the additional encapsulation layer 46 may form package bond pads 48, as previously described. To promote adhesion to the exterior surface, the conductive adhesive material 72 may include a thickness relative to the submount 32 that is greater than or approximately the same thickness as the active electrical elements 30 and additional encapsulation material 46 .To provide electrical communication between the conductive trace 42-2 and the additional conductive trace 71-1, one or more conductive interconnects 73, such as metal slugs, vias, or traces, may be provided through the submount 32 as illustrated in FIG. 6, or the conductive interconnects 73 may wrap around the side edges of the submount 32.

[0051]

[0127] FIG. 7 illustrates an LED including a plurality of LED pixels according to embodiments disclosed herein. 2E, but includes a plurality of LED chips 75-1 through 75-3, 76-1 through 76-3, 77-1 through 77-3, and 78-1 through 78-3 that are spaced apart from one another and that each form a plurality of LED pixels that are packaged together within the same LED package 74. As illustrated, LED chips 75-1 through 75-3 form a first LED pixel, LED chips 76-1 through 76-3 form a second LED pixel, LED chips 77-1 through 77-3 form a third LED pixel, and LED chips 78-1 through 78-3 form a fourth LED pixel. , forming a plurality of LED pixels. In a particular embodiment, each LED pixel comprises a red LED chip, a blue LED chip, and a green LED chip. The LED package 74 further includes an active electrical element 30′ configured to electrically connect with the plurality of pixels, the plurality of conductive traces 42-1 through 42-16, and the plurality of package bond pads 48-1 through 48-4, as previously described. Notably, the LED package 74 may be configured with the same number of package bond pads 48-1 through 48-4 as previously described for a single pixel LED package (e.g., the LED package 26 of FIG. 2H). As illustrated, the LED package 74 is configured with a supply voltage (V dd ), ground (V ss), color selection signals, brightness level (or gray level) signals, analog signals, coded color selection signals, coded brightness level selection signals, digital signals, clock signals, and asynchronous data signals, as will be described in more detail below. Thus, active electrical element 30′ includes four input / output and power connections, but active electrical element 30′ is configured to independently change the drive conditions of each of multiple LED chips 75-1 through 75-3, 76-1 through 76-3, 77-1 through 77-3, and 78-1 through 78-3, as will be described in more detail below. Notably, conductive trace 42-1 may be electrically connected to the anodes of each of LED chips 75-1 through 75-3, 76-1 through 76-3, 77-1 through 77-3, and 78-1 through 78-3 for common anode control. Conductive trace 42-1 is also electrically connected between package bond pad 48-1 and active electrical element 30'. Conductive trace 42-2 is electrically connected between package bond pad 48-4 and active electrical element 30', conductive trace 42-9 is electrically connected between package bond pad 48-3 and active electrical element 30', and conductive trace 42-10 is electrically connected between package bond pad 48-2 and active electrical element 30'. In other embodiments, LED package 74 may be configured for common-cathode control, as previously described. To provide electrical communication with an increased number of LED pixels in LED package 74, active electrical element 30' may include an increased number of contact pads 38 for communication with an increased number of conductive traces 42-1 through 42-16. Four of the contact pads 38 are electrically connected to package bond pads 48-1 through 48-4 as previously described, and the remaining contact pads 38 are electrically connected to different ones of LED chips 75-1 through 75-3, 76-1 through 76-3, 77-1 through 77-3, and 78-1 through 78-3.To allow LED package 74 to control multiple LED pixels with a reduced number of input signal connections, active electrical element 30 may include circuitry configured to receive input communication signals, perform a partial pixel selection function, and independently communicate operating states to each of LED chips 75-1 through 75-3, 76-1 through 76-3, 77-1 through 77-3, and 78-1 through 78-3 of each LED pixel. In this regard, when multiple LED packages 74 are arranged together to form an array of LED pixels for display applications, the resulting display will have a reduced number of LED packages 74 compared to a similarly sized display in which each LED package comprises only a single LED pixel. In this regard, the total number of communication signals between an external source (e.g., control element 18 of FIG. 1B ) and the LED pixels may be reduced. As with the single-pixel embodiment (e.g., FIG. 2E ), nearly infinite combinations of communication signal routing are within the scope of this disclosure, including simple variations in which one or more metal traces are configured along the same planes as previously described for FIGS. 3A and 3B .

[0052]

[0128] FIG. 8 illustrates an active electrical element 30 (also known as a is a block schematic diagram illustrating components of an active electrical element 30' of FIG. 7. As previously described, the active electrical element 30 may be incorporated into an LED package to enable active matrix addressing for a corresponding LED display. The active electrical element 30 receives power from an external source (e.g., control element 18 of FIG. 1B). The active electrical element 30 is configured to receive an input signal and independently maintain and / or change drive conditions for one or more LEDs in the LED package. As described in more detail below, the input signal may be analog, digital, or a combination of analog and digital formats, and may include a single communication line or multiple communication lines. In certain embodiments, the active electrical element 30 comprises a memory element 80, which may include one or more volatile and non-volatile memory elements. The memory element 80 may comprise one or more of a bipolar transistor, a field-effect transistor, an inverter, a logic gate, a dynamic random access memory (DRAM), a static random access memory (SRAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, an operational amplifier, a capacitor, and a look-up table, among others. In certain embodiments, the memory element 80 comprises at least one of a sample-and-hold circuit, a latch circuit, and a flip-flop circuit. In certain embodiments, the memory element 80 comprises a volatile memory element configured to store the operating state of one or more LEDs based on the input signal. During operation, each time an updated input signal is received by the active electrical element 30, the volatile memory element is updated with a new operating state for one or more LEDs, and the one or more LEDs are activated and maintained in accordance with the new operating state accordingly. In this regard, the volatile memory element may be configured to store a temporary operating state, and the active electrical element 30 is thereby configured to change the drive conditions of the one or more LEDs in accordance with the temporarily stored operating state. In certain embodiments, the volatile memory element may additionally be configured to store other states or conditions that may not be considered temporary, such as calibration factors or electrical transfer functions such as gains. In this regard, one or more of the temporary operating state and the non-temporary state or condition may be used collectively to generate drive conditions for one or more LEDs.In certain embodiments, memory element 80 comprises a non-volatile memory element configured to store preset data or information that may also be used to change the operating state of one or more LEDs. A non-volatile memory element, such as a look-up table or hash table, may be provided to change the operating state based on the operating conditions or environment of the LED package. For example, a thermal management element, such as that shown in FIG. 8, that monitors the operating temperature of the LED package may be embedded within active electrical element 30, and the operating state of one or more LEDs may be adjusted accordingly based on a comparison of the operating temperature with a value stored by the non-volatile memory element. In certain embodiments, the thermal management element includes a temperature sensor or temperature sensor input from an external temperature sensor. In other embodiments, ambient light level information from a light sensor may be compared to a value stored in the non-volatile memory element to change the brightness level of one or more LEDs. In further embodiments, the non-volatile memory element may be programmed to store positioning data, including default or later-programmed positioning data, for the LEDs or LED pixels of the display. The positioning may be programmed before or after installation of the LED display. The positioning may include positioning for individual LED chips, individual LED packages containing LED pixels, and individual LED panels that may collectively form an LED display. In this regard, a common control line may be connected to two or more LEDs, LED pixels, or LED packages, and the positioning may be used to interpret the input signal and drive only the intended LEDs connected by the common control line.

[0053]

[0129] The active electrical element 30 also includes a resistor R1 for R2 and a resistor R3 for R4. In certain embodiments, a decoder or control logic element may include active electrical elements to receive one or more of the input signals and convert them into a unique combination of output signals.30, a unique combination of output signals is provided in the memory element 80, and this unique combination is used to change different operational states of one or more LEDs. In particular, the decoder or control logic element may output a combination of output signals that may be stored in a volatile memory element and periodically updated. Each time the volatile memory element is updated, the operational state of one or more LEDs is changed or updated via the driver element 82. In certain embodiments, the decoder element is configured to provide row or column selection information for one or more LEDs, or brightness or gray level information for each of the LEDs. In the case of an LED package configuration including multiple LED pixels, the decoder element may be configured to provide pixel or sub-pixel selection within the LED package to the memory element 80. The decoder element may also be configured to provide programming, set point information, or calibration information to the memory element 80. In certain embodiments, the decoder element may be configured to select specific pixels that share a control line by decoding a predefined position setting for the specific pixel on the shared control line, so that only the specific pixel will respond to the control signal. The predefined position setting may be programmed and stored in the memory element 80, such as a non-volatile memory element. In certain embodiments, driver element 82 (or buffer element) comprises a source driver element, a sink driver element, or both a source driver element and a sink driver element. A source driver element is typically used when the LEDs are configured for common-cathode control, and a sink driver element is typically used when the LEDs are configured for common-anode control. In certain embodiments, the source driver and sink driver may be included within active electrical element 30, and thus the source driver and sink driver may be configured to provide differential voltage outputs to control one or more LEDs. In certain embodiments, active electrical element 30 may also include one or more signal conditioning elements configured to convert, manipulate, or otherwise transform control signals before they are received by the source driver or sink driver.The signal conditioning elements may be configured to convert analog or digital signals for applications such as gamma correction or to apply other nonlinear transfer functions. In certain embodiments, the decoder / control logic communicates directly with the signal conditioning elements, while in other embodiments, the decoder / control logic assumes the task or function of the signal conditioning elements in the digital domain. In such embodiments, the signal conditioning elements may simply comprise wires when the decoder / control logic assumes its task. The signal conditioning elements may be configured or electrically connected between the memory elements 80 and the driver elements 82 so that signals leaving the memory elements 80 may be transformed or manipulated before reaching the driver elements 82. The signal conditioning elements may be configured or electrically connected between the input signals and the memory elements 80 so that the input signals may be transformed or manipulated before reaching the memory elements 80. Various other arrangements are contemplated, as the division of the various elements of the active electrical elements 30 can be performed in other manners. For example, the decoder / control logic may be considered a single processor unit together with the signal conditioning and memory elements. Additionally, active electrical elements 30 may, depending on the particular application, comprise multiple ESD elements, and / or multiple decoder / control logic elements, and / or multiple memory elements 80, and / or multiple signal conditioning elements, and / or multiple thermal management elements, and / or multiple driver elements 82. Each of the decoder / control logic elements, memory elements 80, signal conditioning elements, thermal management elements, and driver elements can be configured as analog elements, digital elements, and combinations of analog and digital elements, including software and firmware and the like.

[0054]

[0130] FIG. 9 illustrates a configuration of an active electrical element 30 according to an embodiment disclosed herein. 9 is a block schematic diagram illustrating the active electrical elements 30. In FIG. 9, the active electrical elements 30 may include many of the same components as previously described for FIG. 8, including ESD protection elements, decoder / control logic, volatile memory elements, non-volatile memory elements, and thermal management elements. As further shown in FIG. 9, the outputs of the volatile memory elements are connected to the LEDs (LED1-LED2). The active electrical element 30 may split into separate signal lines 84-1 through 84-3 for each of the LEDs (LED1 through LED3). Each of the separate signal lines 84-1 through 84-3 may include different ones of the signal conditioning elements, source driver elements, and sink driver elements, as previously described. In this regard, each of the LEDs (LED1 through LED3) may be independently driven and modulated based on one or more control signals entering the active electrical element 30. Additionally, for different color LEDs, it may be desirable for the different LEDs to be configured on different power supply lines or supply voltage inputs V1, V2. For example, due to the lower band gap of the different material systems (e.g., GaAs, AlGaInP, GaP-based) typically used to form red LEDs compared to blue or green LEDs (e.g., GaN-based), red LEDs typically have a lower turn-on or forward voltage (e.g., 1.8 to 2.4 volts (V)) compared to blue or green LEDs (e.g., 3 to 3.3 V). In this regard, the active control element 30 may be configured with separate connections (e.g., contact pad 38 in FIG. 2A) configured to receive a separate power supply line or input for the red LED (e.g., V1 at approximately 1.8-2.4 V) and a common power supply line or input for both the blue and green LEDs (e.g., V2 at approximately 3-3.3 V).

[0055]

[0131] In addition to various digital memory elements, analog memory elements may also be used. 10 is a schematic diagram illustrating an example structure including an analog volatile memory element that may be included within an active electrical element according to embodiments disclosed herein. In FIG. 10, an example sample-and-hold circuit 86 is shown including a switching device 88, a capacitor 90, an operational amplifier 92, and an optional operational amplifier buffer 94 between the input and capacitor 90. To sample the input signal, the switching device 88 connects the input signal to capacitor 90 through operational amplifier buffer 94, and capacitor 90 stores charge. After sampling the input signal, the switching device 88 disconnects capacitor 90, and the stored charge on capacitor 90 discharges through operational amplifier 92, providing an operating state for a particular LED that is held until the input signal is sampled again. In this manner, the optional operational amplifier buffer 94 and switching device 88 may be considered components of the decoder / control logic (FIGS. 8 and 9), the capacitor 90 may be considered components of the memory element (FIGS. 8 and 9), and the operational amplifier 92 may be considered components of the signal conditioning element (FIGS. 8 and 9), which may be linear or nonlinear depending on the system configuration.

[0056]

[0132] 11A-11F illustrate active electrical 11A is a schematic diagram illustrating an example structure for a driver element that may be included within the device. For video display applications, it may be desirable for the driver element to include a non-inverting circuit configured to linearly drive each LED from a fully off state of approximately 0 microamperes (μA) or approximately 0 V to approximately 1 milliampere (mA) or approximately 3 V with low power consumption. FIG. 11A illustrates an embodiment in which the driver element 96 includes a voltage-controlled current source circuit, such as a transconductance amplifier. In a transconductance amplifier, a differential input voltage is converted to an output current for driving the LEDs. In the simplified diagram of FIG. 11A, the driver element 96 includes a non-inverting circuit, but the driver element 96 requires connections to both terminals of the LEDs for operation, which results in a more complex device layout. Therefore, the driver element 96 is not a sink driver element for common-anode control or a source driver element for common-cathode control. Additionally, resistor R1 needs to be large to reduce input voltage sensitivity, which may reduce the efficiency of the driver element 96. In addition, when the LED needs to be turned off, the output current may have difficulty reaching a low enough value (0 μA) to achieve turn-off. Figure 11B shows that the driver element 98 comprises a transconductance amplifier arranged in an active cascode configuration including a transistor, such as a metal-oxide semiconductor field-effect transistor (MOSFET) M1, and an additional resistor R2, which may facilitate complete turn-off of the LED. 11A, the voltage sensitivity of the driver element 98 may become too high. At full turn-on of the LED, or about 1 mA, the driver element 98 may result in a low voltage input, for example, about 0.05 V, and therefore the active cascode configuration may suffer from an undesirable signal-to-noise ratio.

[0057]

[0133] FIG. 11C shows the active cascode configuration of FIG. 11B with transconductance FIG. 11D illustrates an embodiment of driver element 100 that adds an input amplifier to driver element 98, which includes an amplifier. The added input amplifier may serve to deamplify the voltage for lower signal sensitivity and provide an improved signal-to-noise ratio. Additionally, driver element 100 provides a sinking, or common-anode, configuration for the LED, but with an inverted input voltage. FIG. 11D illustrates an embodiment of driver element 102 similar to the embodiment of FIG. 11C but with a flip-flop polarity connection. In this regard, driver element 102 includes an input amplifier between the input voltage and driver element 98′, which is an inverted polarity version of driver element 98, which includes a transconductance amplifier in an active cascode configuration of FIG. 11B. As illustrated, driver element 102 illustrated in FIG. 11D offers the advantage of being non-inverting, but results in a sourcing, or common-cathode, configuration for the LED. Other driver element arrangements are possible, such as the Howland current pump configurations 104, 106 illustrated in FIGS. 11E and 11F. In Figure 11E, Howland current pump 104 includes an operational amplifier and resistor bridge configured to drive an LED. In Figure 11F, Howland current pump 106 further includes a voltage divider including resistors R5 and R6, added to Howland current pump 104 of Figure 11E to improve performance when little or no current is flowing. In addition, an additional operational amplifier is provided at the voltage input to form a non-inverting voltage follower (e.g., a preamplifier) ​​to provide the high input resistance required for the output buffer of the sample-and-hold circuit to ensure proper hold time.

[0058]

[0134] A plurality of LED packages as disclosed herein may be used to form an LED display. When arranged to form an LED pixel array for an application, it may be advantageous for the location of each individual LED package to be known within its corresponding active electrical element, or for each LED package to have a specific address associated with it. In certain embodiments, each active electrical element within each LED package is configured to store location- or address-specific information, such as the specific row and column in which the LED package is registered. In this regard, the display control unit may transmit signals across the LED pixel array that are coded for a specific location within the LED pixel array, and each active electrical element of each individual LED package is thereby configured to interpret the signals and determine whether to respond to or ignore a particular signal based on the location or address information. In certain embodiments, the active electrical element of each LED package includes a detector element configured to detect the LED package's location within the array of LED packages in the display, work in conjunction with a master controller (e.g., control element 18 of FIG. 1B , along with other hardware / software configurations), and relay that information for memory storage within the active electrical element. This task may be performed after PCB assembly when a special configuration program is run to properly set and store address and calibration information in the non-volatile memory of the active electrical elements, one or more remote memory devices, or both the active electrical elements and one or more remote memory devices.

[0059]

[0135] FIG. 12A illustrates an embodiment of an active electrical element 30 that includes a detector / signal conditioning element. 1 is a block schematic diagram illustrating an active electrical element 30. As previously described, the active electrical element 30 may be incorporated into an LED package to enable an LED display configured for active matrix addressing. The LED package controller 12 is configured to receive an input signal from an external source (e.g., control element 18 of FIG. 1B ) and independently change the drive conditions for one or more LEDs within the LED package. The block diagram of FIG. 12A is similar to that of FIG. 8 and includes a memory element 80 and a driver element 82, as previously described. As illustrated, ESD protection elements, decoder / control logic elements, thermal management elements, and signal conditioning elements may also be included, as previously described. In certain embodiments, one or more of the LEDs may be used as photodetectors to generate signals received by the detector / signal conditioning elements. For example, after installation of multiple LED packages in an LED pixel array, all LED packages connected to a common data bus may not have individual unique addresses. In this regard, an initial setup procedure (or location setup procedure) may be performed, in which each of the LED packages may be scanned with a light beam, and at least one LED in each of the LED packages may act as a photodiode to provide a corresponding voltage and / or current signal corresponding to the specific location of the LED package. In this manner, at least one of the LEDs may operate in a photovoltaic or photoconductive mode during the initial setup procedure. The signal generated by the light beam is used in conjunction with an electrical signal from a master controller (e.g., control element 18 of FIG. 1B , along with other hardware / software configurations) provided over a data bus to cause the components to record their addresses. When a coded signal for each pixel's location is transmitted across the LED pixel array, each LED package may therefore be configured to know to which signal it is supposed to respond. In such an embodiment, the LED driver element 82 may be configured with a high-impedance output to support a photodetector mode for one or more LEDs during an initial setup procedure. In certain embodiments, the detector / signal conditioning element may comprise a voltage detector, a current sensor, or even a wire that delivers the location signal to a decoder / control logic element.In this manner, the active electrical element 30 may be configured to be addressed, and the operating state of at least one of the LEDs may be changed in a manner dependent on information, such as an address, stored in local memory. In certain embodiments, a separate photodiode, not one of the LEDs in the LED package, may be configured within the LED package to provide a location signal to the active electrical element 30. In certain embodiments, the detector / signal conditioning element may be configured to monitor the operating voltage or current of the LEDs and store such information in a memory element. In this regard, the active electrical element 30 may be configured to store monitoring information including operating temperature, location information from a thermal management element, or voltage or current information from the LED via the detector / signal conditioning element. In certain embodiments, the active electrical element 30 may be configured to communicate such monitoring information with an external source (e.g., the control element 18 of FIG. 1B or a separate device), such that the LED display may be configured to self-monitor various operating conditions and generate a report or visual indication if any of the monitored operating conditions are outside a target window. In this regard, the active electrical element 30 may be configured for bidirectional communication with an external source.

[0060]

[0136] FIG. 12B includes a photodiode 110 according to an embodiment disclosed herein. 12A is a bottom view of an LED package 108. The LED package 108 is similar to the LED package 74 of FIG. 7 and includes a plurality of LED chips 75-1 through 75-3, 76-1 through 76-3, 77-1 through 77-3, and 78-1 through 78-3, each forming a plurality of LED pixels, as previously described, and an active electrical element 30′. The LED package 108 may also include package bond pads 48-1 through 48-4 and conductive traces (42-1 through 42-16 in FIG. 7). As illustrated, the LED package 108 includes a photodiode 110 configured to detect and communicate an optical signal to other components of the active electrical element 30′ as described in FIG. 12A. In certain embodiments, the active electrical element 30′ includes a photodiode 110. In certain embodiments, the active electrical element 30′ includes a photodiode 110. Thus, the photodiode 110 is disposed on the active electrical element 30. In other embodiments, the photodiode 110 is disposed outside the active electrical element 30'. For example, in certain embodiments, the LED package 108 includes a black encapsulant that covers the LED package 108 except for areas registered with each of the LED chips 75-1 through 75-3, 76-1 through 76-3, 77-1 through 77-3, and 78-1 through 78-3. In this regard, the photodiode 110 may be disposed adjacent to one of the LED chips 75-1 through 75-3, 76-1 through 76-3, 77-1 through 77-3, and 78-1 through 78-3 such that an adequate amount of the optical signal can reach the photodiode 110 without being absorbed by the black encapsulant. In other embodiments, the photodiode may be incorporated into other LED packages, including, among others, LED package 26 of Figure 2H, LED package 58 of Figure 3A, LED package 66 of Figure 4, LED package 68 of Figure 5, and LED package 70 of Figure 6. As previously described, photodiode 110 may be omitted in certain embodiments, and one or more of LED chips 75-1 through 75-3, 76-1 through 76-3, 77-1 through 77-3, and 78-1 through 78-3 may act as a photodiode when scanned with a light beam during an initial setup procedure.

[0061]

[0137] FIG. 13 is a diagram of an LED display panel according to an embodiment disclosed herein. 1B is a block schematic diagram illustrating various components that may be included in a system-level control scheme for an LED display panel. In a particular embodiment, the components of the system-level control scheme may be included on the backside of the display panel, as previously described in FIG. 1B. During operation, an input signal is received by the LED display panel from an external video source. As previously described, the video source, such as VGA, DVI, HDMI, HUB75, USB, among others, is provided through an appropriate electrical connector. A signal decoder, such as a DVI / HDMI decoder, may be configured to provide conversion of the input signal to other formats, such as 24-bit transistor-to-transistor logic (TTL) or complementary metal-oxide semiconductor (CMOS) color pixel data. For example, the signal decoder may convert the input signal into a 24-line data bus along with other control signals, such as a pixel clock, vertical sync, and horizontal sync, which are then routed to the control element. As previously described, the control element may comprise one or more of an ASIC, a microcontroller, a programmable control element, and a field-programmable gate array FPGA. For example, the control element may comprise an FPGA programmed to scale, offset, or otherwise convert converted data from the signal decoder and provide data buffering for the control lines that ultimately deliver various signals to the LED packages and corresponding LED pixels of the LED display panel. In certain embodiments, the control element is also configured to receive additional inputs used to convert the input signals. For example, the additional inputs may include horizontal and vertical panel position information for the LED display panel within a larger LED display. When multiple LED display panels are assembled together to form a larger LED display, each LED display panel may be configured with a unique position identifier that is relayed to the control element. The unique identifier, such as a serial number or position coordinates, may be pre-assigned before or during installation, or the unique identifier may simply be assigned by the order in which the LED display panels are connected when assembled.In the latter configuration, each of the LED display panels may be configured to communicate with each other via a shift register or the like, so that during installation, when the LED display panels are placed next to each other in a daisy-chain configuration, position information is relayed from one LED display panel to the next in the order in which they are installed, similar to HUB75 compatible panels. The additional input may also include a calibration table, such as a hash table, that provides information so that the control element can adjust the input signal to compensate for any unequal performance characteristics among the LED chips of the LED display panels. For example, after assembly of an LED display panel, the intensity of every LED pixel may be measured, and a calibration table may then be configured to provide information to a control element to scale drive signals differently for different LED pixels based on their initial measured brightness levels.

[0062]

[0138] The control element thus receives the input signal via the signal decoder, as well as the panel position or may be configured to receive additional inputs, including calibration information. As previously described, the control element may comprise one or more integrated circuits of various types. In certain embodiments, the control element comprises an ASIC pre-configured for application in an LED display panel. In other embodiments, the control element comprises an FPGA providing the ability to be programmed and reprogrammed after installation. Accordingly, other support devices, such as power inputs and regulators, programming interfaces, volatile and non-volatile memory elements, and the like, are suggested. The control element is configured to process either the input signals or additional input and output control signals sent to the active electrical elements of each of the LED pixels. In certain embodiments, multiple DACs may be arranged to convert signals from the control element before routing the signals to the LED pixels. The control element may also be configured to output column, row, and LED color selection information to the LED pixels that determines when each LED pixel and each LED chip within each LED pixel responds to the control signals from the multiple DACs. In certain embodiments, one or more column, row, or color selection decoders may be configured to receive and convert the output column, row, and / or LED color selection information from the control element before routing it to the LED pixels. For example, the control element may comprise an FPGA that outputs digital signal codes of 0 and 1 for column, row, or color selection information. Alternatively, a column, row, or color selection decoder may be configured to receive and decode the digital signals so that the active control elements of particular LED pixels in an LED display panel can be activated.

[0063]

[0139] For display applications, LED display panels use an array of LED pixels. The LED package may include a plurality of LED packages arranged in rows and columns to form a color display. Each of the LED packages may include one or more LED pixels including a first LED chip (e.g., a red LED chip), a second LED chip (e.g., a blue LED chip), and a third LED chip (e.g., a green LED chip), as previously described, and active electrical elements. Depending on the drive configuration between the control element and the LED packages, the number of control lines and the number of rows, columns, and color selection lines connected between the control element and each LED package may vary.

[0064]

[0140] FIG. 14 shows that the active electrical element 30 corresponding to a particular LED pixel is connected to a row select signal 14 is a schematic diagram illustrating a configuration configured to receive a row select signal and separate control signals for each of the red, green, and blue LED chips included within the LED pixel. In this regard, a row select signal activates each active electrical element 30 in a particular row of LED pixels, and each column of LED pixels is configured to receive three separate control signals for each of the red, green, and blue LED chips. The three separate control signals may correspond to three separate DAC or analog control signals per column. The control signals may control the brightness level or gray level for each of the red, green, and blue LED chips within a particular LED pixel. Thus, when a control signal is passed along a particular column, the row select signal determines which of the LED pixels corresponds to the signal. As previously described, the active electrical elements 30 corresponding to each LED pixel are configured to store red, green, and blue level signal information and accordingly drive the LED chips in a consistent manner until the active electrical elements 30 are next activated to refresh or update the signal information. Thus, in the configuration of FIG. 14, the active electrical elements 30 are connected to ground and power In addition to the press-fit connections, this is configured with connections to receive four different signal lines (row select, red level, green level, and blue level). This configuration therefore requires at least six connections, increasing PCB routing complexity. In certain embodiments, it may be desirable to have fewer connections, such as the four-connection embodiment shown in the previous embodiment (e.g., FIG. 2E).

[0065]

[0141] FIG. 15 shows that an active electrical element 30 that corresponds to a particular LED pixel 15 is a schematic diagram illustrating a configuration configured to receive a separate row select signal line for each LED chip in an LED pixel and a single color level signal line for all of the LED chips in the LED pixel. In FIG. 15, three separate row select signals (red row select, green row select, and blue row select) separately activate each of the red, green, and blue LED chips in the LED pixel. Thus, a single color level (e.g., a luminance level or gray level) may be provided for the red, green, and blue LED chips in the LED pixel. In this regard, each column may be configured with a single DAC, as previously described. In other embodiments, the active electrical elements 30 may be configured to receive optional column select lines, thereby allowing a single DAC to provide color level signals for multiple columns of LED pixels. In operation, a particular row select signal activates a particular LED chip in response to the color level signal at a particular time. As with the previous embodiment, the active electrical elements 30 are configured to store the color level signal information and drive each of the LED chips accordingly until the active electrical elements 30 are next activated to refresh or update the color level information. 15, active electrical element 30 is configured with connections to receive four or five different signal lines (red row select, blue row select, green row select, color level, and optional column select) in addition to ground and voltage input connections. While overall system complexity is reduced by the reduction in DACs, the requirement of at least six connections may be undesirable in some applications.

[0066]

[0142] FIG. 16 shows that an active electrical element 30 that corresponds to a particular LED pixel 16 is a schematic diagram illustrating a configuration configured to receive a coded row select signal for each LED chip in an LED pixel, and a single color level signal line for all of the LED chips in the LED pixel. In FIG. 16, the color level and optional column select lines may be configured similarly to those previously described for FIG. 15, but the row select signal is reduced to two row select lines (row select RS0, row select RS1). In this regard, the row select lines are configured to provide coded digital signals (combinations of 0 and 1) that determine which LED chips should respond to a particular color level signal. As a non-limiting example, the two row select lines may provide a "00" digital signal corresponding to an operating state in which none of the LED chips should respond, a "01" digital signal corresponding to activation of a red LED chip, a "10" signal corresponding to activation of a blue LED chip, and an "11" signal corresponding to activation of a green LED chip. As in the previous embodiment, the active electrical element 30 is configured to store the color level signal information and, accordingly, consistently drive each of the LED chips until the active electrical element 30 is next activated to refresh or update the color level information. 16, active electrical element 30 is configured with connections for receiving three to four different signal lines (row select RS0, row select RS1, color level, and optional column select) in addition to ground and voltage input connections. The reduction of at least one connection therefore represents an improvement in reduced PCB complexity compared to the embodiments of FIGS. 14 and 15.

[0067]

[0143] FIG. 17 shows how the active electrical element 30 of a particular LED pixel is controlled by a row select signal, a color level 17 is a schematic diagram illustrating an arrangement configured to receive a row select signal and one or more color select signals for the red, green, and blue LED chips contained within an LED pixel. In FIG. 17, the row select signal is configured similarly to the arrangement of FIG. 14, but with a different row select signal for each of the LED chips. Signals for different color levels (e.g., brightness or gray levels) are controlled by a single signal line. In this regard, each column may be configured with a single DAC, as previously described. In other embodiments, a single DAC may be configured to provide signals for color levels to multiple columns of LED pixels. To determine which of the LED chips in an LED pixel should respond to a particular color level signal, two color select lines (color select 0, color select 1) are configured to provide coded digital signals (combinations of 0 and 1) that determine which LED chip should respond to a particular color level signal. As a non-limiting example, the two color select lines may provide a "00" digital signal corresponding to an operating state in which none of the LED chips should respond, a "01" digital signal corresponding to activation of a red LED chip, a "10" signal corresponding to activation of a blue LED chip, and an "11" signal corresponding to activation of a green LED chip. Thus, in the configuration of Figure 17, the active electrical element 30 is configured with connections for receiving four different signal lines (row select, color level, color select 0, color select 1) in addition to ground and voltage input connections.

[0068]

[0144] FIG. 18 is a schematic diagram illustrating a configuration that is similar to the configurations of both FIGS. 16 and 17. In particular, FIG. 18 represents a configuration-independent notation that can represent either the configurations of FIG. 16 or FIG. 17. In FIG. 18, the active electrical element 30 includes color level lines that are the same as the color level lines of FIGS. 16 and 17. The active electrical element 30 of FIG. 18 further includes a device select (DS) line and two color select lines (CS0 and CS1). The DS line is configured to provide a device select signal, which may include at least one of a row select signal and a column select signal. The CS0 and CS1 lines are configured to provide coded signals that can correspond to either the row select RS0 and row select RS1 lines of FIG. 16 or the color select 0 and color select 1 lines of FIG. 17. In this regard, the active electrical element 30 may be configured to control a specific number of operating conditions using several connections. The DS line corresponds to either the column select line of FIG. 16 or the row select line of FIG. 17.

[0069]

[0145] FIG. 19 shows that an active electrical element 30 corresponding to a particular LED pixel is 19 is a schematic diagram illustrating a configuration configured to receive a single row select signal line and a single color level signal line for all LED chips in a pixel. In FIG. 19, the color level and optional column select lines may be configured similarly to those previously described for FIG. 15, but the row select signals are combined into a single row select line. In this regard, the single row select line may be configured to transmit coded signals corresponding separately to each of the LED chips in the LED pixel. The coded signals may include analog signals including at least one of a variable amplitude signal, a variable frequency signal, or a variable phase signal. The coded signals may also include multiplexed or multi-level logic signals. In certain embodiments, the row select line may be configured to provide signals at different voltage states corresponding to different ones of the LED chips. For example, the row select line may be configured as a four-level signal line, with four signal levels each corresponding to one of the following operating conditions: no LED chip selected, red LED selected, blue LED selected, and green LED selected. In certain embodiments, additional active electrical elements may be provided to further facilitate processing of the four-level signal line. Additional active electrical elements may be provided within each LED package or separately from each LED package. As with the previous embodiment, the active electrical elements 30 are configured to store color level signal information and accordingly drive each of the LED chips in a consistent manner until the active electrical elements 30 are next activated to refresh or update the color level information. Thus, in the configuration of FIG. 19, the active electrical elements 30 are configured with connections for receiving two or three different signal lines (row select (multilevel), color level, and optional column select) in addition to ground and voltage input connections. This configuration is desirable for applications with reduced complexity, such as the previously described four-connection configuration (e.g., FIG. 2E).

[0070]

[0146] FIG. 20 shows that an active electrical element 30 that corresponds to a particular LED pixel FIG. 20 is a schematic diagram illustrating a configuration configured to receive a single row select signal line and a single color level signal line for all LED chips in a pixel. FIG. 20 is similar to the configuration of FIG. 19 and includes color level and optional column select lines, as previously described. In FIG. 20, the row select signal line may be configured to transmit a coded signal, such as an asynchronous coded digital signal, with portions of this signal corresponding separately to each of the LED chips in the LED pixel. In certain embodiments, the coded signal includes different pulses corresponding to red LED select, blue LED select, green LED select, and no LED select operating conditions. Other operating states may also be addressed by extending the coding scheme. In this manner, the active electrical element 30 may include a shift register that cycles through each operating state (e.g., no selection, red select, blue select, green select) using each pulse of the coded signal. To prevent the shift register from becoming out of sync, the coded signal may also include a pulse code at the end of each cycle to reset the shift register to the beginning of the next cycle. In addition to sequential pulses, the row select lines may include other coded signals that identify and correspond to different ones of the four or more operating states described above. Thus, in the configuration of FIG. 20, active electrical element 30 is configured with connections (e.g., contact pads 38 in FIG. 2A) for receiving two or three different signal lines (row select (coding), color level, and optional column select) in addition to ground and voltage input connections. Similar to the configuration of FIG. 19, the configuration of FIG. 20 is desirable for applications involving reduced complexity, such as the previously described four-connection configuration (e.g., FIG. 2E).

[0071]

[0147] FIG. 21 illustrates a configuration in which each active electrical element of an LED pixel array is in accordance with the embodiment of FIG. FIG. 21 is a block schematic illustrating a system-level control scheme for an LED display panel configured to receive signal lines such as: In FIG. 21 , input signals, signal decoders, control elements, row / column decoders, panel position inputs, calibration table inputs, and multiple DACs may be provided as previously described for FIG. 13 . In FIG. 21 , column select lines are not included, and optional DAC decoder elements are arranged to enable selection of the correct DAC elements to receive data provided by the common data bus. In other embodiments, the control elements may be configured to include DAC decoding capabilities, and thus DAC decoder elements may not be required. Depending on the number of output pins available on a particular FPGA or other control element, a separate row / color decoder may also not be required.

[0072]

[0148] FIG. 22 is a diagram illustrating an LED panel configured for operation according to the configurations of FIGS. 20 and 21. 22 is a partial plan view illustrating a routing configuration for panel 112. In FIG. 22, multiple LED packages 26 are arranged in rows and columns to form an LED pixel array. Each LED package 26 may include multiple LEDs (e.g., 28-1 through 28-3 in FIG. 2) forming an LED pixel, an active electrical element (30 in FIG. 2), and multiple package bond pads 48-1 through 48-4, as previously described. As illustrated in FIG. 22, the multiple LED packages 26 are connected to multiple color level control lines 114-1 through 114-4, which correspond to the color level select lines in FIG. 20, and multiple row select control lines 116-1 through 116-3, which correspond to the row select lines in FIG. 20. For the LED package 26 labeled in FIG. 22, package bond pad 48-1 is connected to color level control line 114-1, and package bond pad 48-3 is connected to row select control line 116-3. Package bond pad 48-2 is connected to voltage input line 118-1 of a plurality of voltage input lines 118-1 through 118-4, and package bond pad 48-4 is connected to a ground connection plane (not shown). In a particular embodiment, the plurality of color level control lines 114-1 through 114-4 and the plurality of row select control lines 116-1 through 116-3 are connected to a multi-layer connector interface. The LED packages 26 may be arranged at different levels or planes of the LED panel 112, with one or more dielectric layers disposed between them for electrical isolation. For example, the row select control lines 116-1 through 116-3 may be disposed along a first plane closest to the LED packages 26. The color level control lines 114-1 through 114-4 and the voltage input lines 118-1 through 118-4 may be disposed along a different plane at a greater distance from the LED packages 26. Finally, a ground connection plane (not shown) may be disposed along another different plane at a greater distance from the LED packages 26 than the color level control lines 114-1 through 114-4 and the voltage input lines 118-1 through 118-4. Multiple vias 120 may be disposed through the multi-layer connector interface to provide corresponding connections with the package bond pads 48-1 through 48-4. FIG. 22 illustrates only one of many configurations for the routing configuration of the LED panel 112. In other embodiments, the various lines 114-1 through 114-4, 116-1 through 116-3, and 118-1 through 118-4 may be provided in differently arranged vertical and horizontal configurations, including, but not limited to, all vertical and all horizontal configurations.

[0073]

[0149] FIG. 23 shows that the active electrical elements 30 corresponding to particular LED pixels are arranged in rows, columns, FIG. 1 is a schematic diagram illustrating a configuration configured to receive all-digital communications for the LED pixel and / or color selection signals. In addition, bidirectional communication may be achieved via one of many standard or conventional protocols. Thus, many additional tasks are enabled, such as communication handshakes, addressing, status reports, and more extensive command structures. Stated differently, the active electrical element comprises a serial communication element. In this manner, the serial input / output lines are configured to provide digital signals to the active electrical element 30 according to one of a variety of serial communication link technologies. Serial communication technologies typically involve sequentially transmitting or streaming data in single bits over time. The optional clock input may be configured to receive a clock signal that provides cycling information for the LED pixels. In certain embodiments, serial communication (e.g., transmission or reception) may involve high bit rates using differential signaling, including, but not limited to, low-voltage differential signaling (LVDS), transition-minimum differential signaling (TDMS), current-mode logic (CML), and source-coupled logic (SCL). In this regard, the active electrical element 30 may be configured to receive optional differential input / output lines and optional clock differential input / output lines. Certain serial communication technologies may be configured with a self-clocking configuration or a configuration for receiving a self-clocking signal, and thus a clock input may not be required. Such self-clocking configurations may include decoder elements within the active electrical element that include various decoding capabilities for clock recovery, such as 8b / 10b encoding, Manchester coding, phase coding, pulse counting with or without a timed reset, isochronous signal coding, or non-isochronous signal coding. Other communication technologies include, among others, inter-integrated circuit (IIC) communications. 2C) protocol, I3C protocol, Serial Peripheral Interface (SPI), Ethernet, Fibre Channel (FC), Universal Serial Bus (USB), IEEE 1394 or FireWire, HyperTransport (HT), InfiniBand (IB), Digital Multiplex (DMX), DC-BUS or other power line communication protocols, Avionics Digital Video Bus (ADVB), Serial Input / Output (SIO), Controller Area Network (CAN), ccTalk protocol, CoaXPress (CXP), Musical Instrument Digital Interface (MIDI), MIL-STD-1553, Peripheral Component Interconnect Express (PCI Express), Profibus, RS-232, RS-422, RS-423, RS-485, Serial Digital Interface (SDI), Serial AT Attachment (Serial Some configurations may include ATA, Serial Attached SCSI (SAS), Synchronous Optical Network (SONET), Synchronous Digital Hierarchy (SDH), SpaceWire, UNI / O bus, and 1-Wire. Then, the active control element 30 is I 2The active electrical elements 30 are configured to operate (e.g., transmit or receive) using at least a subset of signals compatible with one of the above protocols, including, but not limited to, the C protocol. When configured for all-digital communication, the active electrical elements 30 are configured to latch input data, perform other logic, and provide color or gray levels to the LED pixels of the display. In certain embodiments, the active electrical elements 30 may comprise DAC-controlled current drivers, where one or more DACs are included within the active electrical elements 30 having current-drive outputs. In certain embodiments, the active electrical elements 30 comprise PWM drivers or current sources configured to independently drive each LED of the LED pixels based on a digital input signal. When the active electrical elements 30 are configured for all-digital communication, routing of the LED pixel array may be simplified. In this regard, in certain embodiments, each active electrical element 30 may only need to be configured to receive one communication or signal line, such as a serial input / output line illustrated in FIG. 23.

[0074]

[0150] FIG. 24 shows a configuration in which each active electrical element of an LED pixel array is in accordance with the embodiment of FIG. FIG. 24 is a block schematic diagram illustrating a system-level control scheme for an LED display panel configured to receive signal lines such as: In FIG. 24 , input signals, a signal decoder, a panel position input, and a calibration table input may be provided as previously described for FIG. 13 . In certain embodiments, the control element includes one or more serial communication interfaces or elements, as previously described. Therefore, a DAC element is not required, thereby providing a simplified configuration compared to the block diagram of FIG. 21 . Depending on the number of output pins available on a particular FPGA or other control element, a separate row / color decoder may also not be required. As illustrated, the output of the control element may communicate directly to the LED array using multiple serial outputs in communication with multiple serial lines or strings of LEDs in the LED array. In FIG. 24 , each string of LEDs is shown with two columns for illustrative purposes. In practice, the strings of LEDs may be arranged in rows and columns of different sizes and numbers, or the electrical connections of each string may not follow the rows and columns as shown.

[0075]

[0151] FIG. 25 is a circuit diagram for an LED panel configured for operation according to the configuration of FIG. 25 is a partial plan view illustrating a routing configuration. In FIG. 25, multiple LED packages 26 are arranged in rows and columns to form an LED pixel array. Each LED package 26 may include multiple LEDs (e.g., 28-1 through 28-3 in FIG. 2) forming an LED pixel, an active electrical element (e.g., 30 in FIG. 2), and multiple package bond pads 48-1 through 48-4, as previously described. In this configuration, control lines 116-1 through 116-4 correspond to the serial input / output lines, first and second voltage input lines 118-1 through 118-4 and 120-1 through 120-4 in FIG. 23, and the illustrated ground connection lines 122-1 through 122-4. As illustrated, color level control lines (e.g., 114-1 through 114-4 in FIG. 22) from the DAC are not required, thereby providing a simplified PCB routing configuration. 25, the input electrical connections, including control lines 116-1 through 116-4, voltage lines 118-1 through 118-4, 120-1 through 120-4, and ground lines 122-1 through 122-4, are all located along the same plane or layer of the LED panel. This configuration results in a simpler construction and manufacturing process, as well as reduced costs. In other embodiments, the control lines 116-1 through 116-4, voltage lines 118-1 through 118-4, 120-1 through 120-4, and ground lines 122-1 through 122-4 may be arranged on different planes with different arrangements of dielectric layers and vias to create various connections to each LED package 26. 25, the control lines 116-1 through 116-4, the voltage lines 118-1 through 118-4, 120-1 through 120-4, and the ground lines 122-1 through 122-4 are illustrated as long linear segments spanning the LED panel. The control lines 116-1 to 116-4, voltage lines 118-1 to 118-4, 120-1 to 120-4, and ground lines 122-1 to 122-4 may be arranged in other configurations, such as comb routing or other chain configurations that may reduce crosstalk between the various lines. In certain embodiments, the control lines 116-1 to 116-4, voltage lines 118-1 to 118-4, 120-1 to 120-4, and ground lines 122-1 to 122-4 may not be registered with particular rows and columns of LED packages 26. For example, the control lines 116-1 to 116-4, voltage lines 118-1 to 118-4, 120-1 to 120-4, and ground lines 122-1 to 122-4 may be configured to connect and communicate with subgroups of LED packages 26 arranged in blocks or other shapes across the LED panel.

[0076]

[0152] In certain embodiments, the control element and the LED package of the LED display Signal communication between the LED packages may include transmitting a control signal containing multiple data packets from the control element. A particular data packet may contain control information such as color selection data and brightness level data for individual LED packages in the array. In certain embodiments, the data packets may include file sizes ranging from as little as a single bit of data to much larger file sizes (e.g., large video files). Each data packet may also include a command code configured as an identifier or a series of identifiers that enable each LED package in the array to receive the command code and either respond to the data packet or pass the data packet on to the next LED package. In this manner, LED packages may be arranged to receive different data packets from the control signal in a cascading manner.

[0077]

[0153] 26A and 26B are diagrams illustrating exemplary devices according to embodiments disclosed herein. 1A is a schematic diagram illustrating the arrangement of a data packet 124. The data packet 124 is included in a data stream 126 transmitted over control lines from the control element 18 to the active electrical elements 30 of the LED package 26. In certain embodiments, the data stream 126 may include multiple data streams, including a cascaded approach in which the data stream 126 includes multiple sub-data streams. In certain embodiments, the LED package 26 forms one or more pixels (e.g., 12 in FIG. 1A ), as previously described. There may be additional LED packages disposed before or after the LED package 26 that are configured to receive the data stream 126. In this manner, the LED package 26 may receive the data packet 124 directly from the control element 18 or, in the data stream 126, through another LED package disposed between the control element 18 and the LED package 26. The data packet 124 may include information or data selections (denoted “Data”) for selecting and operating one or more LED chips of the LED package 26, including separate color selection and brightness level data for each LED chip disposed within the LED package 26. The information or data may also include setup data, calibration data, temperature compensation data, and option selection data, among others. Additionally, the data packet 124 may include instructions for turning on or off one or more LED chips in the LED package 26. In certain embodiments, at least a portion of the information or data from the data packet 124 may be stored in a register within the LED package 26 for later use. For applications in which the LED package 26 forms one or more LED pixels including multiple LED chips (e.g., red, green, and blue LED chips), the information or data may include a data subset corresponding to each of the LED chips. The data packet 124 may also include a section containing a command code (denoted “Command”) configured as an identifier or series of identifiers for the data packet 124 that identifies how the active electrical element 30 should respond to the data packet 124.In particular, the command code is configured to identify an action to be performed by the active electrical element 30. In certain embodiments, the action is to transmit data through the LED package 26. The action may include passing the data packet 124 through the LED package 26 or transmitting or retransmitting the data packet 124 through an output port of the LED package 26. In certain embodiments, the action includes performing an internal action within the LED package 26, such as driving one or more of the LED chips within the LED package 26 and transmitting the data packet 124 through the LED package 26. As used herein, an internal action for the LED package 26 may include setting or changing a persistent state over a time frame defined by the data packet 124 or any other associated data packet over a given time frame. The persistent state may include one or more of turning one or more LED chips on or off, changing the color or brightness level of an LED chip, or setting or updating calibration data, among others. In certain embodiments, the action includes driving one or more of the LED chips within the LED package 26 without transmitting the data packet 124 through the LED package 26. In certain embodiments, the action includes transmitting the data packet 124 without performing any other action internal to the LED package 26. Such an action may be based at least in part on one or more other data packets previously received by LED package 26. In further embodiments, another data packet, or a second data packet, received by LED package 26 may include a second command code identifying a second action to perform, the second action including transmitting the second data packet through LED package 26. In other embodiments, the second action includes activating one or more of the LED chips in LED package 26 and transmitting the second data packet through LED package 26. In this manner, data packet 124 is configured with self-identification. In particular embodiments, data packet 124 may include information configured to provide a data handshake with another LED package in data stream 126.The data handshake capability may include a start of packet section (denoted "BOP") and / or end of packet section (denoted "EOP") of the data packet 124 so that the LED package 26 can recognize the receipt and / or transfer of the data packet 124. In certain embodiments, the data stream 126 may include a blank section (denoted "Space"), which is a period of no data or an empty transmission period, located before or after the data packet 124 in the data stream 126. The period of no data transmission may be configured to control the communication speed and prevent buffer overload of control signals for the LED package 26. For example, if multiple LED packages 26 with different communication speeds or clock configurations are configured to receive different data packets from the data stream 126 in a cascaded manner, data overload may occur. Therefore, the period of no data transmission may be provided to ensure that communication effectively occurs at a controlled or slower speed to avoid or reduce buffer overload. The period of no data transmission may also be configured to signal a reset or restart condition or to signal a next frame condition. The period of no data transmission may also be configured at a different location relative to the data packet 124, such as after the data packet 124 as illustrated in Figure 26A, or before the data packet 124 as illustrated in Figure 26B. In certain embodiments, the data packet 124 may include other commands, such as basic on or off instructions for the corresponding LED package 26.

[0078]

[0154] FIG. 27 shows a diagram of a control element 18 connected to a plurality of LED packages 26-1, 26-2, . . . 2 Multiple data packets DP1, DP2…DP to 6-n n 1 is a schematic diagram illustrating a cascaded flow of LEDs. In certain embodiments, any number (n) of LED packages may be provided to form an LED display. As illustrated, the control element 18 generates a plurality of data packets DP1, DP2, ... DP nalong data stream 126, 26-n are configured to transmit data packets DP1, DP2, . . . DP to a plurality of LED packages 26-1, 26-2, . . . 26-n. n Each of the groups of data packets (e.g., DP1, DP2, . . . DP) may be configured, for example, as described for data packet 124 of FIG. 26A or 26B. n , DP1, DP2, . . . DP2) are data packets DP1, DP2, . . . DP2 received by a particular LED package 26-1, 26-2, . . . 26-n. n , 128-n。 For example, the data set 128-1 may form one of the data packets DP1, DP2, . . . DP received by the first LED package 26-1. n , and data set 128-2 corresponds to a group of data packets DP2...DP n , etc. In certain embodiments, a particular data packet (e.g., the first data packet DP1) is configured for a corresponding LED package (e.g., the first LED package 26-1). In this manner, the data packets DP1, DP2, . . . DP n is received by the first LED package 26-1, which performs an action based on the first command code of the first data packet DP1, removes the first data packet DP1 from the data stream 126, and replaces the data packets DP2...DP n Similarly, LED package 26-2 performs an action to remove data packet DP2 and pass or retransmit the remaining data packet DP n This sequence is configured to pass or retransmit the remaining data packets DP of the data set 128-n. nis received by the remaining LED packages 26-n. For a particular display application, each of the LED packages 26-1, 26-2...26-n will transmit their corresponding data packets DP1, DP2...DP1 until the control element 18 transmits a new data set 128-1 for the corresponding LED package 26-1, 26-2...26-n. n In certain embodiments, the control element 18 may be configured to provide a portion of the data stream 126, such as a bit pattern / code or transmission delay, that indicates to the LED packages 26-1, 26-2, ..., 26-n that the previous data set 128-1, 128-2, ..., 128-n is complete and to seek the next data set 128-1, 128-2, ..., 128-n. In the case of a transmission delay between different data sets 128-1, 128-2, ..., 128-n, the time delay may range from 1 microsecond to 0.1 seconds, providing a sufficient timeout for the LED packages 26-1, 26-2, ..., 26-n to begin seeking the next data set 128-1, 128-2, ..., 128-n. In the case of an LED display application, each data set 128-1, 128-2, ..., 128-n may correspond to a data frame or video frame for the LED display. In other LED applications, each data set 128-1, 128-2... 128-n may correspond to an operating state, such as a general illumination color point and / or brightness level, or a static image to be collectively provided by the LED packages 26-1, 26-2... 26-n. In certain embodiments, the first data packet DP1 configured for the first LED package 26-1 may include the same data length as the second data packet DP2. In other embodiments, the first data packet DP1 may include a data length greater than the data length of the second data packet DP2 to transfer more information to the first LED package 26-1, such as color selection data, brightness level data, setup data, calibration data, temperature compensation data, and / or option selection data.

[0079]

[0155] FIG. 28 shows a diagram of a control element 18 connected to a plurality of LED packages 26-1, 26-2, . . . 2 Multiple data packets DP1, DP2…DP to 6-n n and one or more talkback data packets TB1, TB2...TB to the control element 18. n 27. The control element 18 and the data stream 126 are configured to process data packets DP1, DP2, . . . DP as described with respect to FIG. n Data set 128-1, 128-2…128-n with groups of LED packages 26-1, 26-2 26-n. In FIG. 28, the first LED package 26-1 is configured to receive and remove the first data packet DP1 from the data stream 126, and then perform actions to replace the first data packet DP1 with the first talkback data packet TB1 in the data set 128-2 or the data stream 126 exiting the first LED package 26-1. Similarly, the remaining LED packages 26-2...26-n provide corresponding data packets DP2...DP n and subsequently combines them into the corresponding talkback data packets TB2...TB n The talkback data packets TB1, TB2, . . . TB n may then form a data set 128-c configured to communicate information about the LED packages 26-1, 26-2...26-n back to the control element 18 for monitoring. n The control element 18 transmits talkback data packets TB1, TB2, . . . TB n , TB1, TB2, TB3, TB4, TB5, TB6, TB7, TB8, TB9, TB10, TB11, TB12, TB13, TB14, TB15, TB16, TB17, TB18, TB19, TB20, TB21, TB22, TB23, TB24, TB25, TB26, TB27, TB28, TB29, TB30, TB31, TB32, TB33, TB34, TB35, TB36, TB37, TB38, TB39, TB40, TB41, TB42, TB43, TB44, TB45, TB46, TB47, TB48, TB49, TB50, TB51, TB52, TB nmay also be configured to provide data checksum parity or other data validation to the control element 18. In such an embodiment, the data packets DP1, DP2...DP n , TB1, TB2, . . . TB3 are transmitted to the active electrical elements 30 of the corresponding LED packages 26-1, 26-2, . . . 26-n via talkback data packets TB1, TB2, . . . TB4, TB5, TB6, TB7, TB8, TB9, TB10, TB11, TB12, TB13, TB14, TB15, TB16, TB17, TB18, TB19, TB20, TB21, TB22, TB23, TB24, TB25, TB26, TB27, TB28, TB29, TB30, TB31, TB32, TB33, TB34, TB35, TB36, TB37, TB38, TB39, TB40, n , DP1, DP2, DP3, DP4, DP5, DP6, DP7, DP8, DP9, DP10, DP11, DP12, DP13, DP14, DP15, DP16, DP17, DP18, DP19, DP20, DP21, DP22, DP23, DP24, DP25, DP26, DP27, DP28, DP29, DP30, DP31, DP32, DP33, DP34, DP35, DP36, DP37, DP38, DP39, DP40, DP41, DP42, DP43, DP44, DP45, DP46, DP47, DP48, DP49, DP50, DP51, DP52, DP53, DP54, DP55, DP56, DP57, DP58, DP59, DP60, DP61, DP62, DP63, DP64, DP65, DP66, DP67, DP68, DP69, DP70, DP71, DP72, DP73, DP74, DP75, DP76, DP77, DP78, DP79, DP80, DP81, DP82, DP83, DP84, DP85, DP86, DP87, DP88, DP89, DP90, DP91, DP92, DP93, DP94, DP95, DP96, DP97, DP98, DP99, DP100, DP99, DP101, DP1102 n , one or more of the talkback data packets TB1, TB2, ... TB n ) into the data stream 126.

[0080]

[0156] FIG. 29 illustrates LED packages 26-1, 26-2 receiving a data stream 126. A data packet DP configured to provide information to all of 6-2...26-n ALL-1 , D.P. ALL-2 a plurality of data packets DP1, DP2, . . . DP from the control element 18, n 27. The control element 18 and the data stream 126 are configured to process the data packets DP1, DP2, ... DP n , 26-n. In a particular embodiment, the data sets 128-1, 128-2, ..., 128-n are provided to the LED packages 26-1, 26-2, ..., 26-n in a data packet DP configured as a common or broadcast data packet for all of the LED packages 26-1, 26-2, ..., 26-n. ALL-1 , D.P. ALL-2In this regard, the first LED package 26-1 further includes one or more of the data packet DP ALL-1 , D.P. ALL-2 and responds to the data packet DP along the data stream 126. ALL-1 , D.P. ALL-2 , so that the remaining LED packages 26-2...26-n may also receive and respond accordingly. ALL-1 , D.P. ALL-2 , instructs all of the LED packages 26-1, 26-2, ... 26-n to turn on or off or provide a brightness level for all of the LED packages 26-1, 26-2, ... 26-n in response to user input or ambient light sensing. ALL-1 , D.P. ALL-2 , TB1, TB2, . . . TB3, TB4, TB5, TB6, TB7, TB8, TB9, TB10, TB11, TB12, TB13, TB14, TB15, TB16, TB17, TB18, TB19, TB20, TB21, TB22, TB23, TB24, TB25, TB2 n In certain embodiments, the same data may be provided. The data set 128-1, 128-2, ... 128-n corresponds to the first data packet DP ALL-1 and the second data packet DP ALL-2 , each of which instructs the LED packages 26-1, 26-2 . . . 26-n to turn on. ALL-1 , and DP which provides a common brightness setting for LED packages 26-1, 26-2...26-n ALL-2 29, the data packet DP ALL-1 , D.P. ALL-2 are illustrated at the beginning and end of the data sets 128-1, 128-2 . . . 128-n, but in other embodiments, the data packets DP ALL-1 , D.P. ALL-2may be located anywhere within the data sets 128-1, 128-2, ... 128-n. In a particular embodiment, the data packet DP ALL-1 , D.P. ALL-2 may be retransmitted through LED package 26-n to form data set 128-c that is received by control element 18.

[0081]

[0157] FIG. 30 shows at least one of the LED packages 26-1, 26-2, . . . 26-n. a plurality of data packets DP1, DP2, . . . DP from the control element 18, further including one or more subsequent data packets CDP2 configured to provide additional information to the n 27. The control element 18 controls the cascaded flow of data packets DP1, DP2, ... DP n30 ) to LED packages 26-1, 26-2, ... 26-n. In certain embodiments, data sets 128-1, 128-2, ... 128-n further include a follow-up data packet CDP2 configured to provide additional data or information to at least one of LED packages 26-1, 26-2, ... 26-n (e.g., the second LED package 26-2 in FIG. 30 ). In this regard, follow-up data packet CDP2 is positioned after data packet DP2 and before data packet DP3 within data sets 128-1, 128-2, ... 128-n of data stream 126. Additionally, the command code of follow-up data packet CDP2 may be configured to remove and respond to follow-up data packet CDP2 after the first LED package 26-1 passes on follow-up data packet CDP2 and the second LED package 26-2 removes and responds to data packet DP2. In certain embodiments, subsequent data packet CDP2 includes color selection data and / or brightness level data that may be additional to the color selection data and / or brightness level data received from data packet DP2. In certain embodiments, subsequent data packet CDP2 includes at least one of setup data, option selection data, and calibration data. For example, in certain embodiments, the active electrical elements 30 of one or more of LED packages 26-1, 26-2...26-n may be configured without flash memory, and subsequent data packet CDP2 as disclosed herein may be configured to provide one or more transfer functions following a reset or initial start-up condition. The transfer functions may include temperature compensation information, gamma functions, and the like.

[0082]

[0158] According to embodiments disclosed herein, the plurality of LED packages may include: The LED packages may be arranged serially to receive a cascading stream of data packets. A plurality of LED packages may form an array of LED packages, which may form at least a portion of an LED display panel, an LED sign panel, or a general lighting panel. In such embodiments, one or more of the LED packages may include active electrical elements, as previously described, that receive and perform actions on one or more of the data packets. In certain embodiments, the array of LED packages may be arranged on the panel in a serpentine arrangement configured to provide a cascading stream of data packets while providing reduced footprint electrical routing or traces between the LED packages.

[0083]

[0159] FIG. 31 illustrates a LE configured for operation in accordance with embodiments disclosed herein. FIG. 31 is a partial plan view illustrating a routing configuration for a D-panel 130. In FIG. 31, multiple LED packages 26 are arranged in rows and columns to form an LED pixel array. Each LED package 26 may include multiple LEDs (e.g., 28-1 through 28-3 in FIG. 2) forming LED pixels, an active electrical element (e.g., 30 in FIG. 2), and multiple package bond pads 48-1 through 48-4, as previously described. In FIG. 31, the package bond pads 48-1, 48-3 of each LED package 26 are configured as communication ports for transmitting and receiving a cascaded stream of data packets of a data stream. In particular, each package bond pad 48-3 is pre-assigned as an input port (designated "DIN" for data in) for the data stream, and each package bond pad 48-1 is pre-assigned as an output port (designated "DOUT" for data out) for the data stream. Each package bond pad 48-2 is configured as a voltage port (VDD), and each package bond pad 48-4 is configured as a ground port (GND). In this manner, a data stream may be received at the package bond pad 48-3 of the LED package 26 in the lower right corner (designated "INPUT") of the LED panel 130. At least a portion of the data stream may then exit the LED package 26 via the package bond pad 48-1 and be received by an adjacent LED package 26. A plurality of communication bus lines 132-1 through 132-3 for the data stream are arranged to connect the package bond pad 48-1 of one LED package 26 with the package bond pad 48-3 of the next LED package 26. In certain embodiments, the communication bus lines 132-1 through 132-3 are configured to connect the LED packages 26 consecutively in a serpentine manner. 31, communication bus lines 132-1 through 132-3 sequentially connect LED packages 26 from right to left across the last row of LED panel 130, and from left to right across the next row up from the last row. This sequence is repeated for each additional row of LED panel 130, forming a serpentine arrangement.Depending on the alternating direction of the serial connections from row to row, different ones of the communication bus lines 132-1 through 132-3 may include different lengths to make connections between package bond pads 48-1 and 48-3 of the serially connected LED packages 26. For example, communication bus line 132-1 may include a shorter length and alternate from row to row with communication bus line 132-3 having a longer length. As illustrated, communication bus line 132-2 is positioned to connect one row to another and may include the same or a similar length as communication bus line 132-1. In this manner, all of the communication bus lines 132-1 through 132-3 may be located on the same layer or plane of the LED panel 130 while providing serial connections for data streams to the LED packages 26. Although not shown, at least some power connections for the LED packages 26 may be located on a different layer or plane than the communication bus lines 132-1 through 132-3.

[0084]

[0160] FIG. 32 illustrates a selectively assignable 32 is a partial plan view illustrating a routing configuration for an LED panel 134 including LED packages 26 with communication ports, either single- or bidirectional. In FIG. 32, multiple LED packages 26 are arranged and connected in serpentine rows and columns to form an LED pixel array. Each LED package 26 may include multiple LEDs (e.g., 28-1 through 28-3 in FIG. 2) forming LED pixels, an active electrical element (e.g., 30 in FIG. 2), and multiple package bond pads 48-1 through 48-4, as previously described. In FIG. 32, package bond pad 48-2 (VDD) and package bond pad 48-4 (GND) are configured similarly to FIG. 32, while package bond pads 48-1 (D2), 48-3 (D1) of each LED package 26 are configured as communication ports for transmitting and receiving a cascaded stream of data packets of a data stream. As illustrated, each of package bond pads 48-1 is connected to each LED package. 32, package bond pads 48-1, 48-3 are arranged in the upper left corner of each LED package 26, and each of package bond pads 48-1, 48-3 is arranged in the lower right corner of each LED package 26, similar to FIG. 31. In FIG. 32, package bond pads 48-1, 48-3 are configured as selectively assignable communication ports based on how communication bus lines 132-1 through 132-3 are arranged to input and output data streams through each of LED packages 26. In this regard, communication bus lines 132-1 through 132-3 may be arranged to input or output data streams from either package bond pad 48-1, 48-3 of each LED package 26. Upon power-up or after a reset of the LED panel 134, when a particular LED package 26 initially receives a data stream, active electrical elements of the LED package 26 are configured to identify a first of the first and second communication ports (e.g., one of the package bond pads 48-1, 48-3) that receives an input signal from the data stream and selectively assign the first of the first and second communication ports as an input port and selectively assign the second of the first and second communication ports (e.g., the other of the package bond pads 48-1, 48-3) as an output port. In this manner, the package bond pads 48-1, 48-3 may be configured as bidirectional communication ports within each LED package 26. Thus, a particular LED package 26 may have package bond pad 48-1 assigned as an input port, while other LED packages 26 in the same LED panel 134 may have package bond pad 48-1 assigned as an output port. In certain embodiments, the active electrical element of each LED package 26 may comprise circuitry configured to selectively assign input and output communication portions. For example, the active electrical element may comprise circuitry including tri-state buffers such that the active electrical element may assign input and output ports in a register when an input communication signal is received.By providing such selectively assignable communication ports, the routing of the communication bus lines 132-1 to 132-3 between the LED packages 26 may be simplified with reduced length, thereby resulting in lower costs and enabling higher resolution for the LED panel 134.

[0085]

[0161] FIG. 33 illustrates a selectively assignable communication channel according to an embodiment disclosed herein. 33 is a partial plan view illustrating another routing configuration for an LED panel 136 including a plurality of LED packages 26 with communication ports. In FIG. 33, the plurality of LED packages 26 are arranged and connected in serpentine rows and columns to form an LED pixel array. Each LED package 26 may include a plurality of LEDs (e.g., 28-1 through 28-3 in FIG. 2) forming an LED pixel, an active electrical element (e.g., 30 in FIG. 2), and a plurality of package bond pads 48-1 through 48-4, as previously described. In FIG. 33, some of the package bond pads 48-1 through 48-4 are provided in a different arrangement than the illustration in FIG. 32. In particular, package bond pad 48-1 is configured as a ground port (GND) in FIG. 33, package bond pad 48-2 remains a voltage port (VDD), and package bond pads 48-3 (D1), 48-4 (D2) are configured as selectively assignable communication ports. In this manner, the selectively assignable communication ports are positioned closer to each other within the same LED package 26 and closer to the selectively assignable communication ports of adjacent LED packages 26. Accordingly, the communication bus lines 132-1, 132-2 may be further simplified with reduced length between the LED packages 26. In particular, the communication bus line 132-1 may form a straight line between adjacent LED packages 26 along each row of the LED panel 136. The longer communication bus line 132-2 connects one row to another and is positioned around the periphery of the LED panel 136.

[0086]

[0162] FIG. 34 illustrates a voltage line 118 and a ground line according to an embodiment disclosed herein. 33 illustrates the routing configuration for the LED panel 136 of FIG. 33 with the addition of 122. 1 is a partial plan view. By having multiple LED packages 26 with one or more selectively assignable communication ports (e.g., one or more of package bond pads 48-1 through 48-4), a simplified routing arrangement for communication lines 132-1, 132-2 enables a simplified routing arrangement for voltage lines 118 and ground lines 122 of an LED panel 136. In particular, such a routing configuration enables communication lines 132-1, 132-2, voltage lines 118, and ground lines 122 to all be located on the same layer or plane of the LED panel 136. In certain applications, it may be beneficial for one or more of the voltage lines 118 or ground lines 122 to be located on a different plane than the communication bus lines 132-1, 132-2 to improve power distribution, reduce voltage droop from trace resistance, and reduce noise from crosswalk and other sources. In particular embodiments, the communication bus lines 132-1, 132-2 and the voltage line 118 may be disposed on a first layer or plane of the LED panel 136, and the ground line 122 may be disposed on a second layer or plane of the LED panel 136 with electrical vias connecting the ground line 122 to the package bond pads 48-1 of each LED package 26. A subset distribution on the second layer or plane of the LED panel 136 may be provided to reduce the number of electrical vias.

[0087]

[0163] In each of FIGS. 31 to 34, the LED package 26 includes four packages. 31-34 , the LED packages 26 may include additional package bond pads. In certain embodiments, the LED packages 26 may have at least two additional package bond pads configured to provide clock signals in and out to provide synchronization or other timing sequences for the LED packages 26. In certain embodiments, serially connected LED packages 26 may be configured with a self-clocking configuration or a configuration for receiving a self-clocking signal, and thus, a clock input may not be required. In certain embodiments, the additional package bond pads may be configured to receive additional voltage inputs for power conservation. For example, one or more red LED chips in an LED package 26 may run at a lower voltage using a different voltage input than one or more blue or green LED chips in the same LED package 26. Additionally, one or more logic circuit arrangements in the active electrical element 30 may run at a lower voltage using a different voltage input.

[0088]

[0164] As used herein, the serially connected LED packages 26 The data packet DP may be configured with a degree or other compensation, calibration, correction, or transfer function capability. Such capabilities or techniques may include one or more look-up tables, calculations based on transfer coefficients, or a combination of look-up tables and transfer coefficient calculations to provide a piecewise continuous transfer function. In certain embodiments, the data packet DP, the subsequent data packet CDP, or the common or broadcast data packet DP ALLOne or more of may include command codes configured to prompt active electrical elements in one or more of the LED packages 26 to enable communication from such lookup tables and / or transmission coefficient calculations to a single LED package 26, a subgroup of LED packages 26, or all of the LED packages 26 in the data stream 126.

[0089]

[0165] As disclosed herein, receiving data from a data stream In certain embodiments, the active electrical element may perform one or more actions in response to the received data in combination with one or more of the current state of the LED package or a previous command received by the active electrical element. One or more actions may be performed based on commands identified by data received from the ream.

[0090]

[0166] FIG. 35 is a diagram illustrating a configuration of a semiconductor device for an active electrical element according to an embodiment disclosed herein. 1 is a schematic diagram illustrating various inputs and corresponding actions of an active electrical element 30. As illustrated, active electrical element 30 is configured to receive input data stream 126A and act according to various inputs and internal states 138-1 through 138-n, which are used to identify data stream 126A and one or more corresponding actions 140-1 through 140-n to perform. In particular, one or more inputs and internal states 138-1 through 138-n are received by control logic 141 of active electrical element 30. One or more inputs or internal states 138-1 through 138-n include a current state 138-1 of active electrical element 30 (and corresponding LED package 26), a current command 138-2 corresponding to a command code received from a current portion of input data stream 126A, a previous command 138-3 corresponding to a previous command code received from a previous portion of input data stream 126A, and one or more additional inputs (... 138-n). The current state 138-1 may include a reset or activation condition for the active electrical element 30, such as resetting a register to an initial state. If the LED package 26 is configured with a bidirectional communication port, the initial state may include resetting the bidirectional communication port to look for an input signal. The current state 138-1 may also include waiting for data input from one or more communication ports. After receiving data from the input data stream 126A, the current state 138-1 may include maintaining the operating conditions of the LED package 26 or implementing a common or broadcast command and any corresponding continuing data commands. Upon receiving the current command 138-2, the control logic 141 of the active electrical element 30 may then identify one or more actions 140-1 through 140-n to perform based on one or more combinations of the control logic 141 inputs and the internal states 138-1 through 138-n, and may include changing the current state 138-1.One or more actions 140-1 through 140-n may include transmitting or retransmitting data 140-1 from input data stream 126A to output data stream 126B, transmitting LED data 140-2, such as a talkback packet, to output data stream 126B, or any number of other actions 140-3, 140-4, ... 140-n, including energizing LED chips or other elements of LED package 26, turning on or off the output of LED package 26, sending data to a calibration register according to received input data stream 126A, identifying and assigning bidirectional communication ports of LED package 26 as different ones of input and output ports, changing the data rate according to input or output data stream 126A / 126B, implementing a particular set of options for LED package 26, or changing the drive conditions of LED package 26. In this regard, the active electrical element 30 may comprise a finite state machine configured to identify and perform an action based on one or more finite or current states of the current or previous input commands and the LED package 26 .

[0091]

[0167] FIG. 36 illustrates a finite state machine 142 according to an embodiment disclosed herein. 35 is a schematic diagram illustrating an active electrical element 30 configured according to any number of states 144-1 through 144-4, which correspond to current state 138-1 of FIG. 35. The power-up or reset state 144-1 may include an initial state for resetting registers and communication ports to an initial state. After the power-up or reset state 144-1, the active electrical element 30 may proceed to a communication port setup state 144-2, where the active electrical element 30 waits for data input from a data stream. Upon receiving the data input, the active electrical element 30 may allocate input and output ports for the corresponding LED packages. Commands received from various input signals may be configured according to any number of states 144-1 through 144-4. The power-up or reset state 144-1 may include an initial state for resetting registers and communication ports to an initial state. After the power-up or reset state 144-1, the active electrical element 30 may proceed to a communication port setup state 144-2, where the active electrical element 30 waits for data input from a data stream. Upon receiving the data input, the active electrical element 30 may allocate input and output ports for the corresponding LED packages. Depending on the command code, the active electrical element 30 may advance to one of the command states 144-3, 144-4. Command state 144-3 corresponds to implementing and / or maintaining operating conditions for individual LED packages of the active electrical element 30 in accordance with the received command code. Command state 144-4 corresponds to implementing and / or maintaining common or broadcast operating conditions for all LED packages in the data stream. In normal operation, the active electrical element 30 may advance from the startup or reset state 144-1 to the communication port setup state 144-2 before advancing and cycling between the command states 144-3, 144-4 in accordance with various command codes received along with other conditions, such as timeout conditions. As illustrated, all of the various states 144-1 through 144-4 may loop back to themselves until a condition or command is provided to change the active electrical element 30 to another of the various states 144-1 through 144-4. In particular embodiments, a command or condition may cause one of the various states 144-1 through 144-4 to change to another of the various states 144-1 through 144-4, as indicated by the dashed lines between different ones of the various states 144-1 through 144-4. While only four states 144-1 through 144-4 are illustrated, the active electrical element 30 and finite state machine 142 may have additional states in accordance with embodiments disclosed herein. Accordingly, FIG. 36 is provided as a high-level conceptual diagram of the basic operation of the active electrical element 30. It should be understood that the same operation can be represented in many different ways, such as combining command states into one and demoting a first command condition to a subordinate state. In particular embodiments, all states 144-1 through 144-4 may be configured with one or more timeout conditions that cause the particular state 144-1 through 144-4 to change to a previous one of the states 144-1 through 144-4, which may ultimately force a reset condition. In this regard, the active electrical element 30 may avoid being stuck in the unresponsive states 144-1 to 144-4.

[0092]

[0168] In certain embodiments disclosed herein, the LED package includes an LED The LED panel includes an active electrical element configured to detect adverse operating conditions or corresponding error signals from one or more LEDs in the package. In certain embodiments, the active electrical element may be configured to provide and switch between both forward and reverse bias states for one or more LEDs. The forward bias state may be provided to activate or turn on one or more LEDs, and the reverse bias state may be provided separately to one or more of the LEDs for other capabilities, including current leakage measurement and reverse bias voltage measurement. In certain embodiments, the active electrical element may be configured to provide forward voltage monitoring and corresponding adjustment to the drive signal for one or more LEDs. An LED panel is disclosed that includes multiple LED packages configured to provide both forward and reverse bias states. The LED panel may be configured to enable one or more of the LED packages to perform a self-test routine upon startup or at other intervals or times. Such a self-test routine may include comparing reverse leakage measurements with reverse leakage requirements and forward voltage measurements with forward voltage requirements for any of the LEDs in each LED package. Such a self-test routine may also include a temperature evaluation for any of the LEDs. In certain embodiments, the reverse leakage measurement and the forward voltage measurement may be added to or may replace the data returned to the control element (e.g., 18 in FIG. 28). In response to an improper reverse leakage value, the active electrical element of a particular LED package may shut down the particular LED in the LED package, shut down an LED pixel in the LED package, or shut down the entire LED package during normal operation of the LED panel to prevent current from diverting away from other LEDs, LED pixels, or LED packages. In response to a deviation in the forward voltage measurement, the active electrical element of a particular LED package may generate a drive signal, such as a PWM signal, for one or more of the LEDs in the package. The LEDs may responsively adjust their signals. In certain embodiments, an exemplary self-test routine may include cycling through each LED to perform an initial brightness measurement, performing internal reverse leakage and / or forward voltage measurements, and providing one or more diagnostic signals via LED color or pulse sequence for an external machine to detect and decode. In certain embodiments, the self-test routine may provide an output signal indicating at least one of a pass or fail condition for the LEDs in the package. The output signal may be communicated to an electrical port as a digital signal. In other embodiments, the output signal may be communicated as an optical signal through one or more of the LEDs in the package. In certain embodiments, the self-test routine may cycle through steps in which the LEDs are more slowly electrically activated to provide a visible signal to a human observer. In this manner, the optical signal may include a code that can be interpreted from the blinking of one or more LEDs at a predetermined color, duration, and / or number. In certain embodiments, the optical signal may first be communicated at a high speed that is undetectable or difficult to detect by a human observer, followed by communication at a slower speed to provide a human-readable code for human detection. The LED package may be configured to automatically perform such a self-test routine upon power startup, or the LED package may be configured to perform such a self-test routine when directly connected to a separate power source for testing. Additionally, a time delay may be provided between the high-speed communication and the low-speed communication codes at power-on, sufficient enough for the controller to have time to send a command to stop the self-test routine before the low-speed communication is displayed or transmitted. Thus, the display screen may only blink in accordance with the high-speed communication when power is first applied, and the master controller can send an all-off command almost instantly after startup. In this way, the initial high-speed blinking during startup is difficult to detect by a human observer.

[0093]

[0169] 37-42 illustrate concepts related to the active electrical elements described herein. 37-42 are provided as overall schematics and block diagrams to represent the present invention. While FIGS. 37-42 are illustrated as overall schematics and block diagrams, various configurations and additional supporting elements and circuits may be present in various embodiments. In FIGS. 37-42, any lines connecting different elements may include a single line or multiple lines depending on the application and the type of signal being transmitted (e.g., analog or digital). Again, these diagrams are intended to generally convey concepts. The addition of other resistive, capacitive, and active elements may be required to achieve desired functionality and performance. Other arrangements, such as source and / or sink drivers, are also contemplated. Additionally, it should be understood that other arrangements, such as using one ADC with multiplexer switches instead of separate ADC inputs for each node, are within the scope of this disclosure. Also, as before, separate voltage inputs can be used for LEDs with different voltage requirements (e.g., a voltage input for a red LED separate from a voltage input for a green or blue LED).

[0094]

[0170] FIG. 37 illustrates an active electrical element 30 according to an embodiment disclosed herein. FIG. 1 is a schematic diagram illustrating an embodiment configured to detect normal or adverse operating conditions of at least one LED 146. As illustrated, the driver 148 of the active electrical element 30 is essentially the analog interface of the active electrical element 30 and includes a pull-up resistor R6 set at a high resistance value (e.g., 10,000-100,000 ohms), a threshold detector 150, and a resistor network R1-R5 of different resistance values ​​with select switches FET1-FET3 coupled to resistors R3-R5, respectively. The threshold detector 150 may include a comparator / op-amp configuration for communicating an error (ERR) signal to the control logic 141. Such an error signal may include, among other things, an electrical short or open state for LED 1. The control logic 141 is the digital interface of the active electrical element 30 and includes resistor select (R-select) and resistor select (R-select) switches coupled to the driver 148. and PWM circuitry. The cathode of LED 146 is coupled to pull-up resistor R6, threshold detector 150, and resistor network R1-R5. In normal operation, selector switches FET1-FET3 enable selection of resistors R3-R5 to provide a predetermined current limit, and selector switch FET4 is coupled to the PWM circuitry of control logic 141 to provide brightness control for LED 146. When LED 146 is in an electrical short condition, the fault is detected as a high voltage, such as above 2 V or above 3 V, and a corresponding fault signal is communicated to control logic 141. When LED 146 is in an electrical open condition, the fault is detected as a low voltage, such as below 0.5 V, depending on the particular resistor selection. Although only LED 146 is illustrated, the concepts described herein are also applicable to multiple LED arrangements, in which case a separate or multiplexed threshold detector 150 is configured with each LED. Similar to previously described embodiments, the active electrical element 30 as configured in Figure 37 may be incorporated into the same LED package as one or more LEDs (e.g., LED 146). Additionally, the active electrical element 30 may be configured to communicate with and respond to commands from another control element (e.g., control element 18 of Figure 1B).

[0095]

[0171] FIG. 38 illustrates an active electrical element 30 according to an embodiment disclosed herein. 38 is a schematic diagram illustrating an embodiment configured to provide both forward and reverse bias states to at least one LED 146. In a particular embodiment, control logic 141 includes a reverse bias control output signal configured, via appropriate active elements, to supply a voltage level near Vss or near Vdd to LED 146 according to the output signal. Because the technical term "reverse bias" suggests that a high-level control logic 141 output results in a reverse bias state, the output signal can simply be coupled with an inverter 152 provided within driver 148. Thus, LED 146 may be either forward biased or reverse biased depending on the particular operating condition. Inverter 152, or an inverter logic element, may have sufficient output characteristics to drive LED 146. As with other aspects, the addition of other elements may be required to meet all requirements. In FIG. 38, ADC 154 is configured to detect the voltage of LED 146 relative to the operating condition of LED 146. Thus, ADC 154 is positioned to replace threshold detector 150 of FIG. 37. In a particular embodiment, ADC 154 comprises at least one of a resistor-capacitor (RC) circuit or an analog filter located in driver 148 and a digital filter circuit located in control logic 141. ADC 154 may further comprise a comparator, a sampling element with digital feedback, and additional filtering in the digital domain. Other arrangements / methods for analog-to-digital conversion are contemplated. To measure operating conditions such as reverse leakage of LED 146, control logic 141 may apply a reverse bias to LED 146 so that the anode of LED 146 is near 0 V. In a reverse-biased state with the PWM circuit turned off, the cathode of LED 146, coupled to pull-up resistor R6, will be at or near V if LED 146 exhibits suitably low reverse leakage. ddIf the LED 146 is leaking under a reverse bias condition, the cathode of the LED 146 will have a lower voltage. This can be sensed by the ADC 154 or a limit sensor and used by the control logic 141 to take appropriate action, such as shutting down the LED 146 and notifying the master control element 18 via a communication protocol. In this regard, the ADC 154 may form a level sensor configured to provide an error signal while the LED 146 is in a reverse bias condition. Thus, the ADC 154 is configured to detect a voltage related to the operating condition of the LED 146 while the LED 146 is in a reverse bias condition.

[0096]

[0172] In other embodiments, the control logic 141 may be implemented by one or more LEDs within the LED package. Multiple LEDs may be shut down, or the control logic 141 may shut down the entire LED package in response to detected reverse leakage. In FIG. 37, the control logic 141 may adjust the control signal to the LED 146 in response to the detected reverse leakage. As illustrated, the driver 148 may include resistor networks R1-R5 and select switches FET1-FET4, and the control logic 141 may include an R-select circuit and a PWM circuit, as described with respect to FIG. 37. As discussed above, during a reverse bias condition of the LED 146, the PWM circuit will be switched off. In certain embodiments, such a configuration of the active electrical elements 30 may enable adjustment and improved control of the operating conditions of the LED 146 beyond detecting voltage levels and responding only to pass and fail conditions. The resistor networks R1-R5 act as a current limiting circuit for the LED 146, and in this way, without active feedback, precisely control the current of the LED 146 in response to small LED voltage changes. These changes are observed overall over the life of the LED 146. The LED 146 forward voltage level feedback from the ADC 154 may be used as part of the calculation to determine and / or adjust the PWM duty cycle of the LED 146. For example, if the ADC 154 detects a decrease in the LED 146 forward voltage level, the control logic 141 may responsively increase the LED 146 PWM duty cycle to compensate for the brightness difference that would otherwise be observed. This pseudo-current control may be preferred over other methods of current control because it requires fewer resources (e.g., additional chip space and power) to implement. Along with the LED 146 forward voltage level feedback, transfer curves, temperature compensation data, and input brightness level data may also be part of the calculation to determine and adjust the PWM duty cycle. Additionally, the ADC 154 may provide the LED 146 voltage level monitoring to the control logic 141 so that an electrical short or electrical open condition of the LED 146 may also be detected. In this manner, the ADC 154 is configured to detect the voltage associated with the operating condition, such as the forward voltage level, of the LED 146 while the LED 146 is in a forward biased state.According to embodiments disclosed herein, ADC 154 may be configured to transmit measured data (e.g., reverse leakage and forward voltage measurements) to active electrical element 30 for continuous output to a master control element (e.g., control element 18 of FIG. 1B ). While only LED 146 is illustrated in FIG. 38 , the concepts described herein are also applicable to multiple LED arrangements, where a separate ADC 154 is configured with each LED, or where a network of switches (e.g., a multiplexer) allows one ADC 154 to obtain voltage measurements from several LEDs. As with previously described embodiments, active electrical element 30 as configured in FIG. 38 may be incorporated into the same LED package as one or more LEDs (e.g., LED 146).

[0097]

[0173] FIG. 39 illustrates the resistor network of FIG. 38 according to an embodiment disclosed herein. 39 is a schematic diagram illustrating an embodiment in which resistor networks R1-R5 and corresponding select switches FET1-FET3 are replaced with a current source 156 in active electrical element 30. In FIG. 39, pull-up resistor R6 and inverter 152 are coupled to LED 146, as described for FIG. 38. Current source 156 is configured to provide a current to LED 146 that is selectable (e.g., several levels) or adjustable (e.g., many levels). While the schematic diagram of current source 156 is more general than resistor networks R1-R5 and corresponding select switches FET1-FET3 of FIG. 38, later figures will use current source 156 to represent any method for controlling LED current, including resistor networks R1-R5 and corresponding select switches FET1-FET3 of FIG. 38. Control logic 141 includes a current selection circuit (or resistor selection circuit in FIG. 37) that is generally used to set a maximum current or brightness level based on the chip size or the like of LED 146. Such a selection may generally be made at initial setup and not necessarily changed thereafter. In certain embodiments, PWM may be omitted and LED 146 may be driven solely by current source 156, as previously described for the Howland current pump of FIG. 11E. In certain embodiments, current source 156 may include a built-in 39. In some embodiments, the active electrical element 30 may be equipped with temperature measurement feedback, and therefore feedback from the ADC 154 may not be required. In certain embodiments, temperature measurement feedback may be provided to the current source 156 by one or more components of the ADC 154. While only an LED 146 is illustrated in FIG. 39, the concepts described herein are also applicable to multiple LED arrangements. As with previously described embodiments, the active electrical element 30 as configured in FIG. 39 may be incorporated into the same LED package as one or more LEDs (e.g., LED 146).

[0098]

[0174] FIG. 40 is a schematic diagram illustrating a multiple LED embodiment similar to that of FIG. As illustrated, separate ones of the pull-up resistors R6-1 through R6-3 within the active electrical element 30 are coupled to corresponding ones of the plurality of LEDs 146-1 through 146-3. Additionally, each of the LEDs 146-1 through 146-3 is coupled to a corresponding ADC 154-1 through 154-3 and a corresponding current source 156-1 through 156-3. In FIG. 40, the inverter 152 is configured to change or switch from a forward bias state to a reverse bias state for each of the LEDs 146-1 through 146-3. In other embodiments, the active electrical element 30 may include separate inverters 152 for each of the LEDs 146-1 through 146-3. As discussed above, separate V dd The voltage input can be utilized to conserve power by driving the LEDs 146-1 through 146-3 at their respective voltage levels, with less power dissipation within the active electrical element 30. While current sources 156-1 through 156-3 are illustrated, resistor networks (e.g., R1 through R5 in FIG. 38) and selector switches (e.g., FET1 through FET3 in FIG. 38) may also be configured for each of the LEDs 146-1 through 146-3. Thus, the active electrical element 30 of FIG. 40 is configured to provide electrical open detection, electrical short detection, forward voltage monitoring, and reverse leakage monitoring for each of the LEDs 146-1 through 146-3 and to responsively regulate or shut off individual or groups of the LEDs 146-1 through 146-3. As with previously described embodiments, the active electrical element 30 as configured in FIG. 40 may be incorporated into the same LED package as the LEDs 146-1 through 146-3. Although multiple ADCs 154-1 to 154-3 are illustrated, a single ADC may be provided to detect voltages or voltage levels at multiple nodes, such that the single ADC is configured to provide at least one of reverse leakage measurements and forward voltage measurements for multiple LEDs 146-1 to 146-3.

[0099]

[0175] FIG. 41 illustrates a supply voltage V dd , ground V s s 41 is a schematic diagram illustrating the active electrical element 30 of FIG. 40 configured with multiple ports, including a V 1 port and a V 2 port, and bidirectional communication ports. dd , V ss In addition to the four ports, I / O port 1, and I / O port 2, active electrical element 30 includes four ports on the right side of the figure that are coupled to LEDs 146-1 through 146-3. As illustrated, LEDs 146-1 through 146-3 are electrically coupled to inverter 152, pull-up resistors R6-1 through R6-3, ADCs 154-1 through 154-3, and current sources 156-1 through 156-3, as previously described. In other embodiments, current sources 156-1 through 156-3 may be replaced with corresponding resistor networks and selection switches, as previously described. Bidirectional communication ports I / O port 1 and I / O port 2 are electrically coupled to one or more I / O buffers 158. I / O buffer 158 includes circuitry (e.g., various buffers and tri-state buffers) configured to, in conjunction with control logic 141, assign bidirectional communication ports I / O Port 1 and I / O Port 2 as either input (data in) or output (data out) communication ports based on how active electrical elements 30 are connected in the system. In response to an input data connection at either bidirectional communication port I / O Port 1 or I / O Port 2, control logic 141 assigns the input port direction and the output port direction accordingly. Control logic 1 41 may include one or more additional elements generally illustrated in FIG. 41, such as a memory element, a clock or oscillator, and / or a filter and ADC connected to a temperature sensor and resistor-capacitor to provide thermal management capabilities. In particular embodiments, one or more of ADCs 154-1 through 154-3, or a separate ADC, may be configured to provide a temperature measurement by measuring a voltage provided by a temperature sensor.

[0100]

[0176] FIG. 42 shows a polarity independent (P.A.) 42 is a schematic diagram illustrating the active electrical element 30 of FIG. 41 configured with polarity-agnostic, or polarity-independent, input capability. As illustrated, the active electrical element 30 may receive or connect multiple connections (e.g., ports P1-P4) from input ports or pins and route separate signal lines to V dd , V ss , DATA IN, and DATA OUT signal lines. Ports P1-P4 thus form a plurality of polarity-independent connection ports configured to receive or transmit various signals. In particular embodiments, switching network 160 includes circuitry configured to self-configure regardless of the order in which ports P1-P4 are connected. An exemplary circuit for switching network 160 may include a network of actively controlled switches, such as MOSFETs with gates biased according to voltage levels sensed at the inputs. In particular embodiments, switching network 160 may provide some of the functionality of I / O buffer 158 of FIG. 41. Thus, in particular embodiments, it may be desirable to combine the functionality of I / O buffer 158 of FIG. 41 into switching network 160. As illustrated by the dashed lines in active switching network 160 of FIG. 42, each of ports P1-P4 is connected to a voltage dd , V ss , DATA IN, and DATA OUT signal lines. In this way, the active electrical element 30 of the LED package can be connected to the package bond pads (e.g., 48-1 to 48-4 in FIG. 2I) of the LED package via V dd , V ss, input communication, and output communication. For output communication, at least one of the ports (e.g., ports P1-P4) may be configured as an output communication port. Because the switching network 160 also includes a power source, a power pin must first be designated and switched to the appropriate node. This power input can be achieved through a passive circuit (e.g., an RC network control gate of an FET). As an example, FIG. 43 is a general schematic diagram illustrating a four-input rectifier 162 that may be used to provide initial power to the switching network 160 of FIG. 42. As illustrated, each of the ports P1-P4 is coupled to a pair of low-voltage connections, such as bipolar diodes, Schottky diodes, and the like. Such diodes may consume much more power due to their voltage drop (especially for low-voltage LED components); therefore, the four-input rectifier 162 may only be used to initially power the switching network 160 of FIG. 42, after which active elements and logic can be used to make the final switch connections. In this manner, the power switching network of FIG. 42 may then use low-voltage switches, such as MOSFETs, to bypass the diode rectifiers (e.g., 162 of FIG. 43) to provide low-resistance routing of the power pins. In particular embodiments, MOSFETs may be included in the active rectifier of the switching network 160 used in combination with the four-input rectifier 162. In other embodiments, an active rectifier may be used in place of the four-input rectifier 162 by replacing each of the diodes illustrated in FIG. 43 with actively controlled switches, such as MOSFETs and / or transistors, including bipolar junction transistors.

[0101]

[0177] As previously explained, compressed digital code or encoded signals, etc. Active electrical elements of an LED package configured to receive digital codes from a control element of an LED display are disclosed. For example, the active electrical elements may be configured to receive an encoded digital signal (e.g., FIG. 20) that utilizes reduced data bits in the data stream to communicate a larger amount of command code. In this regard, the active electrical elements may be configured to receive compressed digital codes and then expand the digital codes for the data stream received by the active electrical elements. Accordingly, the expansion of the received digital codes may include any nonlinear function or algorithm for expanding the received data stream, including an exponential inverse power function that can increase the dynamic range of the data stream. The dynamic range of a digital signal may refer to the range of signal levels (e.g., upper and lower values) generally described by the number of bits. One form of compression simply relates to how such bits are used. Bits are often used to linearly generate current or power input to an LED. This can result in inefficient use of the bit depth (e.g., dynamic range) for a display system, as human observers perceive light in a nonlinear manner that is more similar to logarithmic or power-law functions, such as those used for gamma correction. The dynamic range of a given number of bits may be small (e.g., the highest level of an 8-bit code is 255 times the lowest level excluding zero), but that dynamic range can be extended by many orders of magnitude when transforming the data to match the eye's nonlinear response. As an example, instead of having a dynamic range of 255 with 8 bits, by applying a gamma of 2.2, one obtains a dynamic range of approximately 200,000 while still using only 8 bits. Without compression, 18 bits would be required to achieve the same level of dynamic range. Thus, dynamic range may refer to the useful number of bits, sampling, or resolution of the data stream of an active electrical element.Thus, active electrical elements as disclosed herein may be configured to receive compressed data and expand such data to provide a greater observed and useful dynamic range. As just described, in certain embodiments, the compression and expansion scheme may follow a power law formula (e.g., gamma correction) to increase the dynamic range between the digital image and the image perceived by a human observer. In other embodiments, the compression and expansion scheme may include groups of adjacent LED pixels / packages or LED pixels / packages in close proximity to one another. Such groups of LED pixels may be applicable to embodiments in which the groups of LED pixels are under the control of a common electrical element in an LED display matrix. In particular, an LED package may include two or more adjacent LED pixels and a compressed data code; the expanded data code subsequently reduces data inefficiency by removing redundancies in the data that might be expected between neighbors of two or more adjacent LED pixels. Thus, a common code is decoded or expanded to provide codes for two or more adjacent LED pixels or sub-pixels.

[0102]

[0178] As described above with respect to Figures 41 and 42, several two-way communication ports Disclosed are LED packages capable of receiving compressed digital data at any of several bidirectional communication ports or at polarity-independent package bond pads (e.g., 48-1 through 48-4 in FIG. 2I) and decompressing such digital data. Additionally, disclosed are LED packages capable of receiving transfer functions or transfer function values ​​to be applied within the LED package at any of several bidirectional communication ports or at polarity-independent package bond pads (e.g., 48-1 through 48-4 in FIG. 2I). The transfer function may include one or more subsets of transfer function coefficients for the active electrical elements to interpolate. In this manner, the transfer function may be calculated in the digital domain. In embodiments, the transfer function may include a piecewise transfer function. According to embodiments disclosed herein, a transfer function may be applied to an ADC input (e.g., ADC 154 in FIG. 38 ), to a PWM output (e.g., PWM circuit in FIG. 38 ), and to a DAC-controlled output of an active electrical element to direct or control one or more of a temperature measurement of one or more LEDs in an LED package or a brightness output of one or more LEDs in an LED package. As used herein, a “transfer function” refers to any type of function, which may be implemented in any number of ways, for converting input data to output data such that the output data differs from the input data. In certain embodiments, the transfer function may be configured to transform data according to a linear function, such as additive, multiplicative, and the like. In certain embodiments, the transfer function may be configured to transform data according to a nonlinear function, such as an exponential function, a logarithmic function, a transcendental function, an algorithmic function, a Fourier transform (e.g., a discrete Fourier transform), and the like. The transfer function may be applied to temperature control by converting a temperature sensor value to generate a corresponding control signal for the LED for temperature, brightness, or voltage regulation, as well as combinations thereof. In certain embodiments, the transfer function may be configured to receive and convert multiple inputs of data values ​​from multiple sources, such as an input from a control element (18 in FIG. 1B), an input from a temperature sensor, and an input including a forward voltage measurement or reverse leakage measurement of the LED. The input from a control element external to the LED package may be configured as a serial communication or serial input including, among other things, a desired brightness, a calibration, and a transfer coefficient. The input from the temperature sensor or the input including the forward voltage and / or reverse leakage measurement may be generated internally within the particular LED package. Thus, an LED package is disclosed that includes an active electrical element configured to receive a data value and convert the data value according to the transfer function. In certain embodiments, the data value includes a compressed data code received by the active electrical element, and the active electrical element is configured to convert the compressed data code to an uncompressed data code.The unfolded data code may include brightness levels or other control signals for the LEDs in the LED package.

[0103]

[0179] In certain embodiments disclosed herein, the active The electronic device is configured to receive data from a data stream including user-selectable color depth data. Color depth may refer to the number of data bits used to indicate or represent the color of an LED or LED pixel. For example, a 1-bit color depth may include monochrome colors such as black and white, while a 24-bit color depth may include 8 bits for each of the red, blue, and green LEDs in a particular LED package. Depending on the application, the user-selectable color depth data may include color depths ranging from 1-bit color depth to 100-bit color depth. In certain embodiments, a user may select a color depth for one or more LED packages in the LED display, which may be selectable from any one of 24-bit, 30-bit, 36-bit, and 48-bit color depths. In certain embodiments, a particular bit depth (e.g., one of 24-bit, 30-bit, 36-bit, and 48-bit color depths) may be achieved by selecting the next higher bit depth and zero-padding some least significant bits for the difference. Depending on the selected color depth, the data stream received by the active electrical elements of a particular LED package may be adjusted according to the bit size corresponding to the selected color depth. For example, when changing from a larger color depth to a smaller color depth, the number of corresponding bits and transmission time are reduced. In this way, the bit size of the selectable color depth data is adjustable. At different communication speeds for the data stream, there may be a trade-off between the bit size or depth associated with the color depth, the frame rate, and the number of pixels or sub-pixels in the control chain.

[0104]

[0180] As disclosed herein, the active electrical elements of the LED package may be any Contains compressed or encoded signal and color depth data corresponding to any number of command codes. The LEDs or LED pixels may be configured to receive various data signals, including, but not limited to, data signals from a single LED or LED pixel. As previously described, command codes may be included as part of a data packet in the data stream. In certain embodiments, a command code for a particular LED or LED pixel may include an identifier signal that indicates to the active electrical elements how the particular LED or LED pixel should respond to the command code. By way of example, the identifier signal may include a digital “0” signal indicating that the command code is a single-pixel command code for a single LED or single LED pixel, or a digital “1” signal indicating that the command code is an all-pixel command code for all LEDs or all LED pixels. In certain embodiments, the single-pixel data may be removed from the data stream by the particular pixel receiving the data and replaced with talkback data or talkback data packets, as previously described. The single-pixel command codes may include any one of commands to skip a pixel, set brightness return to voltage, set brightness return temperature and state, and return or talkback back leakage, among others. The command code to skip a pixel enables the ability to address a particular LED or LED pixel in the chain without affecting other LEDs or LED pixels upstream. The all pixel command code may include any one of setting the brightness for all LEDs or LED pixels or an end of command code. In certain embodiments, the end of frame command code is provided to indicate that an LED or LED pixel should respond to the next single pixel command code. In certain embodiments, the single pixel command code may be transmitted or retransmitted along the chain to address a particular LED or LED pixel. In this regard, an active electrical element of an LED package responsive to a single pixel command code may responsively transmit a single pixel command code with a modified code to indicate the "executed" command code and then wait until the end of frame command code is received before responding to the next single pixel command code.Such an active electrical element is sometimes referred to as a pseudo-repeater in cascaded communication because it receives and retransmits data, sometimes modifying or replacing the data and not always returning the same data that it received.

[0105]

[0181] Either a single pixel command code or a full pixel command code (e.g., Examples of command codes that can be either 0 or 1 in the case of the "All" command bit may include any one of the following: reset, set options, set RGB calibration, set RGB transfer coefficients, set RGB thermal coefficients command codes, load data, and load program. The load data and load program may be used to send and / or receive any data or program to and / or from the memory elements of the active electrical elements. In certain embodiments, the set option command code may be followed by additional data bytes where each bit represents one of the following options: red LED off, green LED off, blue LED off, disable thermal shutdown, disable red LED shutdown, disable green LED shutdown, disable blue LED shutdown, baud rate 0, baud rate 1, color depth 0, color depth 1, turn off / on parity fail, PWM type 0, PWM type 1, resistor select 0, resistor select 1, resistor select 2, do not turn off shorted LEDs, use thermal compensation, setup check to ensure the power-on reset condition is addressed, and use voltage compensation to set the mode in which forward voltage feedback is used to adjust the PWM duty cycle. The communication speed 0 and 1 options may provide up to four communication speeds for the output or may be provided to detect a communication speed from the input. In this regard, an LED package is disclosed that includes an active electrical element configured to change or adapt the communication speed of data without a transmitted clock signal. The color depth 0 and 1 options allow for color depths including 24-bit depth, 30-bit depth, 36-bit depth, and 48-bit depth. It may be configured to toggle.

[0106]

[0182] As explained above, certain embodiments may utilize pulsed methods such as PWM. This may involve controlling the brightness and / or gray level output of the LEDs through PWM control. Under overall PWM control, the LEDs may be electrically activated for a fraction of the PWM period or for a duty cycle of the PWM period. The PWM period, sometimes referred to as the PWM rate or PWM frequency, corresponds to the length of time to complete each PWM cycle. For LED display applications utilizing PWM control, higher PWM frequencies are typically desired. Below 60 Hz, the human eye may be able to detect LED flicker, while between 60 Hz and 1000 Hz, beating with other cycling (PWM or scanning) sources or recording equipment may occur. In this regard, LED displays as disclosed herein are provided that are capable of PWM operation at effective PWM frequencies of at least 60 Hz, or at least 1,000 Hz, or at least 10,000 Hz, or in the range including 60 Hz and 10,000 Hz, or in the range including 60 Hz and 1,000 Hz, or in the range including 1,000 Hz and 10,000 Hz.

[0107]

[0183] Higher PWM frequencies result in increased power consumption and reduced linearity. There may be trade-offs involved. In addition, the PWM frequency for a display application can be limited by the color or bit depth for the display and the clock or counter rate. Specifically, the PWM period is equal to the bit depth divided by the clock frequency. In this regard, in a high dynamic range (HDR) display, as the bit depth increases, the PWM frequency is reduced proportionally to the clock frequency. Therefore, while a conventional method for increasing the PWM frequency involves increasing the clock frequency, the actual clock frequency can be limited to a range including 1 MHz and 50 MHz, and some exemplary display applications operate at a clock frequency of 3 MHz. The bit depth corresponds to the number of bits used to represent a particular color in the display. Each bit has two possible values, 0 or 1, and therefore the total number of bits for a particular bit depth is calculated by raising the number of possible values ​​(2) to the power corresponding to the bit depth. In this way, a 2-bit depth (e.g., 2 2 ) corresponds to a total of 4 bits, and a 4-bit depth (e.g., 2 4 ) corresponds to a total of 16 bits, and a 16-bit depth (e.g., 2 16 ) corresponds to a total of 65,536 bits. Therefore, for display applications with higher bit depths, higher PWM frequencies may be difficult to achieve within the range of allowable clock frequencies.

[0108]

[0184] According to embodiments disclosed herein, an effective LED display The effective PWM frequency is increased by segmenting the duty cycle over which the LEDs are electrically activated within each PWM period. Stated differently, the effective PWM frequency is achieved without changing the clock or bit depth and still maintaining the same PWM period (e.g., the PWM period still equals the bit depth divided by the clock frequency, but the effective PWM frequency becomes the clock frequency multiplied by the number of segments divided by the bit depth). One way to segment the duty cycle within a PWM period is to permute or reorder the sequence of clock counters that are compared to a desired level, with the result being an output control signal to a driver that operates at least one LED. In this way, the duty cycle within each PWM period may be segmented over a series of pulses that activate and deactivate each LED multiple times within each PWM period, rather than continuously keeping the LEDs electrically activated for the duration of the duty cycle. In certain embodiments, the active electrical elements disclosed herein incorporated within one or more LED packages of an LED display can individually control the duty cycle for one or more sets of one or more LEDs. It can be divided into:

[0109]

[0185] FIG. 44A shows an example in which the active electrical element 30 is a diode for one or more LEDs. FIG. 44A is a schematic diagram illustrating an embodiment configured to partition a service cycle. While FIG. 44A includes the components described below, active electrical element 30 may include many other components, as previously described, that are not reproduced in FIG. 44A for illustrative purposes. In this regard, FIG. 44A may represent an example of a sub-block implementation of a potentially more complex element. As previously described, active electrical element 30 is configured to receive a data stream and responsively transmit drive or control signals to one or more LEDs. The data stream is received by active electrical element 30 and may optionally be stored in memory element 164 or a register. Memory element 164 may include any of a memory element, a register element, and / or a chip, as previously described for memory element 80 of FIG. 8. Additionally, one or more signal conditioning elements 166 may be configured to convert, manipulate, or otherwise transform the control signals from the data stream before the drive signals are transmitted to one or more LEDs, as described for the signal conditioning element of FIG. 8. Separate signal conditioning element inputs may be provided to introduce transfer coefficients and the like, as previously described for signal conditioning element 166. In certain embodiments, signal conditioning element 166 may be optional. In other embodiments, signal conditioning element 166 may be implemented using hard logic built into active electrical element 30 for a specific task. In still other embodiments, a programmable device such as a microcontroller may be used to convert data by calculation through program instructions or other means. Comparator 168 is configured to receive a command signal from the data stream using memory element 164 and, if present, signal conditioning element 166. Comparator 168 is also configured to receive a clock or counter signal using clock 170 and counter 171 and, in response, output a control signal based on a comparison of the command signal from the data stream with the counter signal.Clock 170 and counter 171 may include any of the clock configurations previously described. In Figure 44A, clock 170 and counter 171 are illustrated within active electrical element 30, although in other embodiments, clock 170 may be located outside active electrical element 30. Additionally, inputs for data streams, signal conditioning, and counter conversions are actually illustrated within active electrical element 30, as external inputs may route through intervening components within active electrical element 30, as previously described.

[0110]

[0186] During operation, the clock 170 and counter 171 are Counter 171 provides a sequential count corresponding to the desired bit depth of the PWM period. In this manner, counter 171 sequentially counts the total number of bits for the bit depth and then resets or rolls over to zero. As used herein, sequential counting refers to counting the total number of bits in numerical order (e.g., 0, 1, 2, 3, 4, ...), while non-sequential counting refers to ordering the total number of bits according to a sequence of numbers that includes all of the same total number of bits but is in a non-numerical order during one PWM period. Thus, comparator 168 compares bits from the data stream after any signal conditioning / conversion with the count value provided by counter 171 after any counter conversion as described below, and responsively provides a control signal to driver 172. During an exemplary PWM period or cycle, a data value corresponding to several bits depending on the bit depth is received from the data stream and compared to the counter value. When the counter value is less than the data value, comparator 168 may responsively provide a control signal to driver 172 to electrically activate a corresponding LED or LEDs. As the count value advances, a comparator 168 electrically deactivates the corresponding LED or LEDs when the count value exceeds the data value. The comparator 168 may responsively provide a control signal to the driver 172 to control the LED. In this manner, PWM control is provided to the LED, where the LED is electrically activated for a duty cycle of the PWM period and electrically deactivated for the remainder of the PWM period. The driver 172 may include any of the driver devices and elements as previously described, including the driver element 82 as described with respect to FIG. 8. In particular embodiments, the comparator 168 may be configured to perform a simple comparison of the data value and the counter value, such as less than, less than or equal to, greater than, greater than or equal to, and / or not equal to. In other embodiments, the comparator 168 may be configured to perform the comparison based on additional logical operations.

[0111]

[0187] As further illustrated in FIG. 44A, a counter conversion device 174 or circuit may be provided to receive counter signals from clock 170 and counter 171 and responsively convert the counter signals before they are received by comparator 168. In this manner, counter conversion device 174 may be configured to rearrange the order of the counter signals so that comparator 168 performs the comparisons with each of the above-described data values ​​in a non-sequential order (e.g., non-numerical order) over each PWM period. By applying the comparisons non-sequentially, the output of comparator 168 may undergo multiple transitions over each PWM period. In this manner, the duty cycle may be segmented into multiple electrically activated portions depending on the data value, rather than a single continuous duty cycle, thereby increasing the effective PWM frequency for the LEDs. In certain embodiments, counter conversion device 174 may be configured to be selectable between a numerically ordered sequence and one or more non-numerically ordered sequences over each PWM period depending on the application, such that active electrical element 30 can selectively toggle between a segmented duty cycle and a single-pulse duty cycle. In this regard, the same counter conversion device 174 may provide numerically ordered counter values ​​that are not converted or altered from the counter 171 in certain applications, but may provide converted and non-numerically ordered counter values ​​in other applications. In certain embodiments, a separate counter conversion input may be provided to the counter conversion device 174 to provide the ability to select between a numerically ordered sequence and a non-numerically ordered sequence.

[0112]

[0188] FIG. 44B shows the counter conversion device 174 of FIG. 44A, which is connected to the LEDs, LED1 to FIG. 44B is a schematic diagram illustrating an embodiment configured to share a duty cycle among multiple LEDs, LED1 through LED3, to partition the corresponding duty cycle for LED3. Like FIG. 44A, FIG. 44B may include many other components, as previously described, that are not reproduced in FIG. 44B. In this regard, FIG. 44B may represent an example of a potentially more complex implementation of a sub-block of elements. In FIG. 44B, clock 170 and counter 171 are configured similarly to FIG. 44A. However, counter conversion device 174 output is shared among multiple LEDs, LED1 through LED3. In this manner, each of LEDs, LED1 through LED3, includes a corresponding and separate memory element 164-1 through 164-3, signal conditioning element 166-1 through 166-3, comparator 168-1 through 168-3, and driver 172-1 through 172-3. Thus, the output of counter conversion device 174 is shared with each of comparators 168-1 through 168-3 for comparison with separate data signals for each of LEDs, LED1 through LED3. In particular embodiments, LEDs, LED1 through LED3, may comprise any number of LEDs forming multiple sub-pixels or matrices of sub-pixels served by a single counter conversion device 174.

[0113]

[0189] 45 to 50 show the counter conversion device 17 of FIG. 44A for PWM control. 4, sequential counter sequences, and various non-sequential or 44A provide table diagrams each representing a modified counter sequence. In certain embodiments, the counter conversion device 174 of FIG. 44A may have a select / control input to allow selection among any number of count sequences, such as those illustrated in FIGS. 45-50. In each of FIGS. 45-50, each row of the table represents data values ​​that may be received from the data stream for a particular desired output power or LED brightness. These data values ​​are represented as sequential decimal values ​​(e.g., 1, 2, 3, etc.) and their corresponding binary values ​​(e.g., 0000, 0001, 0010, etc.). Each column represents the counter value (sequential and / or modified) in binary values ​​for each step of the counter sequence. For illustrative purposes, the example shown in FIGS. 45-50 is provided for a 4-bit depth display application in which 16 possible values ​​(e.g., 0, 1, 2...15) are provided for each color or gray level. In fact, the embodiments illustrated in Figures 45-50 are scalable to larger bit-depth applications for higher resolution displays, including, but not limited to, 24-bit, 30-bit, 36-bit, and 48-bit configurations. Each of these bit-depth configurations would be divided by 3 for bit depth per pixel (e.g., 8, 10, 12, or 16 bits). In the case of three-color or other multiple sub-pixel components, a single counter and converted counter signal can be shared among all sub-pixels, each with its own data, comparator, and driver as previously described for Figure 44B.

[0114]

[0190] FIG. 45 shows a circuit for providing a counter sequence to the comparator of FIG. 44A in numerical order. FIG. 45 illustrates a table diagram. In this regard, the data value over a particular PWM period is compared by a comparator (168 in FIG. 44A) to a counter value that starts at 0 and progresses sequentially through a numerical sequence to 15. Because FIG. 45 represents linear counter values ​​that are not converted, the modified counter value portion of the table remains empty. When the data value is greater than the counter value, a control signal (e.g., "1") is provided to electrically activate the corresponding LED. When the data value is less than or equal to the counter value, a control signal (e.g., "0") is provided to electrically deactivate the corresponding LED. In this regard, a data value of 0 results in the corresponding LED being electrically deactivated for the entire PWM period. A data value of 8 results in the corresponding LED being electrically activated for 8 consecutive counts out of a total 16-count counter sequence, thereby providing a duty cycle corresponding to 50% of the PWM period. As illustrated, for each of the data values ​​0 through 15, the corresponding LED is electrically activated once for the duration of the duty cycle within each PWM period. Stated differently, within each PWM period, there is at most one electrical pulse delivered to the LED, or at most one positive and one negative transition. At low frequencies, this can cause noticeable flickering or blinking, and may additionally result in beating with other light or imaging sources.

[0115]

[0191] Figure 46 shows how non-numerically ordered counter values ​​are converted into a full bit-reversed sequence. 44A according to the sequence shown in FIG. 44A. Rather than comparing data values ​​to the numerically ordered counter values ​​provided by counter 171 of FIG. 44A, counter conversion device 174 of FIG. 44A may reorder the counter values ​​by bit reversal to provide a modified counter value. For example, in counter sequence 3, the sequential counter value 0011 is converted to the reverse order to become the modified counter value 1100, which originally corresponded to counter sequence 12. In the case of full bit reversal, all sequential binary counter values ​​are converted in this manner. This is one of the simplest methods of rearrangement, as it can be achieved by simply wiring the counter's bit output in reverse order and does not require any decision logic, calculations, or lookups. Thus, comparator 168 of FIG. 44A compares data values ​​over a particular PWM period according to the modified counter values, which are arranged in the following non-numerically ordered sequence: 0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15. When the data value is greater than the modified counter value, a control signal (e.g., “1”) is provided to electrically activate the corresponding LED. When the data value is less than or equal to the modified counter value, a control signal (e.g., “0”) is provided to electrically deactivate the corresponding LED. Depending on the particular bit depth and data value, the corresponding LED may be electrically activated and deactivated multiple times to provide a particular net duty cycle. For example, a data value of 8 results in the corresponding LED being electrically activated for 8 non-consecutive counts out of a total of 16 counts, thereby cycling (or transitioning) on ​​and off 8 times to provide a 50% duty cycle of the PWM period. In this way, the effective PWM frequency for a 50% duty cycle is 8 times higher than the rate of FIG. 45. For data values ​​of 0, 1, and 15, the corresponding LEDs would be driven in a manner similar to that illustrated in FIG. 45. The bit-reversal technique of FIG. 46 provides an increased effective PWM rate for many data values, but power consumption may also be increased because the LEDs are cycled on and off more times within each PWM period. As shown, at a 50% data level, a full bit-inverted PWM provides a drive frequency at half the clock rate, which may be much higher than desired. Additionally, linearity issues may occur because the driver may not accurately follow the high-speed signal provided by the comparator.

[0116]

[0192] FIG. 47 shows the modified counter value in accordance with the partial bit reversal sequence of FIG. FIG. 44A illustrates a table diagram for providing to comparator 168. In the case of partial bit reversal, only a portion of the counter bits are reversed. As an example, FIG. 47 illustrates modified counter values ​​obtained by reversing the first two digits of the counter value. Thus, for counter sequence 4, a sequential counter value of 0100, representing a decimal value of 4, is converted to a modified binary counter value of 1000, representing a decimal value of 8. In this example, by converting only the first two digits, the number of transitions at the 50% level is reduced by one-quarter of that with full bit reversal. Thus, comparator 168 of FIG. 44A compares data values ​​over a particular PWM period according to modified counter values ​​arranged in the following non-numerically ordered sequence: 0, 1, 2, 3, 8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15. By applying partial bit reversal, the corresponding LED may be electrically activated and deactivated more times within each PWM period than with the numerically ordered sequence of FIG. 45 and less times than with the full bit reversal sequence of FIG. 46. For example, a data value of 8 results in the corresponding LED being electrically activated and deactivated in successive increments of 4 counts to provide a 50% duty cycle. Thus, for a data value of 8, the corresponding LED will cycle (or transition) on and off twice within each PWM period, thereby doubling the effective PWM frequency compared to FIG. 45 but benefiting from lower power consumption compared to the higher effective PWM frequency of FIG. 46. In certain embodiments, partial bit reversal may include reversing other digits of the sequential binary counter value. In certain embodiments, any number of bits may be reversed, from zero to the total number of counter bits. In certain embodiments, the selection of how many bits are reversed may be hard-coded or hardwired within the system. In still further embodiments, adaptive bit reversal may be utilized to allow for changes to the bit-reversal and / or partial bit-reversal sequence as a user option and / or setting accepted as input.

[0117]

[0193] As explained above, partial bit reversals can occur more frequently than once per PWM period. This provides several advantages over raw counter sequences by providing a transition frequency significantly lower than the clock frequency while providing a much higher transition frequency. However, as the illustration in Figure 47 shows, data levels below 5 and above 11 remain unchanged from the original method (e.g., Figure 45). This may be further addressed by bit segment swapping. Previous embodiments have implemented a method for addressing all counters. In bit segment swapping, segments of bits are swapped without reversing the bits within each segment. For example, to achieve y pulses within a PWM period, x most significant bit segments are swapped with the remaining bits, in this case 2 x =y. As an example, an 8-bit counter having bit positions 76543210 may have bit position 7 as the most significant bit. If four PWM pulses per period are desired for most data values, the most significant two bits (76) may be moved to the least significant positions to provide the sequence 54321076. In this regard, a modified counter using this bit ordering may be communicated to comparator 168 of FIG. 44A.

[0118]

[0194] Figure 48 shows bit segment swapping according to two-segment sequencing. FIG. 44A shows a table diagram for providing the modified counter value to comparator 168 of FIG. 44A . For a two-segment sequence, the modified counter value is obtained by rearranging the 16 values ​​into two different segments, such as all even numbers in one segment, followed by all odd numbers in the second segment. This is achieved, as previously described, by swapping the order of the counter bits so that the most significant bit is moved to the least significant bit position. Thus, comparator 168 of FIG. 44A compares data values ​​over a particular PWM period according to the modified counter values, which are arranged in the following non-numerically ordered sequence: 0, 2, 4, 6, 8, 10, 12, 14, 1, 3, 5, 7, 9, 11, 13, 15. As illustrated, the increased number of data values ​​may correspond to the LEDs being electrically activated and deactivated twice within each PWM period, compared to the partial bit-reversal sequence of FIG. 47 , thereby providing a higher effective PWM frequency for lower and higher data values ​​and values ​​around 50%.

[0119]

[0195] Figure 49 shows bit segment swapping according to 4-segment sequencing. FIG. 49 shows a table diagram for providing the modified counter value to comparator 168 of FIG. 44A according to the modified counter value sequence. For a four-segment sequence, the modified counter value is obtained by rearranging the 16 values ​​into four different segments. Stated differently, the upper two bits are swapped with the lower two bits without reversing the bits within each set. As a result, FIG. 49 shows that the four different segments are provided by starting the modified counter value at 0 and counting four to provide the first four digits of the modified counter sequence, followed by setting the fifth digit at 1 and counting four to provide the next four digits, and so on. Thus, comparator 168 of FIG. 44A compares data values ​​over a particular PWM period according to the modified counter values, which are arranged in the following non-numerically ordered sequence: 0, 4, 8, 12, 1, 5, 9, 13, 2, 6, 10, 14, 3, 7, 11, 15. As illustrated, depending on the data value, the corresponding LED may be electrically activated and deactivated one to four times within each PWM period.

[0120]

[0196] Figure 50 shows bit segment swapping according to 8-segment sequencing. FIG. 50 shows a table diagram for providing modified counter values ​​to comparator 168 of FIG. 44A according to the modified counter values ​​arranged in the following non-numerically ordered order: 0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15. For an eight-segment sequence, the modified counter values ​​are obtained by rearranging the 16 values ​​into eight different segments. Stated differently, the upper three bits are swapped with the lower bits without reversing the bits within each set. As a result, FIG. 50 shows that up to eight different segments can be provided by starting the modified counter value at 0 and counting up to eight to provide the first two digits of the modified counter sequence, followed by setting the third digit at 1 and counting up to eight to provide the next two digits. Thus, comparator 168 of FIG. 44A can select a particular segment according to the modified counter values ​​arranged in the following non-numerically ordered order: 0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15. The data values ​​across the PWM periods are compared. As illustrated, depending on the data value, the corresponding LED may be electrically activated and deactivated one to eight times within each PWM period. While the above examples are provided for 2-segment, 4-segment, and 8-segment sequencing, such embodiments are scalable to larger bit-depth applications for higher resolution displays, including, but not limited to, 24-bit, 30-bit, 36-bit, and 48-bit configurations. For such higher bit-depth applications, the higher segment sequencing may include, among others, 16-segment, 32-segment, and 64-segment sequencing.

[0121]

[0197] In each of Figures 45-50, the last column is zero, and as a result, Even at high brightness levels, the LED is deactivated for one clock pulse corresponding to the last counter sequence value. This is one representation of various implementations of Figures 45-50 in practice. If it is desired that the maximum level have no transitions so that the LED remains activated throughout the entire PWM period, an implementation may omit the last counter value (i.e., the last column) and roll over to zero one cycle earlier than previous implementations. For clarity, all Figures 45-50 show the final optional cycle in which the modified counter is equal to the sequential value 15 in decimal (or 1111 in binary).

[0122]

[0198] Non-numerically ordered and non-numeric ordered sequences as illustrated by the examples in Figures 45-50. By providing various non-numerically ordered and / or modified counting sequences, a higher effective PWM frequency may be achieved. In this regard, active electrical elements configured for PWM control may achieve a higher effective PWM frequency than the PWM frequency calculated by dividing the clock frequency by the bit depth for a particular application. By providing a higher effective PWM frequency, an LED display may advantageously provide a higher dynamic range with precise high and low brightness levels, as well as avoid low-frequency interference effects while maintaining good linearity, without having to increase the clock rate or sacrifice power efficiency. Such non-numerically ordered and / or modified counting sequences may be provided for any of the previously described embodiments, including the LED package 26 of FIGS. 2A-2I having multiple LED chips forming pixels, the LED package 74 of FIG. 7 and / or the LED package 108 of FIG. 12B including multiple groups of LED chips forming multiple pixels, and any of the active electrical element structures, related components, and related system-level configurations as described in FIGS. 8-12A and 14-35. In certain embodiments, the non-numerically ordered and / or modified counting sequences described herein are applicable to all-in-one multi-pixel displays including multiple LED chips formed in pixel groups formed on a common board containing either common active electrical elements such as an ASIC or multiple separate ASICs. Such all-in-one multi-pixel displays may include one or more of chip-on-glass (COG), chip-on-board (COB), package-on-package (POP), package-on-board (POB), or PCB assemblies.

[0123]

[0199] An LED display as described herein can be used to reduce the various A reset may sometimes be required due to an error condition. As previously described, a period of no data transmission and / or a command code including a reset command code may be configured to signal a reset or restart condition. In certain embodiments, the LED display and corresponding active electrical elements may be configured to initiate a reset and / or interrupt condition without requiring a period of no data transmission and / or a reset command code. In this regard, a reset and / or interrupt condition may occur for a time interval longer than that expected in normal operation. A reset condition may be initiated via a common data signal, such as a serial communication signal, by holding a line state high or low across the display. Such a reset condition may be signaled configured to reset all active electrical elements in the display or one or more individual active electrical elements in the display. In the case of one or more individual active electrical elements, the reset signal may be provided with different lengths and / or pulses corresponding to the particular active electrical element. In this regard, active electrical elements that do not respond to the reset signal may simply pass the reset signal on to the next active electrical element. Another approach for signaling a reset to individual active electrical elements in a string is to configure the active electrical elements to respond to a "hard reset next" command. In this way, the command can be directed to the active electrical element preceding the target active electrical element to be reset and direct the reset signal to its output, thus avoiding all previous active electrical elements from receiving the hard reset signal. In certain embodiments, there may be two such commands: a "hard reset one" and a "hard reset all" command. The "hard reset one" command sends an individual reset signal, such as the shorter of the two reset signals. A hard reset all command can direct a longer pulse at the output, signaling all active electrical elements following in the string to reset. The ability to initiate a reset condition by embedding a reset signal within the data stream can be particularly useful for forcing a reset when the LED display and corresponding active electrical elements do not respond to command codes or other reset communications, including periods of no data transmission.

[0124]

[0200] FIG. 51A provides an active electrical element according to a previously described embodiment. FIG. 51B illustrates a normal data stream in return-to-zero (RZ) format that may be used in a digital signal processing system. FIG. 51B illustrates a data stream 178 in RZ format that includes a reset signal 180. As illustrated, the reset signal 180 corresponds to a period of time during which the data stream 178 is held in a high state (e.g., "1") for a longer duration than the portion of the normal data stream 176 of FIG. 51A. In this manner, an active electrical element that is subject to the reset signal 180 may responsively reset its operating state upon receiving the reset signal 180. Additionally, any active electrical element that is not subject to the reset signal 180 may simply pass the reset signal 180 to the next active electrical element without initiating a reset action. While the reset signal 180 is illustrated in a high state (e.g., "1"), the reset signal 180 may alternatively be held in a low state (e.g., "0") or may include pulses of different lengths and / or multiple pulses without departing from the principles disclosed herein. In particular embodiments, data stream 178 may further include one or more commands or instructions indicating the type of reset or interrupt condition to be initiated after receiving reset signal 180. Additionally, data stream 178 may include additional commands indicating the next action to be taken after the reset or interrupt condition is initiated.

[0125]

[0201] Thermal monitoring of the operating temperature of the LED package and / or LED display Thermal management elements may be incorporated within the LED package and / or LED display, as previously described with respect to FIG. 8. Accordingly, the operating state of one or more LEDs within the package and / or display may be adjusted based on the monitored temperature provided by one or more thermal management elements. In some cases, the response time of the thermal management elements may be slow, or the location of the thermal management elements may be spaced significantly away from a particular LED to provide timely thermal compensation. For example, in a three-chip LED package 26 as illustrated in FIG. 2A, the corresponding thermal management elements may provide a single operating temperature for the LED package 26 without distinguishing the individual contributions of each of the separate LED chips 28-1 through 28-3 to the overall operating temperature. In some cases, the LED chips One of the LED chips (e.g., 28-1) may be operating disproportionately hotter than the other LED chips (e.g., 28-2, 28-3). For such conditions, an integrator configured to separately determine thermal management compensation for each of the LED chips 28-1 through 28-3 within the package may be incorporated into the active electrical element 30. For example, the integrator may compare the operating temperature as measured by the thermal management element with one or more different brightness levels being delivered to each of the LED chips 28-1 through 28-3 and with optional calibration constants to calculate individual thermal compensation adjustments for each of the LED chips 28-1 through 28-3.

[0126]

[0202] The color space or color gamut that an LED pixel can display depends on the The color space for an LED pixel comprising a red LED chip, a green LED chip, and a blue LED chip may be defined by the respective color points of the LED chips. For example, the color space for an LED pixel comprising a red LED chip, a green LED chip, and a blue LED chip may be defined as a triangular region in a chromaticity diagram, with the vertices of the triangular region coinciding with the different color points of the LED chips. In certain embodiments, the color space of the incoming video source may be different from the color space defined by the LED chips of the LED pixel. As a result, displayed colors may differ on different monitors unless there is data conversion. In certain applications, the conversion may occur in real time by a video processor before sending the data signal to the LED display. The LED display may have its own video processor to simulate one or several standard color spaces or color gamuts according to the video technology being used. For example, an LED display capable of a relatively wide color gamut may be configured to display a narrower color gamut, such as the National Television Standards Committee (NTSC) color gamut for analog television based on a particular video source. Such a video processor needs to be fairly fast and powerful to do this in real time and therefore may be quite expensive. In certain embodiments, active electrical elements as previously described may be configured for digital signal processing by accepting input data from one color space or color gamut and converting this data to more accurately represent that color space or color gamut of the LED chip controlled by the active electrical element. Because the active electrical elements serve only a small number of sub-pixels (typically 3 for single-pixel RGB and 12 for 2x2 pixel RGB), the task of color space conversion is significantly simpler and does not require a high-speed processor to calculate the conversion for every pixel in the display.

[0127]

[0203] In certain embodiments, the active electrical elements are greater than three for each LED pixel. For example, the active electrical elements may be configured to control four LED chips in a four-point gamut. In such an example, the active electrical elements may be configured to receive three-color input data and convert it to more closely match the expected four-point gamut. In a further example, a controller for an LED display may send a command for green, and rather than simply turning on only the green LEDs, the active electrical elements may calculate a combination of drive signals to the LED chips to match the shade of green expected by the source data in their respective color spaces. Thus, the active electrical elements may convert a green input signal into drive signals for all three or more LED chips in an LED pixel (e.g., a substantially higher green LED emission combined with smaller amounts of blue and red LED emission). In certain embodiments, the active electrical elements capable of digital signal processing may include one or more ASICs comprising one or more of an arithmetic logic unit, a microcontroller, an execution controller, and a digital signal processor.

[0128]

[0204] The embodiments as disclosed herein may include a plurality of LED chips forming a pixel. 2A-6 having a plurality of LED chips, as well as LED package 74 of FIG. 7 and / or LED package 108 of FIG. 12B including multiple groups of LED chips forming multiple pixels. The embodiments as described herein may also be applicable to all-in-one multi-pixel displays including multiple LED chips formed in pixel groups formed on a common board including either common active electrical elements such as an ASIC or multiple separate ASICs. Such all-in-one multi-pixel displays may include one or more of chip-on-glass (COG), chip-on-board (COB), package-on-package (POP), package-on-board (POB), or PCB assemblies. In this regard, any of the active electrical element configurations, associated component configurations, and associated system-level configurations as described in FIGS. 8-12A and 14-51B may be applicable to both LED packages and LED display systems.

[0129]

[0205] In the previously described embodiment, the LED pixels in the display each Each LED pixel may be configured to update its operational state when it receives a specific command to do so. The commands for each LED pixel may be received at different times, and therefore the operational state of each individual LED pixel may be updated at different times based on the frame rate and the placement of the individual LED pixel in the string. In this way, synchronization across all LED pixels in a display can be difficult because each LED pixel may be operating according to its own clock out of sync with the other LED pixels. While this is not a problem for general-purpose applications where the frame rate is higher than the human eye can perceive, some applications utilizing equipment operating at higher rates may require synchronization. For example, advanced displays utilizing three-dimensional (3D) shutter glasses may require even frames for one eye and odd frames for the other eye, with dark periods built in between frames to allow the shutter times to switch. In such applications, all pixels must transition on and off together.

[0130]

[0206] According to embodiments disclosed herein, an LED pixel in an LED display Synchronization is provided so that all LED pixels can be turned off simultaneously to provide a coordinated black screen and / or so that all LED pixels can be turned on at coordinated times to provide a particular image or video. Synchronization may also include coordinating other states of the LED pixels beyond turning them on and off, such as holding all LED pixels at a particular color and / or brightness for a period of time or progressing through multiple operating states in a coordinated manner. LED displays and corresponding systems may include a central or master controller configured to send communication signals to multiple sub-controllers, each of which is responsible for sending communication signals to one or more strings of LED pixels. Additionally, active electrical elements within each LED pixel (e.g., an LED package as previously described) may be configured to receive the communication signals, generate a corresponding synchronization signal, and respond in a coordinated manner with all LED pixels in the display.

[0131]

[0207] FIG. 52 shows a system for an LED display panel according to the synchronization principles of the present disclosure. 52 is a block schematic diagram 182 illustrating a system-level control scheme. A sub-controller 190 is arranged to control one or more LED strings 192 of a plurality of LED pixels 194. The sub-controller 190 in FIG. 52 may employ a control element 18 as previously described. As such, the sub-controller 190 may comprise an integrated circuit such as one or more of an ASIC, a microcontroller, a programmable control element, and an FPGA. In FIG. 52, an exemplary LED string 192 is indicated by a dashed box in the block diagram. Only the LED string 192 is provided in detail. 52, each LED pixel 194 is provided with a label, such as "Px1,1," where the first number represents the row and the second number represents the column. Each active electrical element 30 is registered and housed within a specific one of the LED pixels 194, such that each LED pixel 194 can include logic for responding to received data signals, as described in detail above. Each LED pixel 194 may embody an LED package 26, including one or more LED chips and active electrical elements, as previously described. The subcontroller 190 may be configured to receive one or more signals from a system-level master controller 196 of a larger display. The master controller 196 may be configured to receive one or more signals provided by the receiver 198. In particular applications, the receiver 198 may embody an HDMI / DVI digital receiver configured to receive an HDMI input signal 200. In this manner, the one or more signals from the receiver 198 to the master controller 196 may include one or more color signals (e.g., RED, BLUE, GREEN) as well as various clock signals (e.g., HSYNC, VSYNC, and PIXCLK). For reference, HSYNC refers to the horizontal clock signal corresponding to the line raster, VSYNC refers to the vertical clock signal corresponding to the frame pulse, and PIXCLK refers to the pixel clock. The one or more signals described above are processed by the master controller 196 and routed to one or more of the sub-controllers 190 based on the particular application.For example, multiple ones of the sub-controllers 190 and corresponding LED strings 192 may be combined to form a larger display. In certain embodiments, such as smaller displays, the master controller 196 may not be required. As illustrated, the sub-controllers 190 may also be configured to receive signals from one or more of the microcontrollers and memories 202.

[0132]

[0208] The active electrical element 30 of each LED pixel 194 is associated with each LED pixel 194. The sub-controller 190 may include a processing unit, such as a central processing unit, microprocessor, or even a state machine, that contributes to controlling the logic for controlling the operating states of the LED chips. During serial communication, commands for each LED pixel 194 may be received at different times, and therefore, the operating states of the individual LED pixels 194 and corresponding LED chips may be updated at different times according to the provided frame rate. In accordance with the principles of the present disclosure, each active electrical element 30 may be further configured to synchronize the actions and / or operating states within its corresponding LED pixel 194 with the actions and / or operating states of other LED pixels 194 in which other active electrical elements 30 reside. During a first step, such as startup and / or calibration, the sub-controller 190 may be configured to send different delay parameters to each LED pixel 194 based on the relative location of each LED pixel 194 and when the respective commands should be sent within each frame. These delay parameters may be based on information processed and stored by the memory 202. In this manner, each active electrical element 30 of each LED pixel 194 may be loaded with a delay parameter to help determine when to activate a desired response, such as turning on or off. Because the internal clock frequencies of different LED pixels 194 may be very different, such delay commands alone may be insufficient to achieve suitable synchronization. As such, timing signals relative to a common clock provided by the sub-controller 190 may be utilized, although in clockless communication applications without a separate clock signal, the common clock may be used. may not be easily regenerated and made available at each LED pixel 194.

[0133]

[0209] In accordance with the principles of the present disclosure, each active electrical element 30 The active electrical element 30 of each LED pixel 194 may further include a synchronization counter register 203 configured to count all commands (intended and passed-through) since the last end-of-frame command. In certain embodiments, the synchronization counter register 203 may embody an up-counter that counts up to a set value and / or a down-counter that counts down to zero to generate a desired delay for other events to occur. Other events may include the processing unit of the active electrical element 30 changing the state of one or more of the LED chips in the LED pixel 194, such as turning them on, off, or providing a brightness level. A synchronization counter register 203 may be present in the active electrical element 30. In certain embodiments, a common clock from the sub-controller 190 may send commands at the same pulse interval, such as the same number of commands in each frame. In other embodiments, the sub-controller 190 may include additional commands in a particular frame. When this occurs, the sub-controller 190 may further provide compensation commands and / or conversion factors that allow each active electrical element 30 to compensate for different sized frames in the data stream.As such, the active electrical elements 30 may be configured to correlate a common clock from the sub-controller 190 to both periodic and aperiodic frames.

[0134]

[0210] The processing unit within each active electrical element 30 processes the data to take action. The value provided by the synchronization counter register 203 may be read according to a program, or an interrupt signal may be generated that forces the processing unit to switch to the intended routine when a desired value is reached. For example, the interrupt signal may trigger the processing unit to proceed to an interrupt routine, which then determines the next step or action, such as synchronously turning off all of the LED pixels 194. In certain applications, each LED pixel 194 may be synchronized to within 1 millisecond with other LED pixels 194 controlled by the same subcontroller 190, as well as with other LED pixels controlled by other subcontrollers that are all coupled to the display's master controller 196. By synchronizing each LED pixel 194 with its corresponding subcontroller 190, the subcontroller 190 and any master controller 196 for the subcontrollers 190 may thereby be configured to produce any synchronization effect on all of the LED pixels 194 in the display. In particular embodiments, an overflow register may be provided in the synchronization counter register 203 to allow the processing unit to know when an output is not valid and a counter interrupt event has occurred, such as the subcontroller 190 sending more data than has been counted since the last counter reset. While there are other ways by which the processing unit can know that the counter interrupt event is the first occurrence and not one that has been generated after the synchronization counter register 203 has rolled over back to the same value, the overflow register may be used to provide a more robust means of ensuring counter validity. .

[0135]

[0211] FIG. 53 illustrates a synchronization scheme for the sub-controller 190 of FIG. 52 in accordance with the synchronization principles of the present disclosure. 1 illustrates a general process flow 204. Upon power-up 206, the subcontroller 190 may initialize the LED pixels coupled to it by replicating one or more of calibration parameters, program parameters, and setup parameters from memory and transmitting such information to the LED pixels. In particular embodiments, the subcontroller 190 may initialize the LED pixels with location-specific counter start values ​​stored in registers internal to the active electrical elements 30. In this manner, each LED pixel may be provided with a different counter start value based on its specific location within the LED string. After power-up 206, the subcontroller 190 may then proceed to an execution mode 208 in which the subcontroller 190 transmits a data stream including a specific frame 210 for each LED string controlled by the subcontroller 190. The frame 210 for each LED string may include a sequential arrangement of data, including one or more input bits, bytes, commands, and / or any other data packets. This sequential arrangement may be provided such that the commands and / or data for individual LED pixels are arranged in an order of data packets corresponding to the order of the LED pixels within the LED string. In FIG. 53, this is represented as a Px1,1 command with a data packet, followed by a Px1,2 command with a data packet, etc., to correspond to the arrangement of LED pixels 194 in LED string 192 of FIG. 52. In this manner, the first LED pixel (Px1,1) may execute / receive the Px1,1 command / data packet from frame 210 and pass the executed command / data packet through along with all other command / data packets for the other LED pixels. As such, frame 210 provides a synchronization pulse to each of the LED pixels corresponding to the common clock of sub-controller 190. Frame 210 may further include an end-of-frame (EOF) command or other predefined command, such as a specific command to reset synchronization counter register 203, signaling the LED pixels to proceed to the next frame. The EOF command may also be considered the start of a frame.For synchronization purposes, this may be a better interpretation of whether the EOF command is to be used as the command used to reset (e.g., clear, load, or preset) the synchronization counter register 203. In some embodiments, the EOF command may have a dual purpose: to signal the active electrical element 30 to execute the next non-executing command and to restart the synchronization counter register 203.

[0136]

[0212] FIG. 54 shows the activation of each LED pixel connected to the sub-controller 190 of FIG. FIG. 54 is a schematic process flow 212 for an exemplary process for counter logic within an active electrical element 30. As described above in FIG. 53, the sub-controller 190 may initialize the LED pixels with location-specific counter start values ​​upon power-up 206. As described below, each location-specific counter start value is then used to evaluate each command / data pulse within each active electrical element 30 and determine response timing in coordination with the other active electrical elements 30 in the LED string. As illustrated in FIG. 54, in a first step 214 after power-up 206, an EOF command received by the active electrical element 30 signals advancement to the next frame. In this regard, the EOF command signals the active electrical element 30 to respond to another command. In a second step 216, a first value corresponding to the location-specific counter start value is provided to a synchronous counter register (e.g., 203 of FIG. 52), such as a down counter as illustrated in FIG. 54. As previously described, the active electrical element 30 is configured to generate a patterned pulse synchronization signal 218 based on a pattern in the data stream. In certain embodiments, the synchronization signal 218 is The active electrical element 30 receives a synchronization signal 218 from a serial interface 220 within the active electrical element 30. In a third step 222, the active electrical element 30 receives a synchronization signal 218, and a synchronization counter register (e.g., 203 in FIG. 52) begins a countdown sequence from a counter start value. When the synchronization counter register reaches zero in a fourth step 224, the active electrical element may send an interrupt signal in a fifth step 226. The interrupt signal may trigger a processing unit of the active electrical element 30 to initiate an interrupt routine that causes the LED chip in the LED pixel to take action, such as turning on and / or off synchronously with other LED pixels in the display based on their respective countdown sequences. In certain embodiments, the synchronization routine may require two or more interrupt signals, such as turning the LED off with a first interrupt and turning the LED back on with a subsequent interrupt. In this manner, the active electrical element 30 may then determine whether the previous interrupt signal of the fifth step 226 was the last event, as illustrated in a sixth step 228. If it is not the last event, the process repeats back to the second step 216, where the down counter (synchronization counter register 203) begins counting down from a second location-specific counter start value corresponding to when the active electrical element 30 should proceed to the fifth step 226 and send another interrupt signal. In various embodiments, this process may be repeated any number of times based on the amount of location-specific counter start values ​​provided in start 206. As an example, in a 3D LED display application where the viewer wears 3D shutter glasses, a first interrupt signal may turn all LEDs off, and a second interrupt signal may turn all LEDs back on, effectively creating an all-off time frame within each frame of serial communication that allows the LED shutter glasses to transition from one viewing condition to another, such as from one eye to the other. When the interrupt signal is the last event, the process may return to the beginning at the first step 214.At any time during any of the steps as illustrated in Figure 54, an end of frame signal 230 may cause the process to return to the first step 214, regardless of whether the process flow 212 has finished. The process flow 212 of Figure 54 may operate in parallel with other processes previously described within the active electrical element 30, such as the execution of other programs executed by the processing unit along with some other state machines of the active electrical element 30.

[0137]

[0213] FIG. 55 is an exemplary diagram of the processing unit 242 in the active electrical element 30 of FIG. 54 is a schematic process flow 240 for such a process. The processing unit 242 may include a central processing unit, microprocessor, or even a state machine that contributes to controlling the logic for controlling the operating state of the LED chip associated with each LED pixel. Under normal operation, one or more main program routines 244 may be executed by the processing unit 242. The main program routine 244 may include an initialization routine and executing one or more main programs in an endless loop as described for any of the previous embodiments. Upon receiving an interrupt signal (e.g., step 226 of FIG. 54 ), the processing unit 242 may exit the main program routine 244 and initiate one or more interrupt service routines 246. The interrupt service routines 246 may include polling the source of the interrupt to determine what caused the interrupt and select an appropriate response. For example, the first interrupt signal received may indicate that the LED should be turned off, and the next interrupt signal received may indicate that the LED should be turned back on. The various types of interrupt responses are generally designated as #1-#4 in the process flow 240, indicating that many more interrupt responses are possible beyond simply turning an LED on and off. Some other interrupt responses may include setting a value as a signal to the main program routine 244. In fact, other interrupt responses may be programmable to suit a particular application. Once the intended interrupt response has been determined and executed, process flow returns to the main program routine 244 until the next interrupt signal is initiated. As disclosed herein, an interrupt signal may also be triggered if the active electrical element 30 detects a communication error in the data stream or within the active electrical element. In certain embodiments, the main processing unit controls the LED pixels via PWM drivers as described in the previous embodiments. In events such as those described above, where the LEDs are turned on and off at different times relative to commands that set frame color and intensity, it may be necessary to suspend the PWM through a dark period rather than continuing the PWM counter and turning off the LEDs. In this way, the processing unit may have the ability to not only set the LED (e.g., RGB) intensity, but also suspend the PWM count and resume it after the dark period has ended, thereby resuming the PWM signal at a specific point within the PWM period and duty cycle where the PWM count was suspended.

[0138]

[0214] In certain embodiments of the present disclosure, mitigation of LED pixel failures within an LED string includes: The data stream may be provided by a controller or sub-controller configured with a bidirectional communication port for the LED string. Under normal operation, a first communication port may be configured to provide a data stream out of the controller and into a first end of the LED string, and a second bidirectional communication port may be configured to receive a data stream back from the opposite end of the LED string. When an LED pixel fails within the LED string, the data stream cannot return to the controller. If this occurs, the controller may modify the second bidirectional communication port to also provide a data stream out of the controller and into a second end of the LED string so that LED pixels on either side of the failed LED pixel can still receive data from the data stream. In certain embodiments, the data stream provided by the second bidirectional communication port during an LED pixel failure may be reversed to compensate for the reverse ordering of the LED pixels.

[0139]

[0215] FIG. 56 is a schematic diagram of a system for an LED display panel in accordance with the failure mitigation principles of the present disclosure. 52 , and further includes fault mitigation capabilities as described below. To provide fault mitigation, LED string 192 is coupled to sub-controller 190 at two bidirectional communication ports (DOUT / IN and DIN / OUT). Under normal operation, the sub-controller sends a data stream out the DOUT / IN port and into a first end of LED string 192 at LED pixel Px1,1. The data stream then travels through LED string 192 and a second end of LED string 192 at LED pixel Pxm,1 into the DIN / OUT port of sub-controller 190. Under certain failure modes, the failed LED pixel (shown as 194′ in FIG. 56 ) may no longer respond to the data stream and may be unable to pass the data stream along the LED string 192, thereby preventing LED pixels 194 downstream of the failed LED pixel 194′ from receiving the data stream. The failed LED pixel 194′ may be caused by one or more of a loss of power, an open circuit, and an electrical short, among other failure mechanisms. In FIG. 56 , when the sub-controller 190 stops receiving the returning data stream at the DIN / OUT port, the sub-controller 190 may enter a failure mitigation mode by reconfiguring the DIN / OUT port to provide the data stream to the LED string 192 at its second end near LED pixel Pxm,1. In this manner, the data stream from the reversed DIN / OUT port may be provided back from LED pixel Pxm,1 to LED pixel Px2,3. That is, the data stream provided from the reversed DIN / OUT port in the fault mitigation mode may be arranged inversely to the data stream provided from the DOUT / IN port. Thus, each operational LED pixel 194 may receive its intended portion of the data stream, and only the failed LED pixel 194' is inoperable. In particular embodiments, all communication ports for all LED strings coupled to the sub-controller 190 may be bidirectional communication ports.

[0140]

[0216] In certain embodiments, the sub-controller 190 detects the failed LED pixel 19. It may be useful to identify the location of 4'. When the fault mitigation mode is initiated, the sub-controller 190 may be configured to send a polling command or communication from the DOUT / IN port along the LED string 192. As previously described, each LED pixel 194 in the LED string 192 may also be configured with a bidirectional communication port. During the polling communication, each functioning LED pixel 194 (e.g., Px1,1) receives the polling communication, retransmits the polling communication to the next LED pixel 194 (e.g., Px1,2), reverses the communication direction of the bidirectional port within the LED pixel 194 (e.g., Px1,1), and then returns the polling communication to the sub-controller 190 with a return polling communication, such as a ping, pulse, or data, in the opposite direction to the normal data stream. Because the bidirectional port of the first LED pixel (e.g., Px1,1) is reversed, pings or other return data from each of the downstream LED pixels (e.g., Px1,2 through Px2,1) may be retransmitted through the LED pixel (Px1,1) to the sub-controller 190. The sub-controller 190 may count the received pings or data to determine how many LED pixels 194 were functioning before the first failure on the LED string 192. Other information may be obtained as well. In particular embodiments, the LED pixels 194 receiving the polling communication may responsively provide skip commands to bypass one or more LED pixels 194 in either direction of the data stream. When the polling procedure ends, the bidirectional communication ports of both the sub-controller 190 and the LED pixels 194 may return to their normal communication direction. Alternatively, the bidirectional communication ports may be set to an initial power-up state in which both bidirectional communication ports are set to input, thus allowing the communication direction to be redefined. This polling procedure may also be performed from the DIN / OUT port to determine if there is a single LED pixel failure or multiple LED pixel failure.When multiple LED pixel failures exist, a polling command from each of the bidirectional communication ports may identify only the first and last failed LED pixel of the LED string 192, without providing further information about the intervening LED pixels 194. In certain embodiments, data line taps, as described below, may be placed on one or more portions of the LED string 192 to further refine the failed LED pixel location when there are multiple failures.

[0141]

[0217] FIG. 57 shows how a data line tap can be connected to one or more LED displays 250. FIG. 57 is a top layout diagram of a portion of an LED display 250 for an embodiment provided along LED strings 192-1 through 192-3. For illustrative purposes, three LED strings 192-1 through 192-3 are depicted along the LED display 250, with corresponding communication ports (A through I) of the sub-controller 190 shown to the right of the LED display 250. For LED string 192-1, port A represents the data stream transmitted out from the sub-controller 190, and port B represents the data stream received back to the sub-controller 190 after passing through LED string 192-1. Similarly, ports C and D correspond to LED string 192-2, and ports E and F correspond to LED string 192-3. Ports G, H, and I correspond to data line taps (TAP1 through TAP3) that may be connected to different ones of the LED strings (e.g., 192-1 and 192-2 in FIG. 57). In certain embodiments, the data line taps (TAP1-TAP3) are not coupled to specific ones of the LED pixels 194 like the typical DIN and DOUT communication ports (A-F), but are instead The data line taps (TAP1-TAP3) are coupled between adjacent ones of the LED pixels 194. As illustrated, LED string 192-1 is configured with two data line taps (TAP1 and TAP2), while LED string 192-2 is configured with a single data line tap (TAP3). In practice, any number of data line taps may be connected to any number of LED strings, such as at least one data line tap for each LED string in LED display 250. In other embodiments, only a portion of the LED strings in LED display 250 may include data line taps, as illustrated in FIG. 57. In normal operation, the data line taps (TAP1-TAP3) may be set to high impedance values ​​so that they are normally off or unused. In the event of an LED pixel 194 failure that initiates a fault mitigation procedure, one or more of the data line taps (TAP1-TAP3) may be used to access the LED pixel 194 between the faults and / or to receive data from portions of the LED string that are functioning correctly. As an example, a fault mitigation procedure for LED string 192-2 may perform a polling sequence such as that described with respect to FIG. 56 for ports C and D. If the polling data indicates that tap I (e.g., TAP3) is between two faults, TAP3 is turned on, and appropriate data is sent via TAP3 to the LED pixel 194 between the two faults. As further illustrated in FIG. 57, another fault mitigation method may be to design the placement of LED strings 192-1 through 192-3 on a substrate, such as a PCB board, so that the LED pixels 194 along the outer periphery of the substrate are closer to the ends of the LED strings. During handling and assembly, the LED pixels 194 along the outer periphery may be more susceptible to mechanical damage and failure. By placing these LED pixels 194 toward the ends of LED strings 192-1 through 192-3, the data stream may reach more operational LED pixels in each of LED strings 192-1 through 192-3 under normal operation before reaching the failed LED pixel 194.Additionally, a higher concentration of failed LED pixels 194 along the edges may have a less disruptive effect on the overall appearance of the LED display 250 than in the center of the LED display 250. In certain embodiments, at least five, or at least ten, or in the range of 5 to 10, or in the range of 10 to 50, or in the range of 10 to 100, of the last series-connected LED pixels 194 in one of the LED strings 192-1 to 192-3 are located along the perimeter of the LED display 250. Stated differently, at least half of the LED pixels 194 of the LED display 250 located along the perimeter edge of the LED display 250 may actually be within the last 25% of their respective LED strings 192-1 to 192-3. Additionally, most or all of the data line taps (TAP1 to TAP3) may be located along the perimeter of the LED display 250 to provide easier connections to the LED strings 192-1 to 192-3.

[0142]

[0218] In certain embodiments, any of the preceding aspects and / or the methods described herein Various separate aspects and features as described herein may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein.

[0143]

[0219] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. 1. A method for controlling a light emitting diode (LED) display, comprising: providing a first LED string comprising a plurality of first LED pixels, each first LED pixel of the plurality of first LED pixels comprising at least one LED chip and an active electrical element; loading a different first counter value into the active electrical element of each first LED pixel based on an address of each first LED pixel in the first LED string; and controlling the first LED string by synchronizing an operating state of each first LED pixel of the first LED string and individually turning on or off each first LED pixel based on the different first counter values.

2. The method of claim 1 , wherein the reading of the different counter values ​​is performed by a controller connected to the first LED string.

3. providing a second LED string comprising a plurality of second LED pixels, each second LED pixel of the plurality of second LED pixels comprising at least one LED chip and an active electrical element; loading a different second counter value into the active electrical element of each second LED pixel based on an address of each second LED pixel in the second LED string; The method of claim 1 , further comprising: synchronizing operational states of the plurality of first LED pixels and the plurality of second LED pixels based on the first and second counter values.

4. 4. The method of claim 3, wherein synchronizing the operational states of the plurality of first LED pixels and the plurality of second LED pixels comprises turning the plurality of first LED pixels and the plurality of second LED pixels on or off.

5. The method of claim 1 , wherein synchronizing the operating state of each first LED pixel provides a time frame during which the plurality of first LED pixels are all turned off.

6. 6. The method of claim 5, wherein the LED display is a three-dimensional (3D) LED display requiring 3D shutter glasses for a viewer, and the time frames are determined to allow the 3D shutter glasses to transition from one viewing condition to another while the plurality of first LED pixels are off.

7. 2. The method of claim 1, wherein synchronizing the operational state of each first LED pixel of the first LED string comprises maintaining at least one of a color and brightness state of each first LED pixel of the first LED string for a period of time.

Images