MEMORY INCLUDING MULTIPLE PORTIONS AND USED TO REDUCE PROGRAM DISTURBANCE, AND METHOD FOR PROGRAMMING THE SAME - Patent application

Abstract

To provide a memory and a program method for reducing program disturbance and pass voltage disturbance when operating a three-dimensional memory.SOLUTION: A memory 100 includes a first portion 110, a second portion 120 and a controller 190. The first portion includes a first word line to the k-th word line. The second portion is formed above the first portion and includes the (k+1)th word line to the m-th word line. When the x-th word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to the (x-2)th word line, a second voltage to the (x-1)th word line, and a third voltage to the (x+1)th word line. x, k and m are positive integers.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a memory and a programming method, and more particularly to a memory that includes multiple portions and is used to reduce program disturbance, and a programming method thereof. [Background technology]

[0002] To increase memory capacity, three-dimensional structures of memory have been developed, for example, three-dimensional stacked NAND flash memory is currently available.

[0003] The three-dimensional structure of memory can contain multiple layers to store more data in the same area, which has proven effective in increasing memory capacity.

[0004] However, increasing the number of layers makes program disturb more pronounced. Program disturb increases the programming failure rate of the memory. Also, passing voltage disturb occurs when using multiple layers of memory. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, there is a need in the art for a solution to reduce program disturb and pass voltage disturb when operating 3D memories. [Means for solving the problem]

[0006] One embodiment provides a memory including a first portion, a second portion, and a controller. The first portion includes, from bottom to top, a first word line to a kth word line. The second portion is formed on the first portion and includes, from bottom to top, a (k+1)th word line to an mth word line. When the xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to the (x-2)th word line, a second voltage to the (x-1)th word line, and a third voltage to the (x+1)th word line. x, k, and m are positive integers.

[0007] One embodiment provides a memory including a first portion, a second portion, and a controller. The first portion includes, from bottom to top, the (m+1)th word line to the nth word line. The second portion is formed below the first portion and includes, from bottom to top, the (k+1)th word line to the mth word line. When the xth word line is used to perform a program operation, the controller is used to apply a first voltage to the (x+2)th word line to the nth word line, a second voltage to the (x+1)th word line, a third voltage to the (x-1)th word line, a fourth voltage to the (m+1)th word line to the (x-2)th word line, and a fifth voltage to the (k+1)th word line to the mth word line. x, k, and m are integers. The fifth voltage is lower than the fourth voltage.

[0008] One embodiment provides a program method used to operate a memory. The memory includes a first portion and a second portion. The first portion includes, from bottom to top, a first word line through a kth word line. The second portion is formed on the first portion and includes, from bottom to top, a (k+1)th word line through an mth word line. When an xth word line is used to perform a program operation, the program method includes applying a first voltage to the first word line through an (x-2)th word line, applying a second voltage to the (x-1)th word line, and applying a third voltage to the (x+1)th word line.

[0009] One embodiment provides a programming method for operating a memory. The memory includes a first portion and a second portion formed below the first portion. The first portion includes, from bottom to top, the (m+1)th word line through the nth word line. The second portion includes, from bottom to top, the (k+1)th word line through the mth word line. When the xth word line is used to perform a programming operation, the programming method includes applying a first voltage to the (x+2)th word line through the nth word line, applying a second voltage to the (x+1)th word line, applying a third voltage to the (x-1)th word line, applying a fourth voltage to the (m+1)th word line through the (x-2)th word line, and applying a fifth voltage to the (k+1)th word line through the mth word line. x, k, and m are integers. The fifth voltage is lower than the fourth voltage.

[0010] These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. [Brief explanation of the drawings]

[0011] [Figure 1]FIG. 2 illustrates a memory according to one embodiment. [Figure 2] 2 illustrates the memory of FIG. 1 operating under different conditions. [Figure 3] FIG. 10 illustrates a memory according to another embodiment. [Figure 4] 4A and 4B illustrate the memory of FIG. 3 operating under different conditions. [Figure 5] 4A and 4B illustrate the memory of FIG. 3 operating under different conditions. [Figure 6] FIG. 10 illustrates a memory according to another embodiment. [Figure 7] FIG. 10 illustrates a memory according to another embodiment. [Figure 8] 8 illustrates the memory of FIG. 7 operating under different conditions. [Figure 9] FIG. 10 illustrates a memory according to another embodiment. [Figure 10] 10 illustrates the memory of FIG. 9 operating under different conditions. [Figure 11] FIG. 10 illustrates a memory according to another embodiment. [Figure 12] FIG. 1 illustrates a flowchart of a programming method according to one embodiment. [Figure 13] FIG. 10 shows a flowchart of a programming method according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] 1 illustrates a memory 100 according to one embodiment. The memory 100 may include a first portion 110, a second portion 120, and a controller 190. The first portion 110 may include, from bottom to top, a first word line WL1 through a kth word line WLk. The second portion 120 may be formed on the first portion 110 and may include, from bottom to top, a (k+1)th word line WL(k+1) through an mth word line WLm.

[0013] In this context, when a word line is said to be programmed, it may mean that the word line is used to perform a program operation. The program operation referred to in this context may be, for example, an operation to program a memory cell formed using a set of transistors.

[0014] When the xth word line WLx is used to perform a program operation, the controller 190 may apply a program voltage Vpgm to the xth word line WLx, the controller 190 may apply a first voltage V1 to the first word line WL1 to the (x-2)th word line WL(x-2), the controller 190 may apply a second voltage V2 to the (x-1)th word line WL(x-1), and the controller 190 may apply a third voltage V3 to the (x+1)th word line WL(x+1). x, k, and m are positive integers, and 1 <k<mであり、3≦xである。

[0015] As shown in FIG. 1, the controller 190 may apply a fourth voltage V4 from the (x+2)th word line WL(x+2) to the mth word line WLm when the xth word line WLx is used to perform a program operation, and x <m-1である。

[0016] 1, for example, the x-th word line WLx is disposed in the first portion 110. However, the x-th word line WLx may be disposed in the second portion 120 under other conditions.

[0017] 2 shows the memory 100 of FIG. 1 operating under another condition, in which the xth word line WLx is located in the second portion 120. In terms of applied voltages, FIG. 2 may be similar to FIG. 1, which will not be repeated.

[0018] 1 and 2 are merely examples, and each of the above word lines WL(x-2), WL(x-1), WL(x+1), and WL(x+2) can be located in the first portion 110 or the second portion 120.

[0019] With respect to memory 100, the first voltage V1 may have a first level when the xth word line WLx is in the first portion 110 and may have a second level when the xth word line WLx is in the second portion 120, and the first level may be lower than the second level. For example, the first voltage V1 in FIG. 1 may have a lower value than the first voltage V1 in FIG. 2.

[0020] 3 illustrates a memory 300 according to another embodiment. As with memories 100 and 300, memory 300 may include a third portion 130 in addition to first portion 110 and second portion 120.

[0021] The third portion 130 may be formed on the second portion 120 and may include, from bottom to top, the (m+1)th word line WL(m+1) to the nth word line WLn. As shown in FIG. 3, the controller 190 may apply a fourth voltage V4 from the (x+2)th word line WL(x+2) to the nth word line WLn when the xth word line WLx is used to perform a program operation. <nであり、x<(n-1)である。

[0022] 4 and 5 show the memory 300 of FIG. 3 operating under other conditions. In FIG. 3, the xth word line WLx used to perform a program operation is in the first portion 110. In FIG. 4 and 5, the xth word line WLx is in the second portion 120 and the third portion 130, respectively.

[0023] 3 to 5 are merely examples, and each of the above word lines WL(x-2), WL(x-1), WL(x+1), and WL(x+2) can be located in the first portion 110, the second portion 120, or the third portion 130.

[0024] With respect to memory 300, the first voltage V1 may have a first level when the xth word line WLx is in the first portion 110, a second level when the xth word line WLx is in the second portion 120, and a third level when the xth word line WLx is in the third portion 130, where the first level may be lower than the second level and the second level may be lower than the third level. For example, the first voltage V1 in FIG. 3 may have a lower value than the first voltage V1 in FIG. 4, which may have a lower value than the first voltage V1 in FIG. 5.

[0025] FIG. 6 illustrates a memory 600 according to another embodiment. The memory 600 may be similar to the memory 100 of FIGS. 1 and 2. However, the structures of FIGS. 1 and 2 may include only one deck, while the memory 600 may have a two-deck structure. In other words, the memory 100 may have a one-deck structure, and the memory 600 may have a two-deck structure. As shown in FIG. 6, the first portion 110 is for deck DECK1, and the second portion 120 is for deck DECK2. The two decks DECK1 and DECK2 may be separated by a junction oxide layer OL. The memory 600 may include a lower dummy word line DL, an upper dummy word line DU, and a junction oxide layer OL. The lower dummy word line DL may be formed on the first portion 110. The upper dummy word line DU may be formed below the second portion 120. The junction oxide layer OL may be formed between the lower dummy word line DL and the upper dummy word line DU. The voltages applied to the one-deck structure may be like the voltages applied to the two-deck structure according to the embodiment. For example, the voltages applied to the word lines of memory 600 may be like the voltages applied to the word lines of memory 100 of Figures 1 and 2, and are not repeatedly described.

[0026] Figures 7 and 8 show a memory 700 operating under two conditions according to another embodiment. The memory 700 may include a first portion 710, a second portion 720, and a controller 190. The first portion 710 may include, from bottom to top, the (m + 1)-th word line WL(m + 1) to the n-th word line WLn. The second portion 720 may be formed under the first portion 710 and include, from bottom to top, the (k + 1)-th word line WL(k + 1) to the m-th word line WLm.

[0027] When the x-th word line is used to execute a program operation, the controller 190 may apply a first voltage V71 to the (x + 2)-th word line WL(x + 2) to the n-th word line WLn, the controller 190 may apply a second voltage V72 to the (x + 1)-th word line WL(x + 1), and the controller 190 may apply a third voltage V73 to the (x - 1)-th word line WL(x - 1).

[0028] As shown in FIG. 7, when the word line WLx is disposed in the second portion 720 and the x-th word line is used to execute a program operation, the controller 190 may apply a fifth voltage V75 to the (k + 1)-th word line WL(k + 1) to the (x - 2)-th word line WL(x - 2). In FIG. 7, x, k, and m are integers and (k + 2) < x < (m + 1). The state of FIG. 7 may be substantially the same as the state of FIG. 1. However, FIG. 7 is provided to introduce FIGS. 8 to 11.

[0029] As shown in FIG. 8, when the word line WLx used to execute the program operation is disposed in the first portion 710, the first voltage V71, the second voltage V72, and the third voltage V73 can be applied by the controller 190 as shown in FIG. 7. However, the controller 190 can apply the fourth voltage V74 from the (m + 1)-th word line WL(m + 1) to the (x - 2)-th word line WL(x - 2). The controller 190 can apply the fifth voltage V75 from the (k + 1)-th word line WL(k + 1) to the m-th word line WLm. In FIG. 8, x, k, and m are integers, 0 ≦ k < m, and (m + 2) < x < (n - 1). The fifth voltage V75 can be lower than the fourth voltage V74.

[0030] According to another embodiment, as shown in FIG. 6, the first portion 710 and the second portion 720 shown in FIGS. 7 and 8 can each be of two decks, and the two decks can be separated by a bonding oxide layer. As shown in FIG. 6, the two decks can each have an upper dummy word line and a lower dummy word line.

[0031] FIG. 9 shows a memory 900 according to another embodiment. FIG. 10 shows the memory 900 of FIG. 9 operating under another condition.

[0032] As shown in FIG. 9, the memory 900 can have three portions 910, 920, and 930. The first portion 910 and the second portion 920 can be similar to the portions 710 and 720 shown in FIG. 7. The third portion 930 can be formed on the first portion 910 and includes a plurality of word lines WL(n + 1) to WLq from bottom to top. The condition of FIG. 9 can be similar to FIG. 7 where the word line WLx used to execute the program operation is disposed in the lowermost 920. The controller 190 can apply the first voltage V71 to the plurality of word lines WL(n + 1) to WLq in FIG. 9. The variable q is an integer and q > (n + 1).

[0033] The memory 900 in FIG. 10 may have the same structure as that shown in FIG. 9. The conditions in FIG. 10 may be similar to FIG. 8 where the word line WLx used to execute the program operation is arranged in the upper part 910 above the bottom 920. The voltages applied to the parts 910 and 920 may be similar to the voltages applied to the parts 710 and 720 in FIG. 8. As shown in FIG. 9, the controller 190 may apply a first voltage V71 to a plurality of word lines WL(n + 1) to WLq in the part 930.

[0034] FIG. 11 shows a memory 1100 according to another embodiment. The first part 1110 and the second part 1120 of the memory 1100 may be similar to the parts 710 and 720 in FIG. 8, and the memory 1100 may further include a third part 1130 formed under the second part 1120. Similarly, the x-th word line WLx may be used to execute the program operation. Thus, the memory 1100 may include three parts and may have a structure similar to the memory 900 in FIGS. 9 and 10. As shown in FIG. 11, the third part 1130 may include the first word line WL1 to the k-th word line WLk from bottom to top. The controller 190 may apply a sixth voltage V76 to the first word line WL1 to the k-th word line WLk. 0 < k, and the sixth voltage V76 is lower than the fifth voltage V75.

[0035] Although the numbering of the parts and word lines is not the same, the memories 900 and 1100 shown in FIGS. 9 to 11 may be regarded as the same memory operating under different conditions.

[0036] In FIG. 9, the word line (e.g., WLx) used to execute the program operation is arranged at the bottom of the three parts.

[0037] In FIG. 10, the word line (e.g., WLx) used to execute the program operation is arranged in the second lowest part of the three parts.

[0038] In FIG. 11, the word line (e.g., WLx) used to execute the program operation is arranged at the top of three parts.

[0039] As shown in FIGS. 9 to 11, when the word line WLx used to execute the program operation is arranged in different parts, different voltages can be applied to the word lines below the word line WLx according to the corresponding parts.

[0040] In the examples of FIGS. 9 to 11, the relationship between the voltages may be V76 < V75 < V74. In other words, the same voltage can be applied to the word lines of the same part arranged below the part corresponding to the word line (e.g., WLx) used to execute the program operation, and a lower voltage can be applied to the word lines of the part arranged at a lower position.

[0041] FIG. 12 shows a flowchart of a program method 1200 according to an embodiment. The program method 1200 can be used to operate the memories 100 of FIGS. 1 and 2 and the memories 300 of FIGS. 3 to 5. The method 1200 may include the following steps. Step 1210: When the x-th word line WLx is used to execute the program operation, the program method applies the first voltage V1 to the first word line WL1 to the (x - 2)-th word line WL(x - 2). Step 1220: Apply the second voltage V2 to the (x - 1)-th word line WL(x - 1). Step 1230: Apply the third voltage V3 to the (x + 1)-th word line WL(x + 1).

[0042] Steps 1210 to 1230 may be performed when the xth word line WLx is used to perform a program operation. Furthermore, when the xth word line WLx is used to perform a program operation, the fourth voltage V4 may be applied as shown in Figures 1 to 5 and as described above. The relationships between the voltages shown in Figures 1 to 5 (e.g., V1, V2, V3, and V4) may be as described above.

[0043] Figure 13 shows a flowchart of a programming method 1300 according to one embodiment. The programming method 1300 may be used to operate the memory 700 of Figure 8, the memory 900 of Figures 9 and 10, and the memory 1100 of Figure 11. The method 1300 may include the following steps. Step 1310: if the xth word line WLx is used to perform a program operation, apply a first voltage V71 from the (x+2)th word line WL(x+2) to the nth word line WLn; Step 1320: Apply a second voltage V72 to the (x+1)th word line WL(x+1); Step 1330: Apply a third voltage V73 to the (x-1)th word line WL(x-1); Step 1340: Applying a fourth voltage V74 from the (m+1)th word line WL(m+1) to the (x-2)th word line WL(x-2); Step 1350: Apply the fifth voltage V75 to the (k+1)th word line WL(k+1) to the mth word line WLm.

[0044] Steps 1310 to 1350 may be performed when the xth word line WLx is used to perform a program operation. Furthermore, when the xth word line WLx is used to perform a program operation, the sixth voltage V76 may be applied as shown in FIG. 11 and as described above. The relationships between the voltages shown in FIGS. 7 to 11 (e.g., V71, V72, V73, V74, V75, and V76) may be as described above.

[0045] In summary, by using a memory that is partitioned to have multiple parts and applying voltages to the word lines of the memory according to the parts, according to simulation and experiment, program disturb and pass voltage disturb can be reduced.Furthermore, by using the same voltage source to apply voltages to the word lines of the same part or the word lines of different parts, fewer voltage sources are required, and the area of ​​the system can be reduced.Therefore, the problems in the art can be reduced.

[0046] Those skilled in the art will readily observe that numerous modifications and variations of the devices and methods may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. [Explanation of symbols]

[0047] 100 memory 110 First Part 120 Second Part 130 Third Part 190 Controller 300 memory 600 memory 700 memory 710 First Part 720 Second Part 900 memory 910 First Part 920 Second Part 1100 memory 1110 First Part 1120 Second Part 1130 Third Part 1200 Programming Method 1300 Programming Method

Claims

1. a first deck having a first set of word lines; a second deck below the first deck and including a second set of word lines; coupled to the first deck and the second deck; applying a program voltage to a first word line of the first set of word lines; applying a first passing voltage to a second word line of the second set of word lines while applying the program voltage to the first word line; applying a second passing voltage to a third word line of the first set of word lines while applying the program voltage to the first word line, the third word line being between the first word line and the second word line; a controller configured to Equipped with The memory device, wherein the second passed voltage is greater than the first passed voltage.

2. The memory device of claim 1 , wherein the third word line is not directly adjacent to the first word line.

3. 2. The memory device of claim 1, wherein the controller is further configured to apply the second passing voltage to each of the first set of word lines between the first word line and the second word line, excluding a word line immediately adjacent to the first word line, while applying the program voltage to the first word line.

4. The memory device of claim 1 , further comprising a junction oxide layer between the first deck and the second deck.

5. a first dummy word line between the first word line and the junction oxide layer; a second dummy word line between the junction oxide layer and the second word line; The memory device of claim 4 further comprising:

6. 10. The memory device of claim 1, wherein the controller is further configured to apply a third passing voltage to each of the first set of word lines above the first word line, excluding a word line immediately adjacent to the first word line, while applying the program voltage to the first word line.

7. 1. A method for operating a memory device including a first deck having a first set of word lines and a second deck below the first deck having a second set of word lines, comprising: applying a program voltage to a first word line of the first set of word lines; applying a first passing voltage to a second word line of the second set of word lines while applying the program voltage to the first word line; applying a second passing voltage to a third word line of the first set of word lines between the first word line and the second word line while applying the program voltage to the first word line; Equipped with The method wherein the second pass voltage is greater than the first pass voltage.

8. The method of claim 7 , wherein the third word line is not directly adjacent to the first word line.

9. 8. The method of claim 7, further comprising: applying the second passing voltage to each of the first set of word lines between the first word line and the second word line, excluding a word line immediately adjacent to the first word line, while applying the program voltage to the first word line.

10. The method of claim 7 , wherein the memory device further comprises a junction oxide layer between the first deck and the second deck.

11. The memory device is a first dummy word line between the first word line and the junction oxide layer; a second dummy word line between the junction oxide layer and the second word line; The method of claim 10 further comprising:

12. 8. The method of claim 7, further comprising: applying a third passing voltage to each of the first set of word lines above the first word line, excluding a word line immediately adjacent to the first word line, while applying the program voltage to the first word line.

Images