Improved memory modules save wiring space on motherboards

Abstract

To provide an improved memory module to save wiring space on a motherboard, and a device and a computing system with the memory module.SOLUTION: A device includes a DIMM 201 for connecting a motherboard 202. The DIMM201 includes connectors 203_1 and 203_2 along a central axis 201 of the DIMM 201. The DIMM201 further includes a first semiconductor chip (PMIC chip 211) located in a first region of the DIMM 201 that resides between an edge portion of the DIMM201 and the side of the connector. The DIMM 201 includes a second semiconductor chip (high-performance semiconductor chip 204) located in a second region of the DIM 201 existing between the opposite edge portion of the DIM 201 and the opposite side of the connector.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The field of the invention relates generally to electronics, and more particularly to an improved memory module that conserves wiring space on a motherboard. [Background technology]

[0002] 1a and 1b show a pair of small outline dual in-memory modules 101_1, 101_2 (SODIMMs) arranged in a "butterfly" configuration (FIG. 1a shows a side view, and FIG. 1b shows a top view). In butterfly operation, the SODIMMs 101_1, 101_2 are arranged so that their respective faces are parallel to the motherboard 102 to which they are connected.

[0003] 1a and 1b, both SODIMMs 101_1, 101_2 have edges that include electrical input / output (I / O) that physically and electrically connect with corresponding connectors 103_1, 103_2 attached to the motherboard 102. Each connector 103_1, 103_2 also has electrical wiring that physically secures the SODIMM 101_1, 101_2 to the motherboard 102 and transmits signals between the SODIMM 101_1, 101_2 and the motherboard 102.

[0004] Typically, the butterfly SODIMMs are placed near a high performance semiconductor chip 104, such as a processor, that uses the memory chips on the SODIMMs 101_1, 101_2 as local or main memory.

[0005] 1a and 1b, one JEDEC (Semiconductor Engineering Association) Dual Data Rate (DDR) memory channel is routed to each SODIMM (e.g., a first DDR5 memory channel is routed to a first SODIMM 101_1, a second DDR5 memory channel is routed to a second DIMM 101_2, etc.) Thus, a high-performance semiconductor chip 104 accesses memory chips on different SODIMMs 101_1, 101_2 by accessing different memory channels emanating from the high-performance semiconductor chip. [Brief explanation of the drawings]

[0006] A better understanding of the present invention can be obtained from the following detailed description taken in conjunction with the following drawings.

[0007] [Figure 1a] 1 shows a prior art SODIMM butterfly arrangement. [Figure 1b] 1 shows a prior art SODIMM butterfly arrangement.

[0008] [Figure 2] Improved SODIMM is shown.

[0009] [Figure 3a] 1 illustrates an embodiment of an improved SODIMM. [Figure 3b] 1 illustrates an embodiment of an improved SODIMM. [Figure 3c] 1 illustrates an embodiment of an improved SODIMM. [Figure 3d] 1 illustrates an embodiment of an improved SODIMM. [Figure 3e] 1 illustrates an embodiment of an improved SODIMM.

[0010] [Figure 4] 1 shows a computer system.

[0011] [Figure 5] Indicates a data center.

[0012] [Figure 6] Shows rack. DETAILED DESCRIPTION OF THE INVENTION

[0013] A problem with the butterfly arrangement of FIGS. 1a and 1b is that there is a significant inefficiency in signal routing between the high performance semiconductor chip 104 and the memory chips on the SODIMM 101_1 that are closest to the high performance semiconductor chip 104.

[0014] Here, as shown by highlighted signal trace 105, there is a significant "fold" in that the trace travels an extended distance away from high performance semiconductor chip 104 so that it can reach connector 103_1, only to fold back in the opposite direction to reach high performance semiconductor chip 104.

[0015] As system designers increasingly seek ways to pack more functionality into smaller form factors, space for signal traces within motherboard 102 becomes more constrained. Here, the extended, folded run segment 106 of trace 105, highlighted in FIG. 1a, corresponds to an inefficient use of motherboard space. If segment 106 could be shortened, the freed up space could be used for other signals, easing the routing space constraints of motherboard 102.

[0016] Figures 2(a) and 2(b) show an improved approach in which the connector 203 of an improved form factor DIMM 201 is positioned along the central axis 210 of the DIMM 201 rather than along the edge of the DIMM. Figure 2(a) shows a side view and Figure 2(b) shows a top view.

[0017] With reference to the side view of FIG. 2(a), the placement of the connector 203_2 along the central axis 210 of the improved form factor DIMM 201 significantly reduces the length of the folded trace segment 206. That is, rather than extending all the way to the far end of the DIMM 201, in a direction away from the high-performance semiconductor chip 204, the signal trace instead only needs to extend to the central region of the DIMM 201. Thus, the length of the folded segment 206 in FIG. 2(a) is (approximately) half the length of the folded segment 106 in the prior art solution of FIG. 1(a).

[0018] Furthermore, as seen in FIG. 2(b), the memory chips coupled to different channels are arranged "side by side," rather than the memory chips of one SODIMM 101_1 being between the high-performance semiconductor chip 104 and the memory chips of the other SODIMM 101_2, as seen in FIG. 1b.

[0019] When arranged side by side, memory chips in both channels can be placed in the improved form factor DIMM 201. That is, the memory chips in the first JEDEC DDR memory channel "CH1" (e.g., a DDR5 memory channel) are placed in the top portion of the DIMM 201, and the memory chips in the second JEDEC DDR memory channel "CH2" are placed in the bottom portion of the DIMM 201 (the memory chips in both regions / channels have an "A" portion on the right and a "B" portion on the left).

[0020] Both memory channels have associated connectors unique to the modified form factor DIMM 201. That is, connector 203_1 couples memory chips in the upper region of DIMM 201 to a first memory channel CH1, and connector 203_2 couples memory chips in the lower region of DIMM 201 to a second memory channel CH2 (in various embodiments, the modified form factor DIMM 201 includes a buffer chip coupled between the memory chips and the connectors).

[0021] Therefore, the approach of Figures 2(a) and 2(b) not only saves wiring space on the motherboard 202 but also saves hardware implementation (one less DIMM printed circuit board is consumed) compared to the approach of Figures 1a and 1b.

[0022] In various embodiments, there is one power management integrated circuit (PMIC) chip per channel or per DIMM. Thus, for the particular modified form factor DIMM 201 of Figures 2(a) and 2(b), there may be one or two PMIC chips. Regardless, in various embodiments, the single or pair of PMIC chips 211 are positioned along the central axis 210 of the modified form factor DIMM 201 on the upper side of the DIMM (connectors 203_1, 203_2 are positioned along the central axis 210 of the DIMM 201 on the lower side of the DIMM 201).

[0023] 2(a) and 2(b), there may be two ranks per memory channel (the upper memory chip corresponds to one rank and the lower memory chip corresponds to the second rank). Each rank is divided into an A half and a B half, with the A half on the side of the DIMM 201 farther from the high-performance semiconductor chip 204 and the B half on the side of the DIMM 201 closer to the high-performance semiconductor chip 204.

[0024] Figures 3a through 3e show additional improved form factor DIMM versions that position the connector along the central axis of the DIMM. Figure 3a shows a DIMM similar to DIMM 201 of Figures 2a and 2b, but with an additional memory chip for storing error correction code (ECC) information. Thus, the DIMM of Figure 3a is slightly longer than the DIMM of Figures 2a and 2b.

[0025] FIG. 3b shows a single channel card that connects to only one channel and therefore has half the memory chips (and (approximately) half the length) of the DIMM 201 of FIGS. 2a and 2b.

[0026] Figure 3c shows a single-rank DIMM for low-profile implementation. Here, the memory chips are not located on the top side of the DIMM to keep the DIMM's vertical height low (thereby eliminating a rank per channel compared to a DIMM with memory chips mounted on both sides). The DIMM can be dual-channel, as in Figures 2a and 2b, or single-channel, as in Figure 3b. Additionally, the DIMM in Figure 3c may or may not include ECC memory chips.

[0027] Figure 3d shows another solution that integrates two ranks of memory chips per channel, but with one rank of memory chips located on the top surface of the DIMM and the other rank of memory chips mounted directly on the motherboard. The solution in Figure 3d can be used, for example, in systems with a fixed amount of memory on the motherboard. The overall memory capacity can be expanded by adding one rank per channel per DIMM.

[0028] The connector, for example, can be a source of emitting radiation that introduces electrical noise into the system or elsewhere. Figure 3e shows that the noise emitted from the connector of the improved form factor DIMM described above can be attenuated, for example, by shielding the connector with a grounded conductive material (e.g., metal foil) that encapsulates the connector between the top surface of the motherboard and the bottom surface of the DIMM.

[0029] One or more DIMMs can be connected to a channel, depending on the system designer's preferences. Thus, for example, another improved form factor DIMM can be placed next to DIMM 201 in FIG. 2(b), where the top region of the other DIMM has memory chips coupled to a first channel and the bottom region of the other DIMM has memory chips coupled to a second channel.

[0030] The improved form factor DIMMs described above may include dynamic random access memory (DRAM) chips, non-volatile byte-addressable memory chips such as Intel's Optane™ memory (e.g., a three-dimensional cross-point memory in which resistive memory cells are stacked on top of a chip substrate), or a combination of DRAM and non-volatile byte-addressable memory chips.

[0031] It is pertinent to note that the above teachings may be applicable to other modules besides DIMMs. For example, various other types of modules having one or more semiconductor chips that connect to a printed circuit board (motherboard) may have connectors located along the central axis of the module.

[0032] The chips that can be placed in such modules can be any of a number of different high performance semiconductor chips (e.g., systems-on-chips, accelerator chips (e.g., neural network processors), graphics processing units (GPUs), general purpose graphics processing units (GPGPUs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs)), "X" processing units ("XPUs"), where "X" can be any processor other than a general purpose processor (e.g., G for graphics, D for data, I for infrastructure, etc.).

[0033] PCB boards with modules utilizing the teachings herein can be assembled into chassis having dimensions compatible with industry-standard racks (such as racks with width openings of 19 inches (482.6 mm) or 23 inches (584.2 mm) and mounting holes for chassis having heights in specific height units (e.g., 1U, 2U, 3U, where U=1.75 inches (44.45 mm)). An example is the dimensions of the IEC 60297 Mechanical Structures of Electronic Equipment—482.6 mm (19 inch) series mechanical structures. In general, however, chassis of any size are possible.

[0034] The above-mentioned chip package electrical I / O to motherboard connections may be compatible with or used to transport signals associated with various data center computing and networking system interconnect technologies. Examples include, for example, data and / or clock signals associated with Infinity Fabric (e.g., associated with and / or implemented in Advanced Micro Devices (AMD™) products) or any of its derivatives, a specification developed by the Cache Coherent Interconnect for Accelerators (CCIX) Consortium or its derivatives, a specification developed by the GEN-Z Consortium or its derivatives, a specification developed by the Coherent Accelerator Processor Interface (CAPI) or its derivatives, a specification developed by the Computer Express Link (CXL) Consortium or its derivatives, a specification developed by the HyperTransport Consortium or its derivatives, Ethernet, InfiniBand, NVMe-oF, PCIe, etc.

[0035] A PCB board having modules utilizing the above teachings, and / or the PCB board's associated electronic system, may include the major components of an entire computer system (e.g., CPU, main memory controller, main memory, peripheral controller, large capacity non-volatile storage), or may include the functionality of only some subset of an entire computer system (e.g., a chassis containing primarily the CPU processor power supply, a chassis containing primarily the main memory control and main memory, a chassis containing primarily the storage controller and storage). The latter may be particularly useful for isolated computing systems.

[0036] Unlike traditional computers, where the core components of a computing system (e.g., CPU processor, memory, storage, accelerators, etc.) are all housed within a common chassis and connected to a common motherboard, in a decoupled computer system, such components are integrated onto separate pluggable cards or other pluggable components (e.g., CPU card, system memory card, storage card, accelerator card, etc.) that connect to a larger, exposed backplane or network rather than the same, narrow motherboard. As such, for example, a CPU computer power supply can be added by adding a CPU card to the backplane or network, system memory can be added to the backplane or network by adding a memory card, etc. Such systems can exhibit even faster card-to-card connections than traditional computers. One or more decoupled computers and / or traditional computers / servers can be identified as points of delivery (PoDs) for computing system functionality in a larger configuration of an information technology (IT) implementation, such as a data center.

[0037] 4 illustrates an exemplary system that can utilize the teachings provided herein. System 400 includes a processor 410 that provides processing, operational management, and instruction execution for system 400. Processor 410 can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or combination of processors, for providing processing for system 400. Processor 410 controls the overall operation of system 400 and can be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or a combination of such devices.

[0038] In one example, system 400 includes an interface 412 coupled to processor 410, which may represent a high-speed or high-throughput interface for system components requiring a higher bandwidth connection, such as memory subsystem 420, a graphics interface component 440, or an accelerator 442. Interface 412 represents interface circuitry that may be a standalone component or may be integrated on a processor die. If present, graphics interface 440 interfaces to the graphics component to provide a visual display to a user of system 400. In one example, graphics interface 440 may drive a high-definition (HD) display that provides output to the user. High resolution refers to a display with a pixel density of approximately 100 PPI (pixels per inch) or greater and may include formats such as Full HD (e.g., 1080p), Retina display, and 4K (ultra-high definition or UHD). In one example, the display may include a touchscreen display. In one example, graphics interface 440 generates a display based on data stored in memory 430, based on operations performed by processor 410, or both. In one example, graphics interface 440 generates a display based on data stored in memory 430, or based on operations performed by processor 410, or both.

[0039] Accelerator 442 may be a fixed-function offload engine that can be accessed or used by processor 410. For example, an accelerator within accelerator 442 may provide a compression (DC) function, an encryption service such as public key encryption (PKE), a cipher, a hash / authentication function, decryption, or other function or service. In some embodiments, an accelerator within accelerator 442 may additionally or alternatively provide a field selection controller function as described herein. In some cases, accelerator 442 may be integrated into a CPU socket (e.g., a connector to a motherboard or circuit board that contains a CPU and provides an electrical interface with the CPU). For example, accelerator 442 may include programmable processing elements such as a single or multi-core processor, a graphics processing unit, a logic execution unit (LES), a single or multi-level cache, a functional unit usable to independently execute programs or threads, an application-specific integrated circuit (ASIC), a neural network processor (NNP), an “X” processing unit (XPU), programmable control logic, and a field-programmable gate array (FPGA). The accelerator 442 can provide multiple neural networks, processor cores, or graphics processing units that can be enabled for use with artificial intelligence (AI) or machine learning (ML) models. For example, the AI ​​models can use or include reinforcement learning schemes, Q-learning schemes, deep Q-learning, or asynchronous advantage-actor-critical (A3C), combinatorial neural networks, recurrent combinatorial neural networks, or other AI or ML models, or any combination thereof. Multiple neural networks, processor cores, or graphics processing units can be enabled for use with the AI ​​or ML models.

[0040] Memory subsystem 420 represents the main memory of system 400 and provides storage for code executed by processor 410 or data values ​​used in executing routines. Memory subsystem 420 can include one or more memory devices 430, such as read-only memory (ROM), flash memory, volatile memory, or a combination of such devices. Memory 430 stores and hosts, among other things, an operating system (OS) 432, providing a software platform for executing instructions on system 400. Additionally, applications 434 can execute on the software platform of OS 432 in memory 430. Applications 434 represent programs having their own operating logic for performing the execution of one or more functions. Processes 436 represent agents or routines that provide auxiliary functionality to OS 432 and / or one or more applications 434. OS 432, applications 434, and processes 436 provide the software logic that provides functionality to system 400. In one example, memory subsystem 420 includes memory controller 422, which generates and issues commands to memory 430. It will be understood that the memory controller 422 can be a physical part of the processor 410 or a physical part of the interface 412. For example, the memory controller 422 can be an integrated memory controller integrated on circuitry with the processor 410. In some examples, a system on a chip (SOC or SoC) integrates one or more of a processor, graphics, memory, a memory controller, and input / output (I / O) control logic into a single SoC package.

[0041] Volatile memory is memory whose state (and the data stored therein) is indeterminate when power to the device is interrupted. Dynamic volatile memory requires the data stored in the device to be refreshed in order to maintain its state. An example of dynamic volatile memory is DRAM (Dynamic Random Access Memory) or variants such as Synchronous DRAM (SDRAM). As described herein, the memory subsystem may be compatible with many memory technologies, such as DDR3 (Double Data Rate Version 3, first released by JEDEC (Semiconductor Engineering Association) on June 27, 2007). DDR4 (DDR Version 4, initial specification published by JEDEC in September 2012), DDR4E (DDR Version 4), LPDDR3 (Low Power DDR Version 3, JESD209-3B, August 2013 by JEDEC), LPDDR4 (LPDDR Version 4, JESD209-4, first published by JEDEC in August 2014), WIO2 (registered trademark) (Wide Input / Output Version 2, JESD229-2, first published by JEDEC in August 2014), HBM (High Bandwidth Memory Module) The memory may be compatible with several memory technologies, such as JEDEC standards (JESD325, first published by JEDEC in October 2013), LPDDR5 (Low Power DDR5, JESD209-5, first published by JEDEC in February 2019), DDR5 (DDR Version 5, JESD79-5, first published by JEDEC in July 2020), HBM2 (HBM Version 2, currently under discussion by JEDEC), or other combinations of memory technologies, and technologies based on derivatives or extensions of such specifications. JEDEC standards are available at www.jedec.org.

[0042] Although not specifically shown, it will be understood that system 400 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, etc. A bus or other signal lines may communicatively or electrically couple components to each other, or may couple components both communicatively and electrically. A bus can include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other electrical circuitry, or a combination thereof. A bus can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCIe) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Remote Direct Memory Access (RDMA), an Internet Small Computer System Interface (iSCSI), NVM Express (NVMe), a Coherent Accelerator Interface (CXL), a Coherent Accelerator Processor Interface (CAPI), a Universal Serial Bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) Standard 1394 bus.

[0043] In one example, system 400 includes an interface 414 that can be coupled to interface 412. In one example, interface 414 represents an interface circuit that can include standalone components and integrated circuits. In one example, multiple user interface and / or peripheral components are coupled to interface 414. Network interface 450 provides system 400 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 450 can include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a Universal Serial Bus (USB), or other wired or wireless, standards-based, or proprietary interface. Network interface 450 can transmit data to a remote device, and the remote device can transmit the data stored in memory. Network interface 450 can receive data from a remote device, and the remote device can store the received data in memory. Various embodiments can be used in conjunction with network interface 450, processor 410, and memory subsystem 420.

[0044] In one example, system 400 includes one or more input / output (I / O) interfaces 460. I / O interface 460 can include one or more interface components (e.g., voice, alphanumeric, haptic / touch, or other interfaces) through which a user interacts with system 400. Peripheral interface 470 can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that depend on system 400 for connectivity. A dependent connection is a connection provided by system 400 to a software platform, hardware platform, or both, on which operations are performed and with which a user interacts.

[0045] In one example, system 400 includes a storage subsystem 480 for storing data in a nonvolatile manner. In one example, in a particular system implementation, at least certain components of storage 480 may overlap with components of memory subsystem 420. Storage subsystem 480 includes storage 484, which may be or may include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic disks, solid-state disks, or optical-based disks, or a combination thereof. Storage 484 holds code or instructions and data 486 in a persistent state (e.g., values ​​are retained despite an interruption of power to system 400). While storage 484 may be generally considered "memory," memory 430 is typically an execution or operating memory that provides instructions to processor 410. While storage 484 is nonvolatile, memory 430 may include volatile memory (e.g., the value or state of data is indeterminate if power is interrupted to system 400). In one example, storage subsystem 480 includes a controller 482 that interfaces with storage 484. In one example, controller 482 may be a physical part of interface 414 or processor 410, or may include circuitry or logic in both processor 410 and interface 414.

[0046] A non-volatile memory (NVM) device is memory whose state is determinable even when power to the device is interrupted. In one embodiment, the NVM device may comprise a block-addressable memory device such as NAND technology, or more specifically, multi-threshold level NAND flash memory (e.g., single-level cell ("SLC"), multi-level cell ("MLC"), quad-level cell ("QLC"), tri-level cell ("TLC"), or other NAND). The NVM device may also comprise a byte-addressable write-in-place three-dimensional cross-point memory device or other byte-addressable write-in-place NVM device (also referred to as persistent memory), such as single-level or multi-level phase change memory (PCM) or switched phase change memory (PCMS), NVM devices using chalcogenide phase change materials (e.g., chalcogenide glasses), metal oxide-based, oxygen vacancy-based, and conductive bridge random access memory (CB-RAM), nanowire memory, ferroelectric random access memory (FeRAM, FRAM®), magnetoresistive random access memory (MRAM) incorporating memristor technology, spin-transfer torque (STT) MRAM, spintronic magnetic junction memory-based devices, magnetic tunnel junction (MTJ)-based devices, DW (domain wall) and SOT (spin orbit transfer)-based devices, resistive memory including thyristor-based memory devices, or any combination of the above, or other memories.

[0047] A power source (not shown) provides power to the components of system 400. More specifically, the power source typically interfaces with one or more power supplies of system 600 to provide power to the components of system 400. In one example, the power source includes an AC-DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be a renewable energy (e.g., solar-powered) power source. In one example, the power source includes a DC power source, such as an external AC-DC converter. In one example, the power source or power supply includes wireless charging hardware for charging in proximity to a charging field. In one example, the power source can include an internal battery, an AC power source, a motion-based power source, a solar power source, or a fuel cell power source.

[0048] In one example, system 400 can be implemented as a disaggregated computing system. For example, system 600 can be implemented with computational threads of interconnected processors, memory, storage, network interfaces, and other components. High-speed interconnects such as PCIe, Ethernet, or optical interconnects (or combinations thereof) can be used. For example, the threads can be designed according to specifications promulgated by the Open Compute Project (OCP) or other disaggregated computing efforts that seek to modularize major architectural computer components into rack-pluggable components (e.g., rack-pluggable processing components, rack-pluggable memory components, rack-pluggable storage components, rack-pluggable accelerator components, etc.).

[0049] FIG. 5 illustrates an example data center. Various embodiments may be used within or in conjunction with the data center of FIG. 5. As shown in FIG. 5, data center 500 may include an optical fabric 512. Optical fabric 512 may generally include a combination of optical signal media (such as optical cables) and an optical switching infrastructure that allows any particular thread in data center 500 to send signals to (and receive signals from) other threads in data center 500. However, optical, wireless, and / or electrical signals may be transmitted using fabric 512. The signaling connections that optical fabric 512 provides to any given thread may include connections to both other threads in the same rack and threads in other racks. Data center 500 includes four racks 502A-502D, each housing a pair of sleds: 504A-1 and 504A-2, 504B-1 and 504B-2, 504C-1 and 504C-2, and 504D-1 and 504D-2. Thus, in this example, data center 500 includes a total of eight sleds. Optical fabric 512 can provide sled signaling connections to one or more of the other seven sleds. For example, via optical fabric 512, sled 504A-1 in rack 502A may have a signaling connection with sled 504A-2 in rack 502A and six other sleds 504B-1, 504B-2, 504C-1, 504C-2, 504D-1, and 504D-2 distributed across other racks 502B, 502C, and 502D in data center 500. The embodiment is not limited to this example. For example, fabric 512 may provide optical and / or electrical signals.

[0050] 6 shows that environment 600 includes multiple computing racks 602, each including a top-of-rack (ToR) switch 604, a pod manager 606, and multiple pooled system drawers. Generally, a pooled system drawer may include pooled computer drawers and pooled storage drawers, for example, to run isolated computing systems. Optionally, the pooled system drawer may also include pooled memory drawers and pooled input / output (I / O) drawers. In the illustrated embodiment, the pooled system drawers include an Intel® XEON® pooled computer drawer 608, and an Intel® ATOM™ pooled computer drawer 210, pooled storage drawer 212, pooled memory drawer 214, and pooled I / O drawer 616. Each of the pooled system drawers is connected to the ToR switch 604 via a high-speed link 618, such as a 40 Gigabit per second (Gb / s) or 100 Gb / s Ethernet link or a 100 Gb+ / s Silicon Photonics (SiPh) optical link. In one embodiment, the high-speed link 618 comprises an 800 Gb / s SiPh optical link.

[0051] Again, the drawer may be designed according to specifications promulgated by the Open Compute Project (OCP) or other decoupled computing efforts that seek to modularize major architectural computer components into rack-pluggable components (e.g., rack-pluggable processing components, rack-pluggable memory components, rack-pluggable storage components, rack-pluggable accelerator components, etc.).

[0052] As shown by their connection to network 620, multiple computing racks 600 may be interconnected via their ToR switches 604 (e.g., to pod-level switches or data center switches). In some embodiments, groups of computing racks 602 are managed as separate pods via pod managers 606. In one embodiment, a single pod manager is used to manage all racks in a pod. Alternatively, a distributed pod manager may be used for pod management operations.

[0053] The multi-rack environment 600 further includes a management interface 622 that is used to manage various aspects of the RSD environment, including managing rack configurations, and corresponding parameters are stored as rack configuration data 624.

[0054] Embodiments herein may be implemented in various types of computing devices, including smartphones, tablets, and personal computers, as well as network equipment such as switches and routers, racks, and blade servers used in data center and / or server farm environments. Servers used in data centers and server farms include array server configurations, such as rack-based servers or blade servers. These servers are interconnected via various network configurations, such as dividing a set of servers into local area networks (LANs) with appropriate switching and routing capabilities between LANs to form private intranets. For example, cloud hosting facilities typically employ large data centers with numerous servers. Blades comprise separate computing platforms, i.e., "servers on cards," configured to perform server-type functions. Thus, each blade includes components common to a traditional server, including a main printed circuit board (mainboard) that provides appropriate integrated circuits (ICs) and internal wiring (e.g., buses) for coupling other components mounted on the board.

[0055] Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, registers, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision whether an example is implemented using hardware and / or software elements may depend on a number of factors, such as desired computational speed, power levels, thermal tolerances, processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints, as desired for a given implementation. It should be noted that hardware, firmware, and / or software elements may be collectively or individually referred to herein as "modules," "logic," "circuitry," or "circuitry."

[0056] Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. The computer-readable medium may include a non-transitory storage medium for storing logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, such as volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, or writable or rewritable memory. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0057] According to some examples, a computer-readable medium may include a non-transitory storage medium for storing or maintaining instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or operations according to the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. The instructions may be implemented according to a predefined computer language, method, or syntax to instruct a machine, computing device, or system to perform a particular function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0058] One or more aspects of at least one example may be implemented by expressive instructions stored on at least one machine-readable medium that represent various logic within a processor, which instructions, when read by a machine, computing device, or system, cause the machine, computing device, or system to produce logic for performing the techniques described herein. Such expressions, known as "IP cores," may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities to be loaded into manufacturing machines that actually produce the logic or processor.

[0059] Appearances of the phrase "one example" or "example" do not necessarily all refer to the same example or embodiment. Any aspect described herein can be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with reference to the same figure or element. The division, omission, or inclusion of block functions shown in the accompanying figures does not necessarily mean that hardware components, circuits, software, and / or elements for implementing those functions are necessarily divided, omitted, or included in the embodiments.

[0060] Some examples may be described using the terms "coupled" and "connected," along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may mean that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other.

[0061] The terms "first," "second," and the like, used herein do not denote order, quantity, or importance, but rather are used to distinguish one element from another. The terms "a" and "an" used herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term "asserted," as used herein with respect to a signal, indicates a state of the signal that is active and can be achieved by applying a logic level of either logic 0 or logic 1 to the signal. The terms "following" or "after" may refer to immediately following or following some other event or events. Other sequences of steps may be performed according to alternative embodiments. Furthermore, additional steps may be added or deleted depending on the particular application. Any combination of changes may be used, and those skilled in the art, having the benefit of this disclosure, will recognize numerous variations, modifications, and alternative embodiments thereof.

[0062] Unless otherwise indicated, disjunctive language such as the phrase "at least one of X, Y, or Z" is understood in context as generally used to indicate that an item, term, etc. may be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is not generally intended, and should not be intended, to imply that a particular embodiment requires that at least one of X, at least one of Y, or at least one of Z, respectively, be present. Furthermore, unless otherwise indicated, a conjunction such as the phrase "at least one of X, Y, and Z" should be understood to mean X, Y, Z, or any combination thereof, including "X, Y, and / or Z."

[0063] An apparatus has been described that includes a memory module having a connector along a central axis of the memory module, the memory module further including a first set of memory chips disposed in a first region of the memory module between an edge of the memory module and a side of the connector, and a second set of memory chips disposed in a second region of the memory module between an opposing edge of the memory module and an opposing side of the connector.

[0064] In various embodiments, the memory module is a dual in-line memory module (DIMM). In various embodiments, the memory module is a small outline dual in-memory module (SODIMM). In various embodiments, a first set of memory chips is coupled to a memory channel. In various embodiments, a second set of memory chips is coupled to the memory channel. In various embodiments, the second memory channel is coupled to a rank of memory chips on the memory module. In various embodiments, the first set of memory chips is part of a rank that stores ECC information. In various embodiments, the memory module has additional memory chips on a surface of the memory module, and the first and second sets of memory chips are on opposite sides of the memory module.

[0065] A computing system has been described. The computing system includes a motherboard having a first connector. A memory module includes a second connector along a central axis of the memory module. The first connector is connected to the second connector. The memory module further includes a first set of memory chips disposed in a first region of the memory module between an edge of the memory module and a side of the connector, and a second set of memory chips disposed in a second region of the memory module between an opposing edge of the memory module and an opposing side of the connector.

[0066] An apparatus is described. The apparatus includes a module for connecting to a printed circuit board. The module includes a connector along a central axis of the module. The module further includes a first semiconductor chip disposed in a first region of the module between an edge of the module and a side of the connector, and a second semiconductor chip disposed in a second region of the module between an opposing edge of the module and an opposing side of the connector. [Other possible items] (Item 1) A memory module having a connector along a central axis of the memory module, the memory module further having a first set of memory chips disposed in a first region of the memory module between an edge of the memory module and a side of the connector, and a second set of memory chips disposed in a second region of the memory module between an opposing edge of the memory module and an opposing side of the connector. An apparatus comprising: (Item 2) Item 1, wherein the memory module is a dual in-line memory module (DIMM). (Item 3) Item 10. The device of item 1, wherein the first set of memory chips is coupled to a memory channel. (Item 4) 4. The apparatus of claim 3, wherein the second set of memory chips is coupled to the memory channel. (Item 5) Item 4. The apparatus of item 3, wherein a second memory channel is coupled to a rank of memory chips on the memory module. (Item 6) Item 10. The apparatus of item 1, wherein the first set of memory chips is part of a rank that stores ECC information. (Item 7) Item 10. The device of item 1, wherein the memory module has additional memory chips on a surface of the memory module and has the first set of memory chips and the second set of memory chips on an opposite surface of the memory module. (Item 8) a motherboard having a first connector; a memory module having a second connector along a central axis of the memory module, the first connector being connected to the second connector, the memory module further having a first set of memory chips disposed in a first region of the memory module between an edge of the memory module and a side of the second connector, and a second set of memory chips disposed in a second region of the memory module between an opposing edge of the memory module and an opposing side of the second connector; A computing system comprising: (Item 9) Item 9. The computing system of item 8, wherein the memory module is a dual in-line memory module (DIMM). (Item 10) Item 10. The computing system of item 8, wherein the first set of memory chips is coupled to a memory channel. (Item 11) Item 11. The computing system of item 10, wherein a second set of the memory chips is coupled to the memory channel. (Item 12) Item 11. The computing system of item 10, wherein a second memory channel is coupled to a rank of memory chips on the memory module. (Item 13) 9. The computing system of claim 8, wherein the first set of memory chips is part of a rank that stores ECC information. (Item 14) 9. The computing system of claim 8, wherein the memory module has an additional memory chip on a surface of the memory module, the first set of memory chips and the second set of memory chips on an opposite surface of the memory module. (Item 15) A module for connecting to a printed circuit board, the module having a connector along a central axis of the module, the module further having a first semiconductor chip disposed in a first region of the module between an edge of the module and a side of the connector, and a second semiconductor chip disposed in a second region of the module between an opposing edge of the module and an opposing side of the connector. An apparatus comprising:

Claims

1. 1. A memory module having a connector along a central axis of the memory module, the memory module further having a first set of memory chips disposed in a first region of the memory module between an edge of the memory module and a side of the connector, and a second set of memory chips disposed in a second region of the memory module between an opposing edge of the memory module and an opposing side of the connector. Equipped with the connector includes a first connector and a second connector, the first connector coupling the first set and the second set of memory chips in an upper region of the memory module to a first memory channel, and the second connector coupling the first set and the second set of memory chips in a lower region of the memory module to a second memory channel.

2. 10. The apparatus of claim 1, wherein the memory module is a dual in-line memory module (DIMM).

3. The device described in claim 1, wherein the second memory channel is coupled to a rank of memory chips on the memory module.

4. 2. The apparatus of claim 1, wherein the first set of memory chips is part of a rank that stores ECC information.

5. 2. The apparatus of claim 1, wherein the memory module has an additional memory chip on one side of the memory module and the first set of memory chips and the second set of memory chips on an opposite side of the memory module.

6. The device described in claim 1, wherein the first set of memory chips includes memory chips arranged in the upper region and the lower region, and the second set of memory chips includes memory chips arranged in the upper region and the lower region.

7. The device described in claim 1, wherein the first set of memory chips includes memory chips of a first rank, the second set of memory chips includes memory chips of a second rank, the memory chips of the first rank being located on a first side of the central axis, and the memory chips of the second rank being located on a second side of the central axis.

8. The device described in claim 1, further comprising a single power management integrated circuit (PMIC) chip located in the upper region, the single PMIC chip being for both channels.

9. The device described in claim 1, further comprising a first power management integrated circuit (PMIC) chip disposed in the upper region for the first memory channel, and a second PMIC chip disposed in the upper region for the second memory channel.

10. The device described in Claim 9, wherein the first PMIC chip and the second PMIC chip are arranged along the central axis, and when viewed from above, at least a portion of the first PMIC chip overlaps with the first connector, and at least a portion of the second PMIC chip overlaps with the second connector.

11. The device described in claim 1, further comprising ground shielding around the first connector and the second connector.

12. A computing system comprising an apparatus according to any one of claims 1 to 3.

13. A computing system according to claim 12, comprising an apparatus according to claim 4 or 5.

14. 1. A module for connecting to a printed circuit board, the module having a connector along a central axis of the module, the module further having a first semiconductor chip disposed in a first region of the module between an edge of the module and a side of the connector, and a second semiconductor chip disposed in a second region of the module between an opposing edge of the module and an opposing side of the connector. Equipped with The connector includes a first connector and a second connector, the first connector couples the first set of semiconductor chips and the second set of semiconductor chips in an upper region of the module to a first memory channel, and the second connector couples the first set of semiconductor chips and the second set of semiconductor chips in a lower region of the module to a second memory channel.

15. A memory module comprising: a printed circuit board (PCB) having a first side and a second side; a first group of memory chips and a second group of memory chips arranged on the PCB, the first group of memory chips including memory chips for a first channel and a second channel, and the second group of memory chips including memory chips for the first channel and the second channel; a first connector for the first channel and a second connector for the second channel on the second surface of the PCB for installing the memory module on a system board, wherein when installed, the first surface and the second surface are parallel to the system board and the first connector and the second connector are aligned along a central axis of the PCB between the first group of memory chips and the second group of memory chips; A memory module comprising:

16. A memory module as described in claim 15, wherein the first group of memory chips includes memory chips arranged on the first surface and the second surface, and the second group of memory chips includes memory chips arranged on the first surface and the second surface.

17. A memory module as described in claim 15, wherein the first group of memory chips includes memory chips of a first rank, the second group of memory chips includes memory chips of a second rank, the memory chips of the first rank being located on a first side of the central axis, and the memory chips of the second rank being located on a second side of the central axis.

18. The memory module of claim 15, wherein the first group of memory chips is part of a rank that stores error correction code (ECC) information.

19. The memory module of claim 15, further comprising a single power management integrated circuit (PMIC) chip disposed on the first surface, the single PMIC chip being for both channels.

20. The memory module of claim 15, further comprising a first power management integrated circuit (PMIC) chip disposed on the first surface for the first channel, and a second PMIC chip disposed on the first surface for the second channel.

21. A memory module as described in claim 20, wherein the first PMIC chip and the second PMIC chip are arranged along the central axis, and when viewed from above, at least a portion of the first PMIC chip overlaps with the first connector, and at least a portion of the second PMIC chip overlaps with the second connector.

22. The memory module of claim 15, further comprising ground shielding around the first connector and the second connector.

23. A motherboard; a processor chip disposed on the motherboard; a memory module coupled to the processor chip, a printed circuit board (PCB) having a first side and a second side; a first group of memory chips and a second group of memory chips arranged on the PCB, the first group of memory chips including memory chips for a first channel and a second channel, and the second group of memory chips including memory chips for the first channel and the second channel; a first connector for the first channel and a second connector for the second channel on the second surface of the PCB for installing the memory module on the motherboard, wherein when installed, the first surface and the second surface are parallel to the motherboard and the first connector and the second connector are aligned along a central axis of the PCB between the first group of memory chips and the second group of memory chips; a memory module including: A computer system comprising:

24. A computer system as described in claim 23, wherein the first group of memory chips includes memory chips arranged on the first surface and the second surface, and the second group of memory chips includes memory chips arranged on the first surface and the second surface.

25. The computer system described in claim 23, wherein the first group of memory chips includes memory chips of a first rank, the second group of memory chips includes memory chips of a second rank, the memory chips of the first rank being located on a first side of the central axis, and the memory chips of the second rank being located on a second side of the central axis.

26. The computer system of claim 23, further comprising a single power management integrated circuit (PMIC) chip disposed on the first surface, the single PMIC chip being for both channels.

27. ​​The computer system of claim 23, further comprising a first power management integrated circuit (PMIC) chip disposed on the first surface for the first channel, and a second PMIC chip disposed on the first surface for the second channel.

28. The computer system of claim 23, further comprising ground shielding around the first connector and the second connector.

29. The computer system of claim 23, wherein the first connector and the second connector are intended to be inserted into corresponding connectors on the motherboard to install the memory module on the motherboard.

30. The computer system of claim 23, wherein the processor chip includes a central processing unit (CPU).

31. The computer system of claim 23, wherein the processor chip includes a graphics processing unit (GPU).

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