Semiconductor module, semiconductor device, and vehicle

Abstract

To detect breaking of specific wiring of a semiconductor module and a semiconductor device early.SOLUTION: A semiconductor module 1 comprises: a semiconductor element 3 whose top face is formed with a top face electrode including at least a first main electrode 30a; a lamination substrate 2 on which a plurality of circuit plates including a first circuit plate 22 and a second circuit plate 23 are arranged; a first main terminal 61 electrically connected with the first main electrode; a first auxiliary terminal 63 and a second auxiliary terminal 64 electrically connected with the top face electrode; and a main current wiring member 4 for electrically connecting the first main electrode and the first main terminal to each other. A first path r1 electrically connected with the first auxiliary terminal from the top face electrode via first auxiliary wiring W3 is provided between the top face electrode and the first auxiliary terminal. A second path r2 electrically connected with the second auxiliary terminal from the top face electrode via the main current wiring member, the second circuit plate and second auxiliary wiring W5 in this order is provided between the top face electrode and the second auxiliary terminal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module, a semiconductor device, and a vehicle. [Background technology]

[0002] 2. Description of the Related Art Semiconductor modules have substrates on which semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and FWDs (Free Wheeling Diodes) are mounted, and are used in inverter devices and the like.

[0003] In this type of semiconductor module, for example, in Patent Document 1, a semiconductor element is disposed on the upper surface of a laminated substrate. A plurality of electrodes (including a main electrode, a gate electrode, and a sense electrode) are formed on the upper surface of the semiconductor element. For example, the main electrode of the semiconductor element is electrically connected to a main terminal for external connection via wiring members such as a circuit board or wire. These wiring members, which form part of the current path that flows through the main terminal, may be called, for example, a main current wiring member.

[0004] In addition, control wiring for controlling switching operation is connected to the semiconductor element. For example, the gate electrode of the semiconductor element is connected to an external gate terminal via the gate wiring. Furthermore, corresponding to the gate wiring, the main electrode or sense electrode of the semiconductor element is connected to an external auxiliary electrode via an auxiliary wiring. Such control wiring may be called, for example, a control wiring member. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-068740 Summary of the Invention [Problem to be solved by the invention]

[0006] In semiconductor modules, the current flowing through the control wiring is smaller than that through the main current wiring. For this reason, relatively thin bonding wires are used for the control wiring. Furthermore, one end of the control wiring is connected to the surface of the semiconductor element, which generates heat during switching operations. In this case, the control wiring is likely to deteriorate due to thermal cycling and eventually break. This could adversely affect the operation of the semiconductor module, making it desirable to detect breaks early.

[0007] The present invention has been made in view of the above points, and one of its objects is to provide a semiconductor module that allows early detection of a break in a specific wiring. [Means for solving the problem]

[0008] a first main terminal electrically connected to the first main electrode; a first auxiliary terminal and a second auxiliary terminal electrically connected to the top electrode; and a main current wiring member electrically connecting the first main electrode to the first main terminal. A main current path is provided between the first main electrode and the first main terminal, electrically connected to the first main terminal via the main current wiring member and the second circuit board in this order; a first path is provided between the top electrode and the first auxiliary terminal, electrically connected to the first auxiliary terminal via the first auxiliary wiring; and a second path is provided between the top electrode and the second auxiliary terminal, electrically connected to the second auxiliary terminal via the main current wiring member, the second circuit board, and the second auxiliary wiring in this order. [Effects of the Invention]

[0009] According to the present invention, it is possible to detect a break in a specific wiring at an early stage. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line AA. [Figure 3] 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line BB. [Figure 4] 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention; [Figure 5] FIG. 2 is a partially enlarged view of FIG. [Figure 6] FIG. 10 is a plan view showing a semiconductor device according to a modified example. [Figure 7] FIG. 7 is an equivalent circuit diagram of a semiconductor device according to a modified example of FIG. 6. [Figure 8] FIG. 10 is a plan view showing a semiconductor device according to another modified example. [Figure 9] FIG. 9 is an equivalent circuit diagram of a semiconductor device according to a modified example of FIG. 8. [Figure 10] FIG. 2 is a plan view of a semiconductor device showing a variation of FIG. [Figure 11] FIG. 5 is an equivalent circuit diagram of a semiconductor device showing a variation of FIG. 4. [Figure 12] FIG. 5 is an equivalent circuit diagram of the semiconductor device showing another variation of FIG. 4. [Figure 13] 1 is a schematic plan view showing an example of a vehicle to which a semiconductor device of the present invention is applied; DETAILED DESCRIPTION OF THE INVENTION

[0011] A semiconductor module and a semiconductor device to which the present invention can be applied will be described below. Fig. 1 is a plan view of a semiconductor device according to this embodiment. Fig. 2 is a cross-sectional view of the semiconductor device shown in Fig. 1 taken along line AA. Fig. 3 is a cross-sectional view of the semiconductor device shown in Fig. 1 taken along line BB. Fig. 4 is an equivalent circuit diagram of the semiconductor device according to this embodiment.

[0012] In the following figures, the X direction represents the direction in which multiple semiconductor elements are arranged, the Y direction represents the direction in which a pair of main terminals face each other, and the Z direction represents the height direction of the semiconductor device (thickness direction of the board). The X, Y, and Z axes in the figures are perpendicular to each other and form a right-handed system. In some cases, the X direction may be referred to as the left-right direction, the Y direction as the front-rear direction, and the Z direction as the up-down direction. These directions (front-rear, left-right, up-down, and down-up directions) are used for convenience of explanation, and their correspondence with the X, Y, and Z directions may change depending on the mounting orientation of the semiconductor device. For example, the heat dissipation side (cooler side) of the semiconductor device is referred to as the bottom side, and the opposite side is referred to as the top side. In this specification, a plan view refers to the top or bottom side of the semiconductor device as viewed from the Z direction. The aspect ratios and relative sizes of the components in each drawing are merely schematic diagrams and may not necessarily match. For convenience of explanation, the relative sizes of the components may be exaggerated.

[0013] A semiconductor device 100 according to this embodiment is a power conversion device that is applied to, for example, an inverter for an industrial or automotive motor. As shown in Figures 1 to 3, the semiconductor device 100 is configured by placing a semiconductor module 1 on the upper surface of a cooler 10. Note that the cooler 10 is an optional configuration relative to the semiconductor module 1.

[0014] The cooler 10 dissipates heat from the semiconductor module 1 to the outside and has an overall rectangular parallelepiped shape. Although not specifically shown, the cooler 10 is configured by providing multiple fins on the underside of a base plate and housing these fins in a water jacket. However, the cooler 10 is not limited to this and can be modified as appropriate.

[0015] The semiconductor module 1 is configured by arranging a laminated substrate 2, a semiconductor element 3, a metal wiring board 4, and the like in a case 5.

[0016] The laminated substrate 2 is formed of, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal-based substrate. The laminated substrate 2 is formed by laminating an insulating plate 20, a heat sink 21, and multiple circuit boards 22-25, and is formed into a rectangular (or square) shape as a whole in a plan view.

[0017] Specifically, the insulating plate 20 is formed as a plate-like body having upper and lower surfaces on the XY plane and has a rectangular shape in a plan view. The insulating plate 20 may be formed from a ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), aluminum oxide (Al2O3), and zirconium oxide (ZrO2).

[0018] The insulating plate 20 may be formed of, for example, a thermosetting resin such as an epoxy resin or a polyimide resin, or a composite material in which a thermosetting resin is filled with glass or a ceramic material. The insulating plate 20 is preferably flexible and may be formed of, for example, a material containing a thermosetting resin. The insulating plate 20 may also be called an insulating layer or an insulating film.

[0019] The heat sink 21 has a predetermined thickness in the Z direction and is rectangular in plan view. The heat sink 21 is formed of a metal plate with good thermal conductivity, such as copper or aluminum. The heat sink 21 is disposed on the lower surface of the insulating plate 20. The lower surface of the heat sink 21 is the surface to be attached to the cooler 10. The lower surface of the heat sink 21 also functions as a heat dissipation surface (heat dissipation area) for dissipating heat from the semiconductor module 1. The heat sink 21 is bonded to the upper surface of the cooler 10 via a bonding material (not shown) such as solder. The heat sink 21 may be disposed on the upper surface of the cooler 10 via a thermally conductive material such as thermal grease or thermal compound.

[0020] The multiple circuit boards 22-25 each have a predetermined thickness and are arranged at predetermined locations on the upper surface of insulating plate 20. Each circuit board is formed as an electrically independent island. For example, circuit board 22 (first circuit board) has a rectangular shape in plan view that is long in the X direction, and is arranged on insulating plate 20 offset toward the positive side in the Y direction.

[0021] Circuit board 23 (second circuit board) has a rectangular (or square) shape in a plan view, and is disposed adjacent to circuit board 22 on the negative side in the Y direction. More specifically, circuit board 23 is biased toward the negative side in the Y direction on insulating plate 20, and is disposed approximately in the center in the X direction. As will be described in detail later, circuit boards 22 and 23 form part of a main current path through which a main current flows.

[0022] Circuit board 24 (third circuit board) has a rectangular (or square) shape in plan view, and is disposed on insulating plate 20 at a corner on the positive side in the X direction and the negative side in the Y direction. That is, the rectangular portion of circuit board 24 is disposed adjacent to circuit board 23 on the positive side in the X direction and adjacent to circuit board 22 on the negative side in the Y direction. Circuit board 24 also has an elongated portion extending from an end of one side of the rectangle toward the negative side in the Y direction. This elongated portion passes under metal wiring board 4 (connecting portion 42), which will be described later.

[0023] Circuit board 25 (fourth circuit board) has a rectangular (or square) shape in plan view, and is disposed on insulating plate 20 at a corner on the negative side in the X direction and the negative side in the Y direction. That is, the rectangular portion of circuit board 25 is disposed adjacent to circuit board 23 on the negative side in the X direction and adjacent to circuit board 22 on the negative side in the Y direction. Circuit board 25 also has a long portion extending from an end of one side of the rectangle toward the positive side in the Y direction. This long portion passes under metal wiring board 4 (connecting portion 42), which will be described later. Circuit board 23 is disposed so as to be sandwiched between circuit boards 24 and 25 in the X direction. Circuit boards 24 and 25 function as circuit boards for relaying control signals (part of the control signal path).

[0024] The shape, location, and number of each circuit board configured in this manner are not limited to those described above and can be changed as appropriate. Furthermore, these circuit boards 22-25 may be formed from metal plates with good thermal conductivity, such as copper or aluminum. Furthermore, circuit boards 22-25 may also be called circuit layers or circuit patterns.

[0025] A plurality of (two in this embodiment) semiconductor elements 3 are arranged on the upper surface of the circuit board 22 via a bonding material S such as solder. The semiconductor elements 3 are formed of a semiconductor substrate such as silicon (Si) and have a rectangular shape in a plan view.

[0026] In addition, the semiconductor element 3 may be composed of a wide bandgap semiconductor element (which may also be called a wide bandgap semiconductor element) formed from a wide bandgap semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), diamond, etc., in addition to the silicon mentioned above.

[0027] The semiconductor element 3 may be a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a diode such as an FWD (Free Wheeling Diode).

[0028] For example, as shown in Fig. 4, the semiconductor element 3 may be configured with a MOSFET. The MOSFET may have a built-in diode (FWD, which will be described later). In this embodiment, a SiC-MOSFET with a built-in diode will be described as an example. Alternatively, the semiconductor element 3 may be configured with an RC (Reverse Conducting)-IGBT element that combines the functions of an IGBT (Insulated Gate Bipolar Transistor) element and an FWD (Free Wheeling Diode) element.

[0029] Furthermore, the semiconductor element is not limited to this, and may be configured by combining the above-mentioned switching elements, diodes, etc. For example, an IGBT element and an FWD element may be configured separately. Furthermore, an RB (Reverse Blocking)-IGBT or the like having sufficient voltage resistance against reverse bias may be used as the semiconductor element 3. Furthermore, the shape, number, and location of the semiconductor element 3 may be changed as appropriate.

[0030] The semiconductor element 3 configured in this manner has an upper surface and a lower surface on the XY plane, and electrodes are formed on each surface. For example, a main electrode 30a and a gate electrode 31 are formed on the upper surface of the semiconductor element 3, and a main electrode 30b is formed on the lower surface of the semiconductor element 3.

[0031] For example, if the semiconductor element 3 is a MOSFET element, the main electrode 30a may be called a source electrode, and the main electrode 30b on the lower surface may be called a drain electrode. If the semiconductor element 3 is an IGBT element, the main electrode 30a may be called an emitter electrode, and the main electrode 30b on the lower surface may be called a collector electrode. Regardless of the type of element, the gate electrode 31 may be called a gate electrode. An auxiliary electrode 32 (see the modified example described later) may be provided on the upper surface of the semiconductor element 3 in addition to the main electrode 30a. The electrodes formed on the upper surface of the semiconductor element 3 (main electrodes 30a, 30a, gate electrode 31, and auxiliary electrode 32) may be collectively called upper electrodes, and the electrodes formed on the lower surface of the semiconductor element 3 may be called lower electrodes. Of the upper electrodes, the gate electrode 31 and auxiliary electrode 32 may be called control electrodes.

[0032] In this embodiment, the main electrode 30a is an electrode through which the main current flows, and is formed in a rectangular shape in plan view having an area covering most of the upper surface of the semiconductor element 3. On the other hand, the gate electrode 31 is an electrode for controlling a gate for turning the main current on and off, and is formed in a rectangular shape in plan view that is sufficiently smaller than the main electrode 30a, and is disposed biased to one side of the semiconductor element 3. The arrangement of each electrode is not limited to this and can be changed as appropriate.

[0033] Furthermore, the semiconductor element 3 in this embodiment may be a so-called vertical switching element in which functional elements such as transistors are formed in the thickness direction of a semiconductor substrate, or may be a horizontal switching element in which these functional elements are formed in the surface direction.

[0034] The main electrode 30a of the semiconductor element 3 and the upper surface of the circuit board 23 are electrically connected by the metal wiring board 4. The metal wiring board 4 constitutes a main current wiring member and functions as part of the path of the main current flowing inside the semiconductor module 1 (main current path).

[0035] The metal wiring board 4 is formed as a plate-like body having an upper surface and a lower surface. The thickness of the metal wiring board 4 may be 0.1 mm or more and 2.5 mm or less. The metal wiring board 4 is formed from a metal material such as copper, copper alloy, aluminum alloy, or iron alloy. The metal wiring board 4 is formed into a predetermined shape, for example, by press working. Note that the shape of the metal wiring board 4 shown below is merely an example and can be modified as appropriate. The metal wiring board 4 may also be called a lead frame. Note that the main current wiring member is not limited to the metal wiring board 4, and may be formed from bonding wires.

[0036] The metal wiring board 4 according to this embodiment has a T-shape in plan view and is bent multiple times in side view. Specifically, the metal wiring board 4 includes two first bonding portions 40 bonded to the main electrode 30a via a bonding material S, a second bonding portion 41 bonded to the upper surface of the circuit board 23 via the bonding material S, and a connecting portion 42 connecting the first bonding portions 40 and the second bonding portions 41. The bonding material S may be any conductive material, such as solder or a sintered metal material.

[0037] The first bonding portion 40 is formed in a rectangular shape smaller than the outer shape of the semiconductor element 3 (main electrode 30a) in a plan view, has upper and lower surfaces on the XY plane, and includes a plate-like portion having a thickness in the Z direction. In this embodiment, two first bonding portions 40 are provided corresponding to the number of semiconductor elements 3. The two first bonding portions 40 are arranged side by side in the X direction and are connected to a connecting portion 42 between them. The first bonding portion 40 is arranged opposite the upper electrode (main electrode 30a) of the semiconductor element 3 in the Z direction and is joined via a bonding material S.

[0038] Second joint portion 41 is formed in a rectangular shape that is smaller than the outline of circuit board 23 in a plan view, has upper and lower surfaces on the XY plane, and includes a plate-like portion that is thick in the Z direction. One end of second joint portion 41 is joined to circuit board 23, while the other end of second joint portion 41 is connected to connecting portion 42.

[0039] The connecting portion 42 comprises two first rising portions that rise from the respective edges of the two first joints 40 corresponding to the number of semiconductor elements 3 on the positive side of the Z direction, have a flat surface on the YZ plane, and have a thickness in the X direction; a second rising portion that rises from the edge of the second joint 41 on the positive side of the Z direction, have a flat surface on the XZ plane, and have a thickness in the Y direction; and a connecting portion that has upper and lower surfaces on the XY plane, has a thickness in the Z direction, and connects the first rising portion and the second rising portion.

[0040] A case 5 is disposed on the outer periphery of the laminated substrate 2. The case 5 is formed in a rectangular frame shape in a plan view so as to surround the outer periphery of the laminated substrate 2, and has a rectangular opening 5a in the center. Specifically, the case 5 has a pair of side walls 50 facing each other in the X direction and a pair of side walls 51 facing each other in the Y direction, and the ends of each are connected to form a rectangular frame shape. In this way, the case 5 surrounds the laminated substrate 2 and houses the semiconductor element 3 and the metal wiring board 4 inside.

[0041] The pair of side walls 50 rise in the Z direction and extend in the Y direction. The pair of side walls 51 rise in the Z direction and extend in the X direction. A step 52 is formed on the inside of each of the side walls 50 and 51.

[0042] The case 5 is also provided with main terminals 60, 61 for main current and control terminals for control (a gate terminal 62, a first auxiliary terminal 63, and a second auxiliary terminal 64, which will be described later). The main terminals 60, 61 are formed of elongated plate-like bodies and are embedded in the approximate center of each side wall 51 in the X direction. The main terminals 60, 61 are arranged to face each other in the Y direction.

[0043] The main terminal 60 constitutes a positive terminal (P terminal) and is embedded in the side wall 51 on the positive side in the Y direction. One end of the main terminal 60 protrudes outward (toward the positive side in the Y direction) from the side wall 51. The other end of the main terminal 60 is electrically connected to the circuit board 22 on the inside of the side wall 51. Therefore, the main terminal 60 is electrically connected to the main electrode 30b (lower electrode) of the semiconductor element 3 via the circuit board 22.

[0044] The main terminal 61 constitutes a negative terminal (N terminal) and is embedded in the side wall 51 on the negative side in the Y direction. One end of the main terminal 61 protrudes outward (toward the negative side in the Y direction) from the side wall 51. The other end of the main terminal 61 is electrically connected to the circuit board 23 on the inside of the side wall 51. Therefore, the main terminal 61 is electrically connected to the main electrode 30a of the semiconductor element 3 via the circuit board 23 and the metal wiring board 4.

[0045] The control terminal is composed of a gate terminal 62, a first auxiliary terminal 63, and a second auxiliary terminal 64. The gate terminal 62, the first auxiliary terminal 63, and the second auxiliary terminal 64 are formed as long, plate-like bodies and embedded in the side wall 51 on the negative side in the Y direction. One end of each of the gate terminal 62, the first auxiliary terminal 63, and the second auxiliary terminal 64 protrudes outward (toward the negative side in the Y direction) from the side wall 51. The other end of each of the gate terminal 62, the first auxiliary terminal 63, and the second auxiliary terminal 64 penetrates the inside of the side wall 51 and is electrically connected to the circuit board 25 and the circuit board 24, respectively. Therefore, the gate terminal 62 is electrically connected to the gate electrode 31 of the semiconductor element 3, the first auxiliary terminal 63 is electrically connected to the main electrode 30a of the semiconductor element 3, and the second auxiliary terminal 64 is electrically connected to the main electrode 30a. The gate terminal 62, the first auxiliary terminal 63, and the second auxiliary terminal 64 are arranged to face each other in the X direction with the main terminal 61 in between. The first auxiliary terminal 63 and the second auxiliary terminal 64 are arranged side by side in the X direction on the positive side of the X direction of the main terminal 61. The first auxiliary terminal 63 is located on the positive side in the X direction, and the second auxiliary terminal is located on the negative side in the X direction.

[0046] The shapes, locations, and numbers of the main terminals 60, 61 and the control terminals are not limited to those described above and can be changed as appropriate. The first auxiliary terminal 63 and the second auxiliary terminal 64 may be called auxiliary emitter terminals or auxiliary source terminals depending on the type of semiconductor element 3.

[0047] Each control terminal and a predetermined electrode are electrically connected via a circuit board or bonding wire (which may be collectively referred to as control wiring). Specifically, the gate electrode 31 of each semiconductor element 3 is connected to the circuit board 25 via a gate wiring W1. The circuit board 25 is connected to the gate terminal 62 via a gate wiring W2. That is, the gate electrode 31 is electrically connected to the gate terminal 62 via the gate wiring W1, the circuit board 25, and the gate wiring W2.

[0048] Furthermore, each first joint 40 and the circuit board 24 are connected by an auxiliary wiring W3. The circuit board 24 is connected to the first auxiliary terminal 63 via the auxiliary wiring W4. That is, the main electrode 30a is electrically connected to the first auxiliary terminal 63 via the first joint 40, the auxiliary wiring W3, and the auxiliary wiring W4. As shown in FIG. 1, some of the gate wirings W1 and the auxiliary wiring W3 are arranged to intersect in a plan view.

[0049] In the present embodiment, the auxiliary wiring W3 connects the first joint portion 40 and the circuit board 24, but the present invention is not limited to this configuration. The auxiliary wiring W3 may directly connect the main electrode 30a and the circuit board 24. The auxiliary wiring W3 may also be called a first auxiliary wiring.

[0050] Furthermore, the circuit board 23 and the second auxiliary terminal 64 are connected by an auxiliary wire W5. As will be described in detail later, it is preferable that the angle formed between the auxiliary wire W5 and the auxiliary wire W3 is 90 degrees or less.

[0051] The wirings W1-W5 are made of conductive wires (bonding wires). The wires may be made of any one of gold, copper, aluminum, gold alloys, copper alloys, and aluminum alloys, or a combination thereof. Materials other than wires may also be used as the wirings. For example, ribbons may be used as the wiring materials.

[0052] As shown in FIG. 4, in this embodiment, between the upper surface electrode (main electrode 30a) of the semiconductor element 3 and the first auxiliary terminal 63, there is provided a first path r1 electrically connected to the first auxiliary terminal 63 via the upper surface electrode (main electrode 30a), auxiliary wiring W3, circuit board 24, and auxiliary wiring W4, and a second path r2 electrically connected to the second auxiliary terminal 64 from the upper surface electrode (main electrode 30a) via the metal wiring board 4, circuit board 23, and auxiliary wiring W5 in this order.

[0053] In addition, a main current path R is provided between the main terminals 60 and 61, electrically connected from the main terminal 60 to the main terminal 61 via the circuit board 22, the main electrodes 30b and 30a of the semiconductor element 3, the metal wiring board 4, and the circuit board 23 in this order. In addition, a gate path is provided between the gate electrode 31 and the gate terminal 62, electrically connected from the gate electrode 31 to the gate terminal 62 via the gate wiring W1, the circuit board 25, and the gate wiring W2 in this order (in FIG. 4, this is the path from the gate electrode 31 to the gate terminal 62).

[0054] The internal space defined by the frame-shaped case 5 is filled with sealing resin 7. The sealing resin 7 seals the laminated substrate 2, the plurality of semiconductor elements 3, the metal wiring board 4, the wiring W1-W5, etc. within the space. In other words, the case 5 defines (forms) an internal space that houses these components (the laminated substrate 2, the plurality of semiconductor elements 3, the metal wiring board 4, the wiring W1-W5, etc.). The internal space may also be called an internal region.

[0055] The sealing resin 7 is made of a thermosetting resin. The sealing resin 7 preferably contains at least one of epoxy, silicone, urethane, polyimide, polyamide, and polyamideimide. For example, an epoxy resin mixed with a filler is suitable for the sealing resin 7 in terms of insulation, heat resistance, and heat dissipation.

[0056] In a semiconductor device, a gate wiring is connected to a gate electrode of a semiconductor element as a control wiring. The gate wiring is necessary for controlling the switching operation of the semiconductor element, and is provided for each semiconductor element.

[0057] In addition, auxiliary wiring (which may be called auxiliary source wiring or auxiliary emitter wiring) is provided in each semiconductor element corresponding to each gate wiring. This auxiliary wiring makes it possible to stably apply a control voltage between the main electrodes (which may be called gate-source or gate-emitter) on the top and bottom surfaces of each semiconductor element, even if a main current flows in the main circuit and a potential difference occurs. It is also possible to suppress oscillations and delays in switching time that may occur due to misalignment of the on / off timing (switching timing) of each semiconductor element.

[0058] The above-mentioned auxiliary wiring is preferably arranged at a potential (which may be referred to as an auxiliary source potential or an auxiliary emitter potential) relatively far from the main circuit so as to be isolated from the main circuit through which the main current flows. Examples of such potentials include the vicinity of or the top surface of a semiconductor element. On the other hand, if one end of the auxiliary wiring is connected to the vicinity of or the top surface of a semiconductor element, the thermal stress and thermal cycles associated with switching the main current may cause the auxiliary wiring joint to deteriorate prematurely and break. Furthermore, this type of control wiring has a smaller cross-sectional area than the wiring constituting the main circuit because it carries a smaller current than the main circuit. Furthermore, it is often formed using bonding wire with a small diameter, which makes it more susceptible to breakage.

[0059] The gate wiring is also bonded to the upper surface of the semiconductor element, so the same phenomenon as the auxiliary wiring can occur. However, in the case of the gate wiring, even if the wiring is broken, the gate potential becomes unstable, and the switching of the semiconductor element cannot be turned on in the first place.

[0060] On the other hand, if the auxiliary wiring is broken, the reference potential between the control circuit (drive circuit) and the main circuit will not be stable, and there is a risk of an overvoltage being applied to the gate electrode. As a result, it is expected that the semiconductor element or the control circuit will be destroyed by the gate overvoltage. In other words, in a power module that handles large currents, a break in the auxiliary wiring will have a greater impact on the entire device than a break in the gate wiring.

[0061] Therefore, the inventor of the present invention conceived the present invention with the objective of preventing the device from being immediately destroyed even if the auxiliary wiring is broken, and of detecting the breakage early and shutting down the device stably.

[0062] In the present invention, in addition to the conventional auxiliary wiring (first auxiliary wiring) and auxiliary terminal (first auxiliary terminal), another auxiliary wiring (second auxiliary wiring) and auxiliary terminal (second auxiliary terminal) are provided. The first auxiliary wiring is connected to a location relatively close to the semiconductor element (e.g., the top surface of the semiconductor element), while the second auxiliary wiring is connected to a location relatively far from the semiconductor element. This makes the second auxiliary wiring less susceptible to the heat of the semiconductor element than the first auxiliary wiring. Therefore, the life of the second auxiliary wiring can be longer than that of the first auxiliary wiring. Therefore, even if the first auxiliary wiring is broken, the device will not be immediately destroyed because the second auxiliary wiring still remains. Furthermore, by dividing the auxiliary wiring into two and the auxiliary terminal into two, even if one auxiliary wiring is broken and the output becomes unstable, the other auxiliary wiring and auxiliary terminal can ensure output stability. Furthermore, by varying the signals of the first auxiliary wiring and the second auxiliary wiring, a break in the first auxiliary wiring can be detected early, allowing the device to be safely shut down.

[0063] For example, before the first auxiliary wiring is disconnected, that is, when the semiconductor module 1 is operating normally, when the switching is turned on (or off), the output changes significantly at a predetermined timing.

[0064] On the other hand, if the first auxiliary wiring is disconnected, the reference potential of the control circuit and the semiconductor element is maintained via the second auxiliary wiring. This makes it possible to prevent damage to the control circuit or the semiconductor element. Furthermore, if the second auxiliary wiring is used, it is possible to intentionally slow down the switching speed. Specifically, if the first auxiliary wiring is disconnected, the timing at which switching is turned on (or off) and the output changes significantly will be delayed by a predetermined time.

[0065] In this way, if the device can detect that the switching timing has been delayed by a predetermined time, it becomes possible to discover early that the first auxiliary wiring has been disconnected. In this case, the operation of the device itself will not become unstable, and the device can be safely shut down.

[0066] Therefore, in the present invention, by providing a second auxiliary wiring as a backup for the first auxiliary wiring, even if the first auxiliary wiring is broken, the reference potential of the circuit is secured via the second auxiliary wiring instead. This makes it possible to prevent the entire device from being immediately destroyed. Furthermore, by delaying the switching operation when the second auxiliary wiring is used, it is possible to easily detect a break in the first auxiliary wiring. As mentioned above, it is not necessary to provide a difference in switching timing between the first auxiliary wiring and the second auxiliary wiring. The presence of two auxiliary terminals (first auxiliary terminal 63 and second auxiliary terminal 64) allows the device to clearly recognize the difference in output, making it possible to quickly detect a break in either auxiliary wiring.

[0067] A specific wiring structure in this embodiment will be described below. Fig. 5 is a partially enlarged view of Fig. 1.

[0068] As shown in Figures 1 and 5, this embodiment includes a plurality of semiconductor elements 3 each having at least a main electrode 30a and a gate electrode 31 formed on its upper surface, a laminated substrate 2 having a plurality of circuit boards arranged on the upper surface of an insulating plate 20, a main terminal 61 electrically connected to the main electrode 30a, a gate terminal 62 electrically connected to the gate electrode 31, a first auxiliary terminal 63 and a second auxiliary terminal 64 electrically connected to the main electrode 30a, and a metal wiring plate 4 electrically connecting the main electrode 30a and the main terminal 61.

[0069] The plurality of circuit boards also include a circuit board 22 (first circuit board) having a semiconductor element 3 disposed on its upper surface, and a circuit board 23 (second circuit board) that electrically connects a main terminal 61 and a metal wiring board 4. The gate electrode 31 and the gate terminal 62 are connected via a gate wiring W1. The main electrode 30a or the metal wiring board 4 and a first auxiliary terminal 63 are connected via an auxiliary wiring W3 (first auxiliary wiring). The circuit board 23 and a second auxiliary terminal 64 are connected via an auxiliary wiring W5 (second auxiliary wiring).

[0070] In this case, the connection point of the auxiliary wiring W3 is near the semiconductor element 3. On the other hand, the connection point of the auxiliary wiring W5 is located on the circuit board 23, which is farther from the semiconductor element 3. Therefore, the connection point of the auxiliary wiring W5 can be located farther from the semiconductor element 3 than the connection point of the auxiliary wiring W3. Therefore, the auxiliary wiring W5 is less susceptible to the heat of the semiconductor element 3 than the auxiliary wiring W3. Furthermore, the auxiliary wiring W3 is connected to the first joint 40 of the metal wiring board 4, which is connected to the main electrode 30a of the semiconductor element 3. On the other hand, the auxiliary wiring W5 is connected to the circuit board 23. The circuit board 23 is cooled via the insulating plate 20 and the heat sink 21, so its temperature is less likely to rise. Therefore, the auxiliary wiring W5 is less susceptible to the heat of the semiconductor element 3 than the auxiliary wiring W3. As a result, the life of the auxiliary wiring W5 can be longer than that of the auxiliary wiring W3. Therefore, the auxiliary wiring W5 can be effectively used as a backup for the auxiliary wiring W3.

[0071] In this embodiment, an independent circuit board 24 (third circuit board) and a circuit board 25 (fourth circuit board) are provided. The circuit board 24 relays the auxiliary wirings W3 and W4 between the main electrode 30a and the first auxiliary terminal 63. The circuit board 25 relays the gate wirings W1 and W2 between the gate electrode 31 and the gate terminal 62.

[0072] In this way, by using the independent circuit board 24 or circuit board 25 as a relay point for the wiring, it is possible to ensure sufficient space for the connection point (bonding point) of the wiring compared to when the wiring from the semiconductor element 3 is directly connected to the control terminal (first auxiliary terminal 63 or gate terminal 62). As a result, it is possible to miniaturize the control terminal to the minimum size.

[0073] It is also preferable that the circuit boards 23 and 24 are at the same potential, which makes it possible to ensure a reference potential between the control circuit and the main circuit.

[0074] Furthermore, it is preferable that the current path from the semiconductor element 3 via the auxiliary wiring W5 is longer than the current path from the semiconductor element 3 via the auxiliary wiring W3. In other words, it is preferable that the impedance in the current path from the semiconductor element 3 via the auxiliary wiring W5 is larger than the impedance in the current path from the semiconductor element 3 via the auxiliary wiring W3. With these configurations, a difference in impedance is created in a given current path, making it possible to create a difference in the switching speed (timing) before and after the auxiliary wiring W3 breaks. Therefore, by detecting this difference on the device side, it is possible to recognize whether or not a break has occurred.

[0075] 5, the connection point of the auxiliary wiring W5 on the circuit board 23 is preferably located at a position offset from the main current path R between the metal wiring board 4 (second joint 41) and the main terminal 61. More specifically, the connection point of the auxiliary wiring W5 may be formed at a position outside the area connecting the joint point of the metal wiring board 4 (second joint 41) and the joint point of the main terminal 61. More preferably, the connection point of the auxiliary wiring W5 is located farther from the main terminal 61 than the joint point of the metal wiring board 4 (second joint 41). With this configuration, the current path via the auxiliary wiring W5 is away from the main circuit, making it less susceptible to the influence of the main current.

[0076] In the present embodiment, the angle formed by the auxiliary wirings W3 and W5 in plan view is preferably 90 degrees or less. This configuration makes it easier to differentiate the respective current paths.

[0077] Furthermore, one or more auxiliary wirings W3 are arranged for the plurality of semiconductor elements 3 connected in parallel. Preferably, one auxiliary wiring W3 is arranged corresponding to each of the plurality of semiconductor elements 3 connected in parallel. With this configuration, since the auxiliary wiring W3 is provided corresponding to each semiconductor element 3, stable switching control can be performed.

[0078] In this embodiment, the semiconductor element 3 is preferably formed of a wide bandgap semiconductor. Wide bandgap semiconductors can carry larger currents than silicon semiconductors and can also operate at high temperatures. With this configuration, the effects of the present invention are more pronounced in a semiconductor module that uses a wide bandgap semiconductor and operates at high temperatures with large currents.

[0079] As described above, according to this embodiment, in addition to the first auxiliary wiring, a backup second auxiliary wiring is provided, and by creating a difference in switching timing before and after the first auxiliary wiring breaks, it is possible to detect the break early and prevent destruction of the device.

[0080] Next, modified examples will be described with reference to Figs. 6 to 12. Fig. 6 is a plan view showing a semiconductor device according to a modified example. Fig. 7 is an equivalent circuit diagram of the semiconductor device according to the modified example of Fig. 6. Fig. 8 is a plan view showing a semiconductor device according to another modified example. Fig. 9 is an equivalent circuit diagram of the semiconductor device according to the modified example of Fig. 8. Fig. 10 is a plan view of a semiconductor device showing a variation of Fig. 1. Fig. 11 is an equivalent circuit diagram of a semiconductor device showing a variation of Fig. 4. Fig. 12 is an equivalent circuit diagram of a semiconductor device showing another variation of Fig. 4. Note that in the following modified examples, components already mentioned will be designated by the same names and symbols, and explanations will be omitted as appropriate. In the modified examples, differences will mainly be described.

[0081] 6 and 7 has a rectangular shape in plan view that is long in the X direction. In FIG. 6, circuit board 23 has a U-shape in plan view, with circuit board 22 disposed inside the U. A notch extending in the Y direction is formed in the center of circuit board 22. Circuit boards 24 and 25 are disposed in this notch. Circuit boards 24 and 25 have elongated shapes that extend in the Y direction and are disposed side by side in the X direction. Circuit board 24 is located on the positive side of the X direction, and circuit board 25 is located on the negative side of the X direction.

[0082] Two circuit boards 26 are arranged on the upper surface of the insulating plate 20, inside the side wall 51 on the positive side in the Y direction. In a plan view, the circuit boards 26 have an elongated shape extending in the Y direction along the side wall 51. The two circuit boards 26 face each other in the X direction, with the main terminal 60 sandwiched between them.

[0083] On the negative side in the X direction, the end of circuit board 23 and the end of circuit board 26 are connected by auxiliary wiring W5. The two circuit boards 26 are also connected to each other by another auxiliary wiring W5. This auxiliary wiring W5 straddles above main terminal 60. The end of circuit board 26 located on the positive side in the X direction is connected to second auxiliary terminal 64 by yet another auxiliary wiring W5. Thus, in FIG. 6, a backup auxiliary wiring (second auxiliary wiring) is formed to extend along the long side of the module. In this case, the two circuit boards 26 form part of the second auxiliary wiring. That is, the second auxiliary wiring is not limited to a wire, and may be formed by a circuit board of a predetermined thickness. The second auxiliary wiring is sufficiently longer than the first auxiliary wiring.

[0084] An auxiliary electrode 32 is formed on the top surface of the semiconductor element 3 separately from the main electrode 30a. The auxiliary electrode 32 may be electrically connected to the main electrode 30a. In FIG. 6, one metal wiring plate 4 is provided for one semiconductor element 3. The side wall 50 of the case is shorter than the side wall 51. The gate terminal 62, the first auxiliary terminal 63, and the second auxiliary terminal 64 are embedded in the side wall 50 on the positive side in the X direction and are arranged side by side in the Y direction. The second auxiliary terminal 64, the first auxiliary terminal 63, and the gate terminal 62 are arranged in this order from the positive side in the Y direction.

[0085] In Fig. 6, one end of auxiliary wiring W3 is joined to auxiliary electrode 32 instead of main electrode 30a. In this case, main electrode 30a and auxiliary electrode 32 are preferably at the same potential. In the modification of Fig. 6, wirings W1-W5 do not overlap each other in plan view. Even with this layout, it is possible to obtain the same effects as those of the above-described embodiment.

[0086] 8 and 9, main terminals 60 and 61 are arranged side by side on the side wall 51 on the negative side in the Y direction. Meanwhile, another main terminal 65 is arranged on the side wall 51 on the positive side in the Y direction. The main terminal 65 is connected to the circuit board 22. The main terminal 65 may also be called an intermediate terminal (M terminal).

[0087] In Fig. 8, two circuit boards 22, each having a portion extending in the Y direction, are arranged side by side in the X direction. Two semiconductor elements 3 are arranged side by side in the Y direction on each circuit board 22. That is, in the modified example shown in Fig. 8, four semiconductor elements 3 are arranged to form a 2 x 2 matrix. For example, the two semiconductor elements 3 on the positive side in the X direction may form an upper arm, and the two semiconductor elements 3 on the negative side in the X direction may form a lower arm.

[0088] A notch extending in the X direction is formed in the center of each circuit board 22. Circuit boards 24 and 25 are arranged in this notch. Circuit boards 24 and 25 have an elongated shape extending in the X direction and are arranged side by side in the Y direction.

[0089] In FIG. 8 , the gate terminal 62, the first auxiliary terminal 63, and the second auxiliary terminal 64 are arranged as a set, and the set of three control terminals is disposed on each of the upper and lower arms. That is, two gate terminals 62, two first auxiliary terminals 63, and two second auxiliary terminals 64 are disposed. The gate terminals 62, the first auxiliary terminals 63, and the second auxiliary terminals 64 are disposed on the side wall 51 on the positive side in the Y direction. The set of control terminals on the upper arm side is disposed on the positive side in the X direction, and the set of control terminals is disposed on the negative side in the X direction. The above-described wiring is connected to each terminal. For example, the second auxiliary terminal 64 of the upper arm and the circuit board 22 of the lower arm are connected by auxiliary wiring W5. The second auxiliary terminal 64 of the lower arm and the circuit board 23 are connected by another auxiliary wiring W5. Even with this configuration, it is possible to obtain the same effects as those of the above-described embodiment.

[0090] 1, the case where one end of the auxiliary wiring W3 is connected to the upper surface of the first joint 40 has been described, but the present invention is not limited to this configuration. For example, as shown in FIG. 10, one end of the auxiliary wiring W3 may be directly connected to the upper surface of the main electrode 30a.

[0091] 11, a wiring may be further provided between the first auxiliary terminal 63 and the second auxiliary terminal 64 and an external control device, electrically connecting the first auxiliary terminal 63 and the second auxiliary terminal 64. The first auxiliary terminal 63 and the second auxiliary terminal 64 are electrically connected at a connection point. In this case, the wiring between the second auxiliary terminal 64 and the connection point may have a resistance (impedance) R1.

[0092] 12, the wiring between the first auxiliary terminal 63 and the connection point may further have a resistance (impedance) R2. In this case, it is preferable that the resistance R2 is larger than the resistance R1. By varying the impedance, it is possible to create differences in switching timing, and it is possible to clearly recognize a change in output when the wiring is broken.

[0093] A vehicle to which the present invention is applied will be described with reference to Fig. 13. Fig. 13 is a schematic plan view showing an example of a vehicle to which the semiconductor device of the present invention is applied. Vehicle 101 shown in Fig. 13 is, for example, a four-wheeled vehicle equipped with four wheels 102. Vehicle 101 may be, for example, an electric vehicle in which the wheels are driven by a motor or the like, or a hybrid vehicle that uses power from an internal combustion engine in addition to a motor.

[0094] The vehicle 101 includes a drive unit 103 that applies power to the wheels 102, and a control device 104 that controls the drive unit 103. The drive unit 103 may be configured with at least one of an engine, a motor, or a hybrid of an engine and a motor, for example.

[0095] The control device 104 controls (for example, controls power) the above-described drive unit 103. The control device 104 includes the above-described semiconductor device 100. The semiconductor device 100 may be configured to control power to the drive unit 103.

[0096] Furthermore, in the above embodiment, the number and arrangement of the semiconductor elements 3 are not limited to the above configuration, and can be changed as appropriate.

[0097] Furthermore, in the above embodiment, the number and layout of the circuit boards are not limited to the above configuration, and can be changed as appropriate.

[0098] In the above embodiment, the laminated substrate 2 and the semiconductor element 3 are configured to be rectangular or square in plan view, but are not limited to this configuration. These configurations may be configured to be polygonal shapes other than those described above.

[0099] Furthermore, although the present embodiment and modifications have been described, other embodiments may be combinations of the above-described embodiments and modifications in whole or in part.

[0100] Furthermore, the present embodiment is not limited to the above-described embodiments and modifications, and may be variously changed, substituted, or modified within the scope of the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or derived other technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea.

[0101] The features of the above embodiment are summarized below. a first main terminal electrically connected to the first main electrode; a first auxiliary terminal and a second auxiliary terminal electrically connected to the top electrode; and a main current wiring member electrically connecting the first main electrode to the first main terminal. Between the first main electrode and the first main terminal, a main current path is provided electrically connected from the first main electrode to the first main terminal via the main current wiring member and the second circuit board in this order. Between the top electrode and the first auxiliary terminal, a first path is provided electrically connected from the top electrode to the first auxiliary terminal via the first auxiliary wiring. Between the top electrode and the second auxiliary terminal, a second path is provided electrically connected from the top electrode to the second auxiliary terminal via the main current wiring member, the second circuit board, and the second auxiliary wiring in this order.

[0102] In the semiconductor module according to the above embodiment, the main current wiring member is made of a metal plate-like body, and the first auxiliary wiring and the second auxiliary wiring are made of metal wires.

[0103] In the semiconductor module according to the above embodiment, one end of the first auxiliary wiring is connected to the upper surface of the main current wiring member disposed opposite the first main electrode.

[0104] In the semiconductor module according to the above embodiment, one end of the first auxiliary wiring is connected to the upper surface of the first main electrode.

[0105] Furthermore, in the semiconductor module according to the above embodiment, the semiconductor element further has an auxiliary electrode electrically connected to the first main electrode as the upper surface electrode, and one end of the first auxiliary wiring is connected to the upper surface of the auxiliary electrode.

[0106] In the semiconductor module according to the above embodiment, the connection point of the second auxiliary wiring is farther from the semiconductor element than the connection point of the first auxiliary wiring.

[0107] In the semiconductor module according to the above embodiment, the plurality of circuit boards further include a third circuit board that relays between the first auxiliary wiring and the first auxiliary terminal.

[0108] Furthermore, in the semiconductor module according to the above embodiment, the semiconductor element further has a gate electrode as the upper surface electrode, and further has a gate terminal electrically connected to the gate electrode, and a gate path is provided between the gate electrode and the gate terminal, electrically connected to the gate terminal via a gate wiring joined from the gate electrode to the gate electrode and a fourth circuit board further provided as one of the plurality of circuit boards, in this order.

[0109] In the semiconductor module according to the above embodiment, the second path is longer than the first path.

[0110] In the semiconductor module according to the above embodiment, the impedance of the second path is greater than the impedance of the first path.

[0111] In the semiconductor module according to the above embodiment, the connection point of the second auxiliary wiring on the second circuit board is provided at a position shifted from the main current path between the main current wiring member and the main terminal.

[0112] In the semiconductor module according to the above embodiment, the angle formed between the first auxiliary wiring and the second auxiliary wiring is 90 degrees or less in plan view.

[0113] In the semiconductor module according to the above embodiment, the first auxiliary wiring is disposed one for each of the plurality of semiconductor elements.

[0114] In the semiconductor module according to the above embodiment, the semiconductor element is formed of a wide bandgap semiconductor.

[0115] In addition, the semiconductor module according to the above embodiment further includes wiring between the first auxiliary terminal and the second auxiliary terminal and an external control device, electrically connecting the first auxiliary terminal and the second auxiliary terminal, and the first auxiliary terminal and the second auxiliary terminal are electrically connected at a connection point.

[0116] In the semiconductor module according to the above embodiment, the impedance from the first auxiliary terminal to the connection point is greater than the impedance from the second auxiliary terminal to the connection point.

[0117] Furthermore, the semiconductor device according to the above embodiment includes the above semiconductor module and a cooler disposed on the lower surface of the laminated substrate.

[0118] Furthermore, the vehicle according to the above embodiment includes the above semiconductor module and semiconductor device. [Industrial Applicability]

[0119] As described above, the present invention has the effect of enabling early detection of a break in a specific wiring, and is particularly useful for semiconductor modules and semiconductor devices for industrial or electrical equipment (vehicle-mounted). [Explanation of symbols]

[0120] 1: Semiconductor module 2:Laminated substrate 3: Semiconductor elements 4: Metal wiring board (main current wiring material) 5: Case 5a: opening 7: Sealing resin 10:Cooler 20: Insulating plate 21: Heat sink 22: Circuit board (1st circuit board) 23: Circuit board (second circuit board) 24: Circuit board (3rd circuit board) 25: Circuit board (4th circuit board) 26: Circuit board (2nd auxiliary wiring) 30a: Main electrode (top electrode, 1st main electrode) 30b: Main electrode (bottom electrode, 2nd main electrode) 31: Gate electrode (top electrode, control electrode) 32: Auxiliary electrode (top electrode, control electrode) 40: 1st joint 41:Second joint 42:Connection part 50: Side wall 51: Side wall 52 :Double part 60: Main terminal (P terminal, 2nd main terminal) 61: Main terminal (N terminal, 1st main terminal) 62: Gate terminal 63: 1st auxiliary terminal 64: 2nd auxiliary terminal 65: Main terminal 100: Semiconductor device (M terminal, third main terminal) 101: Semiconductor device 102: Vehicle 103: Drive unit 104: Control device R: Main current path r1: First route r2: Route 2 R1: Resistor R2 :Resistance S: Bonding material W1: Gate wiring W2: Gate wiring W3: Auxiliary wiring (first auxiliary wiring) W4: Auxiliary wiring W5: Auxiliary wiring (second auxiliary wiring)

Claims

1. a semiconductor element having an upper surface electrode including at least a first main electrode formed on the upper surface; a laminated substrate having a plurality of circuit boards arranged on an upper surface of an insulating plate, the circuit boards including a first circuit board and a second circuit board on which the semiconductor element is arranged; a first main terminal electrically connected to the first main electrode; a first auxiliary terminal and a second auxiliary terminal electrically connected to the upper surface electrode; a main current wiring member electrically connecting the first main electrode and the first main terminal, a main current path is provided between the first main electrode and the first main terminal, the main current path being electrically connected from the first main electrode to the first main terminal via the main current wiring member and the second circuit board in this order; a first path is provided between the upper surface electrode and the first auxiliary terminal, the first path being electrically connected from the upper surface electrode to the first auxiliary terminal via a first auxiliary wiring; a second path is provided between the upper surface electrode and the second auxiliary terminal, the second path being electrically connected from the upper surface electrode to the second auxiliary terminal via the main current wiring member, the second circuit board, and a second auxiliary wiring in this order; The second auxiliary wiring maintains a reference potential of the semiconductor element.

2. A semiconductor module as described in claim 1, wherein the first auxiliary wiring maintains the reference potential of the semiconductor element.

3. The main current wiring member is formed of a metal plate-like body, 3. The semiconductor module according to claim 1, wherein the first auxiliary wiring and the second auxiliary wiring are made of metal wires.

4. 4. The semiconductor module according to claim 3, wherein one end of the first auxiliary wiring is connected to an upper surface of the main current wiring member disposed opposite the first main electrode.

5. 4. The semiconductor module according to claim 1, wherein one end of the first auxiliary wiring is connected to an upper surface of the first main electrode.

6. the semiconductor element further includes an auxiliary electrode as the upper surface electrode, the auxiliary electrode being electrically connected to the first main electrode; 4. The semiconductor module according to claim 1, wherein one end of the first auxiliary wiring is connected to an upper surface of the auxiliary electrode.

7. 7. The semiconductor module according to claim 1, wherein a connection point of the second auxiliary wiring is farther from the semiconductor element than a connection point of the first auxiliary wiring.

8. 8. The semiconductor module according to claim 1, wherein the plurality of circuit boards further include a third circuit board that relays between the first auxiliary wiring and the first auxiliary terminal.

9. the semiconductor element further includes a gate electrode as the upper surface electrode, further comprising a gate terminal electrically connected to the gate electrode; Between the gate electrode and the gate terminal, 9. The semiconductor module according to claim 1, further comprising a gate path electrically connected to the gate terminal through, in this order, a gate wiring joined to the gate electrode and a fourth circuit board further provided as one of the plurality of circuit boards.

10. 10. The semiconductor module according to claim 1, wherein the second path is longer than the first path.

11. 11. The semiconductor module according to claim 1, wherein the impedance of the second path is greater than the impedance of the first path.

12. 12. The semiconductor module according to claim 1, wherein a connection point of the second auxiliary wiring on the second circuit board is provided at a position offset from a main current path between the main current wiring member and the main terminal.

13. 13. The semiconductor module according to claim 1, wherein an angle formed between the first auxiliary wiring and the second auxiliary wiring is equal to or smaller than 90 degrees in a plan view.

14. 14. The semiconductor module according to claim 1, wherein the first auxiliary wiring is disposed for each of the plurality of semiconductor elements.

15. 15. The semiconductor module according to claim 1, wherein the semiconductor element is formed of a wide bandgap semiconductor.

16. a wiring electrically connecting the first auxiliary terminal and the second auxiliary terminal between the first auxiliary terminal and the second auxiliary terminal and an external control device; 16. The semiconductor module according to claim 1, wherein the first auxiliary terminal and the second auxiliary terminal are electrically connected at a connection point.

17. 17. The semiconductor module according to claim 16, wherein an impedance from the first auxiliary terminal to the connection point is greater than an impedance from the second auxiliary terminal to the connection point.

18. a semiconductor module according to any one of claims 1 to 17; a cooler disposed on the lower surface of the laminated substrate.

19. A vehicle comprising the semiconductor module according to any one of claims 1 to 17 or the semiconductor device according to claim 18.

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