Instruction generation device, system, method and program

Abstract

To make data access processing with a vector gather instruction more efficient to further reduce the execution time of the vector gather instruction.SOLUTION: An instruction generation device (1) comprises: a determination unit (11) which analyzes address arrays in access destinations of individual instructions resulting from conversion from a loop structure including a plurality of tasks of data access processing described in a source code to a plurality of first vector gather instructions, to determine whether addresses of corresponding elements among the address arrays in access destinations of the individual instructions are regularly continuous or not; a first generation unit (12) which, if they are regularly continuous, generates a plurality of block address arrays resulting from aggregating regularly continuous addresses with respect to each of the elements; and a second generation unit (13) which generates, from the loop structure, a second vector gather instruction which designates the plurality of block address arrays as an argument.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an instruction generation device, system, method, and program. [Background technology]

[0002] A computer processor that performs vector operations may use an indirect address reference load instruction, known as a vector gather instruction, to read data to be processed from cache memory or memory and store it all together in a register. A vector gather instruction is an instruction that allows the processor to access a wide range of addresses in memory to acquire (gather) data. Patent Document 1 discloses technology related to a function for detecting address overlaps in vector gather instructions. Patent Document 2 also discloses technology for checking multiple memory access instructions in response to a vector gather instruction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-052862 [Patent Document 2] Special Publication No. 2018-530830 Summary of the Invention [Problem to be solved by the invention]

[0004] The addresses of the access targets specified as arguments of a vector gather instruction are generally distributed irregularly in memory, leaving room for improvement in efficiency. The technology disclosed in Patent Document 1 detects duplicate addresses of the access targets, which limits the efficiency of the technology. Furthermore, the technology disclosed in Patent Document 2 requires checking each individual memory access instruction, which also limits the efficiency of the technology.

[0005] In view of the above-mentioned problems, an object of the present disclosure is to provide an instruction generation device, system, method, and program for further improving the efficiency of data access processing using vector gather instructions and further shortening the execution time of vector gather instructions. [Means for solving the problem]

[0006] An instruction generation device according to the present disclosure includes: a determining means for analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access operations described in a source code is converted into a plurality of first vector gather instructions, and determining whether or not there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction; a first generating means for generating a plurality of block address arrays by grouping together addresses for each element having the regular continuity when the regular continuity exists; a second generating means for generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; Equipped with.

[0007] The instruction generation system according to the present disclosure comprises: a storage device that stores the source code; an information processing device that receives the source code and outputs an object code; The information processing device includes: a determining means for analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access operations described in the source code is converted into a plurality of first vector gather instructions, and determining whether or not there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction; a first generating means for generating a plurality of block address arrays by grouping together addresses for each element having the regular continuity when the regular continuity exists; a second generating means for generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; Equipped with.

[0008] The instruction generation method according to the present disclosure includes: The computer analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access processes described in the source code is converted into a plurality of first vector gather instructions; determining whether there is regular continuity in the addresses of corresponding elements among the address arrays of each of the plurality of first vector gather instructions; If there is regular continuity, a plurality of block address arrays are generated by grouping the addresses for each element having the continuity; A second vector gather instruction is generated from the loop structure, with the array of block addresses designated as an argument.

[0009] The instruction generation program according to the present disclosure includes: a determination process of analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access operations written in the source code is converted into a plurality of first vector gather instructions, and determining whether or not there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction; a first generation process for generating a plurality of block address arrays by grouping addresses for each element having the regular continuity when the regular continuity exists; a second generation process for generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; to be executed by the computer. [Effects of the Invention]

[0010] The present disclosure makes it possible to provide an instruction generation device, system, method, and program for further improving the efficiency of data access processing using vector gather instructions and further shortening the execution time of vector gather instructions. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a configuration of an instruction generating device according to a first embodiment. [Figure 2] 1 is a flowchart showing the flow of an instruction generation method according to the first embodiment. [Figure 3] FIG. 10 is a diagram showing an example of source code written in Fortran in which a loop structure including multiple data access processes is described. [Figure 4] 10A and 10B are diagrams illustrating an example of an instruction format and an execution image of a first vector gather instruction according to the related art. [Figure 5] FIG. 1 is a diagram showing the relationship between an address array and address positions on a memory according to a related art. [Figure 6] FIG. 10 is a diagram for explaining the concept of data access by a first vector gather instruction according to the related art. [Figure 7] FIG. 10 is a block diagram showing the configuration of an instruction generation system according to a second embodiment. [Figure 8] 10 is a flowchart showing the flow of an instruction generation process according to the second embodiment. [Figure 9] 10A and 10B are diagrams illustrating an example of a regular continuity determination and a block address arrangement according to the second embodiment. [Figure 10] FIG. 10 is a diagram showing another example of determination of regular continuity according to the second embodiment. [Figure 11] 10A and 10B are diagrams illustrating an example of partially regular continuity determination and a block address arrangement according to the second embodiment. [Figure 12] FIG. 10 is a diagram showing the relationship between a block address array and address positions on a memory according to the second embodiment. [Figure 13] 10 is a diagram showing an example of an instruction format and an execution image of a vector gather block instruction (second vector gather instruction) according to the second embodiment. FIG. [Figure 14] FIG. 10 is a diagram for explaining the concept of data access by a second vector gather instruction according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or corresponding elements are designated by the same reference numerals, and for clarity of explanation, duplicate explanations will be omitted as necessary.

[0013] <Embodiment 1> FIG. 1 is a block diagram showing the configuration of an instruction generation device 1 according to the first embodiment. The instruction generation device 1 is an information processing device for generating object code including vector operation instructions from source code. Here, it is assumed that the source code describes a loop structure including multiple data access operations. It is also assumed that the instruction generation device 1 is capable of converting the loop structure into multiple first vector gather instructions. Here, the vector gather instruction is a vector operation instruction that reads data corresponding to each address in an address array specified in one instruction from a cache memory or memory and stores the data collectively in a register.

[0014] The instruction generation device 1 includes a determination unit 11, a first generation unit 12, and a second generation unit 13. The determination unit 11 analyzes the address array of the access destinations of each instruction when the loop structure is converted into a plurality of first vector gather instructions, and determines whether there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction. Here, "there is continuity in the addresses" means, for example, that the address of the first element in the first address array specified in a first instruction of the plurality of first vector gather instructions is continuous with the address of the first element in the second address array specified in the second instruction. Furthermore, "there is regular continuity" means that there is regularity in the continuity of the first element in the first to Nth address arrays (N is a natural number equal to or greater than 2) and the continuity of the second element in the first to Nth address arrays (N is a natural number equal to or greater than 2). "There is regular continuity" may also mean, for example, that there is a commonality in the continuity.

[0015] If there is regular continuity, the first generation unit 12 generates a plurality of block address arrays by grouping the addresses of each element having the continuity. The second generation unit 13 generates a second vector gather instruction that specifies the plurality of block address arrays as arguments from the loop structure.

[0016] 2 is a flowchart showing the flow of the instruction generation method according to the first embodiment. First, the determination unit 11 analyzes the address array of the access destinations of each instruction when a loop structure including multiple data access operations written in source code is converted into multiple first vector gather instructions (S11). Next, the determination unit 11 determines whether there is regular continuity in the addresses of corresponding elements among the address arrays of the multiple first vector gather instructions (S12). If it is determined in step S12 that there is regular continuity, the first generation unit 12 generates multiple block address arrays by grouping the addresses of each of the consecutive elements (S13). Thereafter, the second generation unit 13 generates a second vector gather instruction from the loop structure, specifying the multiple block address arrays as arguments (S14).

[0017] In this manner, in this embodiment, a group of addresses in which corresponding elements in the address arrays of a plurality of first vector gather instructions have continuity are grouped into a single block address array. Furthermore, a group of addresses in which elements in the address arrays of a plurality of first vector gather instructions have regular continuity are grouped into multiple different block address arrays. Then, a second vector gather instruction is generated that specifies the multiple block address arrays as arguments. Therefore, by executing the second vector gather instruction, data access processing is performed for each block address array in which consecutive addresses are grouped, thereby improving memory access efficiency. This further improves the efficiency of data access processing by the vector gather instruction, thereby further shortening the execution time of the vector gather instruction.

[0018] The instruction generation device 1 includes a processor, a memory, and a storage device (not shown). The storage device stores a computer program that implements the processing of the instruction generation method according to this embodiment. The processor then loads the computer program from the storage device into the memory and executes the computer program. This allows the processor to implement the functions of a determination unit 11, a first generation unit 12, and a second generation unit 13.

[0019] Alternatively, each component of the instruction generation device 1 may be realized by dedicated hardware. Furthermore, some or all of the components of each device may be realized by general-purpose or dedicated circuits, processors, etc., or a combination of these. These may be configured by a single chip, or by multiple chips connected via a bus. Some or all of the components of each device may be realized by a combination of the above-mentioned circuits, etc., and a program. Furthermore, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an FPGA (Field-Programmable Gate Array), a quantum processor (quantum computer control chip), etc., may be used as the processor.

[0020] Furthermore, when some or all of the components of the instruction generation device 1 are realized by multiple information processing devices, circuits, etc., the multiple information processing devices, circuits, etc. may be centrally or distributed. For example, the information processing devices, circuits, etc. may be realized as a client-server system, a cloud computing system, or the like, in a form in which each is connected via a communication network. Furthermore, the functions of the instruction generation device 1 may be provided in a SaaS (Software as a Service) format.

[0021] <Embodiment 2> Here, we will provide additional information on the problems to be solved by the embodiments of the present disclosure. First, the storage destinations of data elements accessed by a vector gather instruction are generally distributed irregularly in memory. Therefore, when a vector gather instruction is generated from a loop structure containing multiple data access operations written in source code, it is necessary to access memory widely in one instruction. When accessing memory widely, the probability that all of the data elements to be gathered are stored in cache memory is low. In addition, multiple pages of physical memory are accessed, so the execution time of a vector gather instruction is significantly longer than that of other instructions. As a result, the proportion of memory access time in the entire program tends to increase. Furthermore, longer memory access times can delay subsequent calculation instructions, leading to an increase in the overall program execution time. Therefore, it is important to speed up data access processing to memory.

[0022] Figure 3 shows an example of Fortran source code SC1, which describes a loop structure including multiple data access operations. Here, a random value is stored in each element of the integer array rand_index. A real-type two-dimensional array table with a size of 4 x 10000 is allocated in memory. The loop structure SC2 implements four data access operations that retrieve values ​​specified by the array rand_index(i) as the column number for row numbers 1 to 4 of the two-dimensional array table, with the loop counter i ranging from 1 to the upper limit iter (64 in this case).

[0023] Here, an existing compiler for vector operations converts the loop structure SC2 in the source code SC1 into four first vector gather instructions (vector gather instruction group SC3). Here, VGT is the first vector gather instruction, V0 is the address of the write destination vector register, and V11 to V14 are the read source address arrays, that is, arrays that store the addresses of the access destinations of the data to be read.

[0024] FIG. 4 shows an example of the instruction format and execution image of a first vector gather instruction according to the related art. Here, the instruction format of the first vector gather instruction is as follows: vx is the address of the write destination vector register, and vy is the read source address array. An example of the first vector gather instruction is "VGT V0, V1." In this execution image, when a processor (not shown) that performs vector operations executes "VGT V0, V1," it searches the cache memory 140. If a miss occurs, it performs memory access to the V1 area in the memory 130. At this time, as described above, the data corresponding to the V1 address array is stored in a distributed manner within the memory 130. Therefore, the processor performs memory access processing at multiple locations within the memory 130, reading data from the memory 130 to the cache memory 140 multiple times. The processor then stores the desired data from the cache memory 140 in the V0 area of ​​the register 151.

[0025] Figure 5 shows the relationship between address arrays and address locations in memory according to the related art. Here, specific examples of address arrays V11 to V14 shown in Figure 3 above and a memory address map are shown. V11 to V14 are address arrays each having iter elements. For example, V11 indicates that addresses [1][1], [1][4], ..., [1][N-2], and [1][N] are stored as elements. Furthermore, on the memory address map, addresses [1][1], [2][1], [3][1], [4][1], [1][2], ... are consecutive addresses. Therefore, the order of elements in the address array differs from the order of addresses in the address map.

[0026] FIG. 6 is a diagram illustrating the concept of data access by a first vector gather instruction according to the related art. For example, assume that a processor performing vector operations executes "VGT V0, V11" in FIG. 3 described above. At this time, as an internal process of the VGT, the processor first searches the cache memory 140 for the address [1][1] of the first element of V11 (S91). If a miss occurs, the processor accesses the memory 130 for data (S92). Then, the processor reads data at addresses [1][1], [2][1], [3][1], and [4][1] from the memory 130 and stores them in the cache memory 140 (S93). After that, the processor reads data at address [1][1] from the cache memory 140 and stores it in the register 151 (S94).

[0027] Next, the processor searches the cache memory 140 for the address [1][4] of the second element of V11 (S95). At this time, data at addresses [1][1], [2][1], [3][1], and [4][1] is stored in the cache memory 140, resulting in a miss, so the processor accesses the memory 130 for data (S96). Then, the processor reads data at addresses [1][4], [2][4], [3][4], and [4][4] from the memory 130 and stores it in the cache memory 140 (S97). At this time, the original cache data is evicted (overwritten) from the cache memory 140. Thereafter, the processor reads data at address [1][4] from the cache memory 140 and stores it in the register 151 (S98). As such, data access by the first vector gather instruction may result in excessive data being read from the memory to the cache memory an excessive number of times, which may result in poor processing efficiency.

[0028] The present disclosure is intended to solve at least some of the above-mentioned problems, and each embodiment will be described below. FIG. 7 is a block diagram showing the configuration of an instruction generation system 1000 according to a second embodiment. The instruction generation system 1000 includes an execution target computer 100 and an instruction generation device 200. The execution target computer 100 and the instruction generation device 200 may be the same device. Furthermore, each of the execution target computer 100 and the instruction generation device 200 may be redundantly implemented by multiple computers, and each functional block may be implemented by multiple computers.

[0029] The execution target computer 100 is a computer capable of executing vector operations. The execution target computer 100 is used, for example, for SIMD (Single Instruction Multiple Data) and scientific and technological calculations. The execution target computer 100 executes object code 112, which is implemented in source code 111 and compiled into a computer program. Specifically, the execution target computer 100 includes a storage unit 110, an IF (Interface) unit 120, a memory 130, a cache memory 140, and a processor 150.

[0030] The storage unit 110 is a non-volatile storage device such as a hard disk or flash memory. The storage unit 110 stores source code 111 and object code 112. The source code 111 is, for example, a source program in which a loop structure including multiple data access processes is described, as shown in FIG. 3 above. The object code 112 is an object program compiled from the source code 111 by the instruction generating device 200. The object code 112 may include a second vector gather instruction according to this embodiment in addition to ordinary object code. Furthermore, the object code 112 may include a first vector gather instruction, or may contain a mixture of the first and second vector gather instructions.

[0031] The IF unit 120 is an interface that performs input and output between the outside and the inside of the execution target computer 100 .

[0032] The memory 130 is a volatile storage device such as RAM (Random Access Memory), and is a storage area for temporarily holding information when the processor 150 is operating. The cache memory 140 is a storage device that temporarily stores part of the data stored in the memory 130. Generally, the cache memory 140 has a smaller storage capacity than the memory 130, but reads and writes data faster than the memory 130.

[0033] The processor 150 includes a register 151 and an instruction execution unit 152. The register 151 is a storage device that stores program instructions, data storage addresses, and other arbitrary data for arithmetic processing. Generally, the register 151 has a smaller storage capacity than the cache memory 140, but reads and writes data faster than the cache memory 140.

[0034] The instruction execution unit 152 is a control device that controls each component of the execution target computer 100. The instruction execution unit 152 loads the object code 112 from the storage unit 110 into the memory 130 and executes the object code 112. In this way, the processor 150 realizes the processing implemented in the source code 111.

[0035] The instruction generation device 200 is an example of the above-mentioned instruction generation device 1. The instruction generation device 200 may be, for example, a general-purpose information processing device, regardless of whether it is capable of executing vector operations. The instruction generation device 200 receives source code 111 from the storage unit 110 in the execution target computer 100, performs compilation including instruction generation processing, and outputs object code 112 to the storage unit 110.

[0036] The instruction generation device 200 includes a storage unit 210, a memory 220, an IF unit 230, and a control unit 240. The storage unit 210 is a non-volatile storage device such as a hard disk or a flash memory. The storage unit 210 stores an instruction generation program 211. The instruction generation program 211 is a computer program that implements the instruction generation process according to this embodiment. The instruction generation program 211 has some or all of the functions of a compiler program that converts source code 111 into object code 112 that includes vector operation instructions.

[0037] The memory 220 is a volatile storage device such as a RAM, and is a storage area for temporarily storing information during operation of the control unit 240. The IF unit 230 is an interface for inputting and outputting data between the outside and inside of the instruction generating device 200.

[0038] The control unit 240 is a processor, i.e., a control device, that controls each component of the instruction generating device 200. The control unit 240 loads the instruction generating program 211 from the storage unit 210 into the memory 220 and executes the instruction generating program 211. In this way, the control unit 240 realizes the functions of an analysis unit 241, a determination unit 242, a generation unit 243, and an output unit 244.

[0039] The analysis unit 241 analyzes the input source code 111. Specifically, the analysis unit 241 detects a loop structure including multiple data access operations described in the source code 111 by analyzing the source code 111. When a loop structure is detected, the analysis unit 241 analyzes an address array of access destinations of multiple first vector gather instructions that can be converted from the loop structure. For example, the analysis unit 241 compares corresponding elements in the address array to analyze the continuity of addresses. More specifically, the analysis unit 241 may analyze the continuity by sorting addresses that are each element of the address array. Alternatively, the analysis unit 241 may convert the detected loop structure into multiple first vector gather instructions and analyze the address array of access destinations of each converted instruction. The analysis process in the analysis unit 241 may be performed by the determination unit 242. In other words, the analysis unit 241 may be configured to be included in the determination unit 242.

[0040] The determination unit 242 is an example of the above-mentioned determination unit 11. The determination unit 242 determines whether there is regular continuity in the addresses of corresponding elements among the address arrays of the first vector gather instructions. Furthermore, the determination unit 242 determines whether there is regular continuity by comparing the continuity among the address arrays of each instruction.

[0041] The generation unit 243 is an example of the first generation unit 12 and the second generation unit 13 described above. When the determination unit 242 determines that there is regular continuity, the generation unit 243 generates a plurality of block address arrays by grouping together the addresses of each element having the continuity. The generation unit 243 also generates a second vector gather instruction that specifies the plurality of block address arrays as arguments from the loop structure. The generation unit 243 may also convert the source code 111 into the object code 112 that includes a vector operation instruction. The generation unit 243 may also convert the source code 111 into the object code 112 that includes either the first or second vector gather instruction.

[0042] Here, if the number of first vector gather instructions is three or more, the following may be performed. That is, if the generation unit 243 determines that there is regular continuity between the address arrays of two or more of the multiple first vector gather instructions and some of the instructions, the generation unit 243 may generate multiple block address arrays from the address arrays of the determined group of instructions. Then, the generation unit 243 generates, from the loop structure, the remaining instructions of the multiple first vector gather instructions and a second vector gather instruction using the multiple block address arrays.

[0043] The output unit 244 outputs the object code 112 generated by the generation unit 243 to the execution target computer 100 .

[0044] 8 is a flowchart showing the flow of the instruction generation process according to the present embodiment 2. First, the analysis unit 241 receives input of the source code 111 stored in the storage unit 110 of the execution target computer 100, and analyzes the input source code 111 (S201).

[0045] Next, the analysis unit 241 attempts to detect a loop structure including multiple data access operations described in the source code 111 by analyzing the source code 111. Then, the analysis unit 241 determines whether or not a loop structure has been detected (S202). For example, if the source code 111 is the source code SC1 in FIG. 3 described above, the analysis unit 241 detects the loop structure SC2. Then, the analysis unit 241 analyzes the address array of the access destinations of multiple first vector gather instructions that can be converted from the loop structure SC2 (S203). At this time, the analysis unit 241 may actually convert the loop structure SC2 into multiple first vector gather instructions and analyze the address array of the access destinations of each converted instruction.

[0046] Then, the determination unit 242 determines whether or not the address array has regular continuity (S204). If it is determined that the address array has regular continuity, the generation unit 243 generates a plurality of block address arrays (S205).

[0047] FIG. 9 is a diagram illustrating an example of a regular continuity determination and a block address array according to the second embodiment. Address arrays V11 to V14 are examples of addresses specified as arguments of instructions when a loop structure (with four iterations) including four data access operations is detected from the source code 111 and converted into four first vector gather instructions. Therefore, four elements (addresses) are stored in each of the address arrays V11 to V14. The determination unit 242 then compares the line numbers of the first elements of the address arrays V11 to V14 between adjacent arrays to determine whether or not there is continuity. Specifically, the determination unit 242 compares the line number [1] of the first element of the address array V11 with the line number [2] of the first element of the address array V12 and determines that there is continuity. Similarly, the determination unit 242 compares the line numbers [2] and [3] of the address arrays V12 and V13 to determine that there is continuity. Furthermore, the determination unit 242 compares row numbers [3] and [4] of address arrays V13 and V14 and determines that there is continuity. Therefore, the determination unit 242 determines that there is continuity in the first elements of address arrays V11 to V14. Similarly, the determination unit 242 determines that there is continuity in each of the second to fourth elements of address arrays V11 to V14.

[0048] Then, the determination unit 242 compares the row number sequences of the first to fourth elements that have been determined to have continuity, and determines whether there is regular continuity between the element sequences. Specifically, the determination unit 242 determines that the row numbers of the first elements in the address arrays V11 to V14 are in the order of [1] to [4], and the row numbers of the second to fourth elements are also in the order of [1] to [4], and that there is regularity in the continuity of the row number sequences between the first to fourth elements in the address arrays V11 to V14 (here, the same, common).

[0049] Therefore, the generation unit 243 generates multiple block address arrays in step S205 described above. Specifically, the generation unit 243 generates a block address array V41 that stores the first elements of address arrays V11 to V14 in this order. Similarly, the generation unit 243 generates block address arrays V42 to V44 that store the second to fourth elements of address arrays V11 to V14 in this order.

[0050] FIG. 10 is a diagram showing another example of the determination of regular continuity according to the second embodiment. In this example, the row numbers of the elements of address arrays V11 to V14 are [3], [1], [4], and [2]. Therefore, the determination unit 242 first sorts address arrays V11 to V14 by the row numbers of the first elements, rearranging them in the order of V12, V14, V11, and V13. The determination unit 242 then determines whether the address array after sorting has regular continuity. In other words, with regard to the order of address arrays of multiple first vector gather instructions that can be converted from a loop structure, it is preferable to perform the determination in step S204 on the order of the address array after sorting. This increases the scope of application of this embodiment and achieves further efficiency.

[0051] FIG. 11 illustrates an example of a determination of partially regular continuity and a block address array according to the second embodiment. In this example, the row numbers of the elements of address arrays V11 to V14 are [1], [2], [3], and [6]. Therefore, when comparing each element of the address arrays after sorting the row numbers, the determination unit 242 determines that address arrays V11 to V13 have regular continuity and that address array V14 does not have regular continuity. The generation unit 243 then generates a block address array V51 that stores the first elements of address arrays V11 to V13 in this order. Similarly, the generation unit 243 generates block address arrays V52 to V54 that store the second to fourth elements of address arrays V11 to V13 in this order. In other words, if the address arrays of multiple first vector gather instructions contain addresses that are discontinuous with the addresses of the other address arrays, the corresponding vector gather instructions are excluded from the block address array generation targets. This allows this embodiment to be applied as long as two or more of the first vector gather instructions that can be converted from a loop structure have regular continuity in some of them, thereby increasing the scope of application of this embodiment and achieving further efficiency.

[0052] Returning to FIG. 8, the explanation will be continued. The generation unit 243 generates a second vector gather instruction that specifies the plurality of block address arrays generated in step S205 as arguments (S206).The generation unit 243 then generates object code 112 that includes the second vector gather instruction from the source code 111 (S207).

[0053] If it is determined in step S204 that the address array does not have regular continuity, the generation unit 243 generates object code by converting the loop structure into a plurality of first vector gather instructions (S209). Alternatively, if no loop structure is detected in step S202, the generation unit 243 generates object code 112 from source code 111 as usual (S208).

[0054] Thereafter, the output unit 244 outputs the object code 112 generated in step S207, S208, or S209 to the execution target computer 100 (S210). As a result, the execution target computer 100 stores the object code 112 in the storage unit 110. Then, the processor 150 of the execution target computer 100 can execute the object code 112 at a predetermined timing.

[0055] 12 is a diagram showing the relationship between block address arrays and address positions on a memory according to the second embodiment. Here, block address arrays V2001, V2002, ..., V2063, and V2064 are examples generated in step S205 of FIG. 8 for the specific example of address arrays V11 to V14 shown in FIG. 5. For example, 64 arrays, V2001 to V2064, are generated, and four elements are stored in each array. Also, on the address map of the memory, for V2001 to V2064, the order of the elements in the block address arrays is the same as the order of the addresses in the address map.

[0056] FIG. 13 is a diagram showing an example of the instruction format and execution image of a vector gather block instruction (second vector gather instruction) according to the second embodiment. The second vector gather instruction according to this embodiment is referred to as a vector gather block instruction. Here, the instruction format of the vector gather block instruction is as follows: VGTBLK is the vector gather block instruction, vx is the address of the write destination vector register, vy is the read source address array, and sz is the number of blocks for one element in vy. An example of a vector gather block instruction is "VGTBLK V0, V4, 4." It is assumed that block address arrays V41, V42, V43, and V44 are stored in V4.

[0057] The execution image at this time is that when the processor 150, which performs vector calculations, executes "VGTBLK V0, V4, 4", it searches the cache memory 140, and if a miss occurs, it performs memory access to the V1 area in the memory 130. At this time, the data corresponding to the address array of V4 is stored in a distributed manner within the memory 130, as described above. However, the processor 150 performs memory access processing on the memory 130 for the number of blocks specified by sz. Specifically, the processor 150 reads data four elements at a time (four times, from V41 to V44) from the memory 130 and reads it into the cache memory 140. Thereafter, the processor 150 stores the data corresponding to V41 to V44 from the cache memory 140 in the areas V0 to V3 in the register 151.

[0058] FIG. 14 is a diagram illustrating the concept of data access by the second vector gather instruction according to the second embodiment. For example, assume that the processor 150 that performs vector operations executes "VGTBLK V0, V4, 4" in FIG. 13 described above. At this time, as internal processing of VGTBLK, the processor 150 first searches the cache memory 140 for the address [1][1] of the first element of V41 (S31). If a miss occurs, the processor 150 performs data access to the memory 130 (S32). Then, the processor 150 reads data at addresses [1][1], [2][1], [3][1], and [4][1] from the memory 130 and stores the data in the cache memory 140 (S33). After that, the processor 150 reads data at address [1][1] from the cache memory 140 and stores the data in the register 151 (S34).

[0059] Next, the processor 150 searches the cache memory 140 for the address [2][1] of the second element of V11 (S35). At this time, data at addresses [1][1], [2][1], [3][1], and [4][1] are stored in the cache memory 140, and a hit occurs, so the processor 150 reads the data at address [2][1] from the cache memory 140 and stores it in the register 151 (S36).

[0060] In this way, the second vector gather instruction increases the probability that the target data will remain in the cache memory when the cache memory is accessed for the second or subsequent times, and also increases the probability that the number of accesses to the memory and the amount of data will be reduced. This makes data access processing more efficient, which means that the execution of the vector gather instruction can be sped up.

[0061] <Other embodiments> Although the above-described embodiment has been described as a hardware configuration, the present disclosure is not limited to this. Any processing in the present disclosure can also be realized by causing a CPU to execute a computer program.

[0062] In the above examples, the program includes instructions (or software code) that, when loaded into a computer, cause the computer to perform one or more functions described in the embodiments. The program may be stored on a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, computer-readable medium or tangible storage medium includes random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technology, CD-ROM, digital versatile disc (DVD), Blu-ray® disc or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device. The program may also be transmitted on a transitory computer-readable medium or communication medium. By way of example and not limitation, transitory computer-readable medium or communication medium includes electrical, optical, acoustic, or other forms of propagated signals.

[0063] The present disclosure is not limited to the above-described embodiments, and may be modified as appropriate without departing from the spirit and scope of the present disclosure. In addition, the present disclosure may be implemented by appropriately combining the respective embodiments.

[0064] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes. (Appendix A1) a determining means for analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access operations described in a source code is converted into a plurality of first vector gather instructions, and determining whether or not there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction; a first generating means for generating a plurality of block address arrays by grouping together addresses for each element having the regular continuity when the regular continuity exists; a second generating means for generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; An instruction generating device comprising: (Appendix A2) The determining means analyzes the continuity of addresses by comparing corresponding elements in each of the address arrays, and determines whether or not the regular continuity exists by comparing the continuity between the address arrays of each instruction. 10. The instruction generating device according to claim A1. (Appendix A3) The determining means analyzes the continuity by sorting the addresses that are elements of the address array. 10. The instruction generating device according to claim A2. (Appendix A4) the plurality of first vector gather instructions is three or more; The first generating means if it is determined that the regular continuity exists between address arrays of two or more and some of the plurality of first vector gather instructions, generating the plurality of block address arrays from the address arrays of the determined group of instructions; The second generating means generating, from the loop structure, the remaining instructions of the plurality of first vector gather instructions and the second vector gather instruction using the plurality of block address arrays; An instruction generating device according to any one of appendices A1 to A3. (Appendix A5) The determination means converting the loop structure into the plurality of first vector gather instructions, and analyzing an address array of access destinations of each instruction after the conversion; An instruction generating device according to any one of appendices A1 to A3. (Appendix B1) a storage device that stores the source code; an information processing device that receives the source code and outputs an object code; The information processing device includes: a determining means for analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access operations described in the source code is converted into a plurality of first vector gather instructions, and determining whether or not there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction; a first generating means for generating a plurality of block address arrays by grouping together addresses for each element having the regular continuity when the regular continuity exists; a second generating means for generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; An instruction generation system comprising: (Appendix B2) The determining means analyzes the continuity of addresses by comparing corresponding elements in each of the address arrays, and determines whether or not the regular continuity exists by comparing the continuity between the address arrays of each instruction. 10. The instruction generation system of claim 1. (Appendix C1) The computer analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access processes described in the source code is converted into a plurality of first vector gather instructions; determining whether there is regular continuity in the addresses of corresponding elements among the address arrays of each of the plurality of first vector gather instructions; If there is regular continuity, a plurality of block address arrays are generated by grouping the addresses for each element having the continuity; generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; Instruction generation method. (Appendix D1) a determination process of analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access operations written in the source code is converted into a plurality of first vector gather instructions, and determining whether or not there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction; a first generation process for generating a plurality of block address arrays by grouping addresses for each element having the regular continuity when the regular continuity exists; a second generation process for generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; An instruction generation program that causes a computer to execute the following.

[0065] Although the present disclosure has been described above with reference to the embodiments (and examples), the present disclosure is not limited to the above-described embodiments (and examples). Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. [Explanation of symbols]

[0066] 1 Instruction generator 11 Judgment section 12 First Generation Section 13 Second Generation Section SC1 Source Code SC2 Loop Structure SC3 Vector gather instructions 1000 Instruction Generation System 100 target computers 110 Storage section 111 Source Code 112 Object Code 120 IF Section 130 memory 140 cache memory 150 processors 151 registers 152 Instruction Execution Unit 200 Instruction generator 210 Storage section 211 Instruction Generator 220 memory 230 IF Section 240 Control Unit 241 Analysis Department 242 Judgment section 243 Generation part 244 Output Section V11 Address Array V12 Address Array V13 address array V14 Address Array V41 Block Address Array V42 block address array V43 block address array V44 block address array V51 block address array V52 block address array V53 block address array V54 block address array V2001 Block Address Array V2002 block address array V2063 Block Address Array V2064 block address array

Claims

1. a determining means for analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access processes described in a source code is converted into a plurality of first vector gather instructions, and determining whether or not there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction; a first generating means for generating a plurality of block address arrays by grouping together addresses for each element having the regular continuity when the regular continuity exists; a second generating means for generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; An instruction generating device comprising:

2. The determining means analyzes the continuity of addresses by comparing corresponding elements in each of the address arrays, and determines whether or not the regular continuity exists by comparing the continuity between the address arrays of each instruction. The instruction generating device according to claim 1 .

3. The determining means analyzes the continuity by sorting the addresses that are elements of the address array. The instruction generating device according to claim 2 .

4. the plurality of first vector gather instructions is three or more; The first generating means if it is determined that the regular continuity exists between address arrays of two or more and some of the plurality of first vector gather instructions, generating the plurality of block address arrays from the address arrays of the determined group of instructions; The second generating means generating, from the loop structure, the remaining instructions of the plurality of first vector gather instructions and the second vector gather instruction using the plurality of block address arrays; The instruction generating device according to any one of claims 1 to 3.

5. The determination means converting the loop structure into the plurality of first vector gather instructions, and analyzing an address array of access destinations of each instruction after the conversion; The instruction generating device according to any one of claims 1 to 3.

6. a storage device that stores the source code; an information processing device that receives the source code and outputs an object code; The information processing device includes: a determining means for analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access processes described in the source code is converted into a plurality of first vector gather instructions, and determining whether or not there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction; a first generating means for generating a plurality of block address arrays by grouping together addresses for each element having the regular continuity when the regular continuity exists; a second generating means for generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; An instruction generation system comprising:

7. The determining means analyzes the continuity of addresses by comparing corresponding elements in each of the address arrays, and determines whether or not the regular continuity exists by comparing the continuity between the address arrays of each instruction. The instruction generation system according to claim 6 .

8. The computer analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access processes described in the source code is converted into a plurality of first vector gather instructions; determining whether there is regular continuity in the addresses of corresponding elements among the address arrays of each of the plurality of first vector gather instructions; If there is regular continuity, a plurality of block address arrays are generated by grouping the addresses for each element having the continuity; generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; Instruction generation method.

9. a determination process of analyzing an address array of access destinations of each instruction when a loop structure including a plurality of data access operations described in the source code is converted into a plurality of first vector gather instructions, and determining whether or not there is regular continuity in the addresses of corresponding elements between the address arrays of each instruction; a first generation process for generating a plurality of block address arrays by grouping addresses for each element having the regular continuity when the regular continuity exists; a second generation process for generating a second vector gather instruction from the loop structure, the second vector gather instruction specifying the array of block addresses as an argument; An instruction generation program that causes a computer to execute the following.

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