Color gratings in microelectronic structures

Abstract

To provide a microelectronic structure and a computing device that remedy the shortcomings of a traditional extreme ultraviolet (EUV) lithography technique by using a manufacturing technique that include a guided self-organization (DSA) operation.SOLUTION: A microelectronic structure 100 includes a first conductive structure 121 that is alternately provided with a second conductive structure 120. Each first conductive structure includes a bottom 121A and a top 121B. Cap structures 149 are respectively on tops of the second conductive structures. The bottom of the first conductive structure is laterally separated from the second conductive structure to align with the second conductive structure, and the top of the first conductive structure is laterally separated from the cap structure, and aligned with the cap structure. The microelectronic structure includes one or more disordered layered regions 143 that are laterally separated from the first conductive structure and are aligned with the first conductive structure.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] Conventional microelectronic fabrication techniques may not be able to reliably pattern particularly small features, resulting in limited size and performance of microelectronic devices. [Brief explanation of the drawings]

[0002]

[0013] Embodiments will be readily understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0014] To facilitate this description, like reference numerals refer to like structural elements, and in which embodiments are shown by way of example, and not by way of limitation, and in which:

[0003] [Figure 1A] 1A-1D are various views of a microelectronic structure including aligned conductive structures according to various embodiments. [Figure 1B] 1A-1D are various views of a microelectronic structure including aligned conductive structures according to various embodiments. [Figure 1C] 1A-1D are various views of a microelectronic structure including aligned conductive structures according to various embodiments.

[0004] [Figure 2] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 3A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 3B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 4A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 4B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 5A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 5B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 6A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 6B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 7A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 7B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 8A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 8B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 9A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 9B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 10A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 10B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 11A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 11B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 12A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 12B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 13A]1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 13B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 14A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 14B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 15A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 15B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 16A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 16B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 17A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 17B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 18A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 18B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 19A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 19B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 20A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 20B]1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 21A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 21B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 22A] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS. [Figure 22B] 1A-1C illustrate steps in an exemplary process for fabricating the microelectronic structure of FIGS.

[0005] [Figure 23] FIG. 1 is a top view of a wafer and die that may include any of the microelectronic structures disclosed herein.

[0006] [Figure 24] FIG. 1 is a cross-sectional side view of a microelectronic device that may include any of the microelectronic structures disclosed herein.

[0007] [Figure 25] FIG. 1 is a cross-sectional side view of a microelectronic package that may include any of the microelectronic structures disclosed herein.

[0008] [Figure 26] FIG. 1 is a cross-sectional side view of a microelectronic device assembly that may include any of the microelectronic structures disclosed herein.

[0009] [Figure 27] FIG. 1 is a block diagram of an example computing device that may include any of the microelectronic structures disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] Disclosed herein is a color grid in a microelectronic structure. For example, the microelectronic structure can include first conductive structures alternating with second conductive structures. Each of the first conductive structures includes a bottom and a top, and each cap structure overlies each of the second conductive structures, with the bottom of the first conductive structure laterally spaced from and aligned with the second conductive structure, and the top of the first conductive structure laterally spaced from and aligned with the cap structure. In some embodiments, the microelectronic structure can include one or more disordered layered regions laterally spaced from and aligned with the first conductive structures.

[0011] Existing conventional lithography techniques, such as existing conventional extreme ultraviolet (EUV) technologies, may not be able to pattern features that are both small enough and low enough in defects to be used in commercial microelectronic devices. For example, conventional EUV lithography can suffer from high roughness and excessive bridging defects at tight pitches (e.g., pitches less than 32 nanometers), which can limit or significantly hinder the deployment of EUV patterning techniques (e.g., spacer-based pitch division techniques with a resist “backbone” defined by EUV lithography). Conventional EUV lithography techniques also suffer from a trade-off between EUV dose and resist thickness. While higher EUV doses have the potential to pattern lines with lower roughness, such higher EUV doses typically require thinner resist layers to achieve the desired depth of focus and avoid pattern collapse. However, these thinner resist layers typically cannot withstand etch transfer (i.e., transferring the resist pattern to one or more underlying layers) as well as thicker resists. These limitations have presented significant obstacles to the adoption of EUV technology in commercial microelectronic manufacturing processes.

[0012] Various of the embodiments disclosed herein can overcome the shortcomings of conventional EUV lithography techniques by using fabrication techniques that include directed self-assembly (DSA) operations. DSA-based techniques can take advantage of the property of some materials to self-assemble into specific patterns under certain conditions, and these patterns can be used in a variety of ways to fabricate small, precise features in microelectronic devices.

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the accompanying drawings, where like reference numerals refer to like parts throughout, there are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0014] Various operations may be described sequentially as multiple separate acts or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations need not be performed in the order presented. The described operations may be performed in a different order than in the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0015] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The phrase "A, B, or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The drawings are not necessarily to scale. While many of the drawings show rectilinear structures with flat walls and square corners, this is for ease of illustration only; actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

[0016] The description uses the phrases "in one embodiment" or "in embodiments." Each of these phrases may refer to one or more of the same or different embodiments. Furthermore, terms such as "comprising," "including," and "having" when used with respect to embodiments of the present disclosure are synonymous. As used herein, "conductive" material refers to an electrically conductive material unless otherwise specified. When used to describe a range of dimensions, the phrase "between X and Y" refers to the range inclusive of X and Y. For convenience, the phrase "FIGS. 1A-1C" may be used to refer to the set of drawings named 1A-1C, the phrase "FIGS. 3A-3B" may be used to refer to the set of drawings named 3A-3B, and so on. Although the resist materials are referred to by various reference numbers that are repeated among different drawings (e.g., resist material 112), this is solely for ease of explanation, and the resist material having a particular reference number referenced in one drawing (e.g., resist material 112 referenced in Figures 4A-4B) is not necessarily the same resist material as the resist material having the same reference number referenced in another drawing (e.g., resist material 112 referenced in Figures 8A-8B).

[0017] 1A-1C are various views of an exemplary microelectronic structure 100 including alternating first conductive structures 121 and second conductive structures 120. FIG. 1A is a side cross-sectional view of the microelectronic structure 100 through section A-A of FIG. 1B, FIG. 1B is a top view of the microelectronic structure 100, and FIG. 1C is a detailed top view of the disordered layered structure 138 of the microelectronic structure 100 (discussed further below). In some embodiments, the microelectronic structure 100 of FIGS. 1A-1C can be part of a metallization layer in a microelectronic device (e.g., as described below with reference to FIG. 24).

[0018] 1A-1B includes alternating first conductive structures 121 and second conductive structures 120. The first conductive structures 121 and second conductive structures 120 may take the form of a juxtaposed arrangement of conductive material spaced apart by first spacers 124 and second spacers 125. In particular, the bottom 121A of the first conductive structure 121 is aligned with the second conductive structure 120, and the first spacer 124 contacts and is between the bottom 121A of the first conductive structure 121 and the second conductive structure 120. The top 121B of the first conductive structure 121 is aligned with the cap structure 149 on the second conductive structure 120, and the second spacer 125 contacts and is between the top 121B of the first conductive structure 121 and the cap structure 149. The sidewalls of first conductive structure 121 and second conductive structure 120 may be substantially straight. The straight sidewalls of first conductive structure 121 may be a product of the DSA-based techniques disclosed herein used to form first conductive structure 121. Other approaches to fabricating similar conductive structures may result in "mushroom-shaped" tops of those conductive structures rather than straight sidewalls.

[0019] The first conductive structure 121 and the second conductive structure 120 may comprise any suitable material. In some embodiments, the first conductive structure 121 may have the same material composition and / or configuration as the second conductive structure 120, whereas in other embodiments, the first conductive structure 121 may have a different material composition and / or configuration than the second conductive structure 120. The first conductive structure 121 and / or the second conductive structure 120 may include one or more layers of various materials, such as one or more layers of a liner material and a fill material. In some embodiments, the liner material may include tantalum, tantalum nitride, titanium, titanium nitride, cobalt, or ruthenium (e.g., combinations thereof), and the fill material may include tungsten, cobalt (e.g., as cobalt silicide), ruthenium, molybdenum, copper, silver, nickel (e.g., as nickel silicide), gold, aluminum, other metals or alloys, or other combinations of materials.

[0020] The first spacer 124 and the second spacer 125 may comprise any suitable dielectric material. In some embodiments, the first spacer 124 may have the same material composition and / or configuration as the second spacer 125, whereas in other embodiments, the first spacer 124 may have a different material composition and / or configuration than the second spacer 125. For example, in some embodiments, the first spacer 124 and / or the second spacer 125 may comprise an inorganic dielectric material such as silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide.

[0021] The sidewalls of the second conductive structures 120 may be aligned with the corresponding sidewalls of the cap structure 149 (i.e., the second conductive structures 120 and the cap structure 149 may be “self-aligned,” as described below). The cap structure 149 may comprise any suitable material. In some embodiments, the cap structure 149 may comprise a hard mask material. For example, the cap structure 149 may comprise silicon nitride. The first conductive structures 121 and the second conductive structures 120 / cap structure 149 may be arranged as multiple parallel lines of material, as shown, thus providing a grid. Because of the alternating different material compositions of this grid, the grid may be referred to as a “color” grid. Such a color grid may be particularly useful for mitigating edge placement errors during manufacturing, as adjacent conductive lines within the grid may be separated by insulating lines within the grid, reducing the likelihood of misalignment in the patterning of a subsequent metallization layer resulting in undesired bridging between the two conductive lines.

[0022] The first conductive structure 121 and the second conductive structure 120 may be disposed in the metallization layer 101 over regions of the microelectronic structure 100 that include the conductive contacts 108 and 128 in the substructure 102. The substructure 102 may include any suitable dielectric material (e.g., on top) and / or conductive material. For example, in some embodiments, the substructure 102 may include an inorganic dielectric material such as silicon oxide, carbon-doped oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, or an insulating metal oxide such as hafnium oxide and zirconium oxide. The conductive contacts 108 and 128 may provide electrical contact to devices or other interconnects (not shown) within the substructure 102 of the microelectronic structure 100. For example, in some embodiments, the conductive contact 108 may be a transistor gate contact, while the conductive contact 128 may be a transistor source / drain contact (or vice versa). The transistors themselves may be in a device layer "below" the conductive contacts 108 / 128 (e.g., as described below with reference to FIG. 24). The conductive contacts 108 / 128 may contact the first conductive structures 121 on the conductive contacts 108 / 128, with sidewalls of the conductive contacts 108 / 128 aligned with corresponding sidewalls of the first conductive structures 121 (i.e., the conductive contacts 108 / 128 and the first conductive structures 121 may be "self-aligned," as described below). The particular configuration of the conductive contacts 108 / 128 in the microelectronic structure 100 of FIGS. 1A-1B is for illustrative purposes only, and any desired configuration of the conductive contacts 108 / 128 may be used.

[0023] The first conductive structure 121 and the second conductive structure 120 may be part of a patterned region 142, and the microelectronic structure 100 may also include one or more unpatterned regions 144. In the microelectronic structure 100 of FIGS. 1A-1B, the unpatterned region 144 may include a first disordered layered region 143 that is aligned with the bottom 121A of the first conductive structure 121 (and aligned with the second conductive structure 120, as described above) and a second disordered layered region 145 that is aligned with the top 121B of the first conductive structure 121 (and aligned with the cap structure 149, as described above). When fabricating the microelectronic structure 100 using a DSA-based technique (e.g., as described below with reference to FIGS. 2-22B), the first disordered layered region 143 and the second disordered layered region 145 of the unpatterned region 144 may have a disordered layered structure 138 similar to that shown in FIG. 1C. The disordered layered structure 138 may include one or more materials patterned according to the disordered layered structure of a DSA material that did not assume an ordered structure during a previous patterning operation (e.g., due to the absence of ordered block copolymer (BCP) material on the unpatterned regions 144, as described below with reference to FIGS. 2-22B). For example, as described below with reference to FIGS. 2-22B, the first disordered layered region 143 may include a material having the same composition as the dielectric material 103, the first spacers 124, and the second conductive structures 120, while the second disordered layered region 145 may include a material having the same composition as the cap structures 149, the second spacers 125, and the first conductive structures 121. As described below, the disordered layered regions 143 / 145 may be patterned during different sets of DSA operations, so that the particular disordered layered pattern in the first disordered layered region 143 may differ from the particular disordered layered pattern in the second disordered layered region 145. The presence of the disordered layered structure 138 may indicate the use of a DSA-based technique during the fabrication of the patterned region 142 in the unpatterned region 144 of the microelectronic structure 100, similar to that shown in FIG.In some embodiments, the non-patterned region 144 may be part of a transition region of the die containing the microelectronic structure 100, may be under a guard ring of the die containing the microelectronic structure 100, or may be within the frame of the die containing the microelectronic structure 100 (e.g., any die 1502 described below with reference to FIG. 23).

[0024] 2-22B illustrate stages in an exemplary process for fabricating the microelectronic structure 100 of FIGS. 1A-1B, according to various embodiments. While the operations of the methods of FIGS. 2-22B may be illustrated with reference to specific embodiments of the microelectronic structure 100 disclosed herein, the methods of FIGS. 2-22B may be used to form any suitable microelectronic structure 100. Although the operations are shown each once and in a particular order in FIGS. 2-22B, the operations may be reordered and / or repeated as appropriate (e.g., different operations performed in parallel when fabricating multiple microelectronic structures 100 simultaneously). In FIGS. 3A-22B, sub-figure "A" is a side cross-sectional view through section AA of sub-figure "B," and sub-figure "B" is a top view.

[0025] 2 is a cross-sectional side view of an assembly including a substructure 102. The substructure 102 may take any form disclosed herein and, in some embodiments, may include a device layer or metallization layer (not shown) as described herein.

[0026] 3A and 3B show the assembly after depositing and patterning an initial grating of mask material 104 on the substructures 102 of FIG. 2. The mask material 104 may comprise any suitable material different from the substructures 102. In some embodiments, the mask material 104 may comprise titanium nitride, silicon nitride, silicon oxide, a silicon anti-reflective coating, a carbon-based hard mask, or amorphous silicon. The mask material 104 may be patterned using any suitable technique, such as a pitch division technique (e.g., pitch division by 2 or pitch division by 4), a DSA technique, a lithography technique, or any other technique or combination of techniques.

[0027] 4A and 4B show the assembly of Figures 3A-3B after depositing and patterning a resist material 112 thereon. The resist material 112 may be deposited using any suitable technique (e.g., spin coating) and may be patterned (e.g., lithographically) to form openings in the resist material 112 at the desired locations of the conductive contacts 108 (exposing the top surface of the substructure 102 at those locations between portions of the masking material 104).

[0028] 5A and 5B show the assembly of Figures 4A-4B after removing at least some of the exposed substructure 102 (e.g., exposed dielectric material) from the assembly. Any suitable selective etching technique may be used to remove portions of the substructure 102.

[0029] 6A and 6B show the assembly of FIGS. 5A-5B after providing sacrificial material 116 to the assembly (to fill the adjacent volume between the opening in substructure 102 and the portion of masking material 104), planarizing the resulting assembly to remove sacrificial material 116 above masking material 104 (e.g., using a chemical-mechanical polishing (CMP) process), and then removing the remaining resist material 112. Any suitable deposition, planarization, and etching techniques may be used.

[0030] 7A and 7B show the assembly of FIGS. 6A-6B after operations similar to those of FIGS. 4A-6B have been performed on the assembly of FIGS. 6A-6B to form structures of sacrificial material 118 at desired locations of conductive contacts 128. The operations of FIGS. 4A-6B and 7A-7B may be performed separately if the materials (i.e., portions of substructure 102) etched during those operations are different and, therefore, may require different etching chemistries and / or etching conditions.

[0031] 8A and 8B show the assembly of FIGS. 7A-7B after depositing and patterning resist material 112 over the assembly. The resist material 112 can be deposited using any suitable technique (e.g., spin coating) and can be patterned (e.g., lithographically) to form line openings in the resist material 112 to expose the sacrificial materials 116 and 118 and the substructure 102 in the same "lines." The pitch of the patterning of the resist material 112 can be twice the pitch of the initial grating of the mask material 104.

[0032] 9A and 9B show the assembly after removing the portions of substructure 102 (e.g., dielectric material) exposed in the assembly of Figures 8A-8B. Any suitable selective etching technique may be used.

[0033] 10A-10B show the assembly of FIGS. 9A-9B after providing metal oxide material 148 thereto. As shown in FIG. 10B, metal oxide material 148 may fill the volume occupied by substructure 102 in the assembly of FIGS. 8A-8B such that sacrificial material 116 / 118 is contained within the trenches and portions of sacrificial material 116 / 118 are between portions of metal oxide material 148. In some embodiments, metal oxide material 148 may be deposited on the assembly of FIGS. 9A-9B, and the resulting assembly may then be planarized (e.g., by CMP) to remove the overburden of metal oxide material 148. Metal oxide material 148 may include any suitable metal oxide, such as aluminum oxide.

[0034] 11A and 11B show the assembly of FIGS. 10A and 10B after replacing sacrificial material 116 / 118 with conductive contacts 108 / 128, respectively, and then planarizing the resulting assembly to remove everything above the top surface of substructure 102. Sacrificial material 116 / 118 may be removed using any suitable selective etching technique, and the material for conductive contacts 108 / 128 may be deposited on the resulting assembly before planarization. In some embodiments, conductive contacts 108 / 128 may have the same material composition, while in other embodiments, conductive contact 108 may have a different material composition than conductive contact 128 (and thus may be formed using a different set of deposition / masking operations).

[0035] 12A and 12B show the assembly of FIGS. 11A-11B after forming a replicated brush 192 on the assembly, depositing a BCP on the replicated brush 192, and processing the resulting assembly to self-assemble the BCP into a first BCP component 117 and a second BCP component 119 according to the template provided by the replicated brush 192. As used herein, "brush" may refer to any material that promotes self-assembly of DSA material on itself and may include large polymers, small polymers, self-assembled monolayers (SAMs), and other suitable materials. The replicated brush 192 may include a first replicated brush component 156 and a second replicated brush component 158. The first replicated brush component 156 may contact the conductive contacts 108 / 128 and the metal oxide material 148, and the second replicated brush component 158 ​​may contact the dielectric material of the substructure 102 to form the replicated brush 192. In some embodiments, the first replica brush component 156 may preferentially adhere to the metal / metal oxide. In some such embodiments, the first replica brush component 156 may be deposited on the assembly of FIGS. 11A-11B, the resulting assembly may be baked, and then rinsed to remove any first replica brush component 156 that is not bonded to the conductive contacts 108 / 128 and the metal oxide material 148. Next, the second replica brush component 158 ​​may be deposited. In some embodiments, the second replica brush component 158 ​​may preferentially adhere to the dielectric material, while in other embodiments, the second replica brush component 158 ​​may not preferentially adhere to the dielectric material and instead may be a "non-selective brush" that bonds to any areas not already covered by the first replica brush component 156. After depositing the second replica brush component 158, the resulting assembly may be baked and then rinsed to remove any excess second replica brush component 158.1C and may include a disordered layered region 132 that may include a material having the same material composition as the first and second replicate brush components 156, 158. In some embodiments, the first replicate brush component 156 (metal / metal oxide selective brush material) may have surface anchoring groups including phosphines, thiols, thiolates, thioacetates, disulfides, alkyl azides, aryl azides, nitriles, phosphates, silyls, alkyl and other phosphonate esters, phosphonamides, sulfonamides, sulfenates, sulfinates, sulfonates, boronic acids, phosphonic acids, carboxylic acids, phosphorus dichloride, alkene, or alkyne materials. In some embodiments, the second replicate brush component 158 ​​(non-selective brush material) may have surface anchoring groups of hydroxyl, amine, or carboxylic acid groups.

[0036] As described above, self-assembly of a BCP can result in the self-separation of a first BCP component 117 and a second BCP component 119 of the BCP, as shown in Figures 12A-12B. For ease of explanation, the DSA-based techniques disclosed herein may refer to a BCP having two components, a first BCP component 117 and a second BCP component 119. However, this is merely exemplary, and any of the techniques disclosed herein may utilize a BCP having more than two components. One example of a BCP that can function as a BCP in the operations disclosed herein is polystyrene-co-poly(methyl methacrylate) (PS-PMMA). When the BCP is PS-PMMA, the first BCP component 117 can be polystyrene (PS), while the second BCP component 119 can be polymethyl methacrylate (PMMA). 12A-12B, self-assembly of the BCP involves the BCP self-segregating its first BCP component 117 and second BCP component 119 into bands, forming alternating vertically oriented regions of the first BCP component 117 and second BCP component 119. The dimensions and spacing of the replicated brushes 192 can be selected to correspond to the size and spacing of the bands of the first BCP component 117 and second BCP component 119 of the BCP, as shown, so that the replicated brushes 192 provide a "template" for the self-assembly of the BCP, aligning the self-assembled BCP as needed with respect to the underlying replicated brushes 192. The BCPs may be able to "stretch" or "contract" around a nominal "intrinsic" spacing of the self-assembled bands of first BCP component 117 / second BCP component 119, allowing for a range of dimensions for the self-assembled bands of first BCP component 117 / second BCP component 119. The particular band-like self-assembly shown in Figures 12A-12B is one example of a pattern into which a BCP may self-assemble; some BCPs may self-assemble into other patterns, and various BCPs may self-assemble into multiple different patterns under different conditions.The disordered layered regions 132 of the replicated brush 192 may not provide a surface on which the BCP may readily self-assemble into alternating vertically oriented regions of the first BCP component 117 and the second BCP component 119; instead, the BCP on the disordered layered regions 132 may self-assemble into disordered layered regions 123 of the first BCP component 117 and the second BCP component 119. The disordered layered regions 123 may have a structure similar to that shown in FIG. 1C.

[0037] 13A and 13B show the assembly of Figures 12A-12B after removal (e.g., using a suitable selective etching technique) of first BCP component 117 and first replica brush component 156. Removal of first BCP component 117 may result in disordered layered region 123 becoming disordered layered region 127, which includes material having the same material composition as second replica brush component 119 (and does not include material having the same material composition as first BCP component 117), and removal of first replica brush component 156 may result in disordered layered region 132 becoming disordered layered region 129, which includes material having the same material composition as second replica brush component 158 ​​(and does not include material having the same material composition as first replica brush component 156).

[0038] 14A and 14B show the assembly of FIGS. 13A-13B after providing dielectric material 103 to the volume previously occupied by first replicate brush component 156 and first BCP component 117. In some embodiments, dielectric material 103 may comprise silicon oxide. Deposition of dielectric material 103 may result in disordered layered region 127 becoming disordered layered region 115, which includes material having the same material composition as second replicate brush component 119 and material having the same material composition as dielectric material 103, and disordered layered region 129 becoming disordered layered region 133, which includes material having the same material composition as second replicate brush component 158 ​​and material having the same material composition as dielectric material 103. The dielectric material 103 may be on the conductive contacts 108 / 128, with sidewalls of the conductive contacts 108 / 128 aligned with corresponding sidewalls of portions of the dielectric material 103 (i.e., the conductive contacts 108 / 128 and portions of the dielectric material 103 may be "self-aligned" due to the DSA technique used to pattern the locations of the dielectric material 103).

[0039] 15A and 15B show the assembly of FIGS. 14A-14B after removal (e.g., using a suitable selective etching technique) of second BCP component 119 and second replicate brush component 158. Removal of second BCP component 119 may result in disordered layered region 113, where disordered layered region 115 includes material having the same material composition as dielectric material 103 (and does not include material having the same material composition as second BCP component 119), and removal of second replicate brush component 158 ​​may result in disordered layered region 135, where disordered layered region 133 includes material having the same material composition as dielectric material 103 (and does not include material having the same material composition as second replicate brush component 158).

[0040] 16A and 16B show the assembly of FIGS. 15A-15B after forming first spacers 124 on the sides of the dielectric material 103. The first spacers 124 may comprise a dielectric material (e.g., as described above) and may be fabricated using any suitable spacer technique (e.g., conformal deposition of the dielectric material, such as by atomic layer deposition (ALD), followed by a "downward" directional etch to remove the dielectric material on the horizontal surfaces and leave the dielectric material on the side surfaces in place). Deposition of the first spacers 124 may result in disordered layered regions 113 and 135 comprising a material having the same material composition as the dielectric material 103 and a disordered layered region 141 comprising a material having the same material composition as the first spacers 124.

[0041] 17A and 17B show the assembly of FIGS. 16A-16B after forming second conductive structures 120 in the openings between pairs of first spacers 124. The second conductive structures 120 may be formed using any suitable deposition technique, followed by a planarization operation (e.g., using CMP). Formation of the second conductive structures 120 may result in the disordered layered regions 141 becoming first disordered layered regions 143 that include material having the same material composition as the dielectric material 103, the first spacers 124, and the second conductive structures 120.

[0042] 18A and 18B show the assembly of FIGS. 17A-17B after forming a replicated brush 192 (including a first replicated brush component 156 and a second replicated brush component 158) on the assembly, depositing a BCP on the replicated brush 192, and processing the resulting assembly to cause the BCP to self-assemble into a first BCP component 117 and a second BCP component 119 according to a template provided by the replicated brush 192. The operations described with reference to FIGS. 18A-18B may take any suitable form (e.g., any of the forms described above with reference to FIGS. 12A-12B). For example, as described above with reference to Figures 12A-12B, first replicate brush component 156 may preferentially adhere to the metal / metal oxide (and thus may preferentially adhere to second conductive structures 120), and second replicate brush component 158 ​​may adhere to any remaining exposed material (and thus may adhere to first spacers 124 and dielectric material 103) to form self-assembled replicate brush 192. Replicate brush 192 may also include disordered layered region 147, which may have a disordered layered structure similar to that of Figure 1C and may include material having the same material composition as first replicate brush component 156 and second replicate brush component 158. The BCP on disordered layered region 147 may self-assemble into disordered layered region 151 of first BCP component 117 and second BCP component 119. Disordered layered region 151 may have a structure similar to that shown in Figure 1C.

[0043] 19A and 19B show the assembly of FIGS. 18A-18B after replacing the first BCP component 117 and the first replicated brush component 156 with the material of the cap structure 149, planarizing the result (e.g., using CMP), and then removing the second BCP component 119 and the second replicated brush component 158, leaving the cap structure 149 in place over the second conductive structures 120. Any suitable selective etching and deposition techniques may be used. The cap structure 149 may be over the second conductive structures 120, with the sidewalls of the second conductive structures 120 aligned with the corresponding sidewalls of the cap structure 149 (i.e., the second conductive structures 120 and the cap structure 149 may be "self-aligned" due to the DSA technique used to pattern the location of the cap structure 149). Formation of cap structure 149 may result in disordered layered regions 151 and 147 becoming disordered layered region 137 comprising material having the same material composition as cap structure 149 .

[0044] 20A and 20B show the assembly of FIGS. 19A-19B after forming second spacers 125 on the sides of cap structures 149. Second spacers 125 may comprise a dielectric material (e.g., as described above) and may be fabricated using any suitable spacer technique (e.g., as described above with reference to FIGS. 16A-16B). Deposition of second spacers 125 may result in disordered layered regions 137 comprising a material having the same material composition as cap structures 149 and disordered layered regions 139 comprising a material having the same material composition as second spacers 125.

[0045] 21A and 21B show the assembly of FIGS. 20A-20B after removal of dielectric material 103. Any suitable selective etching technique may be used. The trenches resulting from the removal of dielectric material 103 may be self-aligned with the conductive contacts 108 / 128, as described above.

[0046] 22A and 22B show the assembly of FIGS. 21A-21B after forming first conductive structures 121 in the trenches. The first conductive structures 121 may be formed using any suitable deposition technique, followed by a planarization operation (e.g., using CMP). Formation of the first conductive structures 121 may result in the disordered layered region 139 becoming a second disordered layered region 145 including a material having the same material composition as the cap structure 149, a material having the same material composition as the second spacer 125, and a material having the same material composition as the first conductive structures 121. As described above with reference to Figures 14A-14B, the first conductive structures 121 may be on the conductive contacts 108 / 128, and the sidewalls of the conductive contacts 108 / 128 may be aligned with the corresponding sidewalls of the first conductive structures 121 (i.e., the conductive contacts 108 / 128 and the first conductive structures 121 may be "self-aligned" due to the DSA technique used to pattern the location of the first conductive structures 121). The assembly of Figures 22A-22B may take the form of the microelectronic structure 100 of Figures 1A-1B. Subsequent manufacturing operations may be performed on the assembly of Figures 22A-22B (e.g., additional metallization layers may be formed, as described further below).

[0047] The microelectronic structures 100 disclosed herein may be included in any suitable electronic component. Figures 23-27 illustrate various examples of devices that may include any of the microelectronic structures 100 disclosed herein.

[0048] FIG. 23 is a top view of a wafer 1500 and die 1502 that may include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. The wafer 1500 may be constructed from a semiconductor material and may include one or more die 1502 having microelectronic structures formed on the surface of the wafer 1500. Each of the die 1502 may be a repeating unit of a semiconductor product that includes any suitable microelectronic structure. After fabrication of the semiconductor product is complete, the wafer 1500 may undergo a singulation process in which the die 1502 are separated from one another to provide individual "chips" of the semiconductor product. The die 1502 may include one or more microelectronic structures 100 (e.g., as described below with reference to FIG. 24), one or more transistors (e.g., some of the transistors 1640 of FIG. 24 described below), and / or support circuitry that routes electrical signals to the transistors, along with any other circuit components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 of FIG. 27) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0049] 24 is a cross-sectional side view of a microelectronic device 1600 that may include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. One or more of the microelectronic devices 1600 may be included in one or more dies 1502 (FIG. 23). The microelectronic devices 1600 may be formed on a substrate 1602 (e.g., wafer 1500 of FIG. 23) and included in a die (e.g., die 1502 of FIG. 23). The substrate 1602 may be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The substrate 1602 may include, for example, bulk silicon or a crystalline substrate formed using a silicon-on-insulator (SOI) substructure. In some embodiments, substrate 1602 may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additionally, materials classified as II-VI, III-V, or IV may also be used to form substrate 1602. While a few examples of materials from which substrate 1602 may be formed are described here, any material that can serve as the foundation for microelectronic device 1600 may be used. Substrate 1602 may be part of a singulated die (e.g., die 1502 of FIG. 23) or wafer (e.g., wafer 1500 of FIG. 23).

[0050] The microelectronic device 1600 may include one or more device layers 1604 disposed on a substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the flow of current in the transistor 1640 between the S / D regions 1620, and one or more S / D contacts 1624 for routing electrical signals to and from the S / D regions 1620. The transistor 1640 may include additional features such as device isolation regions, gate contacts, etc., not shown for clarity. The transistor 1640 is not limited to the type and configuration shown in FIG. 24 and may include a variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors can include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors can include FinFET transistors, such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

[0051] Each transistor 1640 may include a gate 1622 formed of at least two layers: a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of multiple layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. The high-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, if a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

[0052] A gate electrode may be formed on the gate dielectric, and the gate electrode may include at least one p-type work function metal or n-type work function metal, depending on whether transistor 1640 is a p-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may be composed of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additionally, metal layers may be included for other purposes, such as barrier layers. For PMOS transistors, metals that may be used in the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals described below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used in the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals mentioned above with reference to PMOS transistors (e.g., for work function tuning).

[0053] In some embodiments, when viewed as a cross-section of transistor 1640 along the source-channel-drain direction, the gate electrode can be comprised of a U-shaped structure including a bottom that is substantially parallel to the plane of the substrate and two sidewalls that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode can simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewalls that are substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode can be comprised of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode can be comprised of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0054] In some embodiments, pairs of sidewall spacers sandwiching the gate stack may be formed on opposing sides of the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0055] The S / D regions 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S / D regions 1620 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the substrate 1602 to form the S / D regions 1620. The ion-implantation process may be followed by an annealing process to activate the dopants and diffuse them deep into the substrate 1602. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S / D regions 1620. An epitaxial growth process may then be performed to fill the recesses with the material used to fabricate the S / D regions 1620. In some implementations, the S / D regions 1620 may be fabricated using silicon germanium or a silicon alloy such as silicon carbide. In some embodiments, epitaxially deposited silicon alloys may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, S / D regions 1620 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In further embodiments, one or more layers of metal and / or metal alloys may be used to form S / D regions 1620.

[0056] Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from devices (e.g., transistor 1640) in device layer 1604 through one or more metallization layers (shown in FIG. 24 as metallization layers 1606-1610) disposed on device layer 1604. For example, conductive features (e.g., gate 1622 and S / D contacts 1624) in device layer 1604 may be electrically coupled to interconnect structures 1628 in metallization layers 1606-1610. One or more metallization layers 1606-1610 may form a metallization stack (also referred to as an "ILD" stack) 1619 of microelectronic device 1600. While FIG. 24 shows a microelectronic structure 100 included in the "M0" metallization layer 1606 of the metallization stack 1619, this is by way of example only, and any of the microelectronic structures 100 disclosed herein may be included in any of the metallization layers of the metallization stack 1619, as desired.

[0057] The interconnect structures 1628 may be arranged to route electrical signals according to a variety of designs within the metallization layers 1606-1610 (notably, the configuration is not limited to the particular configuration of the interconnect structures 1628 shown in Figure 24). Although a particular number of metallization layers 1606-1610 are shown in Figure 24, embodiments of the present disclosure include microelectronic devices having more or fewer metallization layers than those shown.

[0058] In some embodiments, the interconnect structures 1628 may include lines 1628a and / or vias 1628b filled with a conductive material, such as a metal. The lines 1628a may be arranged to route electrical signals in a planar direction that is substantially parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals into and out of the plane of the perspective view of FIG. 24 . The vias 1628b may be arranged to route electrical signals in a planar direction that is substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple together the lines 1628a of different metallization layers 1606-1610.

[0059] 24, the metallization layers 1606-1610 can include a dielectric material 1626 disposed between interconnect structures 1628. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the metallization layers 1606-1610 can have different compositions. In other embodiments, the composition of the dielectric material 1626 between different metallization layers 1606-1610 can be the same.

[0060] A first metallization layer 1606 may be formed above the device layer 1604. As shown, in some embodiments, the first metallization layer 1606 may include lines 1628a and / or vias 1628b. The lines 1628a of the first metallization layer 1606 may be coupled to contacts (e.g., S / D contacts 1624) of the device layer 1604. The first metallization layer 1606 may be referred to as the "M0" metallization layer. In some embodiments, the M0 metallization layer may include any suitable portion of any of the microelectronic structures 100 disclosed herein.

[0061] The second metallization layer 1608 may be formed above the first metallization layer 1606. In some embodiments, the second metallization layer 1608 may include vias 1628b for coupling the lines 1628a of the second metallization layer 1608 with the lines 1628a of the first metallization layer 1606. Although the lines 1628a and vias 1628b are structurally depicted as lines within each metallization layer (e.g., within the second metallization layer 1608) for clarity, in some embodiments, the lines 1628a and vias 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process). The second metallization layer 1608 may be referred to as the “M1” metallization layer. In some embodiments, the M1 metallization layer may include any suitable portion of any of the microelectronic structures 100 disclosed herein.

[0062] The third metallization layer 1610 (and additional metallization layers, if desired) may be formed successively on the second metallization layer 1608 according to techniques and configurations similar to those described in connection with the second metallization layer 1608 or the first metallization layer 1606. The third metallization layer 1610 may be referred to as the "M2" metallization layer. In some embodiments, the M2 metallization layer may comprise any suitable portion of any of the microelectronic structures 100 disclosed herein. In some embodiments, metallization layers "higher" in the metallization stack 1619 in the microelectronic device 1600 (i.e., farther away from the device layer 1604) may be thicker.

[0063] The microelectronic device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the metallization layers 1606-1610. In FIG. 24, the conductive contacts 1636 are shown in the form of bond pads. The conductive contacts 1636 may be electrically coupled to the interconnect structure 1628 and configured to route electrical signals for the transistors 1640 and other external devices. For example, solder joints may be formed on the one or more conductive contacts 1636 to mechanically and / or electrically couple a chip including the microelectronic device 1600 to another component (e.g., a circuit board). The microelectronic device 1600 may include additional or alternative structures for routing electrical signals from the metallization layers 1606-1610. For example, the conductive contacts 1636 may include other similar features (e.g., posts) that route electrical signals to external components.

[0064] 25 is a cross-sectional side view of an exemplary microelectronic package 1650 that may include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. In some embodiments, the microelectronic package 1650 may be a system-in-package (SiP).

[0065] The package substrate 1652 may be formed of a dielectric material (e.g., ceramic, build-up film, epoxy film with filler particles therein, glass, organic, inorganic, a combination of organic and inorganic, embedded portions formed of different materials, etc.) and may have conductive paths extending through the dielectric material between the face 1672 and the face 1674, or between different locations on the face 1672 and / or between different locations on the face 1674. These conductive paths may take the form of any of the interconnect structures 1628 described above with reference to FIG. 24 .

[0066] The package substrate 1652 may include conductive contacts 1663 that are coupled to conductive paths (not shown) through the package substrate 1652, thereby enabling circuitry within the die 1656 and / or interposer 1657 to be electrically coupled to various of the conductive contacts 1664 (or to other devices (not shown) included in the package substrate 1652).

[0067] The microelectronic package 1650 may include an interposer 1657 coupled to a package substrate 1652 via conductive contacts 1661 of the interposer 1657, first-level interconnects 1665, and conductive contacts 1663 of the package substrate 1652. The first-level interconnects 1665 shown in FIG. 25 are solder bumps, although any suitable first-level interconnects 1665 may be used. In some embodiments, the interposer 1657 may not be included in the microelectronic package 1650; instead, the die 1656 may be directly coupled to the conductive contacts 1663 at the face 1672 by the first-level interconnects 1665. More generally, one or more die 1656 may be coupled to the package substrate 1652 via any suitable structure (e.g., a silicon bridge, an organic bridge, one or more waveguides, one or more interposers, wire bonds, etc.).

[0068] The microelectronic package 1650 may include one or more dies 1656 coupled to an interposer 1657 via conductive contacts 1654 of the die 1656, first-level interconnects 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled to conductive paths (not shown) through the interposer 1657, allowing circuitry within the die 1656 to be electrically coupled to various of the conductive contacts 1661 (or to other devices (not shown) included in the interposer 1657). The first-level interconnects 1658 shown in FIG. 25 are solder bumps, although any suitable first-level interconnects 1658 may be used. As used herein, "conductive contacts" may refer to portions of conductive material (e.g., metal) that serve as an interface between different components. Conductive contacts may be recessed in, coplanar with, or extend away from the surface of a component, and may take any suitable form (e.g., conductive pads or sockets).

[0069] In some embodiments, underfill material 1666 may be disposed between package substrate 1652 and interposer 1657 around first-level interconnect 1665, and molding compound 1668 may be disposed around die 1656 and interposer 1657 and in contact with package substrate 1652. In some embodiments, underfill material 1666 may be the same as molding compound 1668. An exemplary material that may be used for underfill material 1666 and molding compound 1668 is, optionally, an epoxy molding material. Second-level interconnect 1670 may be coupled to conductive contacts 1664. The second-level interconnect 1670 shown in FIG. 25 is a solder ball (e.g., for a ball grid array configuration), although any suitable second-level interconnect 1670 (e.g., a pin in a pin grid array configuration or a land in a land grid array configuration) may be used. The second level interconnect 1670 may be used to couple the microelectronic package 1650 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another microelectronic package as recognized in the art and described below with reference to FIG. 26.

[0070] The die 1656 may take the form of any of the embodiments of die 1502 described herein (e.g., may include any of the embodiments of microelectronic device 1600). In embodiments in which the microelectronic package 1650 includes multiple dies 1656, the microelectronic package 1650 may be referred to as a multi-chip package (MCP). The dies 1656 may include circuitry for performing any desired function. For example, one or more of the dies 1656 may be logic dies (e.g., silicon-based dies) and one or more of the dies 1656 may be memory dies (e.g., high-bandwidth memory).

[0071] Although the microelectronic package 1650 shown in FIG. 25 is a flip-chip package, other package architectures can be used. For example, the microelectronic package 1650 can be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the microelectronic package 1650 can be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 1656 are shown in the microelectronic package 1650 of FIG. 25, the microelectronic package 1650 can include any desired number of dies 1656. The microelectronic package 1650 can include additional passive components, such as surface-mount resistors, capacitors, and inductors, located on either the first side 1672 or the second side 1674 of the package substrate 1652 or on the interposer 1657. More generally, the microelectronic package 1650 can include any other active or passive components recognized in the art.

[0072] 26 is a cross-sectional side view of a microelectronic device assembly 1700 that may include one or more microelectronic packages or other electronic components (e.g., dies) that include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. The microelectronic device assembly 1700 includes multiple components disposed on a circuit board 1702 (which may be, for example, a motherboard). The microelectronic device assembly 1700 includes multiple components disposed on a first side 1740 of the circuit board 1702 and on an opposing second side 1742 of the circuit board 1702; typically, components may be disposed on one or both sides 1740 and 1742. Any of the microelectronic packages described below with reference to the microelectronic device assembly 1700 may take the form of any of the embodiments of the microelectronic package 1650 described above with reference to FIG. 25 (e.g., may include one or more microelectronic structures 100 in a die).

[0073] In some embodiments, circuit board 1702 may be a printed circuit board (PCB) including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 1702. In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0074] The microelectronic device assembly 1700 shown in Figure 26 includes a package-on-interposer structure 1736 coupled to a first surface 1740 of a circuit board 1702 by bonding components 1716. The bonding components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (as shown in Figure 26), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical bonding structure.

[0075] The package-on-interposer structure 1736 may include a microelectronic package 1720 coupled to a package interposer 1704 by a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as, for example, those described above with reference to the coupling component 1716. While a single microelectronic package 1720 is shown in FIG. 26 , multiple microelectronic packages may be coupled to the package interposer 1704, and indeed additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the microelectronic package 1720. The microelectronic package 1720 may be or include, for example, a die (die 1502 in FIG. 23 ), a microelectronic device (e.g., microelectronic device 1600 in FIG. 24 ), or any other suitable component. In general, the package interposer 1704 may spread connections to a wider pitch or reroute certain connections to different connections. For example, the package interposer 1704 may couple a microelectronic package 1720 (e.g., a die) to the set of BGA conductive contacts of the mating component 1716 for coupling to the circuit board 1702. In the embodiment shown in FIG. 26 , the microelectronic package 1720 and the circuit board 1702 are attached to opposite sides of the package interposer 1704. In other embodiments, the microelectronic package 1720 and the circuit board 1702 may be attached to the same side of the package interposer 1704. In some embodiments, three or more components may be interconnected by the package interposer 1704.

[0076] In some embodiments, the package interposer 1704 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the package interposer 1704 may be formed from a polymeric material such as epoxy, fiberglass-reinforced epoxy, epoxy with inorganic filler, ceramic material, or polyimide. In some embodiments, the package interposer 1704 may be formed from alternative rigid or flexible materials. Such materials may include the same materials mentioned above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including, but not limited to, through-silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures recognized in the art.

[0077] Microelectronic device assembly 1700 may include a microelectronic package 1724 coupled to a first surface 1740 of circuit board 1702 by a coupling component 1722. Coupling component 1722 may take the form of any of the embodiments described above with reference to coupling component 1716, and microelectronic package 1724 may take the form of any of the embodiments described above with reference to microelectronic package 1720.

[0078] 26 includes a package-on-package structure 1734 coupled to a second surface 1742 of a circuit board 1702 by a bonding component 1728. The package-on-package structure 1734 may include a microelectronic package 1726 and a microelectronic package 1732 coupled to one another by a bonding component 1730, such that the microelectronic package 1726 is disposed between the circuit board 1702 and the microelectronic package 1732. The bonding components 1728 and 1730 may take the form of any of the embodiments of the bonding component 1716 described above, and the microelectronic packages 1726 and 1732 may take the form of any of the embodiments of the microelectronic package 1720 described above. The package-on-package structure 1734 may be configured according to any art-recognized package-on-package structure.

[0079] FIG. 27 is a block diagram of an exemplary computing device 1800 that may include one or more microelectronic structures 100 according to any of the embodiments disclosed herein. For example, any suitable components of the computing device 1800 may include one or more of the microelectronic device assembly 1700, microelectronic package 1650, microelectronic device 1600, or die 1502 disclosed herein. While numerous components are shown in FIG. 27 as being included in the computing device 1800, any one or more of these components may be omitted or duplicated as appropriate depending on the application. In some embodiments, some or all of the components included in the computing device 1800 may be mounted on one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SoC) die.

[0080] 27 , the computing device 1800 may not include one or more of the components shown in FIG. 27 , but the computing device 1800 may include interface circuitry for coupling one or more components. For example, the computing device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuits) to which the display device 1806 may be coupled. In another set of examples, the computing device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuits) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0081] Computing device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. Processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. Computing device 1800 may include memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0082] In some embodiments, computing device 1800 may include a communications chip 1812 (e.g., one or more communications chips). For example, communications chip 1812 may be configured to manage wireless communications for the transfer of data to and from computing device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not include any wires, although in some embodiments they may not.

[0083] The communications chip 1812 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., the IEEE 802.16-2005 amendment), the Long Term Evolution (LTE) project with any amendments, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX networks. The acronym stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications chip 1812 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications chip 1812 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications chip 1812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communications chip 1812 may operate according to other wireless protocols. The computing device 1800 may include an antenna 1822 for facilitating wireless communication and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0084] In some embodiments, the communications chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., Ethernet). As noted above, the communications chip 1812 may include multiple communications chips. For example, a first communications chip 1812 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications chip 1812 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications chip 1812 may be dedicated to wireless communications, and the second communications chip 1812 may be dedicated to wired communications.

[0085] Computing device 1800 may include battery / power circuitry 1814. Battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 1800 to an energy source (e.g., AC line power) separate from computing device 1800.

[0086] Computing device 1800 may include a display device 1806 (or corresponding interface circuitry, as described above). Display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat-panel display.

[0087] The computing device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as described above). The audio output device 1808 may include any device that produces an audible indicator, such as a speaker, a headset, or earphones.

[0088] The computing device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as described above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output).

[0089] Computing device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as described above), which may communicate with a satellite-based system and receive the location of computing device 1800 in an art-recognized manner.

[0090] The computing device 1800 may include other output devices 1810 (or corresponding interface circuitry, as described above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0091] The computing device 1800 may include other input devices 1820 (or corresponding interface circuitry, as described above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0092] Computing device 1800 may have any desired form factor, such as a handheld or mobile computing device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server computing device or other network computing component, a vehicle computing device (e.g., a vehicle control unit, a laptop computing device, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, computing device 1800 may be any other electronic device that processes data.

[0093] The following paragraphs provide various examples of the embodiments disclosed herein.

[0094] Example 1 is a microelectronic structure that includes:

[0095] a metallization layer including conductive structures; a first disordered layered region laterally spaced from and aligned with a bottom of the conductive structures; and a second disordered layered region above the first disordered layered region, the second disordered layered region laterally spaced from and aligned with a top of the conductive structures.

[0096] Example 2 includes the subject matter of Example 1, further providing that the first disordered layered region has a different disordered layered pattern than the first disordered layered region.

[0097] Example 3 includes the subject matter of any of Examples 1-2, further providing that the metallization layer includes a first spacer portion adjacent a bottom of the conductive structure, and the first disordered layered region includes a material having the same material composition as the first spacer portion.

[0098] Example 4 includes the subject matter of any of Examples 1-3, further providing that the metallization layer includes a second spacer portion adjacent a top of the conductive structure, and the second disordered layered region includes a material having the same material composition as the second spacer portion.

[0099] Example 5 includes the subject matter of Example 4, further specifying that the material is a first material, the second disordered layered region comprises a second material different from the first material, and the second material is a dielectric material.

[0100] Example 6 includes the subject matter of any of Examples 1-5, further providing that the second disordered layered region comprises a material having the same material composition as the conductive structure.

[0101] Example 7 includes the subject matter of any of Examples 1-6, and further specifies that the conductive structure is a first conductive structure; the metallization layer includes a second conductive structure, the second conductive structure being laterally spaced from and aligned with a bottom of the first conductive structure; and the metallization layer includes a cap structure above the second conductive structure, the cap structure being laterally spaced from and aligned with a top of the first conductive structure.

[0102] Example 8 includes the subject matter of Example 7, further providing that the first disordered layered region comprises a material having the same material composition as the second conductive structure.

[0103] Example 9 includes the subject matter of any of Examples 7-8, further providing that the second disordered layered region comprises a material having the same material composition as the cap structure.

[0104] Example 10 includes the subject matter of any of Examples 7-9, further providing that the cap structure includes silicon and nitrogen.

[0105] Example 11 includes the subject matter of any of Examples 7-10, further specifying that the metallization layer includes a first spacer portion adjacent a bottom of the conductive structure, the first spacer portion being between the first conductive structure and the second conductive structure.

[0106] Example 12 includes the subject matter of any of Examples 7-11, further specifying that the metallization layer includes a second spacer portion adjacent to a top of the conductive structure, the second spacer portion being between the first conductive structure and the cap structure.

[0107] Example 13 includes the subject matter of any of Examples 1-12, further providing that the conductive structures have straight sidewalls.

[0108] Example 14 includes the subject matter of any of Examples 1-13, further including a transistor contact, and further specifying that the conductive structure is above and laterally aligned with the transistor contact.

[0109] Example 15 includes the subject matter of Example 14, further specifying that the transistor contact is a gate contact.

[0110] Example 16 includes the subject matter of Example 14, further specifying that the transistor contacts are source / drain contacts.

[0111] Example 17 includes the subject matter of any of Examples 14-16, further specifying that the transistor contact is in a trench, and the trench also includes a metal oxide.

[0112] Example 18 includes the subject matter of Example 17, further specifying that the transistor contact is in the trench between the first portion of the metal oxide and the second portion of the metal oxide.

[0113] Example 19 includes the subject matter of any of Examples 1-18, further specifying that the metallization layer is an M0 layer.

[0114] Example 20 includes the subject matter of any of Examples 1-19, further specifying that the device layer and an additional metallization layer are between the device layer and the additional metallization layer.

[0115] Example 21 includes the subject matter of any of Examples 1-20, further specifying that the microelectronic structure is part of a die, and the first disordered layered region is part of a transition region of the die, is under a guard ring of the die, or is within a frame of the die.

[0116] Example 22 is a microelectronic structure including a metallization layer including first conductive structures alternating with second conductive structures, each of the first conductive structures including a bottom and a top, each cap structure overlying each of the second conductive structures, the bottoms of the first conductive structures being laterally spaced apart from and aligned with the second conductive structures, and the tops of the first conductive structures being laterally spaced apart from and aligned with the cap structures.

[0117] Example 23 includes the subject matter of Example 22, and further provides for: a first disordered layered region laterally spaced from and aligned with a bottom of the first conductive structure; and a second disordered layered region above the first disordered layered region, the second disordered layered region laterally spaced from and aligned with a top of the first conductive structure.

[0118] Example 24 includes the subject matter of Example 23, further providing that the first disordered layered region has a different disordered layered pattern than the first disordered layered region.

[0119] Example 25 includes the subject matter of any of Examples 23-24, further providing that the metallization layer includes a first spacer portion adjacent a bottom of the first conductive structure, and the first disordered layered region includes a material having the same material composition as the first spacer portion.

[0120] Example 26 includes the subject matter of Example 25, further specifying that each first spacer portion is between each first conductive structure and each second conductive structure.

[0121] Example 27 includes the subject matter of any of Examples 23-26, further providing that the metallization layer includes a second spacer portion adjacent a top of the first conductive structure, and the second disordered layered region includes a material having the same material composition as the second spacer portion.

[0122] Example 28 includes the subject matter of Example 27, further specifying that each second spacer portion is between each first conductive structure and each cap structure.

[0123] Example 29 includes the subject matter of any of Examples 27-28, further providing that the material is a first material, the second disordered layered region comprises a second material different from the first material, and the second material is a dielectric material.

[0124] Example 30 includes the subject matter of any of Examples 23-29, further providing that the second disordered layered region comprises a material having the same material composition as the first conductive structure.

[0125] Example 31 includes the subject matter of any of Examples 23-30, further providing that the first disordered layered region comprises a material having the same material composition as the second conductive structure.

[0126] Example 32 includes the subject matter of any of Examples 23-31, further providing that the second disordered layered region comprises a material having the same material composition as the cap structure.

[0127] Example 33 includes the subject matter of any of Examples 23-33, further specifying that the microelectronic structure is part of a die, and the first disordered layered region is part of a transition region of the die, is under a guard ring of the die, or is within a frame of the die.

[0128] Example 34 includes the subject matter of any of Examples 22-33, further providing that the cap structure includes silicon and nitrogen.

[0129] Example 35 includes the subject matter of any of Examples 22-34, further providing that each of the first conductive structures has straight sidewalls.

[0130] Example 36 includes the subject matter of any of Examples 22-35, further including transistor contacts, and further specifying that each of the first conductive structures overlies and is laterally aligned with each of the transistor contacts.

[0131] Example 37 includes the subject matter of Example 36, further specifying that the transistor contacts include one or more gate contacts.

[0132] Example 38 includes the subject matter of Example 36, further specifying that the transistor contacts include one or more source / drain contacts.

[0133] Example 39 includes the subject matter of any of Examples 36-38, further specifying that the transistor contact is in a trench, and the trench also includes a metal oxide.

[0134] Example 40 includes the subject matter of Example 39, further specifying that each of the transistor contacts is between the first portion of the metal oxide and the second portion of the metal oxide in the trench.

[0135] Example 41 includes the subject matter of any of Examples 22-40, and further specifies that the metallization layer is an M0 layer.

[0136] Example 42 includes the subject matter of any of Examples 22-41, further specifying that the device layer and an additional metallization layer are between the device layer and the additional metallization layer.

[0137] Example 43 is a computing device that includes: a die including microelectronic structures, the microelectronic structures including first conductive structures alternating with second conductive structures, each of the first conductive structures including a bottom and a top, and a respective cap structure overlying each of the second conductive structures, the bottoms of the first conductive structures aligned with the second conductive structures and the tops of the first conductive structures aligned with the cap structure; and a circuit board, the die communicatively coupled to the circuit board.

[0138] Example 44 includes the subject matter of Example 43, further providing that the first conductive structure and the second conductive structure are aligned with the disordered layered region.

[0139] Example 45 includes the subject matter of Example 44, and further specifies that the disordered layered region is part of a transition region of the die, is under a guard ring of the die, or is within a frame of the die.

[0140] Example 46 includes the subject matter of any of Examples 43-45, further specifying that the die is included in a package, and the package is communicatively coupled to a circuit board.

[0141] Example 47 includes the subject matter of Example 46, and further specifies that the package is communicatively coupled to the circuit board by solder.

[0142] Example 48 includes the subject matter of any of Examples 43-47, and further specifies that the circuit board is a motherboard.

[0143] Example 49 includes the subject matter of any of Examples 43-48, and further specifies that the die is part of a processing device or a memory device.

[0144] Example 50 includes the subject matter of any of Examples 43-49, and further specifies that the computing device is a mobile computing device.

[0145] Example 51 includes the subject matter of any of Examples 43-49, and further specifies that the computing device is a laptop computing device.

[0146] Example 52 includes the subject matter of any of Examples 43-49, and further specifies that the computing device is a desktop computing device.

[0147] Example 53 includes the subject matter of any of Examples 43-49, and further specifies that the computing device is a wearable computing device.

[0148] Example 54 includes the subject matter of any of Examples 43-49, and further specifies that the computing device is a server computing device.

[0149] Example 55 includes the subject matter of any of Examples 43-49, and further specifies that the computing device is a vehicle computing device.

[0150] Example 56 includes the subject matter of any of Examples 43-55, further specifying that the computing device further includes a display communicatively coupled to the circuit board.

[0151] Example 57 includes the subject matter of any of Examples 43-56, further specifying that the computing device further includes an antenna communicatively coupled to the circuit board.

[0152] Example 58 includes the subject matter of any of Examples 43-57, further specifying that the computing device further includes a housing around the die and the circuit board.

[0153] Example 59 includes any of the subject matter of Example 58, further providing that the housing comprises a plastic material.

[0154] Example 60 is a computing device that includes a die that includes any of the microelectronic structures described in any of Examples 1-42 and a circuit board, the die being communicatively coupled to the circuit board.

[0155] Example 61 includes the subject matter of Example 60, further specifying that the die is included in a package, and the package is communicatively coupled to a circuit board.

[0156] Example 62 includes the subject matter of Example 61, and further specifies that the package is communicatively coupled to the circuit board by solder.

[0157] Example 63 includes the subject matter of any of Examples 60-62, and further specifies that the circuit board is a motherboard.

[0158] Example 64 includes the subject matter of any of Examples 60-63, and further specifies that the die is part of a processing device or a memory device.

[0159] Example 65 includes the subject matter of any of Examples 60-64, and further specifies that the computing device is a mobile computing device.

[0160] Example 66 includes the subject matter of any of Examples 60-64, and further specifies that the computing device is a laptop computing device.

[0161] Example 67 includes the subject matter of any of Examples 60-64, and further specifies that the computing device is a desktop computing device.

[0162] Example 68 includes the subject matter of any of Examples 60-64, and further specifies that the computing device is a wearable computing device.

[0163] Example 69 includes the subject matter of any of Examples 60-64, and further specifies that the computing device is a server computing device.

[0164] Example 70 includes the subject matter of any of Examples 60-64, and further specifies that the computing device is a vehicle computing device.

[0165] Example 71 includes the subject matter of any of Examples 60-70, further specifying that the computing device further includes a display communicatively coupled to the circuit board.

[0166] Example 72 includes the subject matter of any of Examples 60-71, further specifying that the computing device further includes an antenna communicatively coupled to the circuit board.

[0167] Example 73 includes the subject matter of any of Examples 60-72, and further specifies that the computing device further includes a housing around the die and the circuit board.

[0168] Example 74 includes the subject matter of Example 73, further providing that the housing comprises a plastic material.

[0169] Example 75 includes any of the manufacturing methods disclosed herein. [Other possible claims] [Item 1] A metallization layer including a conductive structure; a first disordered layered region laterally spaced from and aligned with a bottom of the conductive structure; a second disordered layered region above the first disordered layered region, the second disordered layered region being laterally spaced from and aligned with a top portion of the conductive structure; A microelectronic structure comprising: [Item 2] The first disordered layered region has a disordered layer pattern different from that of the first disordered layered region. Item 1. The microelectronic structure of item 1. [Item 3] The metallization layer includes a first spacer portion adjacent to the bottom portion of the conductive structure, and the first disordered layered region includes a material having the same material composition as the first spacer portion. Item 1. The microelectronic structure of item 1. [Item 4] The metallization layer includes a second spacer portion adjacent to the top portion of the conductive structure, and the second disordered layered region includes a material having the same material composition as the second spacer portion. Item 1. The microelectronic structure of item 1. [Item 5] the material is a first material, the second disordered layered region comprises a second material different from the first material, and the second material is a dielectric material; Item 5. The microelectronic structure according to item 4. [Item 6] the second disordered layered region comprises a material having the same material composition as the conductive structure; Item 1. The microelectronic structure of item 1. [Item 7] a device layer; an additional metallization layer, the additional metallization layer being between the device layer and the additional metallization layer; Item 1. The microelectronic structure of item 1, further comprising: [Item 8] a metallization layer including first conductive structures alternating with second conductive structures; Equipped with each of the first conductive structures includes a bottom portion and a top portion; a respective cap structure overlies each of the second conductive structures; the bottom of the first conductive structure is laterally spaced from and aligned with the second conductive structure; The top of the first conductive structure is laterally spaced from and aligned with the cap structure. Microelectronic structures. [Item 9] Each cap structure comprises silicon and nitrogen; Item 9. The microelectronic structure according to item 8. [Item 10] each of the first conductive structures has a straight sidewall; Item 9. The microelectronic structure according to item 8. [Item 11] Transistor Contact Furthermore, each of the first conductive structures overlies and is laterally aligned with each of the transistor contacts; Item 9. The microelectronic structure according to item 8. [Item 12] the transistor contacts include one or more gate contacts; Item 12. The microelectronic structure according to item 11. [Item 13] the transistor contacts include one or more source / drain contacts; Item 12. The microelectronic structure according to item 11. [Item 14] the transistor contact is in a trench, the trench also containing a metal oxide. Item 12. The microelectronic structure according to item 11. [Item 15] each of the transistor contacts is between a first portion of metal oxide and a second portion of metal oxide within each trench; Item 15. The microelectronic structure according to item 14. [Item 16] the metallization layer is an M0 layer; Item 9. The microelectronic structure according to item 8. [Item 17] a die including a microelectronic structure, the microelectronic structure including first conductive structures alternating with second conductive structures, each of the first conductive structures including a bottom and a top, a respective cap structure overlying each of the second conductive structures, the bottoms of the first conductive structures aligned with the second conductive structures and the tops of the first conductive structures aligned with the cap structure; a circuit board, the die being communicatively coupled to the circuit board; 1. A computing device comprising: [Item 18] the first conductive structure and the second conductive structure are aligned with the disordered layered region; Item 18. The computing device of item 17. [Item 19] The disordered layered region is a portion of the transition region of the die; beneath the guard ring of said die; or Within the frame of the die, Item 19. The computing device of item 18. [Item 20] the die is contained in a package, the package being communicatively coupled to the circuit board; Item 18. The computing device of item 17.

Claims

1. a metallization layer including conductive structures; a first disordered layered region laterally spaced from and aligned with a bottom of the conductive structure; a second disordered layered region above the first disordered layered region, the second disordered layered region being laterally spaced from and aligned with a top portion of the conductive structure; A microelectronic structure comprising:

2. the first disordered layered region has a different disordered layer pattern than the second disordered layered region; The microelectronic structure of claim 1 .

3. the metallization layer includes a first spacer portion adjacent the bottom portion of the conductive structure, and the first disordered layered region includes a material having the same material composition as the first spacer portion.

3. The microelectronic structure of claim 1 or 2.

4. the metallization layer includes a second spacer portion adjacent the top portion of the conductive structure, and the second disordered layered region includes a material having the same material composition as the second spacer portion. A microelectronic structure according to any one of claims 1 to 3.

5. the material is a first material, the second disordered layered region comprises a second material different from the first material, and the second material is a dielectric material; The microelectronic structure of claim 4.

6. the second disordered layered region comprises a material having the same material composition as the conductive structure; A microelectronic structure according to any one of claims 1 to 5.

7. a device layer; an additional metallization layer, the additional metallization layer being between the device layer and the additional metallization layer; The microelectronic structure of claim 1 , further comprising:

8. a metallization layer including first conductive structures alternating with second conductive structures; Equipped with each of the first conductive structures includes a bottom portion and a top portion; a respective cap structure overlies each of the second conductive structures; the bottom of the first conductive structure is laterally spaced from and aligned with the second conductive structure; The top of the first conductive structure is laterally spaced from and aligned with the cap structure. Microelectronic structures.

9. Each cap structure comprises silicon and nitrogen; The microelectronic structure of claim 8.

10. each of the first conductive structures has a straight sidewall; 10. The microelectronic structure of claim 8 or 9.

11. Transistor Contact Furthermore, each of the first conductive structures overlies and is laterally aligned with each of the transistor contacts; 11. A microelectronic structure according to any one of claims 8 to 10.

12. the transistor contacts include one or more gate contacts; The microelectronic structure of claim 11.

13. the transistor contacts include one or more source / drain contacts; The microelectronic structure of claim 11.

14. the transistor contact is in a trench, the trench also containing a metal oxide.

14. The microelectronic structure of any one of claims 11 to 13.

15. each of the transistor contacts is between a first portion of metal oxide and a second portion of metal oxide within each trench; The microelectronic structure of claim 14.

16. A microelectronic structure as described in any one of claims 11 to 15, wherein the metallization layer is disposed on a substructure including the transistor contact.

17. A microelectronic structure described in any one of claims 8 to 16, wherein the first conductive structure and the second conductive structure are aligned with a disordered layered region.

18. the metallization layer is an M0 layer; 18. The microelectronic structure of any one of claims 8 to 17.

19. a die including microelectronic structures, the microelectronic structures including first conductive structures alternating with second conductive structures, each of the first conductive structures including a bottom and a top, a respective cap structure overlying each of the second conductive structures, the bottoms of the first conductive structures aligned with the second conductive structures and the tops of the first conductive structures aligned with the cap structure; a circuit board, the die being communicatively coupled to the circuit board; 1. A computing device comprising:

20. the first conductive structure and the second conductive structure are aligned with the disordered layered region; 20. The computing device of claim 19.

21. The disordered layered region is a portion of the transition region of the die; beneath the guard ring of said die; or Within the frame of the die, 21. The computing device of claim 20.

22. the die is contained in a package, the package being communicatively coupled to the circuit board; 22. A computing device according to any one of claims 19 to 21.

Images