Regulator Circuit

Abstract

To provide a regulator circuit which protects over-current while reducing the increase of power consumption and circuit scale.SOLUTION: A regulator circuit 200 includes: an operational amplifier OP1 which generates a difference voltage VQ indicating a difference between a feedback voltage VF resulting from dividing an output voltage VOUT and a reference voltage VREF; a first current path HV_MN0 and MN3 which causes a first current I1 corresponding to the difference voltage to flow; a current mirror circuit which is connected to the first current path and sends a current obtained by copying the first current to an output terminal t3 as an output current Iout; and an over-current protection circuit 202 which limits a current value of the output current to a prescribed value or lower. The over-current protection circuit includes a first transistor MN1 which is connected to the first current path and receives a current Ilimit corresponding to the prescribed value as an upper limit current by a gate thereof and causes the first current to flow between a source thereof and a drain thereof.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a regulator circuit, and more particularly to a regulator circuit having an overcurrent protection function. [Background technology]

[0002] As a regulator that generates a power supply voltage with a constant voltage value and supplies this to a load such as an electronic device, a regulator circuit equipped with a protection function that protects the internal circuit from element damage caused by an overcurrent has been proposed (see, for example, FIG. 10 of Patent Document 1).

[0003] FIG. 1 is a circuit diagram showing an example of a regulator circuit 800 described in Patent Document 1.

[0004] 1 receives a power supply voltage VDD1, generates an output voltage VOUT by stepping down the power supply voltage VDD1, and supplies the output voltage VOUT to a load 14. The regulator circuit 800 includes a stabilized power supply circuit 1, a reference voltage generating circuit 2, an operational amplifier 3, P-channel transistors 6 and 16, N-channel transistors 15 and 830, and resistors 17 and 18. The regulator circuit 800 also includes an overcurrent protection circuit consisting of N-channel transistors 19 and 20, a current source 21, and a NOT gate 22.

[0005] The stabilized power supply circuit 1 is provided to realize the reference voltage generation circuit 2, the operational amplifier 3, and the above-mentioned overcurrent protection circuit using elements with a low withstand voltage lower than that of the power supply voltage VDD1. The stabilized power supply circuit 1 generates a power supply voltage VDD2 by stepping down the power supply voltage VDD1, and supplies this to the reference voltage generation circuit 2, the operational amplifier 3, the current source 21, the NOT gate 22, and the transistor 830.

[0006] The reference voltage generating circuit 2 generates a reference voltage VREF based on the power supply voltage VDD2 and supplies this to the operational amplifier 3. The operational amplifier 3 supplies a differential voltage corresponding to the difference between the reference voltage VREF and a feedback voltage Vfb obtained by dividing the output voltage VOUT to the gates of the transistors 15 and 19.

[0007] Transistor 15 passes a current corresponding to the differential voltage through voltage protection transistor 830 to the primary side (transistor 16) of a current mirror circuit composed of transistors 16 and 16. As a result, a current corresponding to the differential voltage is output as an output current from the secondary side (transistor 6) of the current mirror circuit. At this time, resistors 17 and 18 connected in series receive the output current through an output terminal, and an output voltage VOUT corresponding to the output current is applied to phase compensation capacitor 13 and one end of load 14 through the output terminal. Furthermore, a voltage obtained by dividing output voltage VOUT by resistors 17 and 18 is supplied to operational amplifier 3 as the feedback voltage Vfb.

[0008] Based on the power supply voltage VDD2, the current source 21 generates an upper limit current having a current value corresponding to the upper limit of the allowable output current, i.e., the threshold for determining whether or not the output current is an overcurrent, and sends this to node N5. The upper limit current charges the input capacitance of the NOT gate 22. The transistor 19 discharges the input capacitance of the NOT gate 22 by drawing from node N5 a current corresponding to the differential voltage output from the operational amplifier 3.

[0009] Here, while a relatively small output current is being output from the secondary side of the current mirror circuit, the differential voltage is also relatively small, and so the current drawn by transistor 19 from node N5 is also small. Therefore, at this time, if the current drawn by transistor 19 from node N5 is small compared to the constant current output to node N5 by current source 21, the voltage at node N5 rises.

[0010] On the other hand, while a large output current is being output from the secondary side of the current mirror circuit, the differential voltage is also large, and therefore the current drawn by transistor 19 from node N5 is also large. Therefore, at this time, if the current drawn by transistor 19 from node N5 is large compared to the constant current output to node N5 by current source 21, the voltage at node N5 drops.

[0011] The NOT gate 22 receives the power supply voltage VDD2 and operates as follows: When the voltage at node N5 is equal to or higher than the threshold voltage, the NOT gate 22 supplies a low-level signal to the gate of transistor 20, and when the voltage at node N5 is lower than the threshold voltage, the NOT gate 22 supplies a high-level signal to the gate of transistor 20.

[0012] When a high-level signal is received, transistor 20 is turned off. On the other hand, when a low-level signal is received, transistor 20 is turned on and forcibly grounds the gate of transistor 15. This causes a decrease in the current flowing through the primary side of the current mirror circuit (16, 6), and a corresponding decrease in the current flowing through the secondary side of the current mirror circuit, i.e., the output current.

[0013] In this way, when the output current becomes excessive, the overcurrent protection circuit (19 to 21) forcibly reduces the gate voltage of the transistor 15, thereby reducing the output current and protecting the transistor 6 from the excessive current. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Japanese Patent Application Publication No. 2017-62688 Summary of the Invention [Problem to be solved by the invention]

[0015] In the configuration described in Patent Document 1, if a stabilized power supply circuit 1 with poor load regulation characteristics is used, the power supply voltage VDD2 will fluctuate due to the current flowing through transistor 19. This will cause the threshold voltage of the transistor constituting NOT gate 22 to fluctuate, resulting in fluctuations in the output of NOT gate 22. As a result, the above-mentioned reduction process for the output current will be performed intermittently and repeatedly, causing the output current to fluctuate.

[0016] Therefore, in the regulator circuit described in Patent Document 1, it is necessary to adopt a stabilized power supply circuit 1 having high load regulation characteristics, which is configured, for example, as shown in FIG. 2, with a reference voltage generating circuit 102, an operational amplifier 103, a P-channel transistor 104, a capacitor 130, resistors 170 and 180, etc.

[0017] However, a stabilized power supply circuit with good load regulation characteristics generally consumes high power and has a large circuit area. Therefore, the regulator circuit described in Patent Document 1, which requires a stabilized power supply circuit as shown in Figure 2, has the problem of large power consumption and circuit size.

[0018] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a regulator circuit that can provide overcurrent protection while suppressing increases in power consumption and circuit size. [Means for solving the problem]

[0019] A regulator circuit according to the present invention is a regulator circuit that generates an output voltage having a voltage value corresponding to a reference voltage based on a power supply voltage and outputs the output voltage from an output terminal, and includes: a power supply circuit that generates a low power supply voltage having a voltage value lower than the power supply voltage based on the power supply voltage; an operational amplifier that receives the low power supply voltage and operates by dividing the output voltage and generates a differential voltage representing the difference between the reference voltage and a voltage obtained by dividing the output voltage; a first current path that flows a first current corresponding to the differential voltage; a current mirror circuit that sends a current that is a copy of the first current to the output terminal as an output current; and an overcurrent protection circuit that limits the current value of the output current to a predetermined value or less, and the overcurrent protection circuit is connected to the first current path and includes a first transistor that receives a current corresponding to the predetermined value at its gate as an upper limit current and flows the first current between its source and drain. [Effects of the Invention]

[0020] In the present invention, when generating an output current that is a copy of a first current corresponding to the differential voltage between the voltage obtained by dividing the output voltage and a reference voltage, a transistor controlled to pass a current below a predetermined value is connected to a first current path through which the first current passes, and the first current is passed through the transistor, thereby limiting the upper limit of the current value of the output current to a predetermined value.

[0021] With this configuration, even if a power supply circuit with poor load regulation characteristics is used to lower the withstand voltage of each element, it is possible to prevent malfunction of the overcurrent protection circuit that would cause the output current to flutter. Therefore, since a power supply circuit with a simple configuration can be used to lower the withstand voltage of the elements, it is possible to reduce the area and current consumption of the regulator circuit itself. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a circuit diagram showing a configuration of a conventional regulator circuit. [Figure 2] 1 is a circuit diagram showing an example of the configuration of a stabilized power supply circuit having good load regulation characteristics; [Figure 3] 1 is a circuit diagram showing a configuration of a regulator circuit 200 according to a first embodiment of the present invention. [Figure 4] 10 is a circuit diagram showing a configuration of a regulator circuit 200A as an example of a modified example of the regulator circuit 200. FIG. [Figure 5] 10 is a circuit diagram showing the configuration of a regulator circuit 200B as another example of a modification of the regulator circuit 200. FIG. [Figure 6] FIG. 10 is a circuit diagram showing a configuration of a regulator circuit 200C according to a second embodiment of the present invention. [Figure 7] 10 is a diagram showing the correspondence relationship between the load current and the output current Iout, currents I1 and I3. FIG. [Figure 8] 10 is a diagram comparing the current consumption of the overcurrent protection circuit with respect to the load current between regulator circuits 200, 200A, and 200B and regulator circuit 200C. [Figure 9] FIG. 2 is a circuit diagram showing another example of the configuration of the power supply circuit 201. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. [Example]

[0024] FIG. 3 is a circuit diagram showing the configuration of a regulator circuit 200 according to a first embodiment of the present invention.

[0025] The regulator circuit 200 receives a high power supply voltage HV_VDD and a ground potential VSS at a power supply terminal t1 and a ground terminal t2, and generates an output voltage VOUT having a constant voltage value by stepping down the high power supply voltage HV_VDD. The regulator circuit 200 supplies the generated output voltage VOUT to a load LD connected to output terminals t3 and t4. A phase compensation capacitor C0 is connected between the output terminals t3 and t4 in parallel with the load LD.

[0026] 3, the regulator circuit 200 includes the following various circuits and circuit elements that operate by receiving a high power supply voltage HV_VDD and a ground potential VSS via a power supply line L1 connected to a power supply terminal t1 and a ground line Lg connected to a ground terminal t2: That is, the regulator circuit 200 includes a power supply circuit 201, an overcurrent protection circuit 202, a reference voltage generation circuit RV1, an operational amplifier OP1, P-channel transistors HV_MP0 and HV_MP1, N-channel transistors HV_MN0 and HV_MN3, and resistors R1 and R2.

[0027] The power supply circuit 201 is provided to realize the reference voltage generation circuit RV1, the operational amplifier OP1, and the overcurrent protection circuit 202 using low-voltage elements lower than the high power supply voltage HV_VDD, and includes a current source CD0, an N-channel transistor HV_MN1, and a Zener diode DLZ1.

[0028] The current source CD0 receives the high power supply voltage HV_VDD via the power supply line L1, generates a current having a predetermined constant current value based on the high power supply voltage HV_VDD, and sends this current as a bias current Ibias to a node n1. The cathode of a Zener diode DLZ1 is connected to the node n1. The anode of the Zener diode DLZ1 is connected to the ground line Lg.

[0029] The drain of transistor HV_MN1 is connected to power supply line L1, and its gate is connected to node n1. The source of transistor HV_MN1 and its own back gate are connected to power supply line L2. Based on the high power supply voltage HV_VDD, transistor HV_MN1 sends a current corresponding to the voltage of node n1 from its own source to power supply line L2.

[0030] With this configuration, the power supply circuit 201 generates a voltage obtained by stepping down the high power supply voltage HV_VDD as the low power supply voltage VDD on the power supply line L2.

[0031] The reference voltage generating circuit RV1 receives the low power supply voltage VDD, generates a reference voltage VREF that determines the voltage value of the output voltage VOUT based on the low power supply voltage VDD, and supplies this to the inverting input terminal of the operational amplifier OP1.

[0032] One end of resistor R1 is connected to output terminal t3, and the other end is connected to one end of resistor R2, the other end of which is connected to ground line Lg. Resistors R1 and R2 divide the output voltage VOUT and supply the divided voltage as feedback voltage VF to the non-inverting input terminal of operational amplifier OP1.

[0033] The operational amplifier OP1 receives the low power supply voltage VDD and performs the following operation: That is, the operational amplifier OP1 generates a differential voltage VQ representing the difference between the reference voltage VREF and the feedback voltage VF, and supplies this to the gate of the transistor MN3.

[0034] The transistors HV_MP0 and HV_MP1 have their gates connected to each other and their sources and back gates connected to the power supply line L1, and the gate and drain of the transistor HV_MP0 are connected to each other to form a current mirror circuit. The gate and drain of the transistor HV_MP0 on the primary side of the current mirror circuit are connected to the drain of the transistor HV_MN0 for voltage protection, and the drain of the transistor HV_MP1 on the secondary side is connected to one end of the resistor R1 and the output terminal t3 via a node n2.

[0035] The source and back gate of the transistor HV_MN0 are connected to the drain of the transistor MN3, and the low power supply voltage VDD is applied to the gate of the transistor HV_MN0 via the power supply line L2.

[0036] The back gate of the transistor MN3 is connected to the ground line Lg, and the differential voltage VQ is supplied to the gate.

[0037] The overcurrent protection circuit 202 includes a current source CD1 and N-channel transistors MN0 and MN1.

[0038] Based on the low power supply voltage VDD received via the power supply line L2, the current source CD1 generates a current that specifies a predetermined upper limit value that can be tolerated as an output current output by the regulator circuit 200, i.e., a threshold value that is the boundary between whether or not an overcurrent occurs. The current source CD1 supplies this generated current as the upper limit current Ilimit to the drain and gate of the transistor MN0.

[0039] The gates of transistors MN0 and MN1 are connected to each other via node n3, and the sources and back gates of transistors MN0 and MN1 are both connected to the ground line Lg, forming a current mirror circuit in which the gate and drain of transistor MN0 are connected together. The drain of transistor MN1 on the secondary side of the current mirror circuit is connected to the source of transistor MN3.

[0040] The operation of the regulator circuit 200 shown in FIG. 3 will now be described.

[0041] First, operational amplifier OP1 supplies a differential voltage VQ representing the difference between a feedback voltage VF, which has a voltage value corresponding to the output voltage VOUT, and a reference voltage VREF to the gate of transistor MN3. Transistor MN3 sends a current I1 corresponding to the differential voltage VQ from transistor HV_MP0 on the primary side of the current mirror circuit to transistor MN1 of the overcurrent protection circuit 202 via transistor HV_MN0. As a result, an output current Iout, which has a voltage value corresponding to the current I1, is sent from transistor HV_MP1 on the secondary side of the current mirror circuit to resistor R1 and output terminal t3 via node n2. At this time, an output voltage VOUT corresponding to the output current Iout is applied to load LD, and a feedback voltage VF, which has a voltage value corresponding to the output voltage VOUT, is supplied to the non-inverting terminal of operational amplifier OP1.

[0042] Therefore, through a series of processes by the operational amplifier OP1, transistor MN3, current mirror circuit (HV_MP0, HV_MP1), and resistors R1 and R2, an output voltage VOUT having a voltage value corresponding to the reference voltage VREF is applied to the load LD.

[0043] Furthermore, the regulator circuit 200 is provided with an overcurrent protection circuit 202 that prevents the output current Iout from exceeding an upper limit value represented by the upper limit current Ilimit, i.e., becoming an excessive current, and protects the transistor HV_MP1 from the excessive current.

[0044] The overcurrent protection operation by the overcurrent protection circuit 202 will be described in detail below.

[0045] First, the maximum current value I1max of the current I1 that the transistor MN3 can pass is

[0046]

number

[0047] where L N0 =L N1 , L HV_P0 =L HV_P1 L HV_P0 : Gate length of transistor HV_MP0 L HV_P1 : Gate length of transistor HV_MP1 Then, I1max=(W N1 / W N0 )·Ilimit This becomes:

[0048] Next, the maximum current value IOmax of the output current Iout output by the transistor HV_MP1 is

number

[0049] where L HV_P0 =L HV_P1 Then,

number

[0050] That is, the maximum current value IOmax of the output current Iout output by the regulator circuit 200 can be set by the size ratio of the transistors HV_MP0, HV_MP10, MN0 and MN1 and the upper limit current Ilimit.

[0051] In this case, in the overcurrent protection circuit 202, a transistor MN1 is connected to the current path through which the current I1 corresponding to the differential voltage VQ output by the operational amplifier OP1 flows. The transistor MN1 receives a current corresponding to a predetermined value at its gate as an upper limit current Ilimit and passes the current I1 between its source and drain, thereby preventing the output current Iout from becoming excessive.

[0052] This makes it possible to perform overcurrent protection without malfunction, without causing the output current Iout to flutter, even if fluctuations occur in the low power supply voltage VDD supplied to the overcurrent protection circuit 202. Therefore, as the power supply circuit 201 provided in the regulator circuit 200, a power supply circuit (CD0, HV_MN1, DLZ1) having a simple configuration as shown in Fig. 3, although having poor load regulation characteristics, can be used, thereby making it possible to reduce the circuit area and current consumption.

[0053] In the regulator circuit 200 shown in FIG. 3, the load LD is driven by the unipolar transistor HV_MP1, but the load LD may be driven by an externally attached bipolar transistor.

[0054] FIG. 4 is a circuit diagram showing the configuration of a regulator circuit 200A as an example of a modified regulator circuit that has been made in consideration of the above points.

[0055] The regulator circuit 200A shown in FIG. 4 is identical in configuration to that shown in FIG. 3 except that it is newly provided with a power supply relay terminal t5 connected to the power supply line L1 and a base connection terminal t6, and that the drain of the transistor HV_MP1 is connected only to the base connection terminal t6 rather than to the resistor R1 and the output terminal t3, thereby forming an open-drain configuration.

[0056] In the regulator circuit 200A, as shown in FIG. 4, for example, the collector of a high-voltage bipolar transistor TR is externally connected to a power supply relay terminal t5, the base is externally connected to a base connection terminal t6, and the emitter is connected to a load LD.

[0057] The configuration shown in FIG. 4 makes it possible to drive a heavy load LD while limiting the value of the output current Iout flowing through the base of the externally attached bipolar transistor TR so that the current does not become an overcurrent.

[0058] In addition, in the example shown in Figures 3 and 4, a pair of N-channel transistors MN0 and MN1 is used as the current mirror circuit included in the overcurrent protection circuit 202, but a pair of P-channel transistors may also be used.

[0059] FIG. 5 is a circuit diagram showing the configuration of a regulator circuit 200B as another example of a modified regulator circuit that has been made in consideration of the above points.

[0060] The configuration shown in FIG. 5 is the same as that shown in FIG. 3 except that an overcurrent protection circuit 202a is used instead of the overcurrent protection circuit 202 shown in FIG.

[0061] The overcurrent protection circuit 202a shown in FIG. 5 includes a current source CD2 and P-channel transistors HV_MP2 and HV_MP3.

[0062] Transistors HV_MP2 and HV_MP3 have their gates connected to each other via node n4, and their sources and back gates both connected to the power supply line L1, forming a current mirror circuit with the drain and gate of transistor HV_MP2 connected.

[0063] The current source CD2 is connected between the node n4 and the ground line Lg, and draws from the node n4 an upper limit current Ilimit that represents the upper limit of the allowable output current Iout from the regulator circuit 200B, i.e., the threshold for determining whether or not an overcurrent exists. The drain of the secondary-side transistor HV_MP3 of the current mirror circuit (HV_MP2, HV_MP3) is connected to the back gate and source of each of the transistors HV_MP0 and HV_MP1.

[0064] In the regulator circuit 200B, an overcurrent protection circuit 202a including a transistor HV_MP3 that limits the current value of the current I1 corresponding to the differential voltage VQ to a current value corresponding to the upper limit current Ilimit is provided in the current path (HV_MP3, HV_MN0, MN3) through which the current I1 corresponding to the differential voltage VQ flows, thereby preventing the output current Iout from becoming excessive.

[0065] As described above in detail, the regulator circuit according to the present invention includes the following power supply circuit, operational amplifier, first current path, current mirror circuit, and overcurrent protection circuit.

[0066] The power supply circuit (201) generates a low power supply voltage (VDD) based on a power supply voltage (HV_VDD), the low power supply voltage being lower than the power supply voltage. The operational amplifier (OP1) receives the low power supply voltage (VDD) and generates a differential voltage (VQ) representing the difference between a voltage (VF) obtained by dividing the output voltage (VOUT) and a reference voltage (VREF). A first current (I1) corresponding to the differential voltage (VQ) flows through a first current path (HV_MN0, MN3). The current mirror circuits (HV_MP0, HV_MP1) output a current obtained by copying the first current as an output current (Iout) to an output terminal (t3). The overcurrent protection circuits (202, 202a) are connected to the first current path and receive a current corresponding to a predetermined value at their gates as an upper limit current (Ilimit), while limiting the value of the output current (Iout) to a predetermined value or less by a first transistor that flows the first current between its source and drain.

[0067] As a result, even if fluctuations occur in the low power supply voltage (VDD) supplied to the overcurrent protection circuit, it is possible to perform overcurrent protection without causing the output current to flutter and without malfunction. Therefore, with the regulator circuit of the present invention, a power supply circuit with a simple configuration can be used as the power supply circuit (201) that generates the power supply voltage (VDD) to be supplied to the low-voltage circuit or low-voltage element, making it possible to reduce the circuit area and current consumption. [Example]

[0068] FIG. 6 is a circuit diagram showing the configuration of a regulator circuit 200C according to a second embodiment of the present invention.

[0069] The regulator circuit 200C has the same configuration as that shown in Fig. 3, except that an overcurrent protection circuit 202b is used instead of the overcurrent protection circuit 202 shown in Fig. 3. Therefore, only the configuration and operation of the overcurrent protection circuit 202b will be described below.

[0070] The overcurrent protection circuit 202b includes P-channel transistors MP0 to MP3, N-channel transistors MN0, MN1, MN3, and MN4, and current sources CD3 and CD4.

[0071] The gates of transistors MN0 and MN1 are connected to each other via node n3, and the sources and back gates of transistors MN0 and MN1 are both connected to the ground line Lg. The gate and drain of transistor MN0 are connected to each other to form a current mirror circuit.

[0072] The current source CD3 receives the low power supply voltage VDD via the power supply line L2, and generates a current based on the low power supply voltage VDD to stabilize operation during small current output, and sends this current to the node n3 as a bias current Ibias2.

[0073] The transistors MP2 and MP3 have their gates connected to each other, their sources and back gates connected to the power supply line L2, and the drain and gate of the transistor MP3 connected to each other to form a current mirror circuit. This current mirror circuit (MP2, MP3) supplies a current that is a copy of the current I3 corresponding to the differential voltage VQ that represents the difference between the reference voltage VREF and the feedback voltage VF to the sources of the transistors MP0 and MP1 as a feedback output current IFB.

[0074] The gates of the transistors MP0 and MP1 are connected to each other, and the sources of the transistors MP0 and MP1 are connected to the drain of the transistor MP2, forming a current mirror circuit. The back gates of the transistors MP0 and MP1 are connected to the power supply line L2.

[0075] A current source CD4 is connected to the drain of the transistor MP0 on the primary side of the current mirror circuit (MP0, MP1), and the drain of the transistor MP1 on the secondary side is connected to the drain of the transistor MN0.

[0076] The current source CD4 supplies an upper limit current Ilimit, which indicates a predetermined upper limit value that can be tolerated as the output current Iout output by the regulator circuit 200C, to the gates of the transistors MP0 and MP1.

[0077] The drain of the transistor MP3 on the primary side of the current mirror circuit (MP2, MP3) is connected to the drain of the transistor MN4.

[0078] The gate of the transistor MN4 is supplied with the differential voltage VQ output by the operational amplifier OP1, and the source and back gate are connected to the drain of the transistor MN1 on the secondary side of the current mirror circuit (MN0, MN1).

[0079] The operation of the overcurrent protection circuit 202b will be described in detail below.

[0080] First, the current flowing through transistor MN1 is I1, the current output by transistor MN3 in response to differential voltage VQ output from operational amplifier OP1 is I2, and the current output by transistor MN4 in response to said differential voltage VQ is I3.

[0081] At this time, the current I1 is

number

[0082] where L N4 =L N3 Then, I1=[1+(W N4 / W N3 )]·I2 This becomes:

[0083] The maximum current value I1max of the current I1 that the transistor MN1 can pass is

number

[0084] where L N0 =L N1 , L P0 =L P1 So,

number

[0085] Next, the maximum current value IOmax of the output current Iout that the transistor HV_MP1 can flow is

number

[0086] where L HV_P0 =L HV_P1 L HV_P0 : Gate length of transistor HV_MP0 L HV_P1 : Gate length of transistor HV_MP1 Then, IOmax=(W HV_P1 / W HV_P0 )·I2 This becomes:

[0087] Here, the maximum current value I2max of the current I2 that can flow through the transistor MN3 is:

number

[0088] Therefore, the maximum current value IOmax of the output current Iout that the transistor HV_MP1 can actually flow is

number

[0089] Therefore, the maximum current value IOmax of the output current Iout output by the regulator circuit 200C can be set by the bias currents Ilimit and Ibais2 and the size ratios of the transistors HV_MP0, HV_MP10, MN0, MN1, MN3, and MN4.

[0090] In this way, in the regulator circuit 200C, an overcurrent protection circuit 202b including a transistor MN1 that limits the current value of the current I2 (I3) corresponding to the differential voltage VQ, which represents the difference between the feedback voltage VF corresponding to the output voltage and the reference voltage VREF, is provided in the current path through which the current I2 (I3) flows, to a current value corresponding to the upper limit current Ilimit, thereby preventing the output current Iout from becoming excessive.

[0091] In the overcurrent protection circuit 202b, a current source CD4 generates an upper limit current Ilimit based on a current corresponding to the current I3 (=I2) by a current mirror circuit (MP2, MP3), i.e., a current that is a copy of a current that follows the current value of the output current Iout. Furthermore, a maximum current value I1max of the current I1 that the transistor MN1 can flow is set according to the upper limit current Ilimit.

[0092] In short, the overcurrent protection circuit 202b is connected to a first current path (HV_MN0, MN3), receives a current corresponding to a predetermined value at its gate as an upper limit current (Ilimit), and has a first transistor (MN1) that passes a first current (I2, I3) between its source and drain, as well as the following second transistor, first current source path, and upper limit control circuit.

[0093] The second transistor (MN0) has its gate and drain connected to the gate of the first transistor (MN1) via the first node, and its source connected to the source of the first transistor. The first current source (CD4) generates an upper limit current (Ilimit) corresponding to a predetermined value (upper limit).

[0094] The upper limit control circuits (MP0 to MP3) pass a current corresponding to the first current (I2, I3) through the gate and drain of the second transistor when the first current (I2, I3) is equal to or less than the upper limit current, and pass a current corresponding to the upper limit current through the gate and drain of the second transistor when the first current is greater than the upper limit current.

[0095] The upper limit control circuit includes the following first and second current mirror circuits.

[0096] The first current mirror circuit (MP2, MP3) outputs a current obtained by copying a first current (I2, I3) flowing through a first current path (HV_MN0, MN3) in response to a differential voltage (VQ) indicating the difference between a reference voltage (VREF) and a feedback voltage (VF) as a feedback output current (IFB). The second current mirror circuit has a primary-side transistor (MP0) and a secondary-side transistor (MP1) whose gates are connected to each other and whose sources receive the feedback output current. A first current source is connected to the gate and drain of the primary-side transistor (MP0), and the gate and drain of the second transistor are connected to the drain of the secondary-side transistor (MP1).

[0097] With this configuration, in the overcurrent protection circuit 202b, when the output current Iout is equal to or less than the upper limit current value IOmax, the current I1 flowing through the transistor MN1, the current I3 flowing through the transistor MN4, and the output current Iout change in accordance with the load current Iload sent to the load LD, as shown in FIG. 7.

[0098] Therefore, in the overcurrent protection circuits 202 and 202a shown in Figures 3 to 5, the current consumption is constant regardless of the magnitude of the load current Iload, as shown by the dashed dotted line in Figure 8, but in the overcurrent protection circuit 202b, when the load current Iload is equal to or less than the upper limit current value IOmax, the current consumption decreases as the load current Iload becomes smaller.

[0099] In the regulator circuit 200C shown in FIG. 6, the transistor HV_MP1 can also be modified to have an open drain configuration so that the load LD can be driven by the external bipolar transistor TR, as shown in FIG.

[0100] 6, the current I3 generated by the transistor MN4 may be reflected in the bias current that determines the current output capacity of the operational amplifier OP1. This allows the current output capacity of the operational amplifier OP1 to be adjusted according to the load current, thereby reducing the current consumption of the operational amplifier OP1 when there is no load.

[0101] Furthermore, the power supply circuit 201 included in the regulator circuits 200, 200A to 200C may be a switching regulator including capacitors C2 and C3, a coil LC, a transistor QT, and a control circuit CNT as shown in FIG.

[0102] As shown in Figure 9, a high power supply voltage HV_VDD is applied to one end of a capacitor C2, and the other end is grounded at a ground potential VSS. The high power supply voltage HV_VDD is applied to the drain of an N-channel transistor QT, and its source and back gate are connected to one end of a coil LC. The other end of the coil LC is connected to one end of a capacitor C3 and a control circuit CNT. The control circuit CNT generates a control signal that alternately switches the transistor QT between on and off so that the voltage at the other end of the coil LC becomes a predetermined voltage value lower than the high power supply voltage HV_VDD, and supplies this control signal to the gate of the transistor QT. As a result, a low power supply voltage VDD having the predetermined voltage value is generated at the other end of the coil LC. [Explanation of symbols]

[0103] 200 Regulator circuit 201 Power supply circuit 202 Overcurrent protection circuit CD1 current source MN0~MN3, HV_MP0, HV_MP1 transistors OP1 operational amplifier R1, R2 resistance

Claims

1. A regulator circuit that generates an output voltage having a voltage value corresponding to a reference voltage based on a power supply voltage and outputs the output voltage from an output terminal, a power supply circuit that generates a low power supply voltage having a voltage value lower than the power supply voltage based on the power supply voltage; an operational amplifier that operates by receiving the low power supply voltage and generates a differential voltage that represents the difference between a voltage obtained by dividing the output voltage and the reference voltage; a first current path through which a first current corresponding to the differential voltage flows; a current mirror circuit that outputs a current obtained by copying the first current as an output current to the output terminal; an overcurrent protection circuit that limits the current value of the output current to a predetermined value or less, The overcurrent protection circuit includes: a first transistor connected to the first current path, receiving at its gate a current corresponding to the predetermined value as an upper limit current, and causing the first current to flow between its source and drain.

2. The overcurrent protection circuit includes: a second transistor having its gate and drain connected to the gate of the first transistor via a first node and its source connected to the source of the first transistor; 2. The regulator circuit according to claim 1, further comprising: a first current source that generates the upper limit current based on the low power supply voltage and causes the upper limit current to flow through the gate and drain of the second transistor.

3. the output terminal comprises a first terminal from which the output current is output and a second terminal from which the power supply voltage is output; the first terminal is a terminal for externally connecting a base terminal of a bipolar transistor, 3. The regulator circuit according to claim 1, wherein the second terminal is a terminal for externally connecting an emitter terminal of the bipolar transistor together with a load that receives the output voltage.

4. The overcurrent protection circuit includes: a second transistor having its gate and drain connected to the gate of the first transistor via a first node and its source connected to the source of the first transistor; a first current source that generates the upper limit current; an upper limit control circuit that, when the first current is equal to or less than the upper limit current, causes a current corresponding to the first current to flow through the gate and drain of the second transistor, and, when the first current is greater than the upper limit current, causes a current corresponding to the upper limit current to flow through the gate and drain of the second transistor.

5. The upper limit control circuit a first current mirror circuit that outputs a current that is a copy of the first current as a feedback output current; a second current mirror circuit having a primary side transistor and a secondary side transistor whose gates are connected to each other and whose sources receive the feedback output current; the first current source is connected to the gate and drain of the primary-side transistor; 5. The regulator circuit according to claim 4, wherein the gate and drain of the second transistor are connected to the drain of the secondary transistor.

6. 6. The regulator circuit according to claim 5, further comprising a second current source that generates a current for stabilizing operation during a small current output and causes the current to flow to the first node.

7. The power supply circuit includes: a current source that generates a predetermined constant current based on the power supply voltage and sends the current to a second node; a Zener diode having a cathode connected to the second node and an anode connected to a ground line; 5. The regulator circuit according to claim 1, further comprising: an N-channel transistor having a gate connected to the second node and receiving the power supply voltage at its drain to output the low power supply voltage from its source.

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