Hybrid High Bandwidth Memory

Abstract

A high bandwidth memory is provided that includes a region of dynamic random access memory devices, a region of non-volatile memory devices adjacent to the region of dynamic random access memory devices, and a region of logic devices adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices.

Description

[Technical Field]

[0001] The present invention relates generally to the integration of non-volatile (NV) memory and dynamic random access memory (DRAM) on a memory die, and more specifically to dual-state and multi-state memory to form hybrid high-bandwidth memories in artificial intelligence (AI) systems. [Background technology]

[0002] High-bandwidth memory (HBM) can have higher bandwidth by stacking dynamic random access memory (DRAM) dies. The HBM can be connected to a memory controller on a central processing unit (CPU) or graphics processing unit (GPU) through a substrate that may include an interposer that routes electrical connections. Compared to other types of DRAM memory, the HBM can have a wider memory bus; for example, the HBM can have a 512-channel bus, a 1024-channel bus, a 2048-channel bus, or a 4096-channel bus, using bus connections made through the interposer. The 3D stacked random access memory (RAM) of the HBM can interconnect the memory dies and the CPU / GPU using through-silicon vias (TSVs).

[0003] Resistive RAM (ReRAM or RRAM®) is a type of nonvolatile (NV) random-access computer memory that functions by changing the resistance of the storage device. Phase-change memory (PCM) is a type of nonvolatile random-access computer memory that functions by undergoing an amorphous / crystalline phase transition, which has different electrical resistance values. Summary of the Invention

[0004] According to one embodiment of the present invention, a high-bandwidth memory is provided, the high-bandwidth memory including a region of dynamic random access memory devices, a region of non-volatile memory devices adjacent to the region of dynamic random access memory devices, and a region of logic devices adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices.

[0005] According to another embodiment of the present invention, a high-bandwidth memory is provided that includes a region of dynamic random access memory devices, a region of non-volatile memory devices adjacent to the region of dynamic random access memory devices, a region of logic devices adjacent to both the region of dynamic random access memory devices and the region of non-volatile memory devices, and a protective spacer layer that insulates the region of non-volatile memory devices from the region of dynamic random access memory devices and the logic region from the region of dynamic random access memory devices.

[0006] According to yet another embodiment of the present invention, there is provided a method of forming a high bandwidth memory, the method including the steps of: forming a region of dynamic random access memory devices on a die; forming a region of nonvolatile memory devices on the die adjacent to the region of dynamic random access memory devices; forming a region of logic devices on the die adjacent to both the region of dynamic random access memory devices and the region of nonvolatile memory devices; and forming a protective spacer layer insulating the region of nonvolatile memory devices from the region of dynamic random access memory devices and the logic region from the region of dynamic random access memory devices.

[0007] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which should be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0008] The following description provides details of preferred embodiments with reference to the following drawings:

[0009] [Figure 1] 1 is a cross-sectional side view of a stacked high-bandwidth memory device with integrated non-volatile dual / multi-state memory according to one embodiment of the present invention.

[0010] [Figure 2] 1 is a top view illustrating a high-bandwidth memory device having an arrangement of a non-volatile dual / multi-state memory array and a DRAM array integrated with peripheral logic transistors according to one embodiment of the present invention.

[0011] [Figure 3] 1 is a cross-sectional side view of a region of a dynamic random access memory device of a stacked high bandwidth memory device according to one embodiment of the present invention.

[0012] [Figure 4] 1 is a cross-sectional side view illustrating a region of a logic device of a stacked high-bandwidth memory device according to one embodiment of the present invention.

[0013] [Figure 5] FIG. 2 is a cross-sectional side view of a region of a non-volatile dual / multi-state memory device in a stacked high bandwidth memory device according to one embodiment of the present invention.

[0014] [Figure 6] 1 is a cross-sectional side view illustrating a first inter-layer dielectric (ILD) layer formed over a region of a dynamic random access memory device according to one embodiment of the present invention.

[0015] [Figure 7]1 is a cross-sectional side view illustrating a first inter-layer dielectric (ILD) layer over an area of ​​a logic device and an underlying metallization layer in the first ILD layer, according to one embodiment of the present invention.

[0016] [Figure 8] 1 is a cross-sectional side view illustrating a first inter-layer dielectric (ILD) layer over an area of ​​a non-volatile dual / multi-state memory device and an underlying metallization layer in the first ILD layer, according to one embodiment of the present invention.

[0017] [Figure 9] FIG. 2 is a cross-sectional side view illustrating a second inter-layer dielectric (ILD) layer above a first ILD layer over an area of ​​a logic device, and an upper metallization layer within the second ILD layer, according to one embodiment of the present invention.

[0018] [Figure 10] FIG. 1 is a cross-sectional side view illustrating a second inter-layer dielectric (ILD) layer above a first ILD layer over an area of ​​a non-volatile dual / multi-state memory device, and multiple non-volatile memory devices and upper metallization layers within the second ILD layer, according to one embodiment of the present invention.

[0019] [Figure 11] 1 is a cross-sectional side view of a region of a dynamic random access memory device of a stacked high bandwidth memory device according to one embodiment of the present invention.

[0020] [Figure 12] FIG. 10 is a cross-sectional side view illustrating the formation of a lower mold layer on a capping layer, a support mesh on the lower mold layer, and an upper mold layer on the support mesh above a dynamic random access memory device area, according to one embodiment of the present invention.

[0021] [Figure 13]10A-10C are side cross-sectional views illustrating the formation of upper and lower mold layers and a support mesh on a capping layer over the area of ​​a logic device according to one embodiment of the present invention.

[0022] [Figure 14] 10A-10C are side cross-sectional views illustrating the formation of upper and lower mold layers and a support mesh on a capping layer over the area of ​​a non-volatile memory device according to one embodiment of the present invention.

[0023] [Figure 15] FIG. 1C is a cross-sectional side view illustrating multiple trenches formed through a capping layer, upper and lower mold layers, and a support mesh above a region of a dynamic random access memory device, according to one embodiment of the present invention.

[0024] [Figure 16] FIG. 1C is a cross-sectional side view illustrating a bottom capacitor electrode layer formed in a plurality of trenches adjacent to sidewalls of a mold layer and a support mesh above a region of a dynamic random access memory device, according to one embodiment of the present invention.

[0025] [Figure 17] FIG. 10 is a cross-sectional side view illustrating the removal of an upper mold layer above a support mesh above the area of ​​a dynamic random access memory device, according to one embodiment of the present invention.

[0026] [Figure 18] 10A-10C are cross-sectional side views illustrating the formation of a sacrificial liner on a bottom capacitor electrode layer and on a support mesh above a region of a dynamic random access memory device according to one embodiment of the present invention.

[0027] [Figure 19]FIG. 10 is a cross-sectional side view illustrating removal of the sacrificial liner and lower mold layer from the trench and support mesh above the area of ​​the dynamic random access memory device according to one embodiment of the present invention.

[0028] [Figure 20] 1A is a cross-sectional side view illustrating the removal of the upper and lower mold layers and the support mesh from the area of ​​the non-volatile memory device according to one embodiment of the present invention.

[0029] [Figure 21] FIG. 10 is a cross-sectional side view illustrating the formation of a capacitor dielectric layer over the surface of a bottom capacitor electrode layer and a support mesh, and a top capacitor electrode layer formed over the capacitor dielectric layer, according to one embodiment of the present invention.

[0030] [Figure 22] FIG. 1 is a cross-sectional side view illustrating the formation of a second inter-layer dielectric (ILD) layer having a fill layer on a top capacitor electrode layer, a capacitor top plate formed on the fill layer, and a metallization layer formed on the capacitor top plate, in accordance with one embodiment of the present invention.

[0031] [Figure 23] FIG. 2 is a cross-sectional side view of a second inter-layer dielectric (ILD) layer having a metallization layer formed through a protective spacer layer above a region of a logic device, according to one embodiment of the present invention.

[0032] [Figure 24] FIG. 2 is a cross-sectional side view illustrating a second inter-layer dielectric (ILD) layer having a metallization layer formed on a capping layer above a region of a non-volatile memory device, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0033] Embodiments of the present invention provide non-volatile dual-state / multi-state memory components together with dynamic random access memory on the same die. The combination of non-volatile dual-state / multi-state memory components and dynamic random access memory may provide stacked high-bandwidth memory (HBM). The combined non-volatile dual-state / multi-state memory and dynamic random access memory may provide improved computational performance and reduced power consumption. Improved computational performance and reduced power consumption may result from performing computations in near memory, resulting in fewer data fetches from distant DRAM.

[0034] Embodiments of the present invention may also provide dual-state and multi-state memories that form a hybrid high-bandwidth memory (HBM) for artificial intelligence (AI) systems. For neural network (NN) and other AI computations, data may be retrieved from the HBM and computations performed by the GPU / CPU. The performance of such systems may be limited by the HBM-GPU bandwidth. The wider HBM internal bandwidth provides fewer data transfers between off-chip memory (e.g., DRAM) and the computer (e.g., GPU / CPU) cores. By integrating a processing unit (PCM or ReRAM) into each DRAM die, computations can be parallelized across all DRAM dies, eliminating the limitation of HBM-GPU / CPU bandwidth constraints and improving computer performance. Keeping data local within the HBM may boost the energy efficiency of the system because the energy cost of off-chip data fetches is higher than local data fetches.

[0035] In the reduced precision arithmetic used by AI / NNs, memory-limited operation can be improved by leveraging multi-state memory for computation.

[0036] Embodiments of the present invention also provide methods for fabricating non-volatile dual-state / multi-state memory components with dynamic random access memory on the same die. Peripheral logic (e.g., NAND, NOR, XOR, etc.) can also be included on the same die as the non-volatile dual-state / multi-state memory and dynamic random access memory.

[0037] Exemplary applications / uses to which the present invention may be applied include, but are not limited to, high bandwidth memory devices, artificial intelligence systems, or neural networks.

[0038] Aspects of the present invention are described with respect to given example architectures; however, it should be understood that other architectures, structures, substrate materials, and process features and steps may be varied within the scope of aspects of the present invention.

[0039] Referring now to the drawings, in which like numbers represent the same or similar elements, and initially to FIG. 1 , there is shown a cross-sectional side view of a stacked high-bandwidth memory device with integrated non-volatile dual / multi-state memory in accordance with one embodiment of the present invention.

[0040] In one or more embodiments, stacked high-bandwidth memory device 100 may be formed on a package substrate 110, where interposer 120 may be attached and electrically connected to package substrate 110 via interposer solder bumps 125. Package substrate 110 may have substrate solder bumps 115 for electrical connection to the outside world. The package substrate may be a central processing unit (CPU) or graphics processing unit (GPU) substrate, and interposer 120 may route electrical signals between attached dies.

[0041] In various embodiments, logic die 130 (e.g., a memory controller) may be attached to and electrically connected to interposer 120 via logic die solder bumps 135. In various embodiments, processor die 140 (e.g., a CPU / GPU / system-on-chip) may be attached to interposer 120 via processor die solder bumps 145 and electrically connected to package substrate 110. Logic die 130 may be a logic control unit that may provide logic control support, such as address translation, etc. Processor die 140 may provide processor functionality, such as computation, memory access, and executing software code.

[0042] In one or more embodiments, a stack of high bandwidth memory (HBM) dies 152, 154, 156, 158 may be disposed above the logic die 130, where the high bandwidth memory (HBM) dies 152, 154, 156, 158 may be attached to and electrically interconnected with each adjacent HBM die by through silicon vias 166, 168 and micro solder bumps 165, 167. The HBM die 152 adjacent to the logic die 130 may be attached to and electrically interconnected with the logic die 130 by micro solder bumps 151.

[0043] In one or more embodiments, each high bandwidth memory (HBM) die 152, 154, 156, 158 may include a non-volatile dual / multi-state memory device region 172, 174, 176, 178, which may be comprised of a plurality of phase change memory (PCM) and / or resistive memory (ReRAM or RRAM) devices. The high bandwidth memory (HBM) die 152, 154, 156, 158 may include a plurality of dynamic random access memory (DRAM) devices, where the regions of the DRAM devices may be adjacent to the non-volatile dual / multi-state memory device regions 172, 174, 176, 178. The memory may be synchronous dynamic random access memory (SDRAM).

[0044] In various embodiments, the logic die 130 may be interconnected with the processor die 140 via physical layer (PHY) components 137, 147, where the PHY components may be electrically connected to the interposer 120 via physical layer (PHY) micro-solder bumps 149 and interposer interconnects 127. The PHY components 137, 147 may function as network interface controllers with a communication medium (e.g., metal wires) to provide communication between high-bandwidth memory and the processor die 140. The PHY may connect link layer components (e.g., medium access control (MAC)) to the physical communication medium and provide a means for transmitting bits over such an interconnect.

[0045] FIG. 2 is a top view illustrating a high bandwidth memory device having an arrangement of a non-volatile dual / multi-state memory array and a DRAM array integrated with peripheral logic transistors according to one embodiment of the present invention.

[0046] In one or more embodiments, one or more dynamic random access memory (DRAM) regions 210 containing multiple DRAM devices may be on the HBM die 150, which may form a stack of HBM memory dies 152, 154, 156, and 158. One or more non-volatile memory regions 230 may be on the HBM die 150 and adjacent to the DRAM region 210. A logic region 220 may be adjacent to the one or more DRAM regions 210 and the one or more non-volatile memory regions 230 on the HBM die 150. The DRAM region 210 may include a DRAM memory array including SDRAM, and the non-volatile memory region 230 may include a non-volatile dual / multi-state memory array. The logic region 220 may include peripheral logic transistors, which may enable memory functionality. The peripheral logic may provide precharge circuits, sense amplifiers, and the like, which may route bit lines to charge or discharge cell storage capacitors. DRAM regions 210 may be arranged in quadrants separated by logic regions 220, and non-volatile memory regions 230 may be located within each of the DRAM quadrants.

[0047] FIG. 3 is a cross-sectional side view illustrating a region of a dynamic random access memory device of a stacked high bandwidth memory device according to one embodiment of the present invention.

[0048] In one or more embodiments, the DRAM region 210 may include multiple transistor devices, including gate structures 330, 340 and gate spacers / gate caps 350 above the gate structures 330, 340. In various embodiments, the transistor devices may be planar transistors, fin field-effect transistors (FinFETs), nanosheet transistors, nanowire transistors, and combinations thereof. The transistor devices may be U-channel transistor devices having a U-shaped channel 335 around an elongated gate structure 330, resulting in a larger channel length within a small device footprint. The gate structure 330 of the U-channel transistor device may function as a word line for memory access operations. Bit lines may be formed to the U-channel transistor device through bit line contacts. Isolation regions 320 may be formed in the substrate 310 to isolate the transistor devices and electrically separate various regions of the substrate 310. The substrate may be a semiconductor material on or within which electronic devices may be fabricated. A dielectric fill 360 may be formed on the substrate between adjacent transistor devices for isolation, where the dielectric fill 360 may be silicon oxide (SiO), silicon nitride (SiN), a low-k dielectric, or a combination thereof. The storage node contacts (SNC) 370 may be vias formed to source / drain contacts 375.

[0049] FIG. 4 is a cross-sectional side view illustrating a region of a logic device of a stacked high-bandwidth memory device according to one embodiment of the present invention.

[0050] In one or more embodiments, logic region 220 may include a transistor device including a gate 380 above a channel, and a gate spacer / dielectric cap 390 above gate 380, dielectric filler 360, and source / drain contacts 400 to the substrate. In various embodiments, the transistor device may be a planar transistor, a FinFET transistor, a nanosheet transistor, a nanowire transistor, and combinations thereof.

[0051] FIG. 5 is a cross-sectional side view illustrating a region of a non-volatile dual / multi-state memory device in a stacked high bandwidth memory device according to one embodiment of the present invention.

[0052] In one or more embodiments, the non-volatile memory region 230 may include a transistor device including a gate 410 and a gate spacer / dielectric cap 420. A dielectric fill 360 may be formed over the transistor, and source / drain contacts 430 may be formed through the dielectric fill 360 to the transistor device. In various embodiments, the transistor device may be a planar transistor, a FinFET transistor, a nanosheet transistor, a nanowire transistor, and combinations thereof.

[0053] FIG. 6 is a cross-sectional side view illustrating a first inter-layer dielectric (ILD) layer formed over a region of a dynamic random access memory device according to one embodiment of the present invention.

[0054] In one or more embodiments, a first inter-layer dielectric (ILD) layer 440 may be formed over the dynamic random access memory device region 210, where the first inter-layer dielectric (ILD) layer 440 may be formed by blanket deposition, for example, chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0055] In various embodiments, the first interlayer dielectric (ILD) layer 440 can be a low-k dielectric material, including, but not limited to, carbon-doped silicon oxide (SiO:C, CDO), fluorine-doped silicon oxide (SiO:F), porous silicon dioxide (p-SiO), spin-on dielectric materials (e.g., hydrogen silsesquioxane, methyl silsesquioxane, etc.), other dielectric materials having k values ​​less than 3.9, and combinations thereof.

[0056] In various embodiments, the first interlayer dielectric (ILD) layer 440 can have a thickness in a range from about 40 nanometers (nm) to about 500 nm, or from about 60 nm to about 100 nm, although other thicknesses are also contemplated.

[0057] FIG. 7 is a cross-sectional side view illustrating a first inter-layer dielectric (ILD) layer over an area of ​​a logic device and an underlying metallization layer in the first ILD layer, according to one embodiment of the present invention.

[0058] In one or more embodiments, a portion 450 of the first inter-layer dielectric (ILD) layer 440 may be formed over the logic device region 220, where the portion 450 of the first inter-layer dielectric (ILD) layer 440 may be formed by blanket deposition at the same time that the first inter-layer dielectric (ILD) layer 440 is formed over the dynamic random access memory device region 210. The ILD layer 440 may be formed in a single deposition simultaneously over each of the dynamic random access memory device region 210, the logic device region 220, and the non-volatile memory region 230.

[0059] In various embodiments, portion 450 of first inter-layer dielectric (ILD) layer 440 can have a thickness in a range from about 40 nanometers (nm) to about 500 nm, or from about 60 nm to about 100 nm, although other thicknesses are contemplated. Portion 450 of first inter-layer dielectric (ILD) layer 440 can have the same thickness as first inter-layer dielectric (ILD) layer 440 formed over region 210 of the dynamic random access memory device.

[0060] In various embodiments, a lower metallization layer including, but not limited to, one or more metal lines 470 and one or more vias 460 may be formed in a portion 450 of the first ILD layer 440 above the area of ​​the logic device, where the metal lines 470 and vias 460 may be formed by a damascene or dual damascene type deposition process.

[0061] In various embodiments, the metal lines 470 and vias 460 may be composed of conductive metals such as tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), tantalum (Ta), and / or metal compounds such as titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten nitride (WN), and combinations thereof.

[0062] FIG. 8 is a cross-sectional side view illustrating a first inter-layer dielectric (ILD) layer over an area of ​​a non-volatile dual / multi-state memory device and an underlying metallization layer in the first ILD layer, according to one embodiment of the present invention.

[0063] In various embodiments, a lower metallization layer including, but not limited to, one or more metal lines 490 and one or more vias 480 may be formed in a portion 450 of the first ILD layer 440 over an area of ​​the non-volatile dual / multi-state memory device, where the metal lines 490 and vias 480 may be formed by a damascene or dual damascene type deposition process.

[0064] In various embodiments, the metal lines 490 and vias 480 may be composed of conductive metals such as tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), tantalum (Ta), and / or metal compounds such as titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten nitride (WN), and combinations thereof.

[0065] FIG. 9 is a cross-sectional side view showing a second interlayer dielectric (ILD) layer above a first ILD layer over an area of ​​a logic device, and an upper metallization layer within the second ILD layer, in accordance with one embodiment of the present invention.

[0066] In various embodiments, a second inter-layer dielectric (ILD) layer 455 may be formed over a portion 450 of the first inter-layer dielectric (ILD) layer 440, where the second inter-layer dielectric (ILD) layer 455 may be formed by blanket deposition above the logic region 220. The second inter-layer dielectric (ILD) layer 455 may cover the top surfaces of the metal lines 470.

[0067] In various embodiments, an upper metallization layer including, but not limited to, one or more metal lines 510 and one or more vias 500 may be formed in the second ILD layer 455, where the metal lines 510 and vias 500 may be formed by a damascene or dual damascene type deposition process.

[0068] In various embodiments, the second interlayer dielectric (ILD) layer 455 can have a thickness in a range from about 40 nanometers (nm) to about 500 nm, or from about 60 nm to about 100 nm, although other thicknesses are contemplated.

[0069] In various embodiments, the second interlayer dielectric (ILD) layer 455 can be a low-k dielectric material, where the second interlayer dielectric (ILD) layer 455 can be the same dielectric material as the first interlayer dielectric (ILD) layer 440 and the portion 450 of the first interlayer dielectric (ILD) layer 440.

[0070] In one or more embodiments, a cover layer 520 may be formed over the second ILD layer 455, and the cover layer 520 may function as an etch stop layer. The cover layer 520 may be formed over the metal lines 510 and the second ILD layer 455 by conformal deposition, such as atomic layer deposition (ALD) or plasma-enhanced atomic layer deposition (PEALD).

[0071] In one or more embodiments, the cover layer 520 can be a dielectric layer, such as, for example, SiCO, SiC, SiN, or the like.

[0072] In various embodiments, the cover layer 520 can have a thickness in a range from about 3 nanometers (nm) to about 60 nm, or from about 10 nm to about 30 nm, although other thicknesses are contemplated.

[0073] FIG. 10 is a cross-sectional side view showing a second inter-layer dielectric (ILD) layer above a first ILD layer over an area of ​​a non-volatile dual / multi-state memory device, and multiple non-volatile memory devices and upper metallization layers within the second ILD layer, according to one embodiment of the present invention.

[0074] In various embodiments, a second inter-layer dielectric (ILD) layer 455 may be formed over a portion 450 of the first inter-layer dielectric (ILD) layer 440 in the non-volatile memory region 230, where the second inter-layer dielectric (ILD) layer 455 may be formed by blanket deposition above the non-volatile memory region 230. The second inter-layer dielectric (ILD) layer 455 may cover the top surfaces of the vias 480 and the metal lines 490.

[0075] In various embodiments, one or more non-volatile memory devices can be formed in the second ILD layer 455, where the non-volatile memory devices can include a bottom memory electrode 530, a top memory electrode 550, and a memory material layer 540 between the top memory electrode 550 and the bottom memory electrode 530. In various embodiments, the memory material layer 540 can be a resistive memory material or a phase change memory material.

[0076] In various embodiments, an upper metallization layer including, but not limited to, one or more metal lines 560 and one or more vias may be formed in the second ILD layer 455, where the metal lines 560 and vias may be formed by a damascene or dual damascene type deposition process. The metal lines 560 overlie and are in electrical communication with the top memory electrode 550 and may connect the non-volatile memory device to additional layers and / or contacts. The bottom memory electrode 530 may connect the non-volatile memory device to one or more transistor devices 420 in the non-volatile memory region 230.

[0077] In various embodiments, the second interlayer dielectric (ILD) layer 455 can have a thickness in a range from about 40 nanometers (nm) to about 500 nm, or from about 60 nm to about 100 nm, although other thicknesses are contemplated.

[0078] In one or more embodiments, a cover layer 520 may be formed on the second ILD layer 455 above the non-volatile memory region 230, and the cover layer 520 may act as an etch stop layer.

[0079] FIG. 11 is a cross-sectional side view illustrating a region of a dynamic random access memory device of a stacked high bandwidth memory device according to one embodiment of the present invention.

[0080] In various embodiments, a lithography mask may be used to protect the logic region 220 and the non-volatile memory region 230, and the cover layer 520 over the DRAM region 210 may be removed. The first ILD layer 440 and the second ILD layer 455 may be removed using a selective directional etch, where the first ILD layer 440 and the second ILD layer 455 are the same material and may be removed simultaneously using the same etch process. Removal of the first ILD layer 440 and the second ILD layer 455 may expose the top surfaces of the dielectric fill 360 and the storage node contact (SNC) 370.

[0081] FIG. 12 is a cross-sectional side view illustrating the formation of a lower mold layer on a capping layer, a support mesh on the lower mold layer, and an upper mold layer on the support mesh above a dynamic random access memory device area, in accordance with one embodiment of the present invention.

[0082] In one or more embodiments, a protective spacer layer 570 may be formed on the top surface of the dielectric filling material 360 and the electrical connections 370 in the DRAM region 210, where the protective spacer layer 570 may be formed by conformal deposition (e.g., ALD, PEALD). In various embodiments, the protective spacer layer 570 may be a dielectric material that may function as an etch stop layer, such as SiOC, SiC, SiN, AlNx, AlOx, etc. The protective spacer layer 570 may cover the underlying dielectric filling material 360.

[0083] In various embodiments, protective spacer layer 570 can have a thickness in a range from about 3 nanometers (nm) to about 100 nm, or from about 10 nm to about 30 nm, although other thicknesses are contemplated.

[0084] In one or more embodiments, lower mold layer 580 may be formed over protective spacer layer 570, where mold layer 580 may be formed by blanket deposition. In various embodiments, lower mold layer 580 may be a different dielectric oxide material than the material of protective spacer layer 570, such as SiO, SiOC, AlOx, etc., such that lower mold layer 580 may be selectively removed as a sacrificial layer, while protective spacer layer 570 acts as an etch stop to protect underlying layers.

[0085] In various embodiments, lower mold layer 580 can have a thickness in the range of about 200 nm to about 3000 nm, or about 400 nm to about 1500 nm, although other thicknesses are contemplated.

[0086] In one or more embodiments, support mesh 590 may be formed over lower mold layer 580, where support mesh 590 may be formed by blanket deposition. Support mesh 590 may be a different dielectric oxide material than the material of lower mold layer 580, such as SiO, SiOC, AlOx, etc., such that lower mold layer 580 may be selectively removed as a sacrificial layer while support mesh 590 remains.

[0087] In various embodiments, the support mesh 590 can have a thickness in the range of about 5 nm to about 100 nm, or about 15 nm to about 50 nm, although other thicknesses are contemplated.

[0088] In one or more embodiments, upper mold layer 600 may be formed over support mesh 590, where upper mold layer 600 may be formed by blanket deposition. Upper mold layer 600 may be a different dielectric oxide material than the material of support mesh 590, such as SiO, SiOC, AlOx, etc., so that the upper mold layer may be selectively removed. Upper mold layer 600 may be the same material as lower mold layer 580.

[0089] In various embodiments, upper mold layer 600 can have a thickness in the range of about 10 nm to about 1000 nm, or about 20 nm to about 500 nm, although other thicknesses are contemplated.

[0090] FIG. 13 is a cross-sectional side view illustrating the formation of upper and lower mold layers and a support mesh on a capping layer over the area of ​​a logic device according to one embodiment of the present invention.

[0091] In various embodiments, a protective spacer layer 570 may be formed on the cover layer 520 in the logic region 220, where the protective spacer layer 570 may be formed by conformal deposition (e.g., ALD, PEALD). The protective spacer layer 570 may extend down along the sides of a portion 450 of the first inter-layer dielectric (ILD) layer 440 and a second inter-layer dielectric (ILD) layer 455. In various embodiments, the protective spacer layer 570 may be a dielectric material that can function as an etch stop layer, where the protective spacer layer 570 may be a different dielectric material than the cover layer 520 and the lower mold layer 580. In subsequent processes, the upper and lower mold layers may be removed without damaging the ILD layers 450 and 455, which are completely covered by the protective spacer layer 570.

[0092] In various embodiments, the lower mold layer 580, support mesh 590, and upper mold layer 600 may be formed over the protective spacer layer 570 in various regions.

[0093] FIG. 14 is a cross-sectional side view illustrating the formation of upper and lower mold layers and a support mesh on a capping layer over the area of ​​a non-volatile memory device according to one embodiment of the present invention.

[0094] In various embodiments, a protective spacer layer 570 may be formed over the cover layer 520 in the non-volatile memory region 230, where the protective spacer layer 570 may be formed by conformal deposition (e.g., ALD, PEALD). The protective spacer layer 570 may extend down along the sides of a portion 450 of the first inter-layer dielectric (ILD) layer 440 and the second inter-layer dielectric (ILD) layer 455. The protective spacer layer 570 may insulate the non-volatile memory device region 230 from the dynamic random access memory device region 210 and from the logic region 220. The protective spacer layer 570 may also protect the BEOL low-k dielectric layers (440, 455, and 450) from damage when the mold layers 580, 600 are removed during subsequent process steps during DRAM capacitor formation.

[0095] In various embodiments, the lower mold layer 580, support mesh 590, and upper mold layer 600 may be formed over the protective spacer layer 570 in various regions.

[0096] FIG. 15 is a cross-sectional side view illustrating multiple trenches formed through a capping layer, upper and lower mold layers, and a support mesh above a region of a dynamic random access memory device, according to one embodiment of the present invention.

[0097] In one or more embodiments, multiple trenches 610 may be formed through the upper mold layer 600, the support mesh 590, the lower mold layer 580, and the protective spacer layer 570, where the trenches 610 may be formed by lithographic masking and patterning, and selective directional etching, such as reactive ion etching (RIE). The trenches 610 may overlie and be aligned with the underlying storage node contacts (SNCs) 370.

[0098] FIG. 16 is a cross-sectional side view illustrating a bottom capacitor electrode layer formed in a plurality of trenches and adjacent to the sidewalls of a mold layer and support mesh above a region of a dynamic random access memory device, according to one embodiment of the present invention.

[0099] In one or more embodiments, the bottom capacitor electrode layer 620 may be formed in the plurality of trenches 610, where the bottom capacitor electrode layer 620 may be formed by conformal deposition. The bottom capacitor electrode layer 620 may be on the sidewalls of the top mold layer 600, the support mesh 590, the bottom mold layer 580, and the protective spacer layer 570. Portions of the bottom capacitor electrode layer 620 may be removed from the top surface of the top mold layer 600 by first depositing a sacrificial material, such as OPL, into the trenches 610, followed by etching to remove the electrode layer above the top surface, followed by OPL ashing.

[0100] In various embodiments, the bottom capacitor electrode layer 620 can be a conductive material including, but not limited to, a metal, such as tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), tantalum (Ta), and / or a metal compound, such as titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten nitride (WN), and combinations thereof.

[0101] In various embodiments, the bottom capacitor electrode layer 620 can have a thickness in the range of about 2 nm to about 5 nm, or about 5 nm to about 15 nm, although other thicknesses are contemplated.

[0102] FIG. 17 is a cross-sectional side view illustrating the removal of the upper mold layer above the support mesh above the area of ​​the dynamic random access memory device according to one embodiment of the present invention.

[0103] In one or more embodiments, the top mold layer 600 may be removed using, for example, a selective isotropic etch (e.g., a wet chemical etch), where removal of the top mold layer 600 may expose a portion of the support mesh 590. An upper section of the bottom capacitor electrode layer 620 may extend over the support mesh 590, where the upper section of the bottom capacitor electrode layer 620 may be free-standing on top of the support mesh 590 without any other support. The top mold layer 600 may be removed from the logic region 220 and the non-volatile memory region 230, where the support mesh 590 may be exposed.

[0104] FIG. 18 is a cross-sectional side view illustrating the formation of a sacrificial liner on the bottom capacitor electrode layer and on the support mesh above the area of ​​the dynamic random access memory device according to one embodiment of the present invention.

[0105] In one or more embodiments, a sacrificial liner 630 may be formed on the bottom capacitor electrode layer 620 and on the exposed surface of the support mesh 590 above the dynamic random access memory device region 210. By controlling the thickness of the conformal layer to be greater than ½ CD2, the sacrificial layer 630 may pinch off the space above the mesh layer in the DRAM region. A subsequent anisotropic etch of the sacrificial liner may remove the sacrificial liner 630 in the logic and non-volatile memory regions. This allows for removal of the exposed mesh layer in the logic and non-volatile memory regions without damaging the mesh layer in the DRAM region. Only if CD1 > CD2 can the conformal spacer liner pinch off CD2 without pinching off CD1. The process is spacer liner deposition followed by spacer RIE to expose the mesh in the logic and non-volatile memory regions.

[0106] In various embodiments, the sacrificial liner 630 can be a-Si, a-SiGe, AlOx, or the like.

[0107] In various embodiments, the sacrificial liner 630 can have a thickness in the range of about 5 nm to about 50 nm, or about 10 nm to about 20 nm, although other thicknesses are contemplated. The thickness of the sacrificial liner 630 can result in the lower section of the trench 610 between the bottom capacitor electrode layers 620 being pinched off.

[0108] FIG. 19 is a cross-sectional side view illustrating removal of the sacrificial liner and lower mold layer from the trench and support mesh above the area of ​​the dynamic random access memory device according to one embodiment of the present invention.

[0109] In one or more embodiments, the sacrificial liner 630 and the lower mold layer 580 may be removed using, for example, a selective isotropic etch. Removal of the lower mold layer 580 may form gaps 585 between the support mesh 590 and the protective spacer layer 570 and between the sidewalls of the bottom capacitor electrode layer 620. Note that some open areas in the mesh layer may be formed where the sacrificial liner is not pinched off (not shown), so that the mold layer 580 may be accessed during the isotropic etch process.

[0110] FIG. 20 is a cross-sectional side view illustrating the removal of the upper and lower mold layers and support mesh from the area of ​​the non-volatile memory device according to one embodiment of the present invention.

[0111] Removal of the sacrificial liner 630 and the lower mold layer 580 may expose the protective spacer layer 570 in the non-volatile memory region 230 .

[0112] FIG. 21 is a cross-sectional side view illustrating the formation of a capacitor dielectric layer on the surface of a bottom capacitor electrode layer and a support mesh, and a top capacitor electrode layer formed on the capacitor dielectric layer, in accordance with one embodiment of the present invention.

[0113] In one or more embodiments, a capacitor dielectric layer 640 may be formed over the bottom capacitor electrode layer 620, where the capacitor dielectric layer 640 may be formed by conformal deposition (eg, ALD, PEALD).

[0114] Examples of materials for the dielectric layer 640 include: Al2O3, ZrO2, Y2O3, HfO2, Ta2O5, TiOx, BaHfO2, CoTiOx, SrTiO3, and the like.

[0115] In various embodiments, the capacitor dielectric layer 640 can have a thickness in a range from about 1 nanometer (nm) to about 50 nm, or from about 6 nm to about 20 nm, although other thicknesses are also contemplated.

[0116] In one or more embodiments, the top capacitor electrode layer 650 may be formed on the capacitor dielectric layer 640, where the capacitor dielectric layer 640 may be formed by conformal deposition (e.g., ALD, PEALD). The top capacitor electrode layer 650 may be composed of the same material as the bottom capacitor electrode layer 620.

[0117] In various embodiments, the top capacitor electrode layer 650 can have a thickness in a range from about 2 nm to about 50 nm, or from about 3 nm to about 15 nm, although other thicknesses are contemplated. The capacitor dielectric layer 640 and the top capacitor electrode layer 650 can leave the gap 585 surrounded by the top capacitor electrode layer 650.

[0118] FIG. 22 is a cross-sectional side view illustrating the formation of a second interlayer dielectric (ILD) layer having a fill layer on a top capacitor electrode layer, a capacitor top plate formed on the fill layer, and a metallization layer formed on the capacitor top plate, in accordance with one embodiment of the present invention.

[0119] In one or more embodiments, a fill layer 660 may be formed on the top capacitor electrode layer 650 and in the gap 585, where the fill layer 660 may be formed, for example, by chemical vapor deposition (CVD) to form poly-Si or poly-SiGe.

[0120] In one or more embodiments, a capacitor top plate 670 may be formed on the fill layer 660, where the capacitor top plate 670 may be formed by a CVD, ALD, or PVD metal deposition process.

[0121] In one or more embodiments, a second inter-layer dielectric (ILD) layer 680 may be formed over the capacitor top plate 670, and a top metal line 700 and a metal via 690 may be formed in the second inter-layer dielectric (ILD) layer 680. The top metal line 700 and the metal via 690 may be electrically connected to the capacitor top plate 670.

[0122] FIG. 23 is a cross-sectional side view illustrating a second inter-layer dielectric (ILD) layer having a metallization layer formed through a protective spacer layer above a region of a logic device, according to one embodiment of the present invention.

[0123] In one or more embodiments, a portion 710 of the second interlayer dielectric (ILD) layer 680 having a metallization layer including vias 720 and metal lines 730 can be formed through the protective spacer layer 570 above the logic device region 220.

[0124] FIG. 24 is a cross-sectional side view illustrating a second inter-layer dielectric (ILD) layer having a metallization layer formed on a capping layer above a region of a non-volatile memory device in accordance with one embodiment of the present invention.

[0125] In one or more embodiments, a portion 710 of the second interlayer dielectric (ILD) layer 680 having a metallization layer including vias 740 and metal lines 750 can be formed through the protective spacer layer 570 above the region 230 of the non-volatile memory.

[0126] This embodiment may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as in a storage access network). If the designer does not manufacture the chip or the photolithography masks used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into an appropriate format (e.g., GDSII) for the manufacture of photolithography masks, which typically include multiple copies of the chip design to be formed on a wafer. The photolithography masks are utilized to define the areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0127] Methods such as those described herein can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to sophisticated computer products with displays, keyboards or other input devices, and central processing units.

[0128] It should also be understood that material compounds are described in terms of the elements listed, e.g., SiGe. These compounds may contain different ratios of elements within the compound, e.g., SiGe may contain Si x Ge 1-x where x is less than or equal to 1, etc. Additionally, other elements may be included in the compound and still function according to the present principles. Compounds with additional elements are referred to herein as alloys.

[0129] References herein to "one embodiment" or "an embodiment," and other variations thereof, mean that a particular feature, structure, characteristic, etc. described in connection with an embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment," and any other variations thereof, appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

[0130] It should be understood that the use of any of the following, " / ," "and / or," and "at least one of," is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of both alternatives (A and B), for example, in the case of "A / B," "A and / or B," and "at least one of A and B." As one further example, in the case of "A, B, and / or C" and "at least one of A, B, and C," such language is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first and second listed alternatives (A and B), or the selection of only the first and third listed alternatives (A and C), or the selection of only the second and third listed alternatives (B and C), or the selection of all three alternatives (A, B, and C). This can be extended to many of the items listed, as would be readily apparent to one of ordinary skill in this and related arts.

[0131] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit example embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0132] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like are used herein for ease of description and may describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" such other elements or features. Thus, the term "below" can encompass both an orientation of above and below. A device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. Furthermore, when a layer is referred to as being "between" two layers, it will also be understood that it may be the only layer between the two layers, or that one or more intervening layers may also be present.

[0133] Terms such as "first," "second," etc. may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below could be referred to as a second element without departing from the scope of the present concepts.

[0134] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that it can be directly on the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that it can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0135] While preferred embodiments of the device and method for manufacturing the device have been described, which are intended to be illustrative and not limiting, it should be noted that modifications and variations may be made by those skilled in the art in light of the above teachings. It is hereby understood that changes may be made within the specific embodiments disclosed within the scope of the invention and outlined by the appended claims. Having thus described aspects of the invention with the detail and specificity required by the patent laws, it is in the appended claims that what is claimed and desired to be protected by Letters Patent is set forth.

Claims

1. 1. A high bandwidth memory, comprising: a plurality of dynamic random access memory device regions; a region of a plurality of non-volatile memory devices laterally adjacent the region of the plurality of dynamic random access memory devices; a region of a plurality of logic devices laterally adjacent both the region of the plurality of dynamic random access memory devices and the region of the plurality of non-volatile memory devices; a dielectric filler between and over the plurality of logic devices, between and over the plurality of nonvolatile memory devices, and between and over the plurality of dynamic random access memory devices, the dielectric filler having a top surface at a first level; an interlayer dielectric overlying the dielectric fill in the regions of the plurality of logic devices and the regions of the plurality of non-volatile memory devices, the interlayer dielectric having an upper surface at a second level and having a trench between the regions of the plurality of non-volatile memory devices and the regions of the plurality of logic devices; and a protective spacer layer extending over the interlayer dielectric in the regions of the plurality of nonvolatile memory devices and over the interlayer dielectric in the regions of the plurality of logic devices, and over the regions of the plurality of dynamic random access memory devices, in direct contact with vertical sidewalls of the trench, and having a top surface in the regions of the plurality of dynamic random access memory devices consistently lower than the second level, the protective spacer layer electrically insulating the regions of the plurality of nonvolatile memory devices and the regions of the plurality of logic devices from a region above the protective spacer layer over the regions of the plurality of dynamic random access memory devices. A memory comprising:

2. The memory of claim 1, wherein the protective spacer layer separates the regions of the plurality of logic devices from the regions of the plurality of non-volatile memory devices.

3. The memory of claim 1 , wherein the region of the plurality of non-volatile memory devices comprises a layer of memory material between a top memory electrode and a bottom memory electrode.

4. 10. The memory of claim 1, wherein the protective spacer layer is a dielectric material selected from the group consisting of silicon oxycarbide (SiOC), silicon carbide (SiC), silicon nitride (SiN), aluminum nitride (AlNx), and aluminum oxide (AlOx).

5. 10. The memory of claim 1, further comprising a bottom capacitor electrode layer overlying storage node contacts in said region of said plurality of dynamic random access memory devices.

6. 6. The memory of claim 5, further comprising: a capacitor dielectric layer on said bottom capacitor electrode layer and a top capacitor electrode layer on said capacitor dielectric layer over said region of said plurality of dynamic random access memory devices.

7. The memory of claim 6 further comprising a support mesh, said bottom capacitor electrode layer in contact with said support mesh.

8. 8. The memory of claim 7, wherein the support mesh is selected from the group of dielectric oxide materials consisting of silicon oxide (SiO), silicon oxycarbide (SiOC), and aluminum oxide (AlOx).

9. 10. The memory of claim 1, further comprising a cover layer over the regions of the plurality of logic devices and the regions of the plurality of non-volatile memory devices, the cover layer overlying a layer of memory material between a top memory electrode and a bottom memory electrode.

10. forming a plurality of dynamic random access memory device regions on the die; forming an area on the die of a plurality of non-volatile memory devices laterally adjacent the area of ​​the plurality of dynamic random access memory devices; forming an area of ​​a plurality of logic devices on the die laterally adjacent both the area of ​​the plurality of dynamic random access memory devices and the area of ​​the plurality of non-volatile memory devices; forming a dielectric filler having a top surface at a first level between and over the plurality of logic devices, between and over the plurality of non-volatile memory devices, and between and over the plurality of dynamic random access memory devices; forming an interlayer dielectric over the dielectric filler in the regions of the plurality of logic devices and the regions of the plurality of non-volatile memory devices, the interlayer dielectric having an upper surface at a second level and having a trench between the regions of the plurality of non-volatile memory devices and the regions of the plurality of logic devices; and forming a protective spacer layer that extends over the interlayer dielectric in the regions of the nonvolatile memory devices and over the interlayer dielectric in the regions of the logic devices, and over the regions of the dynamic random access memory devices, in direct contact with vertical sidewalls of the trenches, and whose top surface in the regions of the dynamic random access memory devices is consistently lower than the second level, electrically insulating the regions of the nonvolatile memory devices and the regions of the logic devices from regions above the protective spacer layer over the regions of the dynamic random access memory devices.

1. A method for forming a high bandwidth memory, comprising:

11. The method described in claim 10, wherein the step of forming the protective spacer layer forms the protective spacer layer by a conformal deposition method selected from atomic layer deposition (ALD) and plasma-enhanced atomic layer deposition (PEALD).

12. The step of forming the interlayer dielectric comprises: forming the interlayer dielectric over the dielectric fill material in the regions of the plurality of logic devices, the regions of the plurality of non-volatile memory devices, and the regions of the plurality of dynamic random access memory devices; removing the interlayer dielectric over the dielectric fill material between the regions of the plurality of logic devices and the regions of the plurality of non-volatile memory devices and the interlayer dielectric over the dielectric fill material in the regions of the plurality of dynamic random access memory devices; The method of claim 10, comprising:

13. 11. The method of claim 10, further comprising forming a lower mold layer, a support mesh, and an upper mold layer over the protective spacer layer over the area of ​​the plurality of dynamic random access memory devices.

14. 14. The method of claim 13, further comprising forming a plurality of trenches in the lower mold layer, the support mesh, and the upper mold layer, and forming a bottom capacitor electrode layer in the plurality of trenches, the bottom capacitor electrode layer in contact with the support mesh.

15. 15. The method of claim 14, further comprising forming a capacitor dielectric layer over the bottom capacitor electrode layer and a top capacitor electrode layer over the capacitor dielectric layer in a region over the region of the plurality of dynamic random access memory devices.

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