Efficient dual-pass floating-point arithmetic operators

Abstract

To provide systems and methods related to performing arithmetic operations on floating-point numbers.SOLUTION: Floating-point arithmetic circuitry is configured to receive two floating-point numbers. The floating-point arithmetic circuitry includes a first path configured to perform a first operation on the two floating-point numbers based at least in part on a difference in size between the two floating-point numbers. The floating-point arithmetic circuitry includes a second path configured to perform a second operation on the two floating-point numbers based at least in part on the difference is size between the two floating-point numbers. The first path and the second path diverge from each other after receipt of the floating-point numbers in the floating-point arithmetic circuitry and converge on a shared adder that is used for the first operation and the second operation.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This disclosure relates to integrated circuits designed to perform floating-point arithmetic. More specifically, this disclosure relates to the fabrication of an efficient dual-path floating-point operator and / or an efficient count-leading zeros circuit in a floating-point operator.

Background Art

[0002] Integrated circuit devices can perform floating-point arithmetic on floating-point numbers using enhanced circuit-based floating-point operators. As the number of floating-point operators increases within an integrated circuit device, the requirements for efficiency in implementing the floating-point operators may increase. For example, previous integrated circuit devices may have included dozens to hundreds of floating-point operators, while future integrated circuit device designs may include thousands or tens of thousands of floating-point operators. Therefore, the level of efficiency that was appropriate for previous integrated circuit devices may not be as appropriate for future devices due to the increasing number of floating-point operators.

[0003] This paragraph is intended to introduce the reader to various aspects of the prior art that may be relevant to various aspects of this disclosure, which aspects are described below and / or recited in the claims. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of various aspects of this disclosure. Accordingly, these statements are to be read from this perspective and not as an admission of prior art.

Brief Description of the Drawings

[0004] Various aspects of this disclosure may be better understood by reading the following detailed description and referring to the following drawings. [Figure 1] FIG. [FIGURE NUMBER] is a block diagram of a system for performing floating-point addition according to an embodiment of this disclosure. [Figure 2]This is a block diagram of an integrated circuit capable of implementing a floating-point adder, according to one embodiment of the present disclosure. [Figure 3] This is a block diagram of a single-pass floating-point adder that can be implemented in an integrated circuit, according to one embodiment of the present disclosure. [Figure 4] This is a block diagram of a dual-path floating-point adder using a dedicated subtractor for one path, which may be implemented in an integrated circuit, according to one embodiment of the present disclosure. [Figure 5] This is a block diagram of an addition and rounding circuit that can be implemented in the floating-point adder shown in Figure 3 or Figure 4, according to one embodiment of the present disclosure. [Figure 6] This is a block diagram of an addition and rounding circuit comprising a single bit shifter, which may be implemented in the floating-point adder shown in Figure 3 or Figure 4, according to one embodiment of the present disclosure. [Figure 7] This is a block diagram of a composite adder that adds and rounds input values ​​according to one embodiment of the present disclosure. [Figure 8] This is a block diagram of an adder and rounding circuit that efficiently performs addition and rounding operations according to one embodiment of the present disclosure. [Figure 9] This is a block diagram of a dual-pass adder according to one embodiment of the present disclosure, which converges the dual paths and uses the same adder / subtractor in both paths without including a dedicated adder or subtractor in either path. [Figure 10] This is a block diagram of the dual-pass adder shown in Figure 9 according to one embodiment of the present disclosure, and includes a composite circuit that replaces the leading zero count circuit and normalization shifter of the dual-pass adder shown in Figure 9. [Figure 11] This is a logarithmic structure of the coupling circuit shown in Figure 10, according to one embodiment of the present disclosure. [Figure 12] This is a diagram of a data processing system capable of implementing one or more floating-point operators according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0005] One or more specific embodiments are described below. Not all features of the actual embodiments are described herein in order to provide a concise description of these embodiments. As with any engineering or design project, it is understood that the development of such actual embodiments requires numerous implementation-specific decisions to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, and these goals may differ from embodiment to embodiment. Furthermore, while such development efforts can be complex and time-consuming, it is understood that they are nevertheless routine design, fabrication, and manufacturing tasks for an average engineer interested in this disclosure.

[0006] When introducing elements of various embodiments of this disclosure, the articles “a, an” and “the” are intended to mean that there is one or more elements. The terms “including” and “having” are intended to be inclusive and mean that there may be additional elements other than those listed. Furthermore, it should be understood that references to “several embodiments,” “embodiment,” “one embodiment,” or “one embodiment” in this disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the enumerated features. Furthermore, the phrase A “based on” B is intended to mean that A is at least partially based on B. Furthermore, the term “or” is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical XOR). In other words, the phrase A “or” B is intended to mean A, B, or both A and B.

[0007] As will be discussed in more detail below, embodiments of this disclosure generally relate to logic circuits having floating-point operators. As the number of floating-point operators increases within an integrated circuit (IC) device, the resources consumed by the floating-point operators may increase the demands on efficiency when implementing them. For example, earlier IC devices may contain tens to hundreds of floating-point operators, but future IC device designs may contain thousands or tens of thousands of floating-point operators. One mechanism to improve such efficiency may involve the use of design tools used to synthesize the circuit, which may include multiple (e.g., 10,000) floating-point arithmetic logic units (ALUs) including far paths where the exponents of the numbers being operated on are quite far apart, and near paths where the exponents of the numbers are close to each other. The ALUs may use rounding methods applied to far-path adders that separate adders / subtractors from rounding operations. Far-path adders / subtractors can also be used as near-path subtractors, allowing for circuit reuse between both paths. Furthermore, the near-path may include composite circuits that combine leading zero counting functions with shifts (e.g., left shifts) to create simpler, faster, and smaller circuits.

[0008] With the above in mind, Figure 1 shows a block diagram of a system 10 that can implement an efficient mantissa rounding technique. The designer may want to implement functions including floating-point arithmetic on an integrated circuit device 12 (an IC such as a field-programmable gate array (FPGA)). The designer can specify a high-level program to be implemented, such as an OpenCL program, which allows the designer to more efficiently and easily provide programming instructions for constructing a set of programmable logic cells for the integrated circuit device 12 without requiring specific knowledge of a low-level hardware description language (e.g., Verilog or VHDL). For example, because OpenCL is very similar to other high-level programming languages ​​such as C++, a programmer familiar with such programming languages ​​may have a shorter learning curve than a designer who needs to learn an unfamiliar low-level hardware description language to implement new functions in the IC.

[0009] The designer can implement a high-level design using design software 14, such as a version of Intel® Quartus® from Intel Corporation. The design software 14 can use a compiler 16 to convert the high-level program into a low-level description. The design software 14 can also be used to optimize and / or improve the efficiency of the design. The compiler 16 can provide machine-readable instructions representing the high-level program to the host 18 and the integrated circuit device 12. The host 18 can receive a host program 22, which can be implemented by a kernel program 20. To implement the host program 22, the host 18 can communicate instructions from the host program 22 to the integrated circuit device 12 via a communication link 24, which may be, for example, direct memory access (DMA) communication or peripheral component interconnect express (PCIe) communication. In some embodiments, the kernel program 20 and the host 18 may enable the configuration of floating-point arithmetic circuits 26 on the integrated circuit device 12. The floating-point arithmetic circuit 26 may include circuits and / or other logic elements and may be configured to implement floating-point arithmetic logic in an enhanced circuit configured to perform floating-point multiplication, floating-point addition, rounding, etc.

[0010] Now, we move on to a more detailed discussion of the integrated circuit device 12. Figure 2 shows the integrated circuit device 12, which may be a programmable logic device such as a field-programmable gate array (FPGA). Furthermore, it should be understood that the integrated circuit device 12 may be any other suitable type of programmable logic device (e.g., application-specific integrated circuits and / or application-specific standard products). As shown, the integrated circuit device 12 may have input / output circuits 42 for driving signals from the device and receiving signals from other devices via input / output pins 44. Signals can be routed to the integrated circuit device 12 using interconnection resources 46 such as global and local vertical and horizontal conductive wires and buses. Furthermore, the interconnection resources 46 may include fixed interconnections (conductive wires) and programmable interconnections (i.e., programmable connections between each fixed interconnection). The programmable logic 48 may include combinational logic circuits and sequential logic circuits. For example, the programmable logic 48 may include lookup tables, registers, and multiplexers. In various embodiments, the programmable logic 48 may be configured to execute custom logic functions. A programmable interconnect associated with an interconnect resource can be considered part of the programmable logic 48. The programmable logic may include multiple different types of programmable logic 48 of different layers of programmability. For example, the programmable logic 48 may include various mathematical logic units such as arithmetic logic units (ALUs), each unit configured to perform various mathematical functions (e.g., floating-point arithmetic calculations).

[0011] As discussed previously, programmable logic may include a relatively large number of ALUs (e.g., hundreds, thousands, tens of thousands, etc.), such as floating-point ALUs (FP ALUs). FP ALUs can be implemented using various techniques with varying levels of efficiency. By using the synthesis method disclosed herein, FP adders can be implemented in physically smaller spaces with lower latency. Specifically, the FP adders disclosed herein can utilize separate near-path and far-path circuits that share several circuits before branching, then converging, and branching again. Additionally or alternatively, the synthesis approach can be used to clear leading zeros and shift them into combined shift-leading-zero circuits.

[0012] With this in mind, Figure 3 is a simplified block diagram of one embodiment of the FP adder 100. The FP adder 100 receives two or more floating-point numbers and combines (e.g., adds or subtracts) the floating-point numbers to obtain a result. Each floating-point number includes a sign, an exponent, and a mantissa. For example, in an FP32 number, the FP32 number includes a single sign bit, an 8-bit exponent, and a 23-bit mantissa. In the FP adder 100, these distinct components of the floating-point numbers are received by the FP adder 100. For example, the FP adder 100 receives mantissas 102 and 104 in multiplexers 106 and 108.

[0013] Multiplexers 106 and 108 are controlled based on the result of a comparison between exponents 110 and 112 in comparator 114. Since the two floating-point numbers are received as normalized floating-point numbers with a leading one, one of the numbers (e.g., the smaller number) can be denormalized to align the two floating-point numbers to the same exponent. In this way, comparator 114 selects the number with the higher exponent and sends the corresponding control signal 116 to multiplexer 118. Comparator 114 also sends control signals 120 and 122 to multiplexers 106 and 108. These control signals 120 and 122 enable multiplexers 106 and 108 to ensure that the FP adder 100 receives the mantissa 124 corresponding to the smaller number (e.g., the smaller exponent) from multiplexer 108 and the mantissa 126 corresponding to the larger number from multiplexer 106. Therefore, a larger exponent can be selected as the base exponent. Since it may be necessary to align a smaller number with a larger exponent, the mantissa 124 may be right-shifted in the shifter 128 by the number of positions corresponding to the difference between the respective exponents. The shifted mantissa 130 is output from the shifter 128. The shifted mantissa 130 and mantissa 126 are sent to an adder / subtractor 132, which can add or subtract values ​​based on the sign of the input floating-point number and the selected operation (e.g., addition or subtraction) of the FP adder 100. After addition or subtraction, the result 134 may be denormalized. Therefore, a leading zero count circuit (CLZ) 136 can be used to count the number of zeros before the first 1 and output a control 138 indicating how much the result 134 will be shifted to normalize it in an implicit leading 1 format (e.g., IEEE754FP). In such a shift, the FP adder 100 uses the adder / subtractor 142 to add to or subtract from the base exponent 140 (e.g., a larger exponent) to produce the output exponent 144. The number added to or subtracted by the adder / subtractor 142 also indicates how much of a shift the shifter 146 applies to the result 146 to produce the normalized result 148.

[0014] As previously mentioned, Figure 3 shows a simplified block diagram of one embodiment of the FP adder 100. In practice, additional circuits may be included in the FP adder 100, but may be omitted from Figure 3 for simplification. For example, the FP adder 100 may utilize exception handling for its inputs and / or outputs. The FP adder 100 may also utilize internal functions such as rounding of the sum or difference of the adder / subtractor 132. Rounding operations can be complex and may significantly affect the actual embodiment of the FP adder 100.

[0015] The FP adder 100 can be implemented using a dual-path embodiment that can run faster and more efficiently than the FP adder 100. Specifically, the critical path of the FP adder 100 may include a shifter 128, an adder / subtractor 132, a CLZ 136, and a shifter 146. The shifter 128 may be approximately the same size and speed as the combination of the adder / subtractor 132, the CLZ 136, and the shifter 146.

[0016] In floating-point addition / subtraction, there are two common cases: near case and far case. In the near case, the two input numbers are nearly identical in that their exponents 110 and 112 are equal or differ by a number less than or equal to a threshold (e.g., 1). Therefore, the shifter 128 can shift in one direction (e.g., to the right) by the maximum threshold number of bits (e.g., 1). Subtracting these near numbers can result in a very small value, which means that a large shift may be used. For example, subtracting 1.4999 from 1.5 results in a value of 0.0001, which is shifted to the right multiple times for normalization.

[0017] In the far case, the exponents 110 and 112 are significantly different from the threshold number. For example, the exponents 110 and 112 may differ by more than 2. Here, although the right shift of the shifter 128 is likely large, the result of the subtraction approaches the range normalized using fewer shifts in normalization. For example, the normalization shift (e.g., left shift) can be limited to 1 bit or less.

[0018] In both the far case and the near case, addition results in a right shift of at most 1 bit for normalization. Using these characteristics, an FP adder can be split into a near path for near case subtraction and a far path for far case addition and subtraction. Since both near case addition and far case addition utilize a small post - addition shifter, the far path can also be used to process near case addition.

[0019] FIG. 4 shows a simplified block diagram of an embodiment of an FP adder 160 including a far path 164 and a near path 166. Both the far path 164 and the near path 166 receive the mantissas 124, 126 and generate respective outputs that are transmitted to an output multiplexer 167 configured to select between the near path output and the far path output as the output of the FP adder 160. As shown, the mantissas 124, 126 are generated as described above in relation to the FP adder 100 of FIG. 3. Similarly, both the shifter 128 and the adder / subtractor 132 function as described above in relation to the FP adder 100 of FIG. 3, except that the shifter 128 and the adder / subtractor 132 are in the far path 164 of the FP adder 160. However, the result from the adder / subtractor 132 is transmitted to a single - bit shifter 168 that shifts right or left to generate a far path output 170 that is transmitted to the output multiplexer 167. The size (e.g., 0 or 1) and direction of the shift in the single - bit shifter 168 are transmitted to an adder / subtractor 172 to generate a far exponent 174 from a base exponent 140. When the far path output 170 is selected by the output multiplexer 167, the far exponent is used with the far path output 17 to form a floating - point output.

[0020] The near path 166 receives the mantissa 124 at the shifter 176, and the shifter 176 shifts the mantissa 124 by no more than a threshold number (e.g., 1 bit) to align the mantissa 124 to a larger number as the shifted mantissa 177. The shifted mantissa 177 is subtracted from the mantissa 126 in the subtracter 178 to generate an output 180. The output 180 is sent to the CLZ 136 and the shifter 146 to generate a normalized result 148 and an output exponent 144. The CLZ 136 and the shifter 146 function as described in relation to the FP adder 100 of FIG. 3. The output multiplexer 167 selects the normalized result 148 and the output exponent 144 for near-case subtraction.

[0021] Both the near path 166 and the far path 164 utilize additional shifters (e.g., single-bit shifter 168 and shifter 176) within the FP adder 160 as compared to the FP adder 100. However, these shifters may have smaller area and latency compared to full-precision shifters (such as shifters 128 and 146). Thus, the critical path is reduced to large shifters (e.g., shifters 128 and 146), adders, and small shifters. In the near path 166, the adder is only used as the subtracter 178 that does not utilize rounding. Thus, the subtracter 178 is smaller than the adder / subtracter 132 of the far path 164. The size of the individual components of the FP adder 160 can be larger than that of the FP adder 100, but in the real world where timing closure is achieved, the FP adder 160 can be made smaller because it is easy to combine two separate paths to increase the speed.

[0022] As mentioned above, the subtractor 178 may not utilize rounding due to the nature of subtraction. However, the adder / subtractor 132 in the far path 164 can utilize rounding to accommodate rounding after addition. Figure 5 is a simplified block diagram of the addition and rounding circuit 200. The addition and rounding circuit 200 includes an adder / subtractor 132 that takes a mantissa 126 and a shifted mantissa 130 and produces a result 134. The addition and rounding circuit 200 also includes a processing circuit 202 that takes one or more inputs 203 and calculates / produces a rounding value 204 that controls how the result 134 is rounded. Inputs 203 can be received from a shifter 128, a single-bit shifter 168, and / or other locations in the integrated circuit device 12 that select whether to round and where to apply the rounding. The rounded value 204 is added to the result 134 in the adder 206 to produce the rounded result 208, which is sent to the single bit shifter 168 as result 134.

[0023] In practical embodiments, chaining multiple carry-propagating adders (e.g., adder / subtractor 132 and adder 206) together can be costly in terms of area and latency. As shown in Figure 6, in the addition and rounding circuit 210, this cost can be further complicated by the rounding point, which is implemented as a left or right shift in the shifter 212 between adder / subtractor 132 and adder 206. This addition and rounding circuit 210 can be combined into a single composite adder that combines adder / subtractor 132, rounding point selection in the shifter 212, rounding value calculation in the processing circuit 202, and adder 206 into a single level of logic.

[0024] Figure 7 is a simplified block diagram of an embodiment of the composite adder 218. In the composite adder 218, the input operands (e.g., bits of mantissa 126 and 130) are sent to the respective XOR gates 220 to compute the intermediate signal 222. The input operands are also sent to the respective AND gates 224 to compute the respective generated signal 226. The input operands are also sent to the respective OR gates 228 to compute the propagated signal 230. The generated signal 226 and the propagated signal 230 are sent to a parallel prefix circuit 232, which uses the generated signal 226 and the propagated signal 230 to compute the respective carry signal 236. The calculation of the carry signal may be performed using a rounding circuit node 234. In some embodiments, the prefix tree of the parallel prefix circuit 232 may include a topology such as a Brent-Kung network or a Kogge-Stone network. In some embodiments, an additional layer may be added to the prefix network to implement a structure known as a flagged prefix adder. In other words, the rounding circuit node 234 adds several layers to the multiple layers of the parallel prefix circuit 232 to generate the calculated carry signal 237. The calculated carry signal 237 and each intermediate signal 222 are sent to the respective XOR gates 238 to generate the output signal 240.

[0025] The aforementioned circuit combinations can be resolved with complex networks. As will be discussed below, the overlapping portions of the near path 166 and the far path 164 can be combined to simplify such networks, increase efficiency, and / or reduce latency.

[0026] Figure 8 shows an alternative embodiment for embedding rounding functionality into the addition and rounding circuit 250. The addition and rounding circuit 250 includes an adder / subtractor 132, a processing circuit 202, a parallel prefix circuit 232, and an XOR gate 238. However, instead of shifting the output of the parallel prefix circuit 232, a multiplexer 252 can be used to multiplex the rounding bit (e.g., rounded value 204) with the result 134 which is above one or more least significant bits of the parallel prefix circuit 232, and which has a propagating bit that is forced high using one or more OR gates 254 which OR the result 134 with the rounded value 204. The propagating bit forced high corresponds to the rounded bit from the result 134.

[0027] The addition and rounding circuit 250 is relatively inexpensive because the rounding is performed only on a specific number (e.g., 3) of the least significant bits of the parallel prefix circuit 232. When bits propagate from the parallel prefix circuit 232, a rounding overflow 256 occurs, and the fundamental exponent is adjusted by 1. Thus, the shifter 212 can be placed after the XOR gate 238 if necessary, without compromising performance or increasing area. Further details regarding multiplexer and OR gate-based rounding using the parallel prefix circuit 232 can be found in U.S. Patent Application No. 17 / 133,861, filed December 24, 2020, entitled “Rounding Circuitry for Floating-Point Mantissas,” which is incorporated in its entirety for all purposes.

[0028] As previously mentioned, the rounding shift in the shifter 212 may be performed in the far path 164 at the end of the addition and rounding circuit 250 and / or after the addition. This enables the construction of the FP adder 270 shown in Figure 9, where the far path 272 and the near path 274 have separate parts but share an adder / subtractor 132 for the cost of a single 2:1 multiplexer 276. The rounding circuit 277 may be implemented in the part where the far path 272 is separate from the near path 274 and separate from the adder / subtractor 132, so that simple adder functionality can be accessed directly without using the entire composite adder 218, and the adder / subtractor 132 may be shared between the far path 272 and the near path 274. This separation of the adder / subtractor 132 from the rounding circuit 277 can be implemented without increasing the area or latency compared to the composite adder 218. The only increase involves a single 2:1 multiplexer 276. However, the increase using a single 2:1 multiplexer 276 still saves area by omitting a separate subtractor 178 used in the near pass 166.

[0029] The FP adder 270 derives mantissas 126 and 124 using the same technique used in connection with FP adders 100 and 160. When two near-case floating-point numbers are received, in the near-pass 272, mantissa 124 corresponding to the smaller number may be shifted in the shifter 278. The shifter 278 shifts mantissa 124 by a threshold number (e.g., 1 bit) or less, normalizing mantissa 124 to the larger number as the shifted mantissa 280. For example, if the near-cases include mantissas 124 and 126 corresponding to the same exponent, the shifted mantissa 280 is unshifted from mantissa 124. The shifted mantissa 280 is sent to a single 2:1 multiplexer 276 for the far-pass 274, along with the shifted mantissa 130. A single 2:1 multiplexer 276 selects a mantissa 282 as the chosen mantissa between the shifted mantissa 130 and the shifted mantissa 280. The chosen mantissa 282 is added to or subtracted from mantissa 126 in the adder / subtractor 132, regardless of whether the incoming data is near case or far case.

[0030] In the near case, result 284 from adder / subtractor 132 is sent to CLZ136, and the near pass 274 involves processing result 284 to produce a normalized result 148, similar to how FP adder 100 produces a normalized result 148 from result 134. As can be understood, CLZ136 and shifter 146 may be pedantic implementations. In actual implementations, much more complex designs may be used to split this calculation and optimize latency. For example, CLZ136 may consist of two parts: a leading zero predictor (which fairly accurately guesses the shift based on two inputs to adder / subtractor 132) and a fine-tuning to which CLZ136 is subsequently fine-tuned. This allows the fine-tuning to be performed much smaller (and faster) than the other parts of CLZ136, while the complex calculation part of CLZ136 is performed in parallel with the adder.

[0031] In the case where rounding is used, result 284 is sent to the rounding circuit 277 for rounding and / or normalization, generating the far-pass output 170. When rounding is not used, the far-pass output 170 is the same as result 284 with or without normalization by the rounding circuit 277.

[0032] As shown in the figure, the normalized shift of the near path 274 using the shifter 146 is more complex than the denormalized shift of the far path 272 using the shifter 128. This is because the CLZ 136 is used to determine the amount of normalized shift. Any suitable CLZ 136 implementation can be used in the FP adder 270. However, in some embodiments, the CLZ 136 and the shifter 146 can be combined into a single logic unit. For example, Figure 10 shows an FP adder 300 identical to the FP adder 260, except that the CLZ 136 and the shifter 146 can be replaced using a coupling circuit 302 to produce a normalized result 148. Instead of using separate CLZ 136 and the shifter 146 separately, the normalized result 148 can be determined by examining the results of both circuits together. For example, the operation of the CLZ 136 and the shifter 146 can be described as an IF-THEN-ELSE chain. If CLZ136 determines that the first bit is 1, no shift occurs, and no shift check is performed at subsequent bit positions. If CLZ136 determines that the second bit has a 1 following the 0 of the first bit, a single left shift occurs, and no shift check is performed at subsequent bit positions. Similarly, an IF-THEN-ELSE chain can continue through (multiple) bits until a leading 1 is found. When using such a statement for an FP32 number with a 23-bit mantissa, the condition can be written as follows: near(23)=!near(23)ANDnear(22)=!near(23)AND!near(22)ANDnear(21)=!near(23)AND!near(22)AND!near(21)AND!near(20)AND!near(19)AND!near(18)ANDnear(17) (Formula 1), Here, near(i) represents the amount to shift and the amount to perform the shift, AND is a Boolean AND, and !near(i) represents the complement of near(i). Using Equation 1, each condition can be extracted recursively. For example, recursive conditions include the following: f_a=!near(23)AND!near(22)AND!near(21)AND!near(20)AND!near(19) (Formula 2) near(17) = f_a AND near(18) (Equation 3) near(16)=f_aAND!near(18)ANDnear(17) (Formula 4) near(15)=f_aAND!near(18)AND!near(17)ANDnear(16) (Equation 5).

[0033] These functions allow each level of the shift to be processed with the same magnitude, and the complexity of all bits in the output may differ. Such equations can be implemented using OR and / or AND gates. However, these structures can be transformed into faster logarithmic structures through logic reconstruction using electronic design support tools to form circuits within coupled circuit 302. The results of logic reconstruction may include:

number

[0034] Figure 11 shows one embodiment of a structure 310 that merges CLZs, and the normalization shift can be implemented in a coupling circuit 302 of bits 21 of the FP32 adder after logic reconstruction. As shown, structure 310 receives input bits 312 and combines input bits 312 of levels 314, 316, 318, 320, 322, and 324 as shown to produce an output 326 containing the CLZ and normalization shift. The description of the structure can be manually recursively invoked, and different results may be obtained during synthesis, especially when it is part of a large system. Furthermore, although the foregoing refers to an FP32 with a 23-bit mantissa, similar techniques can be applied to other floating-point formats with mantissas of different sizes. Thus, by using this coupling circuit 302, the size of the CLZ 136 and shifter 146 can be reduced, making it more efficient than implementations with separate CLZ 136 and shifter 136.

[0035] Furthermore, while the illustrated embodiment of the FP adder 300 includes a dual-path technique with a shared adder / subtractor 132 and a coupling circuit 302, some embodiments of the floating-point operator may employ the dual-path technique used herein, while other embodiments may employ the coupling circuit 302 without the dual-path technique.

[0036] The integrated circuit device 12 may be a data processing system, such as the data processing system 350 shown in Figure 12, or a component thereof. The data processing system 350 may include a host processor 352, memory and / or storage circuitry 354, and a network interface 356. The data processing system 350 may include more or fewer components (e.g., an electronic display, a user interface structure, or an ASIC). The host processor 352 may include any suitable processor, such as an INTEL® Xeon® processor or a reduced instruction processor (e.g., a reduced instruction set computer (RISC), or an advanced RISC machine (ARM) processor), which can manage the data processing requests of the data processing system 350 (e.g., to perform machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern recognition, spatial navigation, etc.). The memory and / or storage circuitry 354 may include random access memory (RAM), read-only memory (ROM), one or more hard drives, flash memory, etc. The memory and / or storage circuit 354 can hold data processed by the data processing system 350. In some cases, the memory and / or storage circuit 304 can also store a configuration program (bitstream) for programming the integrated circuit device 12. A network interface 356 may enable the data processing system 350 to communicate with other electronic devices. The data processing system 350 may comprise several different packages or be contained within a single package on a single package substrate.

[0037] For example, the data processing system 350 may be part of a data center that handles a variety of different requests. For instance, the data processing system 350 may receive data processing requests via the network interface 356 to perform machine learning, video processing, speech recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, or other specialized tasks. The host processor 352 can have the programmable logic fabric of the integrated circuit device 12 programmed with multipliers suitable for performing the requested task. For example, the host processor 352 may instruct configuration data (bitstream) stored in memory and / or storage circuit 354 to be programmed into the programmable logic fabric of the integrated circuit device 12. The configuration data (bitstream) may represent a circuit design for one or more sets of floating-point multipliers, which can be mapped to programmable logic and packed together according to the techniques described herein.

[0038] The technologies presented herein and described in the claims clearly improve the current art and are therefore applied to material objects and specific examples of a practical nature that are not abstract, intangible, or purely theoretical. Furthermore, where the claims attached to the end of this specification contain one or more elements designated as "means for performing [function]" or "steps for performing [function]," it is intended that such elements should be construed under § 112(f) of the United States Patent Act. However, with respect to claims containing elements designated in any other way, it is intended that such elements should not be construed under § 112(f) of the United States Patent Act.

[0039] The embodiments described herein are susceptible to various modifications and substitutions, although certain embodiments are shown in the drawings as examples and described in detail herein. However, it should be understood that this disclosure is not intended to be limited to any particular form disclosed. This disclosure will encompass all modifications, equivalents, and substitutions that fall within the spirit and scope of this disclosure, as defined by the exemplary embodiments attached below.

[0040] Examples of Disclosure

[0041] The following numbered sections (or sections) provide for specific exemplary embodiments of the present disclosure.

[0042] Exemplary Embodiment 1 It is a system, and this system is It includes a floating-point arithmetic circuit that accepts two floating-point numbers, Floating-point arithmetic circuits are, A first pass that performs a first operation on two floating-point numbers, at least partially based on the size difference between the two floating-point numbers, This includes a second pass that performs a second operation on the two floating-point numbers, at least partially based on the size difference between the two floating-point numbers, The first and second paths branch off from each other and converge to a shared adder used for the first and second operations before the first and second paths branch off again.

[0043] Exemplary Embodiment 2 The system of an exemplary embodiment 1 includes a comparator that determines the exponential difference between the exponents of two floating-point numbers, and if the difference is less than a threshold, the first pass performs a second operation on the two floating-point numbers.

[0044] Exemplary Embodiment 3 The system of an exemplary embodiment 2 includes a first operation, which involves subtraction if the difference is greater than or equal to a threshold.

[0045] Exemplary Embodiment 4 The system of an exemplary embodiment 2 includes addition if the first operation is greater than or equal to a threshold.

[0046] Exemplary Embodiment 5 The system of an exemplary embodiment 2 includes addition if the first operation is less than a threshold.

[0047] Exemplary Embodiment 6 The system of exemplary embodiment 2 includes a second operation, which involves subtraction if the difference is less than a threshold.

[0048] Exemplary Embodiment 7 The threshold is 2, including the system of an exemplary embodiment 2.

[0049] Exemplary Embodiment 8 A system of an exemplary embodiment 1, including a multiplexer that selects between sending a first shifted mantissa to a shared adder via a first path and sending a second shifted mantissa to a shared adder via a second path.

[0050] Exemplary Embodiment 9 The first pass is a system of an exemplary embodiment 8, which includes a multibit shifter that generates a first shifted mantissa.

[0051] Exemplary Embodiment 10 The second pass is a system of exemplary embodiment 8, which includes a single bit shifter that generates a second shifted mantissa.

[0052] Exemplary Embodiment 11 The second pass is, A leading zero counting circuit receives the result from a shared adder and counts the number of leading zeros in the result, A system of exemplary embodiment 1, comprising a normalization shifter that shifts the result to produce an output normalized at least partially based on the number of leading zeros.

[0053] Exemplary Embodiment 12 The system of an exemplary embodiment 1 includes a coupling circuit that performs shift detection and applies the shift by combining multiple input bits from the result of a shared adder using multiple levels that combine multiple input bits according to a logarithmic structure.

[0054] Exemplary Embodiment 13 The first pass of the system of exemplary embodiment 1 includes a rounding and adding circuit that receives the result from a shared adder and rounds the result.

[0055] Exemplary Embodiment 14 The rounding and adding circuits are: A parallel prefix circuit that receives the result, A multiplexer that controls rounding using a rounding bit in a parallel prefix circuit, An OR gate that sets the propagation bit of a parallel prefix circuit to High based on the position of the rounding bit, A system of an exemplary embodiment 13, including an output multiplexer that shifts the output of a parallel prefix circuit to the left or right by one bit.

[0056] Exemplary Embodiment 15 It is a method, and this method is The first step is to receive a floating-point number, The second step is to receive a floating-point number, The steps include: dividing the first mantissa of the first floating-point number into a first pass and a second pass; Steps include shifting the first mantissa in the first shifter of the first pass to generate the first shifted mantissa, A step of generating a second shifted mantissa by shifting the first mantissa in the second shifter of the second pass, wherein the first shifter is greater than the second shifter. A step of selecting a mantissa to be chosen from the first shifted mantissa and the second shifted mantissa, The steps include adding the selected mantissa to the second mantissa of the second floating-point number in the adder / subtractor, or subtracting the selected mantissa from the second mantissa, The steps include sending the results from the adder / subtractor to the third and fourth passes, The process includes the step of selecting the output between the third and fourth passes.

[0057] Exemplary Embodiment 16 The method of exemplary embodiment 15, wherein the first floating-point number has a smaller exponent than the second floating-point number.

[0058] Exemplary Embodiment 17 A method of an exemplary embodiment 15, which includes the steps of determining how much to shift for normalization (shift amount for normalization) and normalizing the result in a third pass.

[0059] Exemplary Embodiment 18 The method of an exemplary embodiment 15 includes the step of rounding the result in a fourth pass rounding circuit, the rounding circuit including a single bit shift configured to normalize the result after rounding the result.

[0060] Exemplary Embodiment 19 It is a system, and this system is A first input unit configured to receive a first mantissa of a first floating-point number, A second input unit configured to receive a second mantissa of a second floating-point number, A first path having a first shifter configured to shift a first mantissa as a first shifted mantissa, A second path having a second shifter configured to shift a first mantissa as a second shifted mantissa, wherein the second shifter is smaller than the first shifter and the second shifter includes a single-bit shifter, A multiplexer configured to select between a first shifted mantissa and a second shifted mantissa, and to output the selected mantissa, An adder / subtractor configured to receive a mantissa selected from another adder / subtractor, A third path is configured to determine how much to shift the result from the adder / subtractor (the amount of result shift) based on the resulting bit value, and to perform the shift. A fourth path configured to round the results from the adder / subtractor, Includes an output multiplexer configured to select the system output from the results of a third pass and the results of a fourth pass.

[0061] Exemplary Embodiment 20 The third path of the system in exemplary embodiment 19 includes a coupling circuit configured to perform shifts and decisions using a logic tree structure configured to combine multiple inputs of the result at multiple levels to produce multiple output bits.

Claims

1. A system, and said system is It includes a floating-point arithmetic circuit that accepts two floating-point numbers, The floating-point arithmetic circuit is, A first path that performs a first operation on the two floating-point numbers, at least partially based on the size difference between the two floating-point numbers, A second path that performs a second operation on the two floating-point numbers, at least partially based on the size difference between the two floating-point numbers, wherein the first path and the second path branch off from each other and converge to a shared adder used for the first and second operations before the first and second paths branch off again, A multiplexer that selects between sending a first shifted mantissa from the first path to the shared adder and sending a second shifted mantissa from the second path to the shared adder, system.

2. The system according to claim 1, comprising a comparator that determines the exponential difference between the exponents of the two floating-point numbers, wherein if the exponential difference is less than a threshold, the first pass performs the second operation on the two floating-point numbers.

3. The system according to claim 2, wherein the first calculation includes subtraction if the exponential difference is greater than or equal to the threshold.

4. The system according to claim 2, wherein the first calculation includes addition if the exponential difference is greater than or equal to the threshold.

5. The system according to any one of claims 2 to 4, wherein the first calculation includes addition if the exponential difference is less than the threshold.

6. The system according to any one of claims 2 to 4, wherein the second calculation includes subtraction if the exponential difference is less than the threshold.

7. The system according to any one of claims 2 to 4, wherein the threshold includes 2.

8. The system according to claim 1, wherein the first pass includes a multi-bit shifter that generates the first shifted mantissa.

9. The system according to claim 1, wherein the second pass includes a single bit shifter that generates the second shifted mantissa.

10. The second path described above is, A leading zero counting circuit that receives the result from the shared adder and counts the number of leading zeros in the result, The system according to any one of claims 1 to 7, comprising: a normalization shifter that shifts the aforementioned result to produce an output normalized at least partially based on the number of leading zeros.

11. The system according to any one of claims 1 to 7, wherein the second pass includes a coupling circuit that performs shift detection and applies the shift by combining the multiple input bits from the result of the shared adder using multiple levels that combine the multiple input bits according to a logarithmic structure.

12. The system according to any one of claims 1 to 7, wherein the first pass includes a rounding and adding circuit that receives a result from the shared adder, rounds the result, and adds it.

13. The aforementioned rounding and adding circuits are: A parallel prefix circuit that receives the above result, A multiplexer that controls the rounding process with rounding bits in the parallel prefix circuit, Based on the position of the rounding bit, an OR gate is used to set the propagation bit of the parallel prefix circuit to High, The system according to claim 12, further comprising an output multiplexer that shifts the output of the parallel prefix circuit to the left or right by one bit.

14. A method, and said method is The first step is to receive a floating-point number, The second step is to receive a floating-point number, The steps include dividing the first mantissa of the first floating-point number into a first pass and a second pass, The steps include shifting the first mantissa in the first shifter of the first pass to generate the first shifted mantissa, A step of shifting the first mantissa in the second shifter of the second path to generate a second shifted mantissa, wherein the first shifter is greater than the second shifter. A step of selecting a mantissa from the first shifted mantissa and the second shifted mantissa, A step of adding the selected mantissa to the second mantissa of the second floating-point number of the adder / subtractor, or subtracting the selected mantissa from the second mantissa, The steps include transmitting the results from the adder / subtractor to the third and fourth paths, The process includes the step of selecting the output between the third path and the fourth path, method.

15. The method according to claim 14, wherein the first floating-point number has a smaller exponent than the second floating-point number.

16. The method according to claim 14 or 15, further comprising the steps of determining how much to shift for normalization and normalizing the result in the third pass.

17. The method according to any one of claims 14 to 16, comprising the step of rounding the result in a fourth pass rounding circuit, wherein the rounding circuit includes a single bit shift configured to normalize the result after rounding the result.

18. A system, and said system is A first input unit configured to receive a first mantissa of a first floating-point number, A second input unit configured to receive a second mantissa of a second floating-point number, A first path having a first shifter configured to shift the first mantissa as a first shifted mantissa, A second path having a second shifter configured to shift the first mantissa as a second shifted mantissa, wherein the second shifter is smaller than the first shifter and the second shifter includes a single-bit shifter, A multiplexer configured to select between the first shifted mantissa and the second shifted mantissa and output the selected mantissa, An adder / subtractor configured to receive the selected mantissa from the adder / subtractor, A third path is configured to determine how much to shift the result from the adder / subtractor based on the resulting bit value, and to perform the shift. A fourth path configured to round the results from the adder / subtractor, The system includes an output multiplexer configured to select the output of the system from the results of the third pass and the results of the fourth pass, system.

19. The system according to claim 18, wherein the third path includes a coupling circuit configured to perform the shift and decision using a logic tree structure configured to combine the multiple inputs of the result at multiple levels to produce multiple output bits.

20. A system, and said system is A means for receiving a first floating-point number, A means for receiving a second floating-point number, Means for dividing the first mantissa of the first floating-point number into a first pass and a second pass, Means for shifting the first mantissa in the first shifter of the first pass to generate the first shifted mantissa, Means for shifting the first mantissa in the second shifter of the second path to generate a second shifted mantissa, wherein the first shifter is larger than the second shifter, Means for selecting a mantissa to be selected from the first shifted mantissa and the second shifted mantissa, Means for adding the selected mantissa to the second mantissa of the second floating-point number of an adder / subtractor, or for subtracting the selected mantissa from the second mantissa, Means for transmitting the results from the adder / subtractor to the third and fourth paths, The system includes means for selecting an output between the third and fourth paths, system.

21. The system according to claim 20, wherein the first floating-point number has a smaller exponent than the second floating-point number.

22. The system according to claim 20 or 21, comprising means for determining how much to shift for normalization and for normalizing the result in a third pass.

23. The system according to any one of claims 20 to 22, comprising means for rounding the result in a fourth pass rounding circuit, wherein the rounding circuit includes a single bit shift configured to normalize the result after rounding it.

24. An integrated circuit device, wherein the integrated circuit device is A first circuit path that performs a first operation on the two floating-point numbers, at least partially based on the size difference between the two floating-point numbers, A second circuit path that performs a second operation on the two floating-point numbers, at least partially based on the size difference between the two floating-point numbers, A shared adder shared between the first circuit path and the second circuit path, wherein the first and second circuit paths branch off from each other and converge to the shared adder, and the shared adder is used for the first and second operations before the first and second paths branch off again. A comparator that determines the exponential difference between the exponents of the two floating-point numbers, A multiplexer that selects between sending a first shifted mantissa from the first path to the shared adder and sending a second shifted mantissa from the second path to the shared adder, The first pass performs the second operation on the two floating-point numbers if the difference is less than the threshold. The first calculation includes subtraction if the difference is greater than or equal to a threshold. Integrated circuit device.

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