Method and system for patch-by-patch characterization of quantum processors

Abstract

To provide a method for characteristic evaluation of a quantum processor including a plurality of quantum bits.SOLUTION: A method for characteristic evaluation of a quantum processor including a plurality of quantum bits includes applying a characteristic evaluation protocol to a quantum bit patch containing a quantum bit subset. The characteristic evaluation protocol includes a reduction of "patching error," which is a systematic characteristic evaluation error caused by an interaction between a quantum bit inside the patch and a quantum bit outside the patch.SELECTED DRAWING: None

Description

[Technical Field]

[0001] This disclosure relates to the field of quantum computing, and more specifically, to the field of quantum processor characterization. [Background technology]

[0002] The development of useful quantum computers critically depends on reducing execution errors (the difference between the actual execution and the ideal execution of quantum logic operations). The long-term strategy for addressing such errors is quantum error correction, but quantum error correction requires, firstly, very low error rates compared to existing hardware, as well as the excessive overhead of the number of qubits. Complementary strategies suitable for addressing errors in small circuits on existing hardware are collectively called quantum error suppression and relaxation. Both hardware improvements to satisfy the conditions for error correction and most error suppression and relaxation protocols require detailed and highly sensitive characterization of execution errors. Characterizing execution errors for a single qubit or a pair of qubits is common practice, but it is widely understood to be computationally unmanageable for more than a few qubits unless various simplifications and, often, unrealistic assumptions are made. This condition hinders detailed and high-resolution characterization of state-of-the-art quantum processors, which currently have tens to hundreds of qubits.

[0003] As an example, given a Markov model for the execution error to be characterized, the most detailed characterization protocol known to date is called gate set tomography (GST), as described, for example, in Nielsen et al., "Gate Set Tomography," Quantum 5, 557 (2021), which is incorporated herein by reference. Herein, a "gate set" corresponds to a set of quantum logic operations, generally including quantum states, gates, and measurements that are characterized simultaneously with respect to each other. High resolution is achieved in GST by using long periodic sequences of gates such that the estimation error scales as the reciprocal of the sequence length. The flexibility in selecting the execution error to be characterized, and the fact that gates, state execution errors, and measurements are all characterized, means that GST can be considered a generalization and integration of various existing protocols, such as state, measurement, process, and Hamiltonian tomography. However, the detailed output of GST inevitably stretches its resources in terms of both quantum and classical execution time, as well as classical memory. As a result, open-source implementations of GST, which are arguably the industry standard for detailed characterization, currently only support single-qubit or 2-qubit GSTs as standard use cases; see Nielsen et al., "Probing quantum processor performance with pyGSTi," Quantum Science and Technology 5, 044002 (2020).

[0004] A common technique to circumvent the computational barriers of many qubit characterizations is to characterize a small patch (i.e., a small subset) of qubits within a large device and simply ignore all qubits outside the patch. As an example, all experimental uses of GSTs published to date have used either single-qubit or two-qubit patches. The above methods are based on single-qubit "robust phase estimation" and its variations, Kimmel et al., "Robust calibration of a universal single-qubit gate set via robust phase estimation," Phys. Rev. A 92, 06235 (2015), Landa et al., "Experimental Bayesian estimation of quantum state preparation, measurement, and gate errors in multi-qubit devices," Phys. Rev. Research 4, 013199 (2022), and two-qubit "Floquet calibration," Arute et al., "Observation of separated dynamics of charge and spin in the Fermi-Hubbard model," arXiv:2010.07965 (2020), and "Hamiltonian error amplifying tomography," Sundaresan et al., "Reducing Unitary and Spectator Errors in Cross Resonance with Optimized Rotary Echoes," PRX Quantum. It is also used in GST-like fast characterization protocols, including 1,020318(2020). Similarly, most randomized characterization protocols are typically applied to single or two-qubit patches. However, gates intended to act within a particular patch also unintentionally act on additional, typically neighboring, qubits. This significant phenomenon is known as crosstalk, and such crosstalk errors between a patch and its neighborhood cannot be captured by single-patch characterization protocols. [Overview of the Initiative]

[0005] The applicant has found that crosstalk between a characterized patch and its neighbors leads to systematic estimation errors of execution errors occurring within the patch, because qubits outside the patch essentially act as an unmodeled environment. Such systematic errors are referred to herein as patching errors. Patching errors have been found to be a limiting factor in the performance of single-patch characterization protocols, as well as more general patch-based characterization protocols that utilize data from multiple patches, in many realistic scenarios.

[0006] Patch-based characterization protocols are subject to systematic patching errors, as defined above. This disclosure provides a method to overcome this difficulty, enabling efficient, detailed, and high-resolution characterization of the run error in a single patch, unlimited by patching errors. As a result, characterization of multiple patches can be combined into a reliable, complete device characterization. This method involves a novel complementary "adjacent gate sequence" acting on adjacent qubits, in addition to a standard "characterization gate sequence" within a given patch. While the characterization gate sequence is designed to produce measurement results sensitive to the run error of the patch, the adjacent gate sequence is chosen to reduce patching errors by reducing sensitivity to run errors (i.e., crosstalk) related to qubits outside the patch. This yields single-patch and whole-device estimates bearing small patching errors, which are demonstrated to be below the statistical error in the actual regime under consideration.

[0007] In general, the characterization methods disclosed herein may be used to rank multiple quantum processors based on fitted model parameters (e.g., by calculating a measure of fidelity or distance, such as diamond distance, between the ideal and actual execution of at least some or each quantum operation). In other embodiments, the characterization methods may be used to provide optimal control over quantum processors by modifying how pulses implement quantum logic operations on the quantum processor based on the fitted model parameters. In some embodiments, the characterization methods may be used to provide error suppression and mitigation by recompiling quantum algorithms based on the fitted model parameters. For example, recompilation may be performed to minimize the use of the noisiest gates. Quantum algorithms and their applications are generally described in the literature (see, for example, www.quantumalgorithmzoo.org). For example, a quantum algorithm may be a factorization algorithm that finds the prime factors of an n-bit integer for use in cryptography.

[0008] According to a first aspect of the subject matter of this disclosure, a computer-operated method is provided for characterizing execution errors in a set of quantum logic operations of a quantum processor. The set of quantum operations acts on a subset of qubits, which define a qubit patch. The execution error relates to the qubit patch and is modeled by a model. The model includes several model parameters. The method involves applying a set of quantum circuits to the quantum processor, at least some of which include a characterization gate sequence and an adjacency gate sequence. The characterization gate sequence is applicable to the qubit patch and is configured to provide measurement results sensitive to at least some of the model parameters. That is, a small change in the model parameters leads to a large change in the measurement results (and their probability distributions) obtained after applying the characterization sequence. The adjacency gate sequence is outside the patch and is applicable to at least some adjacent qubits that interact with the qubit patch. The adjacency gate sequence is configured to reduce the sensitivity of the measurement results to execution errors related to environment qubits outside the qubit patch. The method further includes measuring patch qubits of a quantum processor using a measuring device, repeating the aforementioned actions of applying and measuring a quantum circuit to collect a set of frequencies, the frequencies being associated with the measurement results and the quantum circuit, and calculating the values ​​of model parameters by fitting the model to the set of frequencies.

[0009] In addition to the functions described above, a computer-based method for characterizing the execution error in a set of quantum logic operations of a quantum processor, according to this aspect of the subject matter of this disclosure, may optionally include one or more of the following functions (i) to (xxxiv) in any technically possible combination or permutation: i. Neighboring qubits include qubits that interact with the qubit patch based on the interaction hypergraph. ii. An interaction hypergraph describes a subset of multiple qubits within a quantum processor that interact via multi-qubit execution errors. iii. A hypergraph describes a subset of multiple qubits within a quantum processor to which native multi-qubit gates can be applied. iv. The characterization gate sequence is a gate set tomography sequence. v. A set of quantum logic operations includes initialization and measurement. vi. The gates within that set of quantum logic operations are configured to operate on a single qubit or a pair of qubits. vii. Measuring a patch qubit is performed by measuring all the qubits in the quantum processor, and further includes calculating a reduced frequency from a set of frequencies and aggregating the result with the same patch qubit measurement result. viii. The adjacent gate sequence is configured to reduce patching errors. ix. The patching error is estimated using a perturbation expansion, and the adjacent gate sequence is configured to cancel out or at least reduce the highest order in the perturbation expansion. x. The highest degree in a perturbation expansion includes perturbation expansion degrees up to a given degree. xi. The highest order in a perturbation expansion is 2. xii. The adjacent gate sequence includes initializing the environment qubits in a state configured to cancel or at least reduce the highest order in the perturbation expansion. xiii. The neighboring gate sequence includes initializing the environment qubits in a neighboring mixed state, which is defined as a state in which the density reduction operator of each neighboring qubit is proportional to the unit operator. In some embodiments, the neighboring mixed state may not be a maximum mixed state (i.e., a state in which the density operators of all environment qubits are proportional to the unit operator). xiv. Neighborhood mixing states are even-numbered mixing

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[0011] According to a second aspect of the subject matter of this disclosure, a computer-based method for characterizing a quantum processor is provided. This method includes sequentially applying the method according to a first aspect of the subject matter of this disclosure to a plurality of patches of qubits of the quantum processor.

[0012] In addition to the features described above, a computer-based method for characterizing a quantum processor according to this aspect of the subject matter of the present disclosure may optionally include one or more of the following features (i) to (iv) in any technically possible combination or permutation: i. Multiple patches are duplicated. ii. Multiple patches cover all of the qubits in the quantum processor. iii. To reduce the overall QPU time, sequences corresponding to different patches, including both characterization sequences and adjacent gate sequences, may be applied in parallel. iv. Gauge optimization.

[0013] According to a third aspect of the subject matter of this disclosure, a non-temporary computer-readable storage medium is provided for storing computer instructions, which are used to cause a computer to execute a method according to the first or second aspect of the subject matter of this disclosure.

[0014] According to a fourth aspect of the subject matter of this disclosure, a computer program product is provided, which, when executed by a computer, performs a method according to the first or second aspect of the subject matter of this disclosure.

[0015] A fifth aspect of the subject matter of the present disclosure is provided for characterizing a quantum processor comprising a plurality of qubits, the method comprising applying a characterization protocol to a qubit patch comprising a subset of qubits, wherein the characterization protocol includes reducing patching errors resulting from interactions between qubits inside the qubit patch and qubits outside the qubit patch.

[0016] In addition to the functions described above, a method for characterizing a quantum processor including multiple qubits according to this aspect of the subject matter of this disclosure may optionally include one or more of the following functions (i) to (vi) in any technically possible combination or permutation: i. Apply the characterization protocol sequentially to multiple patches. ii. Multiple patches cover multiple qubits of the quantum processor together. iii. At least some of the patches are duplicates. iv. The characterization protocol further includes applying an adjacent gate sequence to adjacent qubits outside the qubit patch and interacting with the qubit patch, wherein the adjacent gate sequence is configured to reduce the sensitivity of the measurement results to execution errors related to qubits outside the qubit patch. v. The characterization gate sequence within the characterization protocol is configured to provide measurement results that are sensitive to execution errors within both patches and have reduced sensitivity to execution errors related to qubits outside the patches. vi. Quantum processors are described in terms of quantum dits instead of qubits.

[0017] According to a sixth aspect of the subject matter of this disclosure, a quantum circuit is provided for use in characterizing execution errors in a set of quantum logic operations of a quantum processor. The set of quantum operations acts on a subset of qubits, which define a qubit patch. The execution error relates to the qubit patch and is modeled by a model. The model includes a number of model parameters. The quantum circuit includes a characterization gate sequence applicable to a qubit patch and configured to provide measurement results sensitive to at least some of the model parameters, and an adjacent gate sequence applicable to at least some adjacent qubits interacting with the qubit patch, wherein the adjacent gate sequence is configured to reduce the sensitivity of the measurement results to execution errors related to environmental qubits outside the qubit patch.

[0018] In addition to the functions described above, a quantum circuit for using the execution error in a set of quantum logic operations of a quantum processor for characterization may optionally include one or more of the following functions (i) to (iv) in any technically possible combination or permutation: i. The characterization gate sequence is a gate set tomography gate sequence. ii. The neighboring gate sequence includes initializing neighboring qubits in a neighboring mixed state. iii. The adjacent gate sequence includes a dynamic decoupling sequence configured to reduce patching errors. iv. The adjacent gate sequence includes randomly selected adjacent gates.

[0019] According to a seventh aspect of the subject matter of this disclosure, a system is provided comprising a computer and a quantum processor, wherein the computer has gate-level access to the quantum processor, and the system is configured to carry out a method according to a first, second, fifth, or sixth aspect of the subject matter of this disclosure.

[0020] In this disclosure, the following terms and their derivatives should be understood in accordance with the following commentary.

[0021] The term "qubit" can refer to a two-level quantum system.

[0022] The term "quantum qudit" can refer to an M-level quantum system where M≧2. This includes the qubit case M=2 and can also include the boson mode M=∞.

[0023] The term "axis" can refer to a geometric axis of rotation within a Bloch sphere, such as the x-axis representation of a qubit.

[0024] The term "Hamiltonian" can, depending on the context, refer to the Hamiltonian operator or any term thereof, or to having a Hamiltonian property—that is, the absence of decoherence.

[0025] The term "multi-qubit interaction" can refer to execution errors involving multiple qubits (m>1).

[0026] The term "quantum logic operation" can refer to any of the following operations applied to a quantum processor: initialization, measurement, gate application, and reset operations. Additionally, it can also refer to pulse application, intermediate circuit measurement, and / or adaptive measurement.

[0027] The term "model" refers to a set of quantum logic operations in a quantum processor.

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[0031] The term "fitting" can refer to any form of selecting or updating a model based on measurement results obtained from a quantum processor. This includes, for example, calculating the maximum likelihood point in a given model parameter space, or Bayesian updating of the probability distribution across that parameter space.

[0032] Both the model and the fitting procedure can incorporate machine learning methods, such as artificial neural networks and optimization algorithms, which are used to fit such models to data.

[0033] The term "hypergraph" can refer to a generalization of a graph in which edges can connect any number of vertices.

[0034] The term "patch" can refer to a subset of qubits within a quantum processor.

[0035] The term "patching error" may refer to a systematic estimation error that arises in a characterization protocol applied to a patch within a quantum processor due to undesirable interactions between the characterized patch and additional qubits within the quantum processor.

[0036] The term "environment qubit" may refer to a qubit outside the qubit patch as defined in the characterization method of this disclosure.

[0037] The term "neighboring qubit" can refer to an environment qubit that interacts with a qubit patch (i.e., a qubit outside of that patch).

[0038] The term "gate sequence" can refer to a set of gates (i.e., quantum logic operations) applicable to a given qubit within a given time sequence. In particular, the term "characterization gate sequence" can refer to a set of gates applicable to a patch qubit, and the term "adjacent gate sequence" can refer to a set of gates applicable to an adjacent qubit outside a qubit patch. In particular, a gate sequence can include a set of consecutive bursts of gates in a given time configuration, where the gates in each burst are applied directly and consecutively. As described herein, a gate sequence (e.g., an adjacent gate sequence) can consist of a set of entangled gate sequences (e.g., context gate sequences and dynamic decoupling gate sequences).

[0039] The terms “at least one” and “at least several” are understood to be used herein to provide a general description of the method. For brevity, the description will not be repeated by replacing these terms with the term “each.” However, embodiments in which the terms “at least several” and / or “at least one” are replaced with the terms “each” or “substantially each” are also disclosed herein. [Brief explanation of the drawing]

[0040] Embodiments are described herein, only as non-limiting examples, with reference to the accompanying drawings, in order to better understand the subject matter disclosed herein and to illustrate how it can actually be carried out.

[0041] [Figure 1A] The standard Bloch sphere representation of a two-level system, and key pure states, or ketts, are illustrated. [Figure 1B] Examples of density operator representations of pure states and their corresponding superket representations are provided. [Figure 2]The π and π / 2 rotations of the quantum state around the x-axis of the Bloch sphere are illustrated as examples. [Figure 3A] This illustrates different types of execution errors in quantum processors. [Figure 3B] This illustrates different types of execution errors in quantum processors. [Figure 3C] This illustrates different types of execution errors in quantum processors. [Figure 3D] This illustrates different types of execution errors in quantum processors. [Figure 4] An example of error amplification is given. [Figure 5A] This paper provides a schematic description of qubits within a quantum processor, illustrating patch qubits, neighboring qubits, and environment qubits. [Figure 5B] This paper provides a schematic description of qubits within a quantum processor, illustrating patch qubits, neighboring qubits, and environment qubits. [Figure 6] A flowchart illustrating a broad range of methods according to embodiments of this disclosure is shown. [Figure 7A] The embodiments of this disclosure illustrate the application of quantum circuits, including characterization gate sequences and neighboring gate sequences. [Figure 7B] The embodiments of this disclosure illustrate the application of quantum circuits including context gate sequences. [Figure 7C] The application of quantum circuit clusters according to embodiments of this disclosure is illustrated. [Figure 8] A flowchart illustrating the method according to the embodiments of this disclosure is provided as an example. [Figure 9] This illustrates the scaling of patching errors, both those involving and without initial rotation, for a simulated quantum processor containing two qubits. [Figure 10] This example illustrates the ratio of patching error to statistical error using different neighboring sequence settings for a simulated quantum processor containing three qubits. [Figure 11]A computer implementing the method according to the embodiments of this disclosure is schematically illustrated. [Figure 12] A system that implements the method according to the embodiments of this disclosure is provided as a schematic example. [Modes for carrying out the invention]

[0042] Single qubit state and rotation The standard representation of a single-qubit state and the meaning of rotation operations used in the following explanation are reviewed below.

[0043] Figure 1A shows the Bloch sphere 100 representation of a two-level quantum system, i.e., a qubit. Important quantum states are indicated. Any pure state of a qubit can be represented as a point on the surface of the Bloch sphere. A general pure state 155 is shown along with its vector representation 150. The angular parameters correspond to the polar angle θ160 and the azimuthal angle φ170. In the case of quantum computation, there are two diametrically opposed pure states.

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[0045] Impure states are called mixtures and can be represented as points inside the Bloch sphere—Bloch ball. In this case, the vector representation is replaced by a density operator representation. In Figure 1B, the density operator 180 corresponding to state 150 is shown with its explicit matrix equation 185. The density operator 180 has a unique representation as a linear combination 190 of the Pauli and identity operators. Finally, a vector whose elements are the coefficients of the linear combination is defined as the superket representation 195 of the density operator.

[0046] Figure 2 shows the initial state.

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[0051] Quantum logic operations and execution errors The mathematical forms used in the following explanation will be reviewed below.

[0052] A quantum processor or quantum processing unit (QPU) can generally include multiple qubits and the following types of quantum logic operations. 1. The set of supported initial states, for example, a quantum processor may only support initialization to a single predefined state or to multiple predefined states.

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[0055] One of these three sets is a set of quantum logic operations, or a "gate set."

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[0057] The term "supported" means that it is available as a native capability. Non-native gates can be replaced by equivalent combinations of native gates. Similarly, non-native initial states or measurements can be obtained by applying native gates after applying natively available initial states or before applying natively available measurements. State preparation and measurements

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[0059] Mathematically, each initial state ρ is a density operator, i.e., a positive semi-definite and unit trace operator on a d-dimensional Hilbert space, where d=2 n n is the number of qubits. By selecting a Hilbert-Schmidt-orthonormal basis for the Hermitian operator, each initial state is a vector

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[0064] Each element within the gate set has an ideal implementation as intended by the hardware manufacturer. An ideal gate set is:

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[0066] As will be described in more detail below, we do not restrict the ideal gate G0 to being, for example, a 1- or 2-qubit gate, so as to act non-trivially on only a small subset of qubits. An ideal gate can act non-trivially on all qubits in the QPU and can therefore be considered a quantum circuit layer. Thus, the product of gates is interchangeable with "sequence" or "circuit". In some embodiments of the disclosed method, the set of gates being characterized includes at least one SPAM operation or at least one non-idle gate, i.e., gate G, and therefore G0 is not the identity matrix on all qubits.

[0067] The set of execution errors can be defined as the difference between the actual execution in equation (1) and the ideal execution in equation (2). For simplicity, a Markov error model may be used without limiting the scope of this disclosure. In particular, this means that each gate set element may have its own execution error, independently of other circumstances. Such circumstances may include quantum operations, time, etc., as previously applied. Additionally, it is worth noting that given a Markov error model for the entire device, limiting attention to a particular patch generally leads to non-Markov errors in that patch.

[0068] Ideal gate

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[0072] Figures 3A to 3D illustrate examples of execution errors in single and two-qubit gates. In Figure 3A, the intended X π / 2 The rotating gate over-rotates state 310 to state 330 (shown by a coarse dashed line) instead of the correct state 320 (shown by a fine dashed line). Figure 3B shows X π An error of 375 in the gate's axis of rotation is illustrated. The actual axis of rotation is 370, and state 310' is rotated to state 365 instead of 360. In Figure 3C, amplitude attenuation, or T1-attenuation, is illustrated. The pure states present on the Bloch sphere 350 are:

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[0074] In general, quantum processors are, ideally,

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[0083] Given the basic quantum logic operations within the gate set, each quantum circuit that can be implemented on the QPU is given by j=(j1,...,j t This corresponds to the application of a gate to the initial state of a specific sequence labeled by ) and a subsequent measurement that outputs one of the possible results i=0,...,d-1. The symbol t may indicate the number of gates in the sequence. The probability of the i-th result for sequence j in the gate set is given by the following equation:

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[0085] By repeating the same circuit N times, or N shots, a frequency f i =N i / N can be collected, where N i is the number of times the result i was obtained. The frequency is a multinomial probability variable with mean p i and variance (p i (1 - p i )) / N, and thus the statistical error

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[0087] Finally, an important implication of Equation (3) is that the result probability is invariant under a basis change A ∈ GL(d 2 ),

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[0090] Gate-set tomography (GST) Gate-set tomography (GST) is a well-known protocol for characterizing quantum logic operations. It is described herein as an example of a detailed characterization protocol. Its main drawback is that the resources required scale exponentially with the number of qubits, making it currently difficult to apply to quantum processors with more than a few qubits.

[0091] The GST protocol is reviewed below as a basis for subsequent descriptions of embodiments of this disclosure.

[0092] The goal of GST is to characterize execution errors given gate-level access to the QPU. This goal can be achieved in several steps. 1. Model specifications: Gate set

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[0096] Characterization protocols, particularly GST, require both quantum and classical resources. A practical way to quantify quantum resources is to measure QPU time, which is the amount of time required for the data acquisition step. This is generally a device-dependent function T of the number of shots per set of sequence and characterization sequence. QPU (N,{j}). As an example, in a superconducting qubit device, the length of each sequence is t=t jBecause the gate time is short, for example, around 10 ns, it may not be a substantial factor affecting the QPU time. However, the number of separate sequences N seq |{j}| can be a substantial factor influencing QPU time. Firstly, the number of distinct sequences is equal to the total number of shots N. seq Controlling ×N is important because the reset time is long, which can be around 100 μs. Secondly, T QPU is, N seq It can directly depend on how the sequence is compiled into pulses that act on the qubits.

[0097] This specification provides further details regarding sequence selection (step 2 of the GST protocol) relevant to the subsequent description of embodiments in this disclosure.

[0098] To achieve high sensitivity to model parameters, GST is 1 and

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[0102] The parameter variations δθ that can be amplified are δg=(∂g / ∂θ)δθ, which are those that are exchanged with the germ [g,δg]=0. This defines amp(g), which is the linear space of amplified variations for each germ. The initial goal of the sequence selection algorithm is to obtain all amplified variations Σ α amp(g α ) so that the space has the highest rank, sufficient germ g α It is possible to choose this option.

[0103] Initial circuit and final circuit F, F ’ This is called the reference circuit, and it starts with what is natively available, setting the initial state and measured values.

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[0105] Both goals of sequence selection are:

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[0108] Adjacent Gate Sequence As explained in the background section, detailed characterization methods known in this field, such as GST, require computational resources that become rapidly unfeasible as the number of qubits increases. A standard approach to address this problem is to segment multiple qubits into "patches"—small subsets of qubits—and characterize each patch itself while ignoring the remaining qubits.

[0109] Naive segmentation is a problem resulting from crosstalk—undesirable interaction—between qubits within a patch and qubits in a QPU outside the patch, referred to as "environment qubits." As demonstrated below, patch-environment interaction can lead to inaccurate characterization of execution errors in the patch and can be a limiting factor in the performance of single-patch characterization protocols and multi-patch protocols composed of them. The characterization error in a single-patch protocol introduced by patch-environment interaction may be referred to as "patching error."

[0110] This disclosure addresses the above problem by adding an “adjacent gate sequence” in parallel with the characterization sequence (such as the GST sequence described above), which is applied to a subset of environment qubits referred to as “adjacent qubits” or “patch neighborhoods.” Adjacent qubits may include qubits outside a patch that are interacting with a qubit patch, as defined, for example, by an interaction graph, or more generally, a hypergraph (which may also be referred to as a coupling map) (i.e., environment qubits). The vertices of the interaction hypergraph may represent qubits in the QPU, and the hyperedges may correspond to a subset of qubits suspected of interacting via multi-qubit execution errors or crosstalk. In some embodiments, the interaction hypergraph may be specified by the user. In some embodiments, the hypergraph may be defined such that the hyperedges correspond to a subset of qubits in which a native multi-qubit gate resides within the QPU. The qubits in such a subset must be physically coupled to enable the application of the native gate, and therefore it is natural to expect that these qubits also undergo significant crosstalk. The characterization sequence is configured to produce measurement results that are highly sensitive to the execution error of the characterized patch, while the neighboring gate sequence is configured to reduce the sensitivity of the measurement results to execution errors related to the environment qubit, more specifically the neighboring qubit. Such manipulation of neighboring qubits results in reduced patching errors, enabling reliable characterization of individual patches and, consequently, reliable characterization of the full quantum processor.

[0111] Figure 5A illustrates an interaction graph in a quantum processor 500 containing multiple qubits. The quantum processor 500 has eight qubits labeled Q1 to Q8. The interaction graph shows qubits suspected of interacting via two-qubit execution errors connected by thin lines. Patch 510 may be defined and may contain two qubits Q1 and Q2. Qubits outside the patch may be called environment qubits. Environment qubits that interact with patch qubits may be called neighboring qubits. In Figure 5A, patch 510 is enclosed by a thick solid line. The patch qubits directly interact with qubits Q3, Q4, Q5, and Q6. These four qubits constitute neighboring qubits 520 in an embodiment in which neighboring qubits consist of qubits outside the patch that are directly coupled with qubits within the patch. Neighboring qubits are enclosed by a thick dashed line. Qubits Q7 and Q8 are not neighboring qubits. Based on the interaction graph, these environment qubits interact only indirectly with the patch qubits Q1, Q2, not directly, but through neighboring qubits. More generally, interactions can involve not only pairs of qubits, but also triplets, quadruplets, or more generally, subsets of multiple qubits, in which case the interaction graph used to define neighboring qubits is replaced by a hypergraph.

[0112] Figure 5B illustrates a different interaction graph 500' containing multiple qubits. Each qubit is represented by a circle, and interacting qubits are connected by lines. In this embodiment, interactions are assumed only between geometrically nearest neighbors; that is, a qubit can only interact with qubits that are directly to its left, right, above, or below. Different embodiments may model interactions differently, for example, between the next geometrically nearest neighbors. Patch 510' consists of qubits marked with a checkerboard pattern, such as qubit 512', which has a total of four qubits. Adjacent qubits are marked with a diagonal stripe pattern, such as qubit 520', which has a total of eight qubits. Four qubits, such as qubit 530', are outside both the patch and the adjacent qubits and are marked in plain white.

[0113] Figure 6 is a flowchart illustrating the steps of a computer-based method for characterizing execution errors in a set of quantum logic operations of a quantum processor, according to embodiments of the present disclosure. As described above, a quantum processor may include a plurality of qubits and gate sets. A gate set may include initialization and measurement operations. A gate set may be configured to operate on a single qubit or a pair of qubits. The method may include defining a subset of qubits, also referred to as a qubit patch. A gate set may act on such a qubit patch, and the execution errors related to the qubit patch may be modeled by a model including a plurality of model parameters.

[0114] The method may include step 610 of applying a set of quantum circuits on a quantum processor. Applying the set of quantum circuits may include applying a characterization gate sequence 613 to the qubit patch and applying an adjacent gate sequence 617 to the adjacent qubits. The characterization gate sequence may be, for example, a GST sequence. As described above with reference to Figure 5, adjacent qubits are qubits that are not in the patch but are assumed to be interacting with the qubits in the patch. The adjacent gate sequence is configured to reduce the sensitivity of the measurement results to execution errors related to environment qubits outside the qubit patch.

[0115] The method may further include step 620 of measuring the qubit. The measurement of the qubit may be carried out using a measuring device of the quantum processor. In some embodiments, the measurement may include measuring some or all of the qubits of the quantum processor. In some embodiments, the measurement may include measuring a patch qubit.

[0116] The method may further include step 630, which repeats steps 610-620 to collect a set of measurement results and frequencies associated with the quantum circuit. In some embodiments, the measurement of the qubit may be performed on a patch qubit and an environment qubit. The method may then further include calculating the reduced frequencies from the entire set of frequencies by summing the values ​​of the environment qubit over frequencies corresponding to results that differ only in their properties. In some other embodiments, the measurement of the patch qubit may be performed separately from the environment qubit, and the step of calculating the reduced frequencies may not be necessary.

[0117] The method may further include step 640, which involves fitting the model parameters to the given set of frequencies. The fitting principle may be similar to the fitting principle used in the GST protocol, which is described below.

[0118] In some embodiments, the method can be applied sequentially to a series of different qubit patches. This may provide a complete characterization of the quantum processor.

[0119] In some embodiments, the method may be applied repeatedly to the same qubit patch, and the fitted parameters obtained in each iteration may be used to construct both an adjacent gate sequence and a characterization gate sequence for the next iteration. This may provide characterization of the patch over time.

[0120] In some embodiments, the adjacent gate sequence may be configured to reduce the patching error estimated by perturbation expansion.

[0121] In some embodiments, the adjacent gate sequence may be configured to cancel or reduce the highest order in the perturbation expansion.

[0122] Patching error: mathematical definition The following provides a detailed example, including a precise mathematical definition of patching error. This example is followed by a perturbation calculation of the patching error, an example of an adjacent gate sequence motivated by the perturbation expansion, and a numerical simulation demonstrating the performance of that adjacent gate sequence in a realistic scenario.

[0123] Native gate set including 1- and 2-qubit gates

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[0127] n qubits are considered a "patch" of n qubits patch A qubit and n, which is considered the "environment" env =nn patchThe complementary qubits can be artificially separated. Regarding the error generator, this is L j =L j,patch +L j,env +H j,int to patch, environment, and (Hamiltonian) interaction part

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[0129] The operator or superoperator A should be noted that when it can be written as (where I

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[0132] The goal of the characterization protocol applied to a single patch ("single-patch protocol") is related only to the patch qubits and the execution error L j =h j,patch that occurs in a subset of the gates

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[0139] The single-patch characteristic evaluation protocol does not account for execution errors related to qubits outside the patch. In particular, it is assumed that H int = 0. Under this assumption, the action of each gate G patch having j ∈ J j is

[0140] [Number] becomes, The reduced probability is simplified as follows,

[0141] [Number] This holds when there is no environmental qubit. The single-patch protocol,

[0142] [Number] is assumed to receive a sample from, but instead receives a sample from p i,j to receive a sample, the patch

[0143] [Number] for the execution error within, or equivalently for the gate set

[0144] [Number] an incorrect estimated value is output for. Define the "probability of patching error" as δp = p - p (0) as follows. L j,patch , or alternatively

[0145] [Number] The corresponding systematic (i.e., infinite statistics, N = ∞) deviation in the estimated value of can be defined as the patching error itself.

[0146] As an example of a single-patch characterization protocol, consider GST applied to a single patch. The parameterization or model,

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[0161] The above generalization suggests possible improvements to the goals of a single-patch characterization protocol: the set of patch gates acting on the patch qubits

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[0164] To quantify the degree to which it is important to apply context gates in parallel to corresponding patch gates, the concept of "context dependency" can be defined.

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[0172] Context dependency leads to a tension between reducing patching errors and minimizing the time spent in the wrong context. This translates to a tension between neighboring gate sequences and context gate sequences, both of which act on neighboring qubits during the application of the characterization gate sequence. Generally speaking, strong context dependency favors "sparse" neighboring gate sequences that efficiently suppress patching errors with only a small number of gates.

[0173] Below, we demonstrate perturbation analysis of patching errors. For simplicity, the analysis is performed ignoring context dependency, assuming that all patch gates are intended to operate in an idle context. Next, we demonstrate in simulations that adjacent gate sequences motivated by perturbation analysis can efficiently reduce patching errors even in context-dependent scenarios.

[0174] Patching error: Perturbation calculation The probabilistic patching error δp will be used later to construct an example of an adjacent gate sequence. i,j The perturbation calculation of is described in detail below. In the perturbation expansion, L patch ,L env ,H int However, with a suitable operator norm,

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[0177] For each sequence, the "effective error generator"

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[0192] Initial state, nearby mixed state, and initial rotation The applicant is an environmental qubit ρ env For a specific initial state of, the expression that appears in the first two lines of equation (9)

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[0195] As the first example, H int but

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[0202] More generally, the applicant is an environmental qubit ρ env The initial state is the reduced density matrix ρ on each neighboring qubit y. y If the mixture is as large as possible, that is, ρ x If =I2 / 2, the expression that appears in the first two lines of formula (9)

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[0209] In some embodiments, the patching error may be estimated using a perturbation expansion, and the adjacent gate sequence may include initializing the environment qubits in such a state that it cancels or at least reduces the highest order in the perturbation expansion.

[0210] In some embodiments, the neighboring gate sequence may include initializing the environment qubits in a neighboring mixed state.

[0211] In some embodiments, the neighboring gate sequence may include initializing only the neighboring qubits of the neighboring mixed state.

[0212] In some embodiments, the definition of a neighboring mixed state does not include the maximum mixed state (i.e., a state in which the density operator of all environment qubits is proportional to the unit operator).

[0213] Based on the interpretation of mixed states as probability distributions across pure states, the applicant has found that the preparation of several neighborhood mixed states can be obtained by including “initial rotations” in the neighboring gate sequences. The latter corresponds to assigning several distinct neighboring gate sequences to a given characterization sequence and averaging them over corresponding frequencies. These different neighboring sequences may differ in their initial gates such that the averaging corresponds to the preparation of mixed (and neighborhood mixed) initial states. In other words, a set of quantum circuits may include (or consist of) a set of quantum circuit clusters, each of which includes multiple quantum circuits having the same characterization gate sequence and distinct neighboring sequences. In these embodiments, the method may include combining (e.g., averaging) the frequencies collected on the quantum circuits of the same cluster. The different neighboring sequences may differ in their initial gates such that the combination (e.g., averaging) corresponds to the preparation of mixed (and neighborhood mixed) initial states. Thus, the initial rotations remove the first order in the perturbation expansion of patching errors without requiring complex initialization procedures.

[0214] For example, the initial rotation corresponding to the state in equation (12) is assigned two different adjacent sequences for each characteristic evaluation sequence, the first starting with an idle gate and the second starting with X π It may begin with a gate, both applied in parallel to all neighboring qubits, and then average two different frequencies of each characterization sequence. A characterization method including the initial rotation described above may include, for example, the following steps: 1. A step of providing input, a. A set of {j'} of characterization gate sequences (like GST gate sequences) that can (ideally) operate within the patch, b. A step of providing an input, including N shots for repeating the characterization method presented in the present disclosure, particularly in the appended claims, and measurement steps (a) to (b). 2. For each characteristic evaluation gate sequence j', modify the first (ideal) gate in sequence j'' to obtain a new sequence. The modification is performed by modifying the first gate in sequence j'.

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[0220] The required QPU time is T QPU It can be (N / 2, {j'}∪{j''}). QPU time T for a bare sequence. QPU Compared to (N,{j'}), the number of sequences doubles, but the total number of shots remains the same.

[0221] To reiterate, the patching error due to initial rotation (or neighbor mixing) is only of order 2.

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[0225] As explained below and shown, for example in Figure 7A, an adjacent gate sequence may include an initial rotation followed by an additional gate.

[0226] Figure 7A illustrates a quantum circuit applied to a method performed by a computer to characterize the execution error in a set of quantum logic operations of a quantum processor, according to embodiments of the present disclosure. For example, a characterization sequence 740 (such as a GST sequence) may be applied to a patch qubit 710, and an adjacent gate sequence 750 may be applied to an adjacent qubit 720. In this embodiment, no gates (i.e., idle gates) may be applied to qubits that are outside the patch qubit 710 and are not part of the adjacent qubit 720. After the characterization and adjacent gate sequences 740, 750 are applied, the qubits are measured 760.

[0227] The characterization sequence 740 applied to the patch qubit 710 may be a GST sequence determined according to the GST protocol. The characterization sequence may include an initial reference sequence F 742, a final reference sequence F' 746 for preparing the qubit for measurement, and multiple applications of germ g 744. The neighbor sequence 750 applied to the neighboring qubit 720 may include an initial rotation 753 and a dynamic decoupling sequence 756.

[0228] As explained above, the neighbor gate sequence 750 may include initializing the environment qubits of the neighbor mixed state. In particular, the neighbor sequence 750 may include an initial rotation 753 which may include applying a π rotation along the x-axis to each neighbor qubit only for half of the iterations of each characterization sequence. For the other half, the rotation may not be applied and is instead symbolized as applying the identity gate.

[0229] In some embodiments, at least some of the dynamic decoupling gates (or sets of gates) 756 are applied synchronously with the germ, i.e., the dynamical decoupling ("dynamical decoupling, DD") operation may begin simultaneously with the start of the germ.

[0230] In this disclosure, the term “coordination” may refer to the relative timing in the application of gates. Timing can be affected by the characteristics of the processor. For example, execution error may be sensitive to the time spent idling, even for simple idling of any qubit. Examples of relative timing between gates may include the simultaneous start of one or more gates applied to one or more qubits and one or more other gates applied to one or more other qubits, the simultaneous end of one or more gates applied to one or more qubits and one or more other gates applied to one or more other qubits, or a predetermined delay between one or more gates applied to one or more qubits and one or more other gates applied to the same or one or more other qubits.

[0231] Figure 7B illustrates a method performed by a computer to characterize the execution error in a set of quantum logic operations of a quantum processor according to embodiments of the present disclosure, including a context gate sequence. In embodiments such as those illustrated in Figure 7B, the quantum circuit may include a characterization gate sequence 740B, a context gate sequence 745, and an adjacent gate sequence 750B. As discussed above, gates that act ideally separably with respect to the patch and the environment can be characterized using embodiments of the present disclosure. Such gates may be described as gates that act synchronously with a patch qubit and a corresponding (potentially non-idle) context gate that acts on an environment qubit. The characterization gate sequence 740B may include a characterization gate (or a short sequence of such gates, i.e., a germ) g 744B acting on a qubit in patch 710B. The context gate sequence 745 may include a context gate (or a short sequence of such gates) g' that acts synchronously with the characterization gate on an adjacent qubit 720B or more generally on an environment qubit. The combination of the characterization gate and the context gate may form a circuit layer 743. In some embodiments, the adjacent gate sequence 750B may include a dynamic decoupling gate DD751 and an initial rotation 753B applied to the adjacent qubit 720. The adjacent gate sequence 750B and the context gate sequence 745 may be temporally intertwined. In some embodiments, the dynamic decoupling gate 751 may be aligned with the context gate 745 so as to start after the context gate has finished, while the context gates may be applied synchronously with their corresponding characterization gates. This implies that idle gates are added synchronously with the dynamic decoupling gate DD751 to the characterization sequence, which is shown as a space between consecutive germs g744B. In some embodiments, these idle gates may be replaced by other gates to further reduce patching errors or increase sensitivity to model parameters.Depending on the claimed impact of context dependency on characterization, some context gates may be omitted and / or replaced by adjacent gates, such as dynamic decoupling gates. In some embodiments involving a context gate sequence, at least one adjacent gate may be applied synchronously with the corresponding characterization gate.

[0232] The quantum circuit may further include an initial reference sequence F742B, a final reference sequence F'746B, and a measurement sequence 760B. The germ 744B and reference sequences 742B and 746B may form a characterization gate sequence 740B.

[0233] In some embodiments, the initial and final reference sequences F742B, F'746B may also be performed in conjunction with corresponding context gates (not shown), and the initial rotation may be performed before the context gate corresponding to the (initial) reference sequence F742B.

[0234] It is worth noting that the difference in the application of dynamic decoupling between the embodiment shown in Figure 7A and the embodiment shown in Figure 7B may arise from the claimed effect of context dependency. In the embodiment shown in Figure 7A, context dependency may not be considered significant, and dynamic decoupling may be performed synchronously with the characterization gate. In contrast, in the embodiment shown in Figure 7B, context dependency may be considered significant, and dynamic decoupling may be performed sequentially with respect to the characterization gate.

[0235] Figure 7C illustrates a quantum circuit cluster applied to a method performed by a computer for characterizing execution errors in a set of quantum logic operations of a quantum processor, according to embodiments of the present disclosure. In this embodiment, a clustering of quantum circuits is shown. The quantum circuit cluster may consist of quantum circuits 704 and 706. Quantum circuits 704 and 706 may include the same characterization sequence 740C that can be applied to the qubit of patch 710C and two different neighbor gate sequences 751 and 751' that can be applied to the neighboring qubit 720C. In some embodiments, the two neighbor gate sequences may have different initializations, but the rest of the neighbor gate sequences may be similar. As shown in Figure 7C, the two neighbor sequences 751 and 751' may include different initialization gates for neighboring qubits. In quantum circuit 704, the neighboring qubit 720C may be initialized by applying a π rotation along the x-axis X 757. In quantum circuit 706, the initialization of the neighboring qubit 720C may be performed by applying an idle gate I 757'. The difference between the two adjacent sequences in the illustrated embodiment, 751 and 751', is that of different dynamic decoupling sequences D759 and

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[0239] In some other embodiments, frequency

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[0246] In some other embodiments, the clustering may include more than two quantum circuits per cluster, and each quantum circuit in a given cluster may include different adjacency sequences and the same characterization sequence.

[0247] In some other embodiments, the averaging can be weighted.

[0248] In some other embodiments, averaging can be replaced by a nonlinear function.

[0249] Accidental amplification and de-amplification sequences As explained above, for all quantum circuits j, the patching error is the general initial state ρ env So,

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[0259] commutative projection H int,0 As long as it does not disappear, this is a general case, but the preceding t=t of the effective error generator j Scaling is actually saturating. This is true even for typical, nearly periodic sequences.

[0260] As demonstrated above, accidental amplification implies an undesirable scaling of patching errors with respect to sequence length in a nearly periodic characterization sequence. The applicant has found that adjacent gate sequences including deamping sequences can be used to eliminate accidental amplification of out-of-model execution errors while maintaining a carefully constructed amplification of in-model execution errors. In some embodiments, such deamping sequences may be aperiodic. In some embodiments, such sequences may be periodic and have a deamping period different from the period of the characterization sequence. In some embodiments, such sequences may be unstructured and / or random, or may be carefully structured for deamping. In particular, structured “dynamic decoupling” sequences may be used. Dynamic decoupling (DD) is well known in the art for other applications. As a basic definition, an m-order DD sequence applied to a given set of qubits removes the coherent error relating to that set of qubits up to (and including) the m-order in perturbation theory for an ideal and instantaneous DD gate. A standard example of a first-order DD sequence is given by the so-called XY4 sequence, which can be written as XYXY. Undesirable Hamiltonian evolution e tH When applied to a qubit subjected to =I+O(tH), the XY4 sequence (using an ideal and instantaneous gate) evolves this development

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[0262] In some embodiments of this disclosure, the gates of the DD neighbor sequence may be matched with the gates of the characterization sequence. In some embodiments, the characterization sequence may have a periodic portion (e.g., a GST sequence), and the DD sequence may be applied in parallel with the periodic portion of the sequence (i.e., a GST germ). Synchronization may be such that each dynamic decoupling gate is applied precisely with the first gate of the germ that it can correspond to. The DD gates may be evenly distributed across the germ repeats. An algorithm for generating a quantum circuit including a substantially periodic characterization gate sequence and a neighbor gate sequence incorporating DDs for use in the characterization method of this disclosure may include, for example, the following steps: 1. A step of providing input, a. A characterization gate sequence j that can (ideally) operate within the patch. The sequence is

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[0269] It should be noted that in the algorithm described above, the dynamic decoupling sequence may have a number of gates less than or equal to the Germ number. Furthermore, step 2 is a combination step of the characterization and DD sequence. The dynamic decoupling gates can be applied to adjacent qubits, and therefore, mathematically, this can be expressed as the tensor product of each dynamic decoupling gate and the corresponding gate in the characterization sequence. Equation

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[0272] Furthermore, the QPU time is invariant by the addition of the DD neighbor sequence, since the DD gate can be applied in parallel to the characterization sequence. QPU (N,{j DD})=T QPU (N,{j}).

[0273] Therefore, accidental amplification can be eliminated, reducing patching errors as follows: For first-order (or higher-order) DD sequences, the patching error is:

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[0276] Figure 8 is a flowchart illustrating the steps of a method for characterizing execution errors in a set of quantum logic operations of a quantum processor according to an embodiment of the present disclosure. As described above, a quantum processor may include a plurality of qubits and gate sets. Gate sets may act on a subset of qubits that define a qubit patch, and execution errors related to a qubit patch may be modeled by a model that includes a plurality of model parameters. In the first initialization step 811, the qubits of the quantum processor are in an initial state

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[0278] In some embodiments, the characterization methods described herein may be repeated using multiple different (separate) patches, i.e., the characterization methods may be applied sequentially to multiple subsets of qubits of the quantum processor.

[0279] In some embodiments, multiple distinct patches may cover all of the qubits of the quantum processor. In some embodiments, multiple distinct patches may overlap, i.e., different patches may have at least one common qubit. For example, overlapping patches may be desired to collectively characterize all interactions specified by the interaction hypergraph. In some embodiments, some of the patches may contain more than two qubits (e.g., three, four, five, or more qubits). In some embodiments, sequences corresponding to different patches (including both characterization sequences and adjacent gate sequences) may be applied in parallel to reduce the overall QPU time.

[0280] The method described above assumes qubits, but this method is more generally applicable to QPUs that utilize quantum systems with M≧2 logic states. Quantum systems with two or more logic states are known as "qudits." The mathematical framework of the currently disclosed characterization method is independent of the binary properties of qubits. In the quantum dut embodiment, neighboring mixed states

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[0284] It should be noted that the disclosed methods are based on a logical description of QPUs and may apply when qubits are "encoded" or "logical" rather than "physical," i.e., when they correspond to a general two-dimensional subspace in the space of physical states of a QPU. The same description applies to QPUs described by logical quantum bits, and in particular, to the application of the disclosed methods to QPUs that implement quantum error correction, computation in subspaces without decoherence, and topological quantum computation.

[0285] Simulation results Figure 9 shows simulation results applying characterization methods according to several embodiments of the present disclosure. In particular, Figure 9 provides an example of canceling a first-order error in a perturbation expansion of a patching error. A quantum processor 905 consisting of two qubits is simulated. Patch 907 consists of one qubit, and the environment 909 consists of the other qubit, which is an adjacent qubit. Graphs 910, 920 show the interaction between the patch and the environment ∈ int Patching error δp as a function of intensity i,jThis is shown. Graph 910 shows the patching error without initial rotation - adjacent / environment qubits are initialized to 0. Graph 920 shows the patching error when initial rotation is used. The axes of the graphs are logarithmic in both the x and y axes.

[0286] The simulated characterization sequence j is directed to the patch qubit.

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[0288] What can be seen in the graph is ∈ int This is an eye guide for linear scaling 931 931' and quadratic scaling 932 932', which have the following characteristics. Without the first rotation, the patching error of odd-length sequences marked with black circles is t∈ int The patching error of even-length sequences, scaled to 913 and marked with a white square, is:

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[0292] Figure 10 shows simulation results applying the characterization methods according to several embodiments of the present disclosure. In particular, the GST model parameters, δθ patching / δθ stat The ratio of patching error to statistical error in is illustrated. A quantum processor 1010 consisting of three qubits, including the interaction between the characterized patch and its environment, and context dependency, is simulated. Patch 1013 consists of two qubits labeled q0 and q1. Environment 1017 consists of one qubit labeled q2. Environment qubit q2 interacts only with patch qubit q1. Graphs 1020, 1030, and 1040 show the ratio δθ for coherent parameters (e.g., rotation angle) supported on qubit q0, qubit q1, and q0-q1 interaction, respectively. patching / δθ stat This is shown. Graphs 1050 and 1060 show the ratio δθ for incoherent parameters (e.g., dissipation rate) supported on qubit q0 and qubit q1, respectively. patching / δθ stat This shows that the graph's axes, both the x and y axes, are logarithmic.

[0293] For simplicity, the errors for different parameters are averaged, and this average (y-axis) is plotted as a function of the number of germs in the characterization sequence (x-axis). 10 -4 Only significant execution errors with a larger magnitude are included in the mean. All sequences were repeated for N=300 shots. Four datasets are plotted. The first dataset corresponds to "bare" characterization sequences with no adjacent gate sequences added (shown as circles). The remaining datasets correspond to characterization sequences with the following types of adjacent gate sequences: the first rotation (shown as squares), a structured quadratic dynamic decoupling sequence after the first rotation (shown as triangles), and an equally spaced random sequence after the first rotation (shown as x marks).

[0294] As predicted by the perturbation expansion, a significant reduction in the patching error (compared to the statistical error) for the coherent parameters of qubit q1 is achieved, as shown in Graph 1030. In general, without initial rotation, for some parameters, for some parameters

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[0297] Figure 11 and the following discussion are intended to provide a brief and general description of exemplary computing environments in which the disclosed technology may be implemented. While not required, the disclosed technology is described in the general context of computer executable instructions, such as program modules, executed by a personal computer (PC). Generally, a program module includes routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. Furthermore, the disclosed technology may be implemented in other computer system configurations, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, and mainframe computers. The disclosed technology may also be practiced in a distributed computing environment where tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules may reside in both local and remote memory storage devices.

[0298] Referring to Figure 11, an exemplary system for implementing the disclosed technology includes a general-purpose (classical) computing device in the form of an exemplary conventional PC 1100, comprising one or more processing units 1110, a system memory 1120, and a system bus 1130 that connects various system components, including the system memory 1120, to one or more processing units 1110. The system bus 1130 may be one of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, and / or a local bus using any of various bus architectures. The exemplary system memory 1120 includes read-only memory (ROM) 1122 and random-access memory (RAM) 1127. A basic input / output system (BIOS) 1125 containing basic routines useful for transferring information between elements within the PC 1100 is stored in the ROM 1122. As shown in Figure 11, the system memory 1120 may store computer-executable instructions for performing any of the disclosed techniques (e.g., sending instructions to a quantum computer to apply a characterization gate sequence and an adjacent gate sequence to a subset of qubits, measuring the results, collecting frequencies, and calculating model parameters) in their respective memory portions (generally indicated as executable software 1129 for performing any embodiment of the disclosed synthesis technique).

[0299] An exemplary PC1200 further includes one or more storage devices 1140, such as a hard disk drive for reading and writing to a hard disk, a magnetic disk drive for reading and writing to a removable magnetic disk, and / or an optical disk drive for reading and writing to a removable optical disk (such as a CD-ROM or other optical medium). Such storage devices can be connected to the system bus 1130 by a hard disk drive interface, a magnetic disk drive interface, and / or an optical drive interface, respectively. The drives and their associated computer-readable media provide non-volatile storage for computer-readable instructions, data structures, program modules, and other data for the PC1200. In the exemplary operating environment, other types of computer-readable media that can store data accessible by the PC may also be used, such as magnetic cassettes, flash memory, digital video discs, CDs, DVDs, RAM, NVRAM, and ROM. As used herein, the terms storage, memory, and computer-readable media may not include or encompass the propagating carrier or signal itself.

[0300] The operating system, one or more application programs, other program modules, and several program modules including program data may be stored in the storage device 1140. The storage of quantum measurement results and instructions for obtaining such measurements (and / or instructions for carrying out any embodiment of the disclosed technology) may also be stored in the storage device 1140. The user may input commands and information to the PC 1100 via one or more input devices 1150, such as a keyboard and a pointing device such as a mouse. Other input devices may include a digital camera, microphone, joystick, gamepad, satellite receiver antenna, scanner, etc. These and other input devices are often connected to one or more processing units 1110 via a serial port interface coupled to the system bus 1130, but may be connected by other interfaces such as a parallel port, game port, or universal serial bus (USB). A monitor 1180 or other type of display device is also connected to the system bus 1130 via an interface such as a video adapter. Other peripheral output devices 1160 may include speakers and a printer (not shown). In some cases, a user interface is displayed so that the user can input the circuit for synthesis and verify the success of the synthesis.

[0301] The PC1200 may operate in a networked environment using logical connections to one or more remote computers, such as remote computers 1190. In some examples, this may include one or more network or communication connections 1170. The remote computer 1190 may be another PC, server, router, network PC, peer device, or other common network node, and typically includes many or all of the elements described above with respect to the PC1100, although Figure 11 illustrates only the memory storage device 1195. The personal computer 1100 and / or remote computer 1190 may be connected to a local area network (LAN) and a wide area network (WAN). Such networking environments are common in offices, enterprise-wide computer networks, intranets, and the internet.

[0302] When used in a LAN networking environment, the PC1100 connects to the LAN via a network interface. When used in a WAN networking environment, the PC1100 typically includes a modem or other means for establishing communication over a WAN such as the Internet. In a networked environment, program modules or parts thereof described in relation to the personal computer 1100 may be stored in a remote memory storage device or other location on the LAN or WAN. The illustrated network connection is illustrative, and other means may be used to establish communication links between computers.

[0303] Referring to Figure 12, an exemplary system for implementing the disclosed technology includes a computing environment 1200, the environment including one or more quantum processing units 1210, each including one or more monitoring / measurement devices. The quantum processing units execute quantum circuits provided by classical processing units 1220. The quantum circuits are downloaded to the quantum processing units 1210 or used to program or configure the quantum processing units (e.g., via control lines (quantum buses), 1270). Procedures according to any of the disclosed embodiments (e.g., a high-level description of a set of quantum circuits applied to a qubit patch and neighboring qubits) may be stored in memory 1230.

[0304] Referring to Figure 12, a high-level description of quantum software can be translated into a quantum circuit (e.g., a sequence of quantum gates, or a layer of gates acting in parallel on different qubits). Such a high-level description may, in some cases, be stored on one or more external computers 1260 outside the computing environment 1200 using one or more memory and / or storage devices 1265, and then, if necessary, can be downloaded to the computing environment 1200 via one or more communication connections 1240. The quantum circuit (according to any of the disclosed embodiments) is coupled to a quantum processor 1210.

[0305] The quantum processing unit may be, but is not limited to, one or more of the following: (a) a superconducting quantum computer, (b) an ion-trap quantum computer, (c) a topological quantum computer using, for example, a Majorana zero-mode, (d) a photon quantum computer, or (e) a neutral-atom quantum computer. A set of gates (e.g., using any of the disclosed embodiments) may be transmitted to the quantum processing unit via control lines 1270 in the controller 1250 (or may be otherwise applied). In the illustrated example, the desired quantum computing process is carried out using one or more controllers 1250, each specifically adapted to control one of the corresponding quantum processors 1210. The classical processor 1220 can further interact with a measurement / monitoring device (e.g., a readout device) 1280 to help control and implement the desired quantum computing process (e.g., by reading or measuring data results from the quantum processing unit when available).

[0306] While the principles of the disclosed technology have been described and illustrated with reference to the illustrated embodiments, it will be recognized that the illustrated embodiments can be modified in configuration and detail without departing from such principles. For example, elements of the illustrated embodiments shown in software can be implemented in hardware, and vice versa. Furthermore, technology from any example can be combined with technology described in any one or more of the other examples. It will be understood that procedures and functions, such as those described with reference to the illustrated examples, can be implemented in a single hardware or software module, or separate modules may be provided. The particular configurations described above are provided for convenient illustration purposes, and other configurations can be used.

[0307] Therefore, applying the wording of the clause, this disclosure provides methods, systems, and circuits subject to the following clauses, but is not limited to these: Clause 1: A computer-based method for characterizing the execution error in a set of quantum logic operations of a quantum processor, wherein the set of quantum logic operations acts on a subset of qubits that define a qubit patch, and the execution error related to the qubit patch is modeled by a model that includes a plurality of model parameters, and the method (a) A quantum processor comprising a set of quantum circuits, wherein at least some of the quantum circuits are i) A characterization gate sequence applicable to the qubit patch configured to provide measurement results sensitive to at least some of the model parameters, ii) Applying a set of quantum circuits including an adjacent gate sequence that is applicable to at least some adjacent qubits outside a qubit patch and interacts with the qubit patch, wherein the adjacent gate sequence is configured to reduce the sensitivity of the measurement results to execution errors related to environmental qubits outside the qubit patch. (b) Measuring patch qubits using the measurement device of the quantum processor, (c) Repeat (a) to (b) to collect the measurement results and the set of frequencies associated with the quantum circuit, (d) Computing the model to the set of frequencies to calculate the values ​​of the model parameters.

[0308] Clause 2: As described in Clause 1, neighboring qubits include qubits that interact with a qubit patch based on an interaction hypergraph.

[0309] Clause 3: As described in Clause 2, an interacting hypergraph describes a subset of multiple qubits within a quantum processor that interact via multi-qubit execution errors.

[0310] Clause 4: As set forth in Clause 2, a hypergraph describes a subset of multiple qubits within a quantum processor to which native multi-qubit gates may be applied.

[0311] Clause 5: As described in any of Clauses 1-4, the characterization gate sequence is a gate set tomography sequence.

[0312] Clause 6: As set out in any of Clauses 1-5, the set of quantum logic operations includes initialization and measurement.

[0313] Clause 7: As described in any of Clauses 1-6, the gates in that set of quantum logic operations are configured to operate separably with respect to a single qubit or a pair of qubits.

[0314] Clause 8: Measuring a patch qubit, as described in any of Clauses 1-7, is performed by measuring all qubits in the quantum processor, and further includes calculating a reduced frequency from a set of frequencies and aggregating the result with the same patch qubit measurement result.

[0315] Clause 9: As described in any of Clauses 1-8, the adjacent gate sequence is configured to reduce patching errors.

[0316] Clause 10: As described in Clause 9, the patching error is estimated using a perturbation expansion, and the adjacent gate sequence is configured to cancel out or at least reduce the highest order in the perturbation expansion.

[0317] Clause 11: As stated in Clause 10, the highest degree includes perturbation expansion degrees up to a given degree.

[0318] Article 12: As stated in Article 11, the given degree is second.

[0319] Clause 13: As described in any of Clauses 1 through 12, an adjacent gate sequence includes initializing the environment qubits in a state configured to cancel or at least reduce the highest order in the perturbation expansion.

[0320] Clause 14: As described in any of Clauses 1-13, an adjacent gate sequence involves initializing the environment qubits in a neighboring mixed state, where the density reduction operator for each adjacent qubit is proportional to the unit operator.

[0321] Clause 15: As described in Clause 14, if the neighboring mixing state is an even mixing

[0322]

number

[0323] Clause 16: As set out in any of Clauses 1-15, a set of quantum circuits consists of quantum circuit clusters, each quantum circuit cluster comprising multiple quantum circuits having the same characterization gate sequence and distinct neighboring gate sequences, and the method further comprises combining frequencies collected on the quantum circuits of the same cluster.

[0324] Clause 17: As described in Clause 16, a set of quantum circuits comprises a quantum circuit cluster consisting of two quantum circuits, each having the same characterization gate sequence and a first neighbor gate sequence beginning with an idle gate and a second neighbor gate sequence beginning with a π rotation, respectively, wherein both the first and second neighbor gate sequences are applied to each neighboring qubit, and the method further includes averaging the frequencies collected on the two quantum circuits of each quantum circuit cluster.

[0325] Clause 18: As described in any of Clauses 1 to 17, at least one of the quantum circuits further includes a context gate sequence applicable to one or more environment qubits outside the qubit patch, the context gates of the context gate sequence are applied synchronously to at least some of the characterization gates of the characterization gate sequence of the at least one quantum circuit.

[0326] Clause 19: As described in Clause 18, adjacent gate sequences and context gate sequences are intertwined in time.

[0327] Clause 20: As described in Clause 18 or 19, at least one adjacent gate sequence of the quantum circuit includes at least some adjacent gates that are applied synchronously with at least some of the characterization gates of the characterization gate sequence of the at least one quantum circuit.

[0328] Clause 21: As described in any of Clauses 18-20, at least one adjacent gate sequence of the quantum circuit includes at least some adjacent gates that are successively applied to at least some of the characterization gates of the characterization gate sequence of the at least one quantum circuit.

[0329] Clause 22: As described in any of Clauses 18-21, some of the context gates are configured to form a circuit layer together with the characterization gate sequence.

[0330] Clause 23: As described in any of Clauses 1 to 22, at least one of the quantum circuits includes an adjacent gate sequence that includes randomly selected adjacent gates.

[0331] Clause 24: As described in any of Clauses 1 to 23, at least one of the quantum circuits includes an adjacent gate sequence that includes a dynamic decoupling sequence configured to reduce patching errors.

[0332] Clause 25: As described in Clause 24, the dynamic decoupling sequence is configured to reduce the patching error estimated by perturbation expansion.

[0333] Clause 26: As described in Clause 25, the dynamic decoupling sequence is configured to remove the highest order in the perturbation expansion.

[0334] Article 27: As set forth in Article 26, the highest degree includes perturbation expansion degrees up to a given degree.

[0335] Article 28: As stated in Article 27, the given degree is of degree 2.

[0336] Clause 29: The dynamic decoupling sequence is consistent with the characterization gate sequence of the at least one quantum circuit, as described in any of Clauses 24-28.

[0337] Clause 30: As described in Clause 29, at least some gates of the dynamic decoupling sequence are applied synchronously with at least some gates of the characterization gate sequence of the at least one quantum circuit.

[0338] Clause 31: As described in Clause 29 or 30, at least some gates in the dynamic decoupling sequence are applied sequentially to at least some gates in the characterization gate sequence of at least one quantum circuit.

[0339] Clause 32: As set out in any of Clauses 1 through 31, a qubit patch shall contain at least three qubits.

[0340] Clause 33: A method performed by a computer for characterizing a quantum processor, comprising applying sequentially to a plurality of patches of qubits of the quantum processor the method according to any one of claims 1 to 32.

[0341] Clause 34: As stated in Clause 33, the multiple patches in question are redundant.

[0342] Clause 35: As set out in Clause 33 or 34, multiple patches cover all of the qubits of the quantum processor.

[0343] Clause 36: Further includes gauge optimization as described in any of Clauses 1-35.

[0344] Clause 37: A non-temporary computer-readable storage medium for storing computer instructions, the computer instructions being used to cause a computer to perform any of the methods described in any of Clauses 1 to 36.

[0345] Clause 38: A computer program product including a computer program, wherein the computer program, when executed by a computer, implements any of the methods described in any of Clauses 1 to 36.

[0346] Clause 39: A method for characterizing a quantum processor comprising a plurality of qubits, comprising applying a characterization protocol to a qubit patch comprising a subset of qubits, wherein the characterization protocol comprises reducing patching errors resulting from interactions between qubits inside the qubit patch and qubits outside the qubit patch.

[0347] Clause 40: This includes applying the characterization protocol sequentially to multiple patches, as described in Clause 39.

[0348] Clause 41: As described in Clause 40, the multiple patches together cover multiple qubits of the quantum processor.

[0349] Clause 42: As described in Clause 40 or 41, at least some of the patches in question are duplicates.

[0350] Clause 43: As set out in any of Clauses 39-42, the characterization protocol includes applying an adjacent gate sequence to adjacent qubits outside a qubit patch and interacting with the qubit patch, wherein the adjacent gate sequence is configured to reduce the sensitivity of the measurement results to execution errors related to qubits outside the qubit patch.

[0351] Clause 44: As set out in any of Clauses 39-43, the characterization gate sequence in the characterization protocol is configured to provide measurement results that are both sensitive to execution errors within the patch and have reduced sensitivity to execution errors relating to qubits outside the patch.

[0352] Clause 45: As set out in any of Clauses 1-36 or Clauses 39-44, a quantum processor is described in terms of quantum dits instead of qubits.

[0353] Clause 46: A quantum circuit for use in characterizing the execution error in a set of quantum logic operations of a quantum processor, wherein the set of quantum operations acts on a subset of qubits that define a qubit patch, and the execution error related to the qubit patch is modeled by a model that includes a plurality of model parameters, and the quantum circuit is - A characterization gate sequence applicable to the qubit patch configured to provide measurement results sensitive to at least some of the model parameters, A quantum circuit comprising: an adjacent gate sequence applicable to at least several adjacent qubits interacting with a qubit patch, wherein the adjacent gate sequence is configured to reduce the sensitivity of the measurement result to execution errors related to environment qubits outside the qubit patch.

[0354] Clause 47: As described in Clause 46, the characterization gate sequence is a gate set tomography gate sequence.

[0355] Clause 48: As described in Clause 46 or 47, an adjacent gate sequence includes initializing adjacent qubits in a neighboring mixed state.

[0356] Clause 49: As set out in any of Clauses 46-48, the adjacent gate sequence includes a dynamic decoupling sequence configured to reduce patching errors.

[0357] Clause 50: As set out in any of Clauses 46-49, an adjacent gate sequence includes randomly selected adjacent gates.

[0358] Clause 51: A system comprising a computer and a quantum processor, wherein the computer has gate-level or pulse-level access to the quantum processor, and the system is configured to implement any method described in any of Clauses 1 to 36 or Clauses 39 to 45.

Claims

1. A computer-based method for characterizing execution errors in a set of quantum logic operations of a quantum processor, wherein the set of quantum logic operations acts on a subset of qubits that define a qubit patch, and the execution errors related to the qubit patch are modeled by a model that includes a plurality of model parameters, and the method (a) The quantum processor is provided with a set of quantum circuits, wherein at least some of the quantum circuits are i) A characterization gate sequence applicable to the qubit patch configured to provide measurement results sensitive to at least some of the model parameters, wherein the statistical error of at least some of the model parameters is smaller than the estimated maximum execution error predicted on the quantum processor, ii) Applying a set of quantum circuits, which includes an adjacent gate sequence applicable to and interacting with at least some adjacent qubits outside the qubit patch, wherein the adjacent gate sequence is configured to reduce the sensitivity of the measurement result to execution errors related to the environment qubits outside the qubit patch. (b) Using the measurement device of the quantum processor, measure a subset of the qubits that define the qubit patch, (c) Repeat (a) to (b) to collect the measurement results and the set of frequencies associated with the quantum circuit, (d) A method comprising: fitting the model to the set of frequencies to calculate the values ​​of the model parameters.

2. The method according to claim 1, wherein the characteristic evaluation gate sequence is a gate set tomography sequence, and the method further includes gauge optimization.

3. The method according to claim 1, wherein the adjacent gate sequence includes initializing the environment qubit in a neighboring mixed state, and the reduced density operator of each adjacent qubit is proportional to the unit operator.

4. The aforementioned neighboring mixing state is an even-numbered mixing. [Math 1] The method according to claim 3, wherein m and n are the number of environments and neighboring qubits, respectively.

5. The method according to claim 1, wherein the set of quantum circuits is composed of quantum circuit clusters, each consisting of two quantum circuits having the same characterization gate sequence and a first neighbor gate sequence beginning with an idle gate and a second neighbor sequence beginning with a π rotation, and both the first and second neighbor gate sequences are applied to each neighboring qubit, and the method further comprises averaging the frequencies collected on the two quantum circuits of each quantum circuit cluster.

6. The method according to claim 1, wherein the adjacent gate sequence is configured to reduce patching errors.

7. The method according to claim 6, wherein the patching error is estimated using a perturbation expansion, and the adjacent gate sequence is configured to cancel out or reduce to at least the second order of the highest order in the perturbation expansion.

8. The method according to claim 6, wherein at least one of the quantum circuits includes an adjacent gate sequence that includes a dynamic decoupling sequence configured to reduce patching errors.

9. The method according to claim 8, wherein the dynamic decoupling sequence is matched with the characterization gate sequence of the at least one quantum circuit such that at least some gates of the dynamic decoupling sequence are applied synchronously with at least some gates of the characterization gate sequence of the at least one quantum circuit, or at least some gates of the dynamic decoupling sequence are applied sequentially with at least some gates of the characterization gate sequence of the at least one quantum circuit.

10. The method according to claim 1, wherein at least one of the quantum circuits further includes a context gate sequence applicable to one or more environment qubits outside the qubit patch, and the context gates of the context gate sequence are synchronously applied to at least some of the characterization gates of the characterization gate sequence of the at least one quantum circuit.

11. The method according to claim 1, wherein the quantum processor is described in terms of quantum dits instead of qubits.

12. A method performed by a computer for characterizing a quantum processor, comprising applying sequentially to a plurality of patches of qubits of the quantum processor the method according to any one of claims 1 to 10.

13. A method for characterizing a quantum processor comprising multiple qubits, comprising applying a characterization protocol to a qubit patch comprising a subset of qubits, wherein the characterization protocol includes reducing patching errors caused by interactions between qubits inside the qubit patch and qubits outside the qubit patch, The method comprises applying the characterization protocol sequentially to a plurality of patches, wherein the characterization protocol comprises applying an adjacent gate sequence to adjacent qubits outside the qubit patch and interacting with the qubit patch, wherein the adjacent gate sequence is configured to reduce the sensitivity of the measurement result to execution errors related to the qubits outside the qubit patch.

14. A non-temporary computer-readable storage medium for storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 9 or claim 13.

15. A system comprising a computer and a quantum processor, wherein the computer has gate-level or pulse-level access to the quantum processor, and the system is configured to perform the method according to any one of claims 1 to 9 or claim 13.

16. A quantum circuit for use in characterizing execution errors in a set of quantum logic operations of a quantum processor, wherein the set of quantum operations acts on a subset of qubits that define a qubit patch, and the execution errors related to the qubit patch are modeled by a model that includes a plurality of model parameters, and the quantum circuit - A characterization gate sequence applicable to the qubit patch configured to provide measurement results sensitive to at least some of the model parameters, A quantum circuit comprising: an adjacent gate sequence applicable to at least several adjacent qubits interacting with the qubit patch, wherein the adjacent gate sequence is configured to reduce the sensitivity of the measurement result to execution errors related to environment qubits outside the qubit patch.

17. The quantum circuit according to claim 16, wherein the adjacent gate sequence includes initializing the adjacent qubits in a neighboring mixed state, and the adjacent gate sequence includes a dynamic decoupling sequence configured to reduce patching errors.

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