Systems and techniques for microphone array calibration

Abstract

Disclosed herein are systems and techniques for microphone array calibration, as well as communication systems that can use calibrated microphones. The systems and techniques disclosed herein can provide both phase and magnitude calibration of microphone arrays, improving performance for beamforming and other applications. Additionally, various systems and methods are disclosed herein for local storage of calibration coefficients to microphone arrays (e.g., at the time of manufacture and calibration). Furthermore, various systems and methods disclosed herein can include central application of calibration of microphone arrays (e.g., in an edge processor during operation), replacing uncalibrated microphone signals with calibrated microphone signals further down the signal chain.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefit and priority of U.S. Provisional Application No. 63 / 112,967, titled "Systems and Techniques for Microphone Array Calibration," which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to systems and devices in a daisy-chained network. [Background technology]

[0003] As electronic components become smaller and performance expectations increase, devices that previously had no components, or had few components, now contain more. In some settings, the communication infrastructure used to exchange signals between such components (for example, in a vehicle) has required thick, heavy bundles of cables.

[0004] This disclosure is intended to provide an overview of the subject matter of this patent application. It is not intended to provide an exclusive or thorough description of the invention. Further limitations and shortcomings of prior and traditional approaches will become apparent to those skilled in the art by comparing such systems with some aspects of the invention, as described hereafter in this application with reference to the drawings. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] This specification discloses systems and techniques for microphone array calibration, as well as communication systems in which calibrated microphones may be used. When a microphone array is used for beamforming (e.g., for noise reduction), manufacturing tolerances between different microphones in the array can cause performance degradation of certain beamforming algorithms. Generally, once microphones are distributed and / or installed, further calibration is not possible. Systems and methods for storing calibration coefficients in microphones for use during microphone operation are disclosed. [Means for solving the problem]

[0006] According to one embodiment, a system for microphone array calibration includes a loudspeaker configured to reproduce a test signal; a microphone array configured to receive a test signal and generate a plurality of microphone array signals; a reference microphone positioned between the loudspeaker and the microphone array, configured to receive a test signal and generate a reference signal; and a calibration computer configured to process the plurality of microphone array signals and the reference signal, generate a set of filter coefficients, and transmit the set of filter coefficients to the microphone array.

[0007] In some embodiments, the system further comprises memory associated with a microphone array configured to store a set of filter coefficients. In some embodiments, the memory is located on a microphone array module together with the microphone array. In some embodiments, the memory is cloud-based memory accessible by the microphone array. In some embodiments, the memory is further configured to store microphone information, including at least one of vendor information, product information, version information, model information, capability information, serial number, manufacturing information, configuration information, routing information, and certification information.

[0008] According to some embodiments, the system further comprises a plurality of memory modules, and each of the plurality of memory modules is associated with a respective microphone of the microphone array. In some embodiments, the filter coefficients include phase calibration, frequency calibration, and magnitude calibration. In some embodiments, the system further comprises a two-wire interface, and the transmission of the filter coefficients to the microphone array occurs via the two-wire interface. In some embodiments, each of the plurality of microphone array signals is unique, and each respective microphone of the microphone array is associated with a respective subset of the set of filter coefficients.

[0009] According to another aspect, a method for microphone array calibration includes playing a test signal on a loudspeaker, sampling the test signal with the microphone array, generating a plurality of microphone array signals with the microphone array, sampling the test signal with a reference microphone, generating a reference signal with the reference microphone, generating a set of filter coefficients based on the plurality of microphone array signals and the reference signal, and transmitting the set of filter coefficients to the microphone array.

[0010] According to some embodiments, sampling a test signal with a microphone array includes sampling the test signal with each respective microphone of the microphone array. In some embodiments, generating a set of filter coefficients includes generating a respective subset of filter coefficients for each respective microphone. According to some embodiments, the method further includes storing each respective subset of filter coefficients in each respective microphone. According to some embodiments, the method further includes storing a set of filter coefficients on the microphone array. In some embodiments, transmitting a set of filter coefficients includes transmitting the set of filter coefficients via a two-wire bus. According to some embodiments, the method further includes pre-calibrating a loudspeaker using a reference microphone.

[0011] According to another aspect, a self-calibrating microphone system includes a microphone module including a microphone configured to receive an audio input signal and output a raw microphone output signal, the microphone being pre-calibrated, and a non-volatile memory configured to store microphone calibration coefficients of the microphone, a processor configured to receive the raw microphone signal and the microphone calibration coefficients and generate a calibrated microphone signal, and a microphone signal sink configured to receive the calibrated microphone signal from the processor and output the calibrated microphone signal.

[0012] According to some embodiments, the filter coefficients are configured to provide at least one of phase calibration, frequency calibration, and magnitude calibration. In some embodiments, the system further includes a two-wire bus, and the processor and the microphone signal sink communicate via the two-wire bus. In some embodiments, the processor is further configured to perform a convolution of the raw microphone signal and the microphone calibration coefficients to generate the calibrated microphone signal. [Brief explanation of the drawing]

[0013] This disclosure is best understood from the following detailed description in conjunction with the accompanying drawings. In accordance with standard industry practice, it is emphasized that various features are not necessarily drawn to scale and are used for illustrative purposes only. Where a scale is explicitly or implicitly indicated, only an illustrative example is provided. In other embodiments, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. For the sake of this explanation, similar reference numerals designate similar structural elements. Embodiments are illustrated as examples in the drawings of the accompanying drawings and are not limiting.

[0014] To better understand the nature and advantages of the present invention, the following detailed description of preferred embodiments is to be referenced in relation to the following accompanying drawings.

[0015] [Figure 1] Figure 1 is a block diagram of an exemplary two-wire communication system according to various embodiments. [Figure 2] Figure 2 is a block diagram of node transceivers that may be included in the nodes of the system in Figure 1, according to various embodiments. [Figure 3] Figure 3 shows a portion of a synchronous control frame used for communication within the system of Figure 1, according to various embodiments. [Figure 4] Figure 4 shows superframes used for communication within the system of Figure 1 in various embodiments. [Figure 5] Figure 5 illustrates exemplary formats for synchronous control frames in different operating modes of the system of Figure 1, according to various embodiments. [Figure 6] Figure 6 illustrates exemplary formats for synchronous response frames in different operating modes of the system of Figure 1, according to various embodiments. [Figure 7] Figure 7 is a block diagram of various components of the bus protocol circuit of Figure 2, according to various embodiments. [Figure 8] Figures 8-11 illustrate examples of information exchange along a two-wire bus according to various embodiments of the bus protocol described herein. [Figure 9] Figures 8-11 illustrate examples of information exchange along a two-wire bus according to various embodiments of the bus protocol described herein. [Figure 10] Figures 8-11 illustrate examples of information exchange along a two-wire bus according to various embodiments of the bus protocol described herein. [Figure 11] Figures 8-11 illustrate examples of information exchange along a two-wire bus according to various embodiments of the bus protocol described herein. [Figure 12] Figure 12 illustrates ring topologies of a two-wire bus and unidirectional communication schemes on the bus according to various embodiments. [Figure 13] Figure 13 is a block diagram of devices that can function as nodes or hosts in the system of Figure 1, according to various embodiments. [Figure 14] Figure 14 is a block diagram of a microphone array calibration system according to various embodiments. [Figure 15] Figures 15-17 are flowcharts of methods for microphone array calibration according to various embodiments. [Figure 16] Figures 15-17 are flowcharts of methods for microphone array calibration according to various embodiments. [Figure 17] Figures 15-17 are flowcharts of methods for microphone array calibration according to various embodiments. [Figure 18] Figure 18 is a block diagram of a microphone system to which the calibrations disclosed herein can be applied in various embodiments. [Figure 19] Figure 19 is a flowchart illustrating a method for applying microphone array calibration according to various embodiments. [Figure 20]Figure 20 is a block diagram of a two-wire communication system to which the microphone array calibration disclosed herein may be applied in various embodiments. [Figure 21] Figures 21-22 are flowcharts illustrating various embodiments of methods for calibrating microphones and applying microphone array calibration, respectively. [Figure 22] Figures 21-22 are flowcharts illustrating various embodiments of methods for calibrating microphones and applying microphone array calibration, respectively. [Modes for carrying out the invention]

[0016] This specification discloses systems and techniques for microphone array calibration, as well as communication systems in which calibrated microphones may be used. When a microphone array is used for beamforming (e.g., as part of road noise reduction, other noise reduction, or selective broadcast applications), manufacturing tolerances between different microphones in the array can cause performance degradation of certain beamforming algorithms. Some conventional calibration procedures attempt to address this degradation by generating filter coefficients for the microphones to equalize the magnitude of differences in the frequency response of the microphones. However, conventional calibration procedures fail to consider the effects of phase tolerances across the microphones in the array.

[0017] The systems and techniques disclosed herein can provide both phase and magnitude calibration of microphone arrays, improving beamforming and other application performance. Furthermore, various systems and methods for local storage of calibration coefficients to microphone arrays (e.g., at the time of manufacture and calibration) are disclosed herein. Moreover, the various systems and methods disclosed herein include central application of microphone array calibration (e.g., within an edge processor during operation) where uncalibrated microphone signals can be replaced with calibrated microphone signals below the signal chain. Any of the microphone array calibration systems and methods disclosed herein may be implemented by a communication system disclosed herein (e.g., system 100).

[0018] In the following detailed description, references are made to the accompanying drawings that form part of this specification, similar figures throughout designate similar parts, and examples of possible embodiments are shown. It should be understood that other embodiments may be utilized and structural or logical modifications may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as restrictive.

[0019] Various operations may be described sequentially as multiple distinct actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as meaning that these operations necessarily depend on the order. In particular, these operations may not be performed in the order presented. The operations described may be performed in a different order than in the described embodiments. Various additional operations may be performed, and / or the operations described may be omitted in additional embodiments.

[0020] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0021] In this specification, various components may be referred to or exemplified in the singular (e.g., "a processor," "a peripheral device"), but this is merely for the sake of simplification of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0022] In this description, the phrases “in an embodiment” or “in embodiments” may refer to one or more of the same or different embodiments, respectively. Furthermore, as used in reference to embodiments of this disclosure, terms such as “comprising,” “including,” and “having” are synonymous. As used herein, the term “circuit” may mean, part of, or include, application-specific integrated circuits (ASICs), electronic circuits, and optical circuits, (shared, dedicated, or group) processors and / or (shared, dedicated, or group) memory running one or more software or firmware programs, combinational logic circuits providing the functions described, and / or other suitable hardware.

[0023] Figure 1 is a block diagram of an exemplary half-duplex two-wire communication system 100 in various embodiments. The system 100 includes a host 110, a main node 102-1, and at least one subnode 102-2. Three subnodes (0, 1, and 2) are illustrated in Figure 1. The depiction of the three subnodes 102-2 in Figure 1 is simply illustrative, and the system 100 may include one, two, or more subnodes 102-2 as desired.

[0024] Main node 102-1 can communicate with subnode 102-2 via a two-wire bus 106. Bus 106 may include different two-wire bus links between adjacent nodes along bus 106 to connect nodes along bus 106 in a daisy-chain configuration. For example, as shown in Figure 1, bus 106 may include a link connecting main node 102-1 to subnode 0, a link connecting subnode 0 to subnode 1, and a link connecting subnode 1 to subnode 2. In some embodiments, each link of bus 106 may be formed from a single stranded pair (e.g., an unshielded twisted pair). In some embodiments, each link of bus 106 may be formed from a coaxial cable (e.g., having a core providing a “positive” line and a shield providing a “negative” line, or vice versa). The two-wire bus links also provide a complete electrical path (e.g., a forward current path and a return current path) so as not to require the use of additional grounding or voltage source lines.

[0025] The host 110 may include a processor that programs the main node 102-1 and acts as both the sender and receiver of various payloads transmitted along the bus 106. In some embodiments, the host 110 may be, or include, a microcontroller, for example. Specifically, the host 110 may be the master of inter-integrated sound (I2S) communication occurring along the bus 106. The host 110 may communicate with the main node 102-1 via the I2S / Time Division Multiplexing (TDM) protocol, the Serial Peripheral Interface (SPI) protocol, and / or Inter-Integrated Circuit (I2C) protocol. In some embodiments, the main node 102-1 may be a transceiver (e.g., a node transceiver 120, discussed below with reference to Figure 2) located within the same housing as the host 110. The main node 102-1 may be programmable by the host 110 via the I2C bus for configuration and readability and may be configured to generate the clock, synchronization, and framing for all subnodes 102-2. In some embodiments, an extension of the I2C control bus between the host 110 and the main node 102-1 may be embedded in the data stream transmitted via bus 106, allowing the host 110 to directly access registers and status information for one or more subnodes 102-2, and enabling long-range I2C-to-I2C communication to allow the host 110 to control peripheral devices 108. In some embodiments, an extension of the SPI control bus between the host 110 and the main node 102-1 may be embedded in the data stream transmitted via bus 106, allowing the host 110 to directly access registers and status information for one or more subnodes 102-2, and enabling long-range SPI-to-SPI or SPI-to-I2C communication to allow the host 110 to control peripheral devices 108. In embodiments where the system 100 is included in a vehicle, the host 110 and / or the main node 102-1 may be included in the vehicle's headend.

[0026] Main node 102-1 may generate “downstream” signals (e.g., data signals, power signals, etc., transmitted away from main node 102-1 along bus 106) and may receive “upstream” signals (e.g., transmitted towards main node 102-1 along bus 106). Main node 102-1 may provide a clock signal for synchronous data transmission via bus 106. As used herein, “synchronous data” may include data (e.g., audio signals) that is streamed continuously at regular time intervals between two consecutive transmissions to / from the same node along bus 106. In some embodiments, the clock signal provided by main node 102-1 may be derived from an I2S input provided to main node 102-1 by host 110. Subnode 102-2 may be an addressable network connection point representing a possible destination for data frames transmitted downstream or upstream on bus 106. Subnode 102-2 may also represent a possible source for downstream or upstream data frames. System 100 may enable control information and other data to be transmitted bidirectionally from one node to the next via bus 106. One or more of the subnodes 102-2 may also be powered by signals transmitted via bus 106.

[0027] Specifically, each of the main node 102-1 and subnode 102-2 may include a positive upstream terminal (indicated as "AP"), a negative upstream terminal (indicated as "AN"), a positive downstream terminal (indicated as "BP"), and a negative downstream terminal (indicated as "BN"). The positive and negative downstream terminals of a node may be coupled to the positive and negative upstream terminals of adjacent downstream nodes, respectively. As shown in Figure 1, the main node 102-1 may include a positive and negative upstream terminal, but these terminals may not be used, and in other embodiments, the main node 102-1 may not include a positive and negative upstream terminal. The last subnode 102-2 along the bus 106 (subnode 2 in Figure 1) may include a positive and negative downstream terminal, but these terminals may not be used, and in other embodiments, the last subnode 102-2 along the bus may not include a positive and negative downstream terminal.

[0028] As will be discussed in detail below, the main node 102-1 may optionally periodically send synchronous control frames downstream along with data destined for one or more of the subnodes 102-2. For example, the main node 102-1 may send synchronous control frames at a frequency of 48 kHz every 1024 bits (representing a superframe), resulting in an effective bitrate of 49.152 Mbps on bus 106. Other rates may be supported, including, for example, 44.1 kHz. The synchronous control frames may enable the subnodes 102-2 to identify the beginning of each superframe, and, in combination with physical layer coding / signaling, may enable each subnode 102-2 to derive its internal operating clock from bus 106. The synchronous control frame may include a preamble for signaling the start of synchronization, as well as control fields enabling various addressing modes (e.g., normal, broadcast, discovery), configuration information (e.g., writing to registers on subnode 102-2), transmission of I2C information, transmission of SPI information, remote control of specific general-purpose input / output (GPIO) pins on subnode 102-2, and other services. Parts of the synchronous control frame following the preamble and payload data may be scrambled to reduce the likelihood of information within the synchronous control frame being mistaken for a new preamble and to flatten the spectrum of associated electromagnetic radiation.

[0029] The synchronous control frame may pass through subnodes 102-2 (along with other data that may optionally come from the main node 102-1, but additionally or alternatively from one or more upstream subnodes 102-2, or from subnode 102-2 itself) until it reaches the last subnode 102-2 (i.e., subnode 2 in Figure 1), which is configured by the main node 102-1 as the last subnode 102-2, or which has self-identified itself as the last subnode 102-2. Upon receiving the synchronous control frame, the last subnode 102-2 may transmit a synchronous response frame, followed by any data that it is permitted to transmit (e.g., a 24-bit audio sample within a specified time slot). The synchronous response frame may be passed upstream between subnodes 102-2 (optionally, along with data from downstream subnodes 102-2), and based on the synchronous response frame, each subnode 102-2 may be able to identify the time slot, if any, that subnode 102-2 is permitted to transmit.

[0030] In some embodiments, one or more of the subnodes 102-2 in system 100 may be coupled to and communicate with a peripheral device 108. For example, a subnode 102-2 may be configured to read data from and / or write data to an associated peripheral device 108 using the I2S protocol, pulse density modulation (PDM) protocol, TDM protocol, SPI protocol, and / or I2C protocol, as discussed below. In this specification, “peripheral device 108” may be referred to in the singular form, but this is simply for the sake of discussion, and a single subnode 102-2 may be coupled to zero, one, or two or more peripheral devices. Examples of peripheral devices that may be included in peripheral device 108 include digital signal processors (DSPs), field-programmable gate arrays (FPGAs), ASICs, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), codecs, microphones, microphone arrays, speakers, audio amplifiers, protocol analyzers, accelerometers or other motion sensors, environmental condition sensors (e.g., temperature sensors, humidity sensors, and / or gas sensors), wired or wireless communication transceivers, display devices (e.g., touchscreen displays), user interface components (e.g., buttons, dials, or other control keys), cameras (e.g., video cameras), memory devices, or any other suitable devices for transmitting and / or receiving data. Several examples of different peripheral device configurations will be discussed in detail herein.

[0031] In some embodiments, peripheral device 108 may include any device configured for I2S communication, and peripheral device 108 may communicate with associated subnode 102-2 via the I2S protocol. In some embodiments, peripheral device 108 may include any device configured for I2C communication, and peripheral device 108 may communicate with associated subnode 102-2 via the I2C protocol. In some embodiments, peripheral device 108 may include any device configured for SPI communication, and peripheral device 108 may communicate with associated subnode 102-2 via the SPI protocol. In some embodiments, subnode 102-2 may not be coupled to any peripheral device 108.

[0032] Subnodes 102-2 and their associated peripheral devices 108 may be housed in separate housings, coupled via wired or wireless communication connections, or housed in a common housing. For example, a speaker connected as a peripheral device 108 may be packaged together with the hardware for the associated subnode 102-2 (e.g., a node transceiver 120, discussed below with reference to Figure 2) so that the hardware for the associated subnode 102-2 is housed in a housing that also contains other speaker components. The same may apply to any type of peripheral device 108.

[0033] As discussed above, host 110 can communicate with and control main node 102-1 using multi-channel I2S communication protocols, SPI communication protocols, and / or I2C communication protocols. For example, host 110 can send data via I2S to a frame buffer (not shown) in main node 102-1, and main node 102-1 can read data from the frame buffer and send the data along bus 106. Similarly, main node 102-1 can store data received via bus 106 in a frame buffer and then send the data to host 110 via I2S.

[0034] Each subnode 102-2 may have internal control registers, which may be configured by communication from the main node 102-1. Some such registers will be discussed in detail below. Each subnode 102-2 may receive downstream data and retransmit data further downstream. Each subnode 102-2 may receive and / or generate upstream data, and / or retransmit data upstream, and / or add data to upstream transactions.

[0035] Communication along bus 106 may occur in periodic superframes. Each superframe may begin with a downstream synchronous control frame, be divided into a downstream transmission period (also called the “downstream portion”), an upstream transmission period (also called the “upstream portion”), and a no-transmission period (when bus 106 is not driven), and may end immediately before the transmission of another downstream synchronous control frame. Main node 102-1 may be programmed (by host 110) with some downstream portions for transmitting to one or more of the subnodes 102-2, and some upstream portions for receiving from one or more of the subnodes 102-2. Each subnode 102-2 may be programmed (by main node 102-1) with some downstream portions for retransmitting down bus 106, some downstream portions for consumption, some upstream portions for retransmitting up bus 106, and some upstream portions from which the subnode 102-2 may transmit data received from the subnode 102-2 from its associated peripheral device 108. Communication along bus 106 will be discussed in more detail below with reference to Figures 2 to 12.

[0036] Embodiments of the communication system 100 disclosed herein are unique among conventional communication systems in that all subnodes 102-2 can receive output data via bus 106 within the same superframe (for example, all subnodes 102-2 can receive the same voice sample without sample delay between nodes 102). In conventional communication systems, data is buffered and processed within each node before being passed downstream to the next node in the next frame. As a result, in these conventional communication systems, the data transmission latency depends on the number of nodes (each node adds a delay of one voice sample). In the communication system 100 disclosed herein, bus 106 can add only one cycle of latency, regardless of whether the data is received by the first subnode or the last subnode 102-2. The same applies to upstream communication, where data may be available to the upstream node 102 in the next superframe, regardless of which subnode 102-2 provided the data.

[0037] Furthermore, in embodiments of the communication system 100 disclosed herein, downstream data (e.g., downstream voice data) may be carried on bus 106 by the main node 102-1 or by any of the subnodes 102-2 upstream of the receiving subnode 102-2, and similarly, upstream data (e.g., upstream voice data) may be carried on bus 106 by any of the subnodes 102-2 downstream of the receiving node 102 (i.e., the main node 102-1 or subnode 102-2). Such capability allows a subnode 102-2 to provide both upstream and downstream data at a specific time (e.g., a specific voice sample time). In the case of voice data, this data can be received at the next voice sample of any downstream node 102 or upstream node 102 without further delay (other than the slight delay that enters the superframe boundary). As will be further discussed herein, a control message (e.g., in a synchronous control frame (SCF)) may be moved to the last node 102 (addressing a specific node 102 or broadcast), and an upstream response (e.g., in a synchronous response frame (SRF)) may be created by the last downstream node 102 within the same superframe. Node 102 addressed by the SCF modifies the contents of the upstream SRF in its response. As a result, control and response can be fully performed across multiple nodes 102 within the same voice sample. This also contrasts with conventional communication systems where sample latency occurs between nodes (for relaying messages from one node to another).

[0038] Each of the main node 102-1 and subnode 102-2 may include a transceiver for managing communication between components of system 100. Figure 2 is a block diagram of a node transceiver 120 that may be included in a node of system 100 in Figure 1 (e.g., main node 102-1 or subnode 102-2) according to various embodiments. In some embodiments, the node transceiver 120 may be included in each of the nodes of system 100, and control signals may be provided to the node transceiver 120 via the main pin to indicate whether the node transceiver 120 is functioning as a main node (e.g., when the main pin is high) or as a subnode (e.g., when the main pin is low).

[0039] The node transceiver 120 may include an upstream differential signal (DS) transceiver 122 and a downstream DS transceiver 124. The upstream DS transceiver 122 may be coupled to the positive upstream terminal and the negative upstream terminal discussed above with reference to Figure 1, and the downstream DS transceiver 124 may be coupled to the positive downstream terminal and the negative downstream terminal discussed above with reference to Figure 1. In some embodiments, the upstream DS transceiver 122 may be a low-voltage DS (LVDS) transceiver, and the downstream DS transceiver 124 may be an LVDS transceiver. Each node of system 100 may be AC ​​coupled to bus 106, and data signals may be transmitted along bus 106 (e.g., via upstream DS transceiver 122 and / or downstream DS transceiver 124) using a predetermined form of DS (e.g., LVDS or multipoint LVDS (MLVDS) or similar signal transmission) with appropriate encoding (e.g., differential Manchester coding, two-phase mark coding, Manchester coding, non-zero return, non-zero return inversion with run length limiting (NRZI) coding, or any other suitable coding) to provide timing information via bus 106.

[0040] The upstream DS transceiver 122 and the downstream DS transceiver 124 can communicate with the bus protocol circuit 126, which in turn can communicate with the phase-locked loop (PLL) 128 and the voltage regulator circuit 130, among other components. When the node transceiver 120 is powered on, the voltage regulator circuit 130 can raise a "good power" signal, which is used by the PLL 128 as a power-on reset.

[0041] As described above, one or more of the subnodes 102-2 of system 100 may receive power transmitted via bus 106 simultaneously with data. (Some of the subnodes 102-2 may be configured to have local power supplies provided exclusively for them, so this is optional.) For power distribution, main node 102-1 may DC bias the bus link between main node 102-1 and subnode 0 by (for example, by connecting one of its downstream terminals to a voltage source provided by a voltage regulator through a low-pass filter and grounding the other downstream terminal.) The DC bias may be a predetermined voltage, such as 5 volts, 8 volts, the voltage of a car battery, or a higher voltage. Each consecutive subnode 102-2 may selectively tap its upstream bus link to recover power (for example, using a voltage regulator circuit 130). This power can be used to power subnode 102-2 itself (and optionally, one or more peripheral devices 108 coupled to subnode 102-2). Subnode 102-2 may also selectively bias the downstream bus links for the next subnode 102-2 in the following order with power recovered from either the upstream bus link or the local power supply. For example, subnode 0 may use a DC bias on the upstream link of bus 106 to recover power for subnode 0 itself and / or one or more associated peripheral devices 108, and / or subnode 0 may recover power from the upstream link of bus 106 in order to bias the downstream links of bus 106.

[0042] Therefore, in some embodiments, each node of system 100 may supply power to the next downstream node via a downstream bus link. Powering of nodes may be performed sequentially. For example, after discovering and configuring subnode 0 via bus 106, main node 102-1 may instruct subnode 0 to supply power to its downstream link of bus 106 in order to power subnode 1, and after subnode 1 is discovered and configured, main node 102-1 may instruct subnode 1 to supply power to its downstream link of bus 106 in order to power subnode 2 (and similarly for additional subnodes 102-2 coupled to bus 106). In some embodiments, one or more of the subnodes 102-2 may be powered locally instead of, or in addition to, being powered from their upstream bus link. In some such embodiments, a local power source for a given subnode 102-2 may be used to power one or more downstream subnodes.

[0043] In some embodiments, the upstream bus interface circuit 132 may be located between the upstream DS transceiver 122 and the voltage regulator circuit 130, and the downstream bus interface circuit 131 may be located between the downstream DS transceiver 124 and the voltage regulator circuit 130. Since each link of the bus 106 can carry AC (signal) and DC (power) components, the upstream bus interface circuit 132 and the downstream bus interface circuit 131 can separate the AC and DC components, providing the AC components to the upstream DS transceiver 122 and the downstream DS transceiver 124, and the DC components to the voltage regulator circuit 130. The line-side AC coupling of the upstream DS transceiver 122 and the downstream DS transceiver 124 substantially isolates the transceivers 122 and 124 from the DC components on the line in order to enable high-speed bidirectional communication. As discussed above, the DC component may be tapped for power supply, and the upstream bus interface circuit 132 and the downstream bus interface circuit 131 may include, for example, ferrite, common-mode choke, or inductor to reduce the AC component supplied to the voltage regulator circuit 130. In some embodiments, the upstream bus interface circuit 132 may be included in the upstream DS transceiver 122 and / or the downstream bus interface circuit 131 may be included in the downstream DS transceiver 124, and in other embodiments, the filtering circuit may be outside the transceivers 122 and 124.

[0044] The node transceiver 120 may include transceivers 127 for I2S, TDM, and PDM communication between the node transceiver 120 and the external device 155. While “external device 155” may be referred to in the singular form in this specification, this is merely for illustrative purposes, and multiple external devices may communicate with the node transceiver 120 via the I2S / TDM / PDM transceiver 127. As is well known in the art, the I2S protocol is for carrying pulse code modulation (PCM) information (e.g., between audio chips on a printed circuit board (PCB)). As used herein, “I2S / TDM” may refer to the extension of I2S stereo (2-channel) content to multiple channels using TDM. As is well known in the art, PDM may be used in sigma-delta converters, specifically, the PDM format may represent an oversampled 1-bit sigma-delta ADC signal before decimation. The PDM format is often used as the output format for digital microphones. The I2S / TDM / PDM transceiver 127 can communicate with the bus protocol circuit 126 and pins for communication with an external device 155. Six pins (BCLK, SYNC, DTX[1:0], and DRX[1:0]) are shown in Figure 2, where the BCLK pin may be used for the I2S bit clock, the SYNC pin may be used for the I2S frame synchronization signal, and the DTX[1:0] and DRX[1:0] pins are used for the transmit data channel and the receive data channel, respectively. Two transmit pins (DTX[1:0]) and two receive pins (DRX[1:0]) are shown in Figure 2, but any desired number of receive and / or transmit pins may be used.

[0045] If node transceiver 120 is included in main node 102-1, external device 155 may include host 110, and I2S / TDM / PDM transceiver 127 may provide an I2S slave (for BCLK and SYNC) that can receive data from host 110 and send data to host 110 in synchronization with host 110's I2S interface clock. Specifically, the I2S frame synchronization signal may be received on the SYNC pin as input from host 110, and PLL 128 may use that signal to generate a clock. If node transceiver 120 is included in subnode 102-2, external device 155 may include one or more peripheral devices 108, and I2S / TDM / PDM transceiver 127 may provide an I2S clock master (for BCLK and SYNC) that can control I2S communication with peripheral devices 108. Specifically, the I2S / TDM / PDM transceiver 127 may provide an I2S frame synchronization signal as an output on the SYNC pin. The registers of the node transceiver 120 may determine which I2S / TDM channels and how many I2S / TDM channels are being transmitted as data slots via the bus 106. The TDM mode (TDMMODE) register of the node transceiver 120 may store a value for the number of TDM channels that matches between consecutive SYNC pulses on the TDM transmit pin or TDM receive pin. With knowledge of the channel size, the node transceiver 120 may automatically set the BCLK rate to match the number of bits within the sampling time (e.g., 48 kHz).

[0046] The node transceiver 120 may include a transceiver 129 for I2C communication between the node transceiver 120 and an external device 157. While “external device 157” may be referred to in the singular form in this specification, this is merely for illustrative purposes, and multiple external devices may communicate with the node transceiver 120 via the I2C transceiver 129. As is well known in the art, the I2C protocol provides data transfer using clock (SCL) lines and data (SDA) lines. The I2C transceiver 129 may communicate with the bus protocol circuit 126 and pins for communication with the external device 157. Four pins (ADR1, ADR2, SDA, and SCL) are shown in Figure 2. ADR1 and ADR2 may be used to modify the I2C address used by the node transceiver 120 when the node transceiver 120 functions as an I2C slave (for example, when it is included in the main node 102-1), and SDA and SCL are used for the I2C serial data and serial clock signals, respectively. If the node transceiver 120 is included in the main node 102-1, the external device 157 may include the host 110, and the I2C transceiver 129 may provide an I2C slave that can receive programming instructions from the host 110. Specifically, the I2C serial clock signal may be received on the SCL pin as input from the host 110 for register access. If node transceiver 120 is included in subnode 102-2, external device 157 may include peripheral device 108, and I2C transceiver 129 may provide an I2C master to enable the I2C transceiver to program one or more peripheral devices in accordance with instructions provided by host 110 and transmitted to node transceiver 120 via bus 106. Specifically, I2C transceiver 129 may provide an I2C serial clock signal as an output on the SCL pin.

[0047] The node transceiver 120 may include a transceiver 136 for SPI communication between the node transceiver 120 and the external device 138. While “external device 138” is sometimes referred to in the singular form in this specification, this is merely for illustrative purposes, and multiple external devices may communicate with the node transceiver 120 via the SPI transceiver 136. As is well known in the art, the SPI protocol uses a slave selection (SS) data line, a clock (BCLK) data line, a master-out-slave-in (MOSI) data line, and a master-in-slave-out (MISO) data line to provide data transfer, with the pins corresponding to these four lines shown in Figure 2. The SPI transceiver 136 may communicate with the bus protocol circuit 126 and the pins for communication with the external device 138. If node transceiver 120 is included in main node 102-1, external device 138 may include host 110 or another external device, and SPI transceiver 136 may provide an SPI slave capable of receiving and responding to commands from host 110 or other external devices. If node transceiver 120 is included in subnode 102-2, external device 138 may include peripheral device 108, and SPI transceiver 136 may provide an SPI host to enable SPI transceiver 136 to send commands to one or more peripheral devices 108. SPI transceiver 136 may include a read data first-in, first-out (FIFO) buffer and a write data FIFO buffer. The read data FIFO buffer may be used to collect data read from other nodes 102 and can be read by external device 138 when external device 138 sends an appropriate read command. The write data FIFO buffer may be used to collect write data from external device 138 before the write data is sent to another device.

[0048] The node transceiver 120 may include an interrupt request (IRQ) pin that communicates with the bus protocol circuit 126. If the node transceiver 120 is included in the main node 102-1, the bus protocol circuit 126 may provide event-driven interrupt requests to the host 110 via the IRQ pin. If the node transceiver 120 is included in the subnode 102-2 (for example, if the MSTR pin is low), the IRQ pin may function as a GPIO pin with interrupt request capability. The node transceiver 120 may include other pins in addition to those shown in Figure 2 (for example, as discussed below).

[0049] System 100 can operate in one of several different operating modes. Each node on bus 106 may have a register indicating which operating mode is currently enabled. Examples of the various operating modes that can be implemented are described below. In standby operating mode, bus activity is suppressed to enable comprehensive power saving, and the only traffic required is minimal downstream preamble to maintain synchronization of each node's PLL (e.g., PLL128). Reads and writes across bus 106 are not supported in standby operating mode. In discovery operating mode, main node 102-1 may send predetermined signals along bus 106 to await a suitable response to draw the topology of subnodes 102-2 distributed along bus 106. In normal operating mode, full register access to and from subnodes 102-2 may be available, as well as access to peripheral devices 108 via bus 106 and access from peripheral devices 108. The normal mode can be comprehensively configured by host 110, regardless of the presence or absence of synchronous upstream data and synchronous downstream data.

[0050] Figure 3 shows a portion of a synchronous control frame 180 used for communication within system 100 in various embodiments. Specifically, the synchronous control frame 180 may be used for data clock repair and PLL synchronization, as discussed below. As mentioned above, since communication over bus 106 can occur in both directions, the communication may be time-division into a downstream and an upstream portion. In the downstream portion, the synchronous control frame and downstream data may be transmitted from the main node 102-1, while in the upstream portion, the synchronous response frame and upstream data may be transmitted from each of the subnodes 102-2 to the main node 102-1. The synchronous control frame 180 may include a preamble 182 and control data 184. Each subnode 102-2 may be configured to use the preamble 182 of the received synchronous control frame 180 as a time base for input to the PLL 128. To facilitate this, the preamble 182 does not follow the “rules” of valid control data 184, and therefore can be easily distinguished from the control data 184.

[0051] For example, in some embodiments, communication along bus 106 may be encoded using a differential Manchester coding scheme of clock, zero transitions. According to such a coding scheme, each bit time begins with a clock transition. If the data value is zero, the coded signal transitions again in the middle of the bit time. If the data value is 1, the coded signal does not transition again. The preamble 182 shown in Figure 5 may violate the coding protocol (by having clock transitions that do not occur, for example, at the beginning of bit times 5, 7, and 8), meaning that the preamble 182 does not have to match any valid (e.g., correctly coded) pattern for the control data 184. In addition, the preamble 182 cannot be duplicated by taking a valid pattern for the control data 184 and forcing bus 106 high or low for a period of a single bit time or a period of multiple bit times. The preamble 182 shown in Figure 5 is simply illustrative, and the synchronous control frame 180 may include different preambles 182 that may violate the coding used by the control data 184 in any preferred manner.

[0052] The bus protocol circuit 126 may include a differential Manchester decoder circuit that operates on a clock recovered from bus 106 and detects the synchronous control frame 180 and sends a frame synchronous indicator to the PLL 128. In this way, the synchronous control frame 180 can be detected without using the system clock or a faster oversampling clock. As a result, subnode 102-2 can receive the PLL synchronous signal from bus 106 without requiring a crystal clock source in subnode 102-2.

[0053] As described above, communication along bus 106 may occur in periodic superframes. Figure 4 shows superframes 190 in various embodiments. As shown in Figure 6, a superframe may begin with a synchronous control frame 180. When the synchronous control frame 180 is used as a timing source for the PLL 128, the frequency at which superframes are communicated ("superframe frequency") may be the same as the synchronous signal frequency. In some embodiments where voice data is transmitted along bus 106, the superframe frequency may be the same as the voice sampling frequency used in system 100 (e.g., either 48 kHz or 44.1 kHz), but any preferred superframe frequency may be used. Each superframe 190 may be divided into a downstream transmission period 192, an upstream transmission period 194, and a no-transmission period 196 (e.g., when bus 106 is not driven).

[0054] In Figure 4, the superframe 190 is shown in an initial downstream transmission period 192 and a later upstream transmission period 194. The downstream transmission period 192 may include a synchronous control frame 180 and X downstream data slots 198, where X may be zero. Substantially all signals on bus 106 may be line-coded, and synchronous signals may be transmitted downstream from the main node 102-1 to the last subnode 102-2 (e.g., subnode 102-2C) in the form of a synchronous preamble 182 within the synchronous control frame 180, as discussed above. Downstream data, TDM data, and synchronous data may be contained in X downstream data slots 198 after the synchronous control frame 180. The downstream data slots 198 may have equal widths. As discussed above, the PLL 128 may provide a clock that nodes use to time communications over bus 106. In some embodiments where bus 106 is used to transmit audio data, the PLL 128 may operate at a multiple of the audio sampling frequency (for example, 1024 times the audio sampling frequency, resulting in 1024 bit clocks for each superframe).

[0055] The upstream transmission period 194 may include a synchronous response frame 197 and Y upstream data slots 199, where Y may be zero. In some embodiments, each subnode 102-2 may consume a portion of the downstream data slots 198. The last subnode (e.g., subnode 2 in Figure 1) may respond with a synchronous response frame 197 (after a predetermined response time stored in the last subnode's register). Upstream data, TDM data, and synchronous data may be added by each subnode 102-2 to the upstream data slots 199 immediately after the synchronous response frame 197. The upstream data slots 199 may have equal widths. Subnodes 102-2 that are not the last subnode (for example, subnodes 0 and 1 in Figure 1) may replace their own upstream response with the received synchronous response frame 197 if a read of one of their registers is requested in the synchronous control frame 180 of the superframe 190, or if a remote I2C read is requested in the synchronous control frame 180 of the superframe 190.

[0056] As discussed above, the synchronous control frame 180 can initiate each downstream transmission. In some embodiments, the synchronous control frame 180 may be 64 bits long, but any other preferred length may be used. The synchronous control frame 180 may begin with a preamble 182, as described above. In some embodiments, when the synchronous control frame 180 is retransmitted by subnode 102-2 to a downstream subnode 102-2, the preamble 182 may be generated by the transmitting subnode 102-2 rather than being retransmitted.

[0057] The control data 184 of the synchronous control frame 180 may include fields containing data used to control transactions via the bus 106. Examples of these fields are discussed below, and several embodiments are shown in Figure 5. Specifically, Figure 5 shows exemplary formats for the synchronous control frame 180 in normal mode, I2C mode, and discovery mode according to various embodiments. In some embodiments, different preambles 182 or synchronous control frames 180 may all be used in standby mode so that subnodes 102-2 do not need to receive all of the synchronous control frames 180 until a transition to normal mode is sent.

[0058] In some embodiments, the synchronous control frame 180 may include a count (CNT) field. The CNT field may have any preferred length (e.g., 2 bits) and may be increased from the value used in the previous superframe (modulo the field length). Subnode 102-2 that receives an unexpected CNT value may be programmed to return an interrupt.

[0059] In some embodiments, the synchronization control frame 180 may include a node addressing (NAM) field. The NAM field may have any preferred length (e.g., 2 bits) and may be used to control access to the registers of subnodes 102-2 via bus 106. In normal mode, the registers of subnodes 102-2 may be read and / or written based on the ID of subnode 102-2 and the address of the register. A broadcast transaction is a write that all subnodes 102-2 should undertake. In some embodiments, the NAM field may provide four node addressing modes, including “None” (e.g., data not addressed to any particular subnode 102-2), “Normal” (e.g., a data unicast to a specific subnode 102-2 identified in the address field discussed below), “Broadcast” (e.g., addressed to all subnodes 102-2), and “Discovery.”

[0060] In some embodiments, the synchronous control frame 180 may include an I2C field. The I2C field may have any preferred length (e.g., 1 bit) and may be used to indicate that the period 192 of the downstream transmission includes an I2C transaction. The I2C field may indicate that the host 110 has provided an instruction to the associated subnodes 102-2 to remotely access a peripheral device 108 that acts as an I2C slave.

[0061] In some embodiments, the synchronization control frame 180 may include a node field. The node field may have any preferred length (e.g., 4 bits) and may be used to indicate which subnodes are addressed for normal access and I2C access. In discovery mode, this field may be used to program the identifier of the newly discovered subnode 102-2 in the node ID register of subnode 102-2. Each subnode 102-2 of system 100 may be assigned a unique ID when it is discovered by the main node 102-1, as discussed below. In some embodiments, the main node 102-1 does not have a node ID, while in other embodiments, the main node 102-1 may have a node ID. In some embodiments, a subnode 102-2 attached to the main node 102-1 on the bus 106 (e.g., subnode 0 in Figure 1) is subnode 0, and each subsequent subnode 102-2 has a number one higher than the previous subnode. However, this is merely illustrative, and any suitable subnode identification system can be used.

[0062] In some embodiments, the synchronization control frame 180 may include a read / write (RW) field. The RW field may have any preferred length (e.g., 1 bit) and may be used to control whether the normal access is a read (e.g., RW==1) or a write (e.g., RW==0).

[0063] In some embodiments, the synchronization control frame 180 may include an address field. The address field may have any preferred length (e.g., 8 bits) and may be used to address a specific register of subnode 102-2 via the bus 106. For I2C transactions, the address field may be replaced with I2C control values ​​such as start / stop, wait, RW, and data VLD. For discovery transactions, the address field may have a predetermined value (e.g., as shown in Figure 5).

[0064] In some embodiments, the synchronous control frame 180 may include a data field. The data field may have any preferred length (e.g., 8 bits) and may be used for normal writes, I2C writes, and broadcast writes. The RESPCYCS value (multiplied by 4) may be used to determine the number of elapsed cycles that a newly discovered node should allow between the start of the received synchronous control frame 180 and the start of the transmitted synchronous response frame 197. If the NAM field indicates discovery mode, the node address field and data field discussed below may be encoded as a RESPCYCS value that, when multiplied by a preferred optional multiplier (e.g., 4), represents the time in bits from the end of the synchronous control frame 180 to the start of the synchronous response frame 197. This allows a newly discovered subnode 102-2 to determine an appropriate time slot for upstream transmission.

[0065] In some embodiments, the synchronous control frame 180 may include a cyclic redundancy check (CRC) field. The CRC field may have any preferred length (e.g., 16 bits) and may be used to transmit the CRC value of the control data 184 of the synchronous control frame 180, following the preamble 182. In some embodiments, the CRC may be calculated according to a CCITT-CRC error detection scheme.

[0066] In some embodiments, at least a portion of the synchronous control frame 180 between the preamble 182 and the CRC field may be scrambled to reduce the likelihood that the sequence of bits in this interval periodically coincides with the preamble 182 (and thus could be misinterpreted by subnodes 102-2 at the start of a new superframe 190), and to reduce electromagnetic radiation as described above. In some such embodiments, the CNT field of the synchronous control frame 180 may be used by scrambling logic to ensure that the scrambled field is scrambled differently from one superframe to the next. Various embodiments of the system 100 described herein may omit scrambling.

[0067] As discussed above, in addition to, or instead of, techniques such as scrambling and / or error coding, other techniques can be used to ensure that the preamble 182 can be uniquely identified by subnode 102-2, or to reduce the likelihood that the preamble 182 appears elsewhere in the synchronization control frame 180. For example, a longer synchronization sequence may be used so that a particular encoding of the rest of the synchronization control frame 180 reduces the likelihood of it matching. Additionally or alternatively, the rest of the synchronization control frame may be structured in such a way that no synchronization sequence can occur, for example, by setting a fixed value of "0" or "1" to the appropriate bits.

[0068] The main node 102-1 can send read and write requests to subnodes 102-2, including both requests specific to communication on bus 106 and I2C requests. For example, the main node 102-1 can send read and write requests (indicated using the RW field) to one or more designated subnodes 102-2 (using the NAM field and the node field), indicating whether the request is a request to subnode 102-2 specific to bus 106, an I2C request to subnode 102-2, or an I2C request to be passed to an I2C-enabled peripheral device 108 coupled to subnode 102-2 via one or more I2C ports on subnode 102-2.

[0069] For upstream communication, a synchronous response frame 197 may initiate each upstream transmission. In some embodiments, the synchronous response frame 197 may be 64 bits long, but any other preferred length may be used. The synchronous response frame 197 may also include a preamble and a subsequent data portion, as discussed above with respect to the preamble 182 of the synchronous control frame 180. At the end of downstream transmission, the last subnode 102-2 on bus 106 may wait until the RESPCYCS counter expires, and then begin sending a synchronous response frame 197 upstream. If the upstream subnode 102-2 is targeted by a normal read or write transaction, the subnode 102-2 may generate its own synchronous response frame 197, replacing the one received from downstream. If any subnode 102-2 does not find a synchronous response frame 197 from a downstream subnode 102-2 at the expected time, subnode 102-2 generates its own synchronous response frame 197 and begins sending it upstream.

[0070] The data portion of the synchronous response frame 197 may include fields containing data used to send response information back to the main node 102-1. Examples of these fields are discussed below, and several embodiments are shown in Figure 6. Specifically, Figure 6 shows exemplary formats for the synchronous response frame 197 in normal mode, I2C mode, and discovery mode according to various embodiments.

[0071] In some embodiments, the synchronous response frame 197 may include a count (CNT) field. The CNT field may have any preferred length (e.g., 2 bits) and may be used to transmit the value of the CNT field of the previously received synchronous control frame 180.

[0072] In some embodiments, the synchronous response frame 197 may include an acknowledgment (ACK) field. The ACK field may have any preferred length (e.g., 2 bits) and may be inserted by subnode 102-2 when it generates the synchronous response frame 197 to acknowledge the command received in the previous synchronous control frame 180. Exemplary indicators that may be communicated in the ACK field include wait, acknowledgment, negation (NACK), and retry. In some embodiments, the ACK field may be sized to indicate that a broadcast message has been received and processed, so that subnode 102-2 sends an acknowledgment (e.g., by sending a broadcast acknowledgment to main node 102-1). In some such embodiments, subnode 102-2 may also indicate whether it has data to send (which can be used for request-based upstream transmissions, such as non-TDM input from a keypad or touchscreen, or for preferred upstream transmissions, such as when subnode 102-2 wants to report an error or emergency condition).

[0073] In some embodiments, the synchronous response frame 197 may include an I2C field. The I2C field may have any preferred length (e.g., 1 bit) and may be used to transmit the value of the I2C field of the previously received synchronous control frame 180.

[0074] In some embodiments, the synchronous response frame 197 may include a node field. The node field may have any preferred length (e.g., 4 bits) and may be used to transmit the ID of the subnode 102-2 that generates the synchronous response frame 197.

[0075] In some embodiments, the synchronous response frame 197 may include a data field. The data field may have any preferred length (e.g., 8 bits), and its value may depend on the type of transaction and the ACK response of the subnode 102-2 that generates the synchronous response frame 197. In the case of a discovery transaction, the data field may include the value of the RESPCYCS field of the previously received synchronous control frame 180. When the ACK field indicates a NACK, or when the synchronous response frame 197 is responding to a broadcast transaction, the data field may include a broadcast acknowledgment (BA) indicator (which may indicate whether the last subnode 102-2 received the broadcast write without error), a discovery error (DER) indicator (which indicates whether the newly discovered subnode 102-2 in the discovery transaction matches an existing subnode 102-2), and a CRC error (CER) indicator (which indicates whether the NACK was caused by a CRC error).

[0076] In some embodiments, the synchronous response frame 197 may include a CRC field. The CRC field may have any preferred length (e.g., 16 bits) and may be used to transmit the CRC value of the portion of the synchronous response frame 197 between the preamble and the CRC field.

[0077] In some embodiments, the synchronous response frame 197 may include an interrupt request (IRQ) field. The IRQ field may have any preferred length (e.g., 1 bit) and may be used to indicate that an interrupt was signaled from subnode 102-2.

[0078] In some embodiments, the synchronous response frame 197 may include an IRQ node (IRQNODE) ​​field. The IRQNODE field may have any preferred length (e.g., 4 bits) and may be used to transmit the ID of the subnode 102-2 that signaled the interrupt indicated by the IRQ field. In some embodiments, the subnode 102-2 for generating the IRQ field inserts its own ID into the IRQNODE field.

[0079] In some embodiments, the synchronous response frame 197 may include a second CRC (CRC-4) field. The CRC-4 field may have any preferred length (e.g., 4 bits) and may be used to transmit the CRC values ​​of the IRQ field and the IRQNODE field.

[0080] In some embodiments, the synchronous response frame 197 may include an IRQ field, an IRQNODE field, and a CRC-4 field as the last bits (e.g., the last 10 bits) of the synchronous response frame 197. As discussed above, these interrupt-related fields may have their own CRC protection in the form of CRC-4 (and therefore not protected by the preceding CRC field). Any subnode 102-2 that needs to signal an interrupt to the main node 102-1 inserts its interrupt information into these fields. In some embodiments, a subnode 102-2 with an interrupt wait may have a higher priority than any further downstream subnode 102-2 that also has an interrupt wait. The last subnode 102-2 along the bus 106 (e.g., subnode 2 in Figure 1) may always pop these interrupt fields. If the last subnode 102-2 has no interrupt waiting, it may set the IRQ bit to 0, set the IRQNODE field to its node ID, and provide the correct CRC-4 value. For convenience, the synchronous response frame 197 that propagates the interrupt may be referred to herein as the “interrupt frame”.

[0081] In some embodiments, at least a portion of the synchronous response frame 197 between the preamble 182 and the CRC field may be scrambled to reduce radiation. In some such embodiments, the CNT field of the synchronous response frame 197 may be used by scrambling logic to ensure that the scrambled field is scrambled differently from one superframe to the next. Various embodiments of the system 100 described herein may omit scrambling.

[0082] As discussed above, in addition to, or instead of, techniques such as scrambling and / or error coding, other techniques can be used to ensure that the preamble 182 can be uniquely identified by subnode 102-2, or to reduce the likelihood that the preamble 182 appears elsewhere in the synchronous response frame 197. For example, a longer synchronization sequence may be used so that a particular encoding of the rest of the synchronous response frame 197 reduces the likelihood of it matching. Additionally or alternatively, the rest of the synchronous response frame may be structured in such a way that no synchronization sequence can occur, for example, by setting a fixed value of "0" or "1" to the appropriate bits.

[0083] Figure 7 is a block diagram of the bus protocol circuit 126 of Figure 2 in various embodiments. The bus protocol circuit 126 may include a control circuit 154 for controlling the operation of the node transceiver 120 in accordance with the bus 106 protocol described herein. Specifically, the control circuit 154 may control the generation of a synchronous frame for transmission (e.g., a synchronous control frame or synchronous response frame, as discussed above), the processing of a received synchronous frame, and the execution of a control operation specified in the received synchronous control frame. The control circuit 154 may include programmable registers, as discussed below. The control circuit 154 may create and receive synchronous control frames, respond appropriately to received messages (e.g., associated with a synchronous control frame when the bus protocol circuit 126 is included in subnode 102-2, or from an I2C device when the bus protocol circuit 126 is included in mainnode 102-1), and adjust framing for different operating modes (e.g., normal, discovery, standby, etc.).

[0084] When node transceiver 120 is preparing data for transmission along bus 106, preamble circuit 156 may be configured to generate a preamble for a synchronous frame for transmission and to receive a preamble from a received synchronous frame. In some embodiments, the preamble for downstream synchronous control frames may be sent out by main node 102-1 every 1024 bits. As discussed above, one or more subnodes 102-2 may synchronize with the preamble for downstream synchronous control frames and generate a local, phase-aligned main clock from the preamble.

[0085] The CRC insertion circuit 158 ​​may be configured to generate one or more CRCs for the transmission synchronization frame. The frame / compression circuit 160 may take input data from the I2S / TDM / PDM transceiver 127 (e.g., the frame buffer associated with transceiver 127), the I2C transceiver 129, and / or the SPI transceiver 136, and optionally compress the data, and optionally generate parity check bits or error correction codes (ECCs) for the data. The multiplexer (MUX) 162 may multiplex the preamble from the preamble circuit 156, the synchronization frame, and the data into a transmission stream. In some embodiments, the transmission stream may be scrambled before transmission by the scrambling circuit 164.

[0086] For example, in some embodiments, the frame / compression circuit 160 may apply a floating-point compression scheme. In such embodiments, the control circuit 154 may transmit 3 bits indicating the number of repeating sign bits, followed by a sign bit and N-4 bits of data, where N is the size of the data transmitted over bus 106. The use of data compression may be configured by the main node 102-1 if desired.

[0087] In some embodiments, the received stream entering the node transceiver 120 may be descrambled by a descramble circuit 166. A demultiplexer (DEMUX) 168 may demultiplex the preamble, sync frame, and data from the received stream. A receiving CRC check circuit 159 may check the received sync frame for a correct CRC. If the CRC check circuit 159 identifies a CRC fault in the incoming sync control frame 180, the control circuit 154 may be notified of the fault and will not execute any control commands in the control data 184 of the sync control frame 180. If the CRC check circuit 159 identifies a CRC fault in the incoming sync response frame 197, the control circuit 154 may be notified of the fault and may generate an interrupt in the interrupt frame for transmission to the host 110. The frame de-frame / restore circuit 170 can accept received data, optionally check its parity, optionally perform error detection and correction (e.g., single error correction, double error detection (SECDED)), optionally restore the data, and write the received data to the I2S / TDM / PDM transceiver 127 (e.g., the frame buffer associated with transceiver 127), the I2C transceiver 129, and / or the SPI transceiver 136.

[0088] As discussed above, upstream and downstream data can be transmitted along bus 106 in TDM data slots within the superframe 190. The control circuit 154 may include registers dedicated to managing these data slots on bus 106, some examples of which are discussed below. When the control circuit 154 is included in the main node 102-1, the values ​​of these registers can be programmed into the control circuit 154 by the host 110. When the control circuit 154 is included in the subnode 102-2, the values ​​of these registers can be programmed into the control circuit 154 by the main node 102-1.

[0089] In some embodiments, the control circuit 154 may include a downstream slots (DNSLOTS) register. When the node transceiver 120 is included in the main node 102-1, this register may hold a value for the total number of downstream data slots. This register may also define the number of data slots used for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 of the main node 102-1. In subnode 102-2, as will be discussed in more detail below with respect to LDNSLOTS, this register may define the number of data slots to be passed downstream to the next subnode 102-2 before or after the addition of locally generated downstream slots.

[0090] In some embodiments, the control circuit 154 may include a Local Downstream Slots (LDNSLOTS) register. This register may be unused on the main node 102-1. On the subnode 102-2, this register may define the number of data slots that the subnode 102-2 will use and will not retransmit. Alternatively, this register may define the number of slots that the subnode 102-2 may contribute to the downstream links of the bus 106.

[0091] In some embodiments, the control circuit 154 may include an Upstream Slots (UPSLOTS) register. In the main node 102-1, this register may hold a value for the total number of upstream data slots. This register may also define the number of slots used for I2S / TDM transmission by the I2S / TDM / PDM transceiver 127 of the main node 102-1. In the subnode 102-2, this register may define the number of data slots that are passed upstream before the subnode 102-2 begins to add its own data.

[0092] In some embodiments, the control circuit 154 may include a local upstream slots (LUPSLOTS) register. This register may be unused on the main node 102-1. On the subnode 102-2, this register may define the number of data slots that the subnode 102-2 adds to data before it is sent upstream after receiving data from downstream. This register may also define the number of data slots used for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 on the subnode 102-2.

[0093] In some embodiments, the control circuit 154 may include a broadcast downstream slots (BCDNSLOTS) register. This register may be unused on the main node 102-1. On subnodes 102-2, this register may define the number of broadcast data slots. In some embodiments, broadcast data slots may always occur at the beginning of a data field. The data in a broadcast data slot may be used by multiple subnodes 102-2 and may be passed downstream by all subnodes 102-2, whether they are used or not.

[0094] In some embodiments, the control circuit 154 may include a slot format (SLOTFMT) register. This register may define the format of data for upstream or downstream transmission. The data size of the I2S / TDM / PDM transceiver 127 may also be determined by this register. In some embodiments, valid data sizes include 8 bits, 12 bits, 16 bits, 20 bits, 24 bits, 28 bits, and 32 bits. This register may also include a bit to enable floating-point compression for downstream or upstream traffic. When floating-point compression is enabled, the I2S / TDM data size may be 4 bits larger than the data size over bus 106. All nodes in system 100 may have the same value for SLOTFMT when a data slot is enabled, and these nodes may be programmed by broadcast writes so that all nodes are updated with the same value.

[0095] Figures 8-11 illustrate examples of information exchange along bus 106 according to various embodiments of the bus protocol described herein. Specifically, Figures 8-11 illustrate embodiments in which each subnode 102-2 is coupled to one or more speakers and / or one or more microphones as peripheral devices 108. This is merely illustrative, as any desired arrangement of the peripheral devices 108 can be coupled to any particular subnode 102-2 according to the techniques described herein.

[0096] First, Figure 8 illustrates the consideration of signal transmission and timing for bidirectional communication on bus 106 in various embodiments. The subnodes 102-2 shown in Figure 8 have varying numbers of sensor / actuator elements, and therefore, different amounts of data can be sent to or received from various subnodes 102-2. Specifically, subnode 1 has 2 elements, subnode 4 has 4 elements, and subnode 5 has 3 elements, so the data transmitted by main node 102-1 includes 2 time slots for subnode 1, 4 time slots for subnode 4, and 3 time slots for subnode 5. Similarly, subnode 0 has 3 elements, subnode 2 has 3 elements, subnode 3 has 3 elements, subnode 6 has 1 element, and subnode 7 has 4 elements, so the data transmitted upstream by those subnodes 102-2 includes the corresponding number of time slots. Note that a one-to-one correlation between elements and time slots is not required. For example, a microphone array having three microphones included in peripheral device 108 may include a DSP that combines signals from the three microphones (and possibly information received from main node 102-1 or other subnodes 102-2) to produce a single data sample that may correspond to a single time slot or multiple time slots, depending on the type of processing.

[0097] In Figure 8, the main node 102-1 transmits the SCF, followed by data for a speaker coupled to a specific subnode 102-2 (SD). Each successive subnode 102-2 forwards the SCF and also forwards at least one of the data destined for a downstream subnode 102-2. A specific subnode 102-2 may forward all the data or may omit any data destined for that subnode 102-2. When the last subnode 102-2 receives the SCF, it transmits an SRF, and optionally follows it with any data that subnode 102-2 is permitted to transmit. Each successive subnode 102-2 forwards the SRF along with any data from downstream subnodes 102-2 and optionally inserts data from one or more microphones coupled to a specific subnode 102-2 (MD). In the example in Figure 8, the main node 102-1 sends data to subnodes 1, 4, and 5 (shown as active speakers in Figure 8) and receives data from subnodes 7, 6, 3, 2, and 0 (shown as a microphone array in Figure 8).

[0098] Figure 9 schematically illustrates the dynamic deletion of data from downstream transmissions and the insertion of data into upstream transmissions from the perspective of the downstream DS transceiver 124, under various embodiments. In Figure 9, as in Figure 8, the main node 102-1 transmits the SCF and then the data for subnodes 1, 4, and 5 (SD) in reverse order (for example, the data for subnode 5 is followed by the data for subnode 4, and then the data for subnode 1) (see the row labeled Main). When subnode 1 receives this transmission, subnode 1 deletes its own data and forwards only the SCF and the subsequent data for subnodes 5 and 4 to subnode 2. Subnodes 2 and 3 forward the data without modification so that the data forwarded by subnode 1 is received by subnode 4 (see the row labeled Sub 3) (see the row labeled Sub 2). Subnode 4 deletes its own data and transfers only the SCF and the subsequent data for subnode 5 to subnode 5. Similarly, subnode 5 deletes its own data and transfers only the SCF to subnode 6. Subnode 6 transfers the SCF to subnode 7 (see the line labeled Subnode 6).

[0099] At this point, subnode 7 sends the SRF and its own data to subnode 6 (see the line labeled "Sub 6"). Subnode 6 forwards the SRF, along with the data from subnode 7 and its own data, to subnode 5, which then forwards the SRF, along with the data from subnodes 7 and 6, to subnode 4. Subnode 4 has no additional data to add and therefore simply forwards the data to subnode 3 (see the line labeled "Sub 3"), which then forwards the data, along with its own data, to subnode 2 (see the line labeled "Sub 2"), which then forwards the data, along with its own data, to subnode 1. Subnode 1 has no additional data to add and therefore forwards the data to subnode 0, which then forwards the data, along with its own data. As a result, main node 102-1 receives the SRF and the subsequent data from subnodes 7, 6, 3, 2, and 0 (see the line labeled "Main").

[0100] Figure 10, similar to Figure 9, illustrates another example of dynamic deletion of data from downstream transmissions and insertion of data into upstream transmissions from the perspective of the downstream DS transceiver 124, but in Figure 10, subnodes 102-2 are coupled to both sensors and actuators as peripheral devices 108 so that the main node 102-1 sends data to all of the downstream subnodes 102-2 and receives data back from all of the subnodes 102-2. Also in Figure 10, the data is ordered based on the node address to which it is sent or the node address to which it is sent. Data slots labeled "Y" may be used for data integrity checks or data corrections.

[0101] Figure 11, similar to Figure 9, illustrates another example of dynamic deletion of data from downstream transmissions and insertion of data into upstream transmissions from the perspective of the downstream DS transceiver 124, except that in Figure 11, the data is transmitted sequentially downstream and upstream, rather than in reverse order. Buffering at each subnode 102-2 allows for the selective addition, deletion, and / or transfer of data.

[0102] As discussed above, each subnode 102-2 can delete data from a downstream or upstream transmission, and / or add data to a downstream or upstream transmission. Therefore, for example, the main node 102-1 can send a separate data sample to each of several subnodes 102-2, and each such subnode 102-2 can delete its own data sample and forward only the data destined for the downstream subnode 102-2. On the other hand, a subnode 102-2 can receive data from a downstream subnode 102-2 and forward that data along with additional data. One advantage of transmitting only as much information as necessary is to reduce the amount of power consumed by the system 100 as a whole.

[0103] System 100 may also support broadcast transmissions (and multicast transmissions) from main node 102-1 to subnode 102-2, specifically through a configuration using the downstream slots of subnode 102-2. Each subnode 102-2 may process a broadcast transmission and pass it on to the next subnode 102-2, but a particular subnode 102-2 may "consume" a broadcast message (i.e., not pass the broadcast transmission on to the next subnode 102-2).

[0104] System 100 may also support upstream transmissions (for example, from a particular subnode 102-2 to one or more other subnodes 102-2). Such upstream transmissions may include unicast upstream transmissions, multicast upstream transmissions, and / or broadcast upstream transmissions. As discussed above with respect to downstream transmissions, upstream addressing allows subnode 102-2 to determine, based on its configuration of upstream slot usage, whether to remove data from the upstream transmission and / or to pass the upstream transmission to the next upstream subnode 102-2. Thus, for example, data may be passed by a particular subnode 102-2 to one or more other subnodes 102-2 in addition to, or instead of, passing the data to the main node 102-1. Such sub-sub relationships may be established, for example, via the main node 102-1.

[0105] Therefore, in various embodiments, subnodes 102-2 can operate as active / intelligent relay nodes with the ability to selectively transfer, delete, and add information. Since each subnode 102-2 knows the relevant time slots for receiving / transmitting data internally, subnodes 102-2 can generally perform such functions without necessarily decoding / examining all of the data, and thus can delete data from a time slot or add data to a time slot. Even though subnodes 102-2 do not need to decode / examine all of the data, they can typically reclock the data they transmit / transmit. This can increase the robustness of system 100.

[0106] In some embodiments, bus 106 may be configured for one-way communication in a ring topology. For example, Figure 12 illustrates arrangement 1200 of a main node 102-1 and four subnodes 102-2 in a ring topology and illustrates considerations of signal transmission and timing for one-way communication in arrangement 1200 according to various embodiments. In such embodiments, the node transceiver 120 within the node may include a receive-only transceiver (main input) and a transmit-only transceiver (main output), rather than two bidirectional transceivers for upstream and downstream communication. In the link layer synchronization scheme shown in Figure 12, the main node 102-1 transmits the SCF 180 and, optionally thereafter, "downstream" data 1202 for three speakers coupled to various subnodes 102-2 (as discussed above with reference to Figures 8-11, the data for different speakers may be arranged in any preferred order), and each successive subnode 102-2 transmits the synchronization control frame 180 along with any "upstream" data from the previous subnode 102-2 and its own "upstream" data to provide "upstream" data 1204 (for example, as discussed above with reference to Figures 8-11, the data from eight different microphones may be arranged in any preferred order).

[0107] As described herein, data can be communicated between elements of system 100 in any of several ways. In some embodiments, data can be sent upstream by subnode 102-2 (e.g., using data slot 199) or downstream by subnode 102-2 or main node 102-1 (e.g., using data slot 198) as part of a set of synchronous data slots. The amount of such data can be adjusted by changing the number of bits in the data slot or by including additional data slots. In system 100, data can also be communicated by including it in a synchronous control frame 180 or a synchronous response frame 197. The data communicated in this manner may include I2C control data from host 110 (with responses from peripheral device 108 associated with subnode 102-2), access to registers in subnode 102-2 (e.g., for slot and interface discovery and configuration), write access from host 110 / main node 102-1 to subnode 102-2, and read access from subnode 102-2 to host 110 / main node 102-1, and event signal transmission via interrupt from peripheral device 108 to host 110. In some embodiments, GPIO pins may be used to transmit information from subnode 102-2 to main node 102-1 (e.g., by having main node 102-1 poll the GPIO pins via I2C, or by having the node transceiver 120 of subnode 102-2 generate an interrupt on the interrupt request pin). For example, in some such embodiments, host 110 may send information to main node 102-1 via I2C, and main node 102-1 may then send that information to subnode 102-2 via GPIO pins. Any of the types of data discussed herein as being transmitted via bus 106 may be transmitted using any one or more of these communication paths. Other types of data and data communication techniques within system 100 may be disclosed herein.

[0108] Embodiments of the present disclosure can be implemented in a system using any suitable hardware and / or software to be configured as desired. Figure 13 schematically illustrates a device 1300 that can function as a host or node (e.g., host 110, main node 102-1, or subnode 102-2) in system 100 according to various embodiments. Several components are shown in Figure 13 as being included in device 1300, but any one or more of these components can be omitted or duplicated to suit the application.

[0109] In addition, in various embodiments, device 1300 may not include one or more of the components shown in Figure 13, but device 1300 may include interface circuits for coupling with one or more of those components. For example, device 1300 may not include the display device 1306, but may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1306 can be coupled. In another set of examples, device 1300 may not include the audio input device 1324 or the audio output device 1308, but may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1324 or the audio output device 1308 can be coupled.

[0110] In any of the embodiments disclosed herein, device 1300 may include a node transceiver 120 for managing communication along bus 106 when device 1300 is coupled to bus 106. Device 1300 may include a processing device 1302 (e.g., one or more processing devices) which may be included in or separate from the node transceiver 120. As used herein, the term “processing device” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data which can be stored in registers and / or memory. The processing device 1302 may include one or more DSPs, ASICs, central processing units (CPUs), graphics processing units (GPUs), cryptographic processors, or any other suitable processing devices. Device 1300 may include memory 1304, which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid memory, and / or a hard disk drive.

[0111] In some embodiments, memory 1304 may be used to store working and permanent copies of programming instructions that cause device 1300 to execute any preferred technique among those disclosed herein. In some embodiments, machine-accessible media, methods, systems, and devices (including non-temporary computer-readable storage media) for executing the above techniques are examples of embodiments disclosed herein for communication over a two-wire bus. For example, a computer-readable medium (e.g., memory 1304) may have stored instructions that, when executed by one or more processing devices included in processing device 1302, cause device 1300 to execute any of the techniques disclosed herein.

[0112] In some embodiments, device 1300 may include another communication chip 1312 (e.g., one or more other communication chips). For example, communication chip 1312 may be configured to manage wireless communication for data transfer to and from device 1300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated device does not include any wiring, although in some embodiments it may not.

[0113] The communication chip 1312 may implement any of several wireless standards or protocols, including, but not limited to, the Long-Term Evolution (LTE) project, with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.), including Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), and the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"). IEEE 802.16-compatible broadband radio access (BWA) networks are commonly referred to as WiMAX networks, which are certified by Worldwide Interoperability for Microwave, a certification mark for products that pass conformance and interoperability testing of the IEEE 802.16 standard. It is an acronym for Access. One or more communication chips 1312 may operate according to Global System for Mobile Communications (GSM), General Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Advanced HSPA (E-HSPA), or LTE network. One or more communication chips 1312 may support Enhanced Data for GSM Innovation (EDGE), GSM The device may operate in accordance with the Edge Radio Access Network (GERAN), Universal Terrestrial Radio Connectivity Network (UTRAN), or Advanced UTRAN (E-UTRAN). One or more communication chips 1312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Radio Telecommunications (DECT), Advanced Data Optimization (EV-DO), and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G, and later. In other embodiments, the communication chips 1312 may operate in accordance with other radio protocols. The device 1300 may include an antenna 1322 for facilitating wireless communication and / or receiving other wireless communication (such as AM or FM radio transmission).

[0114] In some embodiments, the communication chip 1312 may manage wired communications using protocols other than those described herein for bus 106. Wired communications may include telecommunications protocols, optical communications protocols, or any other suitable communications protocols. Examples of wired communications protocols that can be enabled by the communication chip 1312 include Ethernet, Controller Area Network (CAN), I2C, Media-Oriented Systems Transport (MOST), or any other suitable communications protocols.

[0115] As described above, the communication chip 1312 may include multiple communication chips. For example, the first communication chip 1312 may be dedicated to short-range wireless communication such as Wi-Fi or Bluetooth®, and the second communication chip 1312 may be dedicated to Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or other long-range wireless communication. In some embodiments, the first communication chip 1312 may be dedicated to wireless communication, and the second communication chip 1312 may be dedicated to wired communication.

[0116] Device 1300 may include a battery / power circuit 1314. The battery / power circuit 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of device 1300 to an energy source separate from device 1300 (e.g., AC line power, voltage provided by a car battery, etc.). For example, the battery / power circuit 1314 may include the upstream bus interface circuit 132 and downstream bus interface circuit 131 discussed above with reference to Figure 2, and may be charged by a bias on bus 106.

[0117] Device 1300 may include a display device 1306 (or a corresponding interface circuit as discussed above). The display device 1306 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0118] Device 1300 may include an audio output device 1308 (or a corresponding interface circuit as discussed above). The audio output device 1308 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0119] Device 1300 may include an audio input device 1324 (or a corresponding interface circuit as discussed above). The audio input device 1324 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a MIDI output).

[0120] Device 1300 may include a GPS device 1318 (or a corresponding interface circuit as discussed above). The GPS device 1318 may communicate with satellite-based systems, as is well known in the art, and may receive the location of device 1300.

[0121] Device 1300 may include another output device 1310 (or a corresponding interface circuit as discussed above). Examples of the other output device 1310 include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. In addition, any preferred peripheral device 108 discussed herein may be included in the other output device 1310.

[0122] Device 1300 may include another input device 1320 (or a corresponding interface circuit as discussed above). Examples of the other input device 1320 include an accelerometer, a gyroscope, an image acquisition device, a keyboard, a cursor control device (such as a mouse, stylus, or touchpad), a barcode reader, a quick response (QR) code reader, or a radio frequency identification (RFID) reader. In addition, any preferred sensor or peripheral device 108 discussed herein may be included in the other input device 1320.

[0123] Any suitable display device, input device, output device, communication device, or memory device described above with respect to device 1300 may function as a peripheral device 108 of system 100. Alternatively or additionally, any suitable display device, input device, output device, communication device, or memory device described above with respect to device 1300 may be included in a host (e.g., host 110) or node (e.g., main node 102-1 or subnode 102-2).

[0124] The elements of system 100 are selected and configured to provide voice control and / or light control via bus 106. In some embodiments, system 100 may be configured to function as a light control system in a vehicle or other environment, comprising a lighting device (e.g., stripline light-emitting diodes (LEDs) or other LED arrangement) that functions as a peripheral device 108 communicating with a node 102 along bus 106, and data may be communicated via bus 106 to control the color, intensity, duty cycle, and / or other parameters of the lighting device. In some embodiments, system 100 may be configured to function as a voice control system in a vehicle or other environment, comprising a microphone or other device including an accelerometer that can function as a peripheral device 108 communicating with a node 102 along bus 106, and data from the accelerometer may be communicated via bus 106 to control other peripheral devices 108 along bus 106. For example, large spikes in acceleration data or other predetermined acceleration data patterns may be used to trigger the generation of sound effects such as cowbells or drum hits by a processing device coupled to node 102, and the sound effects may be output by a speaker coupled to the processing device and / or a speaker coupled to another node 102 along bus 106. Some embodiments of system 100 may combine any of the lighting control techniques and / or sound control techniques disclosed herein.

[0125] While the various embodiments discussed above describe the system 100 in a vehicle setting, this is merely illustrative, and the system 100 can be implemented in any desired setting. For example, in some embodiments, a “portable” implementation of the system 100 may include a portable housing containing the desired components of the system 100, and such an implementation may be particularly suitable for portable applications such as a portable karaoke or entertainment system.

[0126] As described above, in embodiments of system 100 (for example, in which one or more of the peripheral devices 108 include microphones), calibration of microphones in the array may be important for effective beamforming and other operations. Figures 14-22 illustrate exemplary systems and techniques for calibration, as well as applications of calibration during runtime.

[0127] Figure 14 illustrates a calibration system for a microphone module during post-manufacturing performance testing in various embodiments. In the system of Figure 14, the loudspeaker 2120 can reproduce a test signal s(t) to the microphone module 2140 being calibrated. The microphone module 2140 may include one microphone or n microphones M1...M n The array may include 2141...2142. In some examples, n=1, and the microphone array is an array of one microphone. The reference microphone M02130 may be installed between the loudspeaker 2120 and the microphone module 2140, or it may be installed at any suitable known location relative to the loudspeaker 2120 and the microphone module 2140. Microphones M1...M n These are signals m1(t)...m n (t) can be generated, and these signals and the reference microphone signal m0(t) can be processed by the calibration computer 2110. The calibration computer 2110 may include any suitable processing device, for example, a personal computer. The calibration computer 2110 generates a set of filter coefficients K1...K (also referred to herein as “calibration coefficients”). n The filter coefficients can be generated and transmitted to the microphone module 2140 during calibration. The coefficients may be stored in a non-volatile memory 2143 associated with the microphone module 2140 (e.g., a programmable read-only memory (PROM)).

[0128] Microphone modules are generally tested during or after manufacturing. In some cases, speaker 2120 emits a tone, chirp, or frequency range sweep to be received by a reference microphone 2130 and microphones 2141 and 2142 of microphone module 2140, respectively. Then, it is determined whether each of microphones 2141 and 2142 passes the specifications. The response of microphones 2141 and 2142 to the received tone includes frequency measurements, magnitude measurements, and phase measurements. Once it is determined how the received frequency measurements, magnitude measurements, and phase measurements are for the selected microphones 2141 and 2142, calibration coefficients can be determined for each microphone or for the microphone module as a whole. In various cases, magnitude measurements are amplitude measurements. In some cases, some microphone modules fail the test and are discarded.

[0129] Microphone modules that pass the test may be calibrated using test tone (or test chirp, test frequency sweep, etc.) response measurements, and frequency and phase plots may be generated for each microphone 2141, 2142. The frequency and phase plots may be used for future calibration of microphones 2141, 2142. For example, calibration information may be generated for each microphone or the entire microphone module and stored for future microphone calibration and / or compensation. In some examples, conversions are generated for each microphone 2141, 2142, which may be stored and used for subsequent microphone compensation and / or calibration. In some examples, calibration data is stored in memory on the microphone module itself, such as read-only memory, programmable read-only memory (PROM), erasable PROM (EPROM), and electrically erasable programmable read-only memory (EEPROM). In some examples, microphone calibration data is stored outside the microphone. For example, calibration data can be stored in cloud storage and made accessible to a digital signal processor (DSP) for calibration before and during microphone use. In some examples, specific microphone calibration data can be acquired for each microphone using a digital bus networking function.

[0130] In some examples, the calibration of microphones 2141 and 2142 is performed using a reference microphone 2130. For example, the reference microphone 2130 has a known response. Microphone calibration generates calibration coefficients for the microphones. The calibration coefficients can be stored on the microphone module so that they remain with the microphones regardless of where the microphone module is installed.

[0131] According to some embodiments, the calibration coefficient stored for each microphone includes phase data, and in some examples, the calibration coefficient includes a phase tolerance. In some embodiments, the calibration coefficient includes a complex number. In some examples, the calibration coefficient includes an impulse response. In some examples, the calibration coefficient includes a transfer function.

[0132] According to various embodiments, the reference microphone 2130 is a spatial reference point and calibrates the sound received from speaker 2120, which is the main source of uncertainty in speaker 2120. In various examples, the reference microphone 2130 is pre-calibrated. In some examples, the frequency response of the reference microphone 2130 is pre-calibrated. In some examples, the frequency response of the reference microphone 2130 may be used for microphone module 2140. In some embodiments, phase information is included in the calibration and stored in a microphone module such as microphone memory 2143. In some examples, a computing device takes calibration coefficient data stored in microphone module 2140 and applies the data to microphones 2141 and 2142 to calibrate microphones 2141 and 2142.

[0133] In various embodiments, the memory on the microphone module 2143 is an EPROM. In some examples, the memory module 2143 is an EEPROM. In some examples, the memory module 2143 is a one-time programmable (OTP) EPROM. In some embodiments, the memory module 2143 includes additional microphone information, such as vendor information, product information, version information, serial number, device function, and any other microphone information. In some embodiments, the memory is integrated on an MCU or digital networking chip on the microphone module.

[0134] According to various embodiments, the calibration data stored in the microphone module itself includes frequency data, magnitude data, and phase data. In various examples, the magnitude data includes amplitude data. In some examples, the calibration data is communicated via a two-wire interface. In some examples, the calibration data is communicated via an audio communication network such as a digital networking bus.

[0135] According to various embodiments, calibration coefficients may be stored for a single microphone, or for a microphone array. In some examples, a single calibration is stored for the microphone array. For example, if a microphone is off-center and the off-center position of the microphone is discovered during calibration, the same calibration data can be used to calibrate the off-center state of each microphone. The characteristics of the microphone array and microphone module 2140 can be calibrated together. In some examples, each microphone has its own calibration data.

[0136] In some cases, gain and phase correction can appear as if the microphone is shifted. This allows us to see how the signal appears upon arrival and make adjustments if the signal position is incorrect. In various cases, the shift can be either a microphone mismatch or a microphone placement mismatch. Both are indistinguishable and can be treated simultaneously with the same final result.

[0137] In some embodiments, the microphones of module 2140 are calibrated for a selected direction, and after per-sensor calibration, the microphones in the array of microphone module 2140 are calibrated so that microphones 2141 and 2142 have identical frequency and phase responses. Generally, once the microphones are calibrated, the calibration coefficients remain with the microphones and can therefore be used at the location where the microphones are ultimately installed.

[0138] In some examples, memory 2143 includes some calibration data specific to individual microphones and some calibration data applicable to the microphone module 2140. For example, physical characteristics of the microphone module 2140, such as the spacing between microphones in a microphone array, may be stored in memory 2143. In some examples, coefficients are provided to a microphone array mounted in a vehicle head unit so that beamforming can be applied to the driver. For example, the head unit may know what angle and / or direction to focus, but may not know what type of microphone array is installed. If microphone array information is available to the head unit, the head unit can calculate beamforming characteristics. Information about the microphone module that may be stored in memory 2143 includes the number of microphones in the array, the gain range of the microphones, and the physical characteristics of the microphones.

[0139] Referring to Figure 14, in some specific embodiments of the calibration method discussed above, the short-time Fourier transform is used to represent the frequency domain of the corresponding signals S(f), M0(f), M1(f)...M n (f) can be calculated.

[0140] In some embodiments, microphone data for multiple microphone modules in the system is stored on a single memory device in a subnode. In some embodiments, microphone data for all microphone modules in the system is stored on a single memory device in a subnode. For example, calibration data may be stored in the subnode in data storage without onboard processing. In some examples, data is stored after post-installation scenario testing and stored in a network bus node with an available and open memory device.

[0141] Figure 15 is a method 2200 showing operations that can be performed during calibration using a system such as that of Figure 14 according to various embodiments of the present invention. In step 2202, a test signal s(t) is played back through a loudspeaker. For example, the test signal s(t) can be played back through loudspeaker 2120. The test signal s(t) can be a test tone, a chirp, a frequency sweep, or any other type of signal. In step 2204, the microphone audio signals m0(t), m1(t), … m n (t) are sampled from the reference microphone and microphones of the microphone array (e.g., the microphone audio signal m0(t) from the reference microphone 2130, and the microphone audio signals m1(t), … m n (t) from the microphone array of the microphone module 2140).

[0142] In step 2206, the frequency domain signals S(f), M0(f), M1(f), …, M n (f) are determined based on frames of N audio samples of each time domain signal s(t), m0(t), m1(t), …, m n (t). In some examples, the Fourier transform of the frame of N audio samples of each time domain signal s(t), m0(t), m1(t), …, m n (t) is used to calculate the frequency domain signals S(f), M0(f), M1(f), …, M n (f). In step 2208, the calibration coefficients K1(t), …, K n (t) are calculated for each microphone M1, …, M n (e.g., microphones 2141, 2142 of the microphone array of the microphone module 2140). In some examples, to calculate the calibration coefficients, the spectral domain signals M1(f), …, M n(f) and S(f) or M0(f) are used. In some examples, the frequency domain signal calculated in step 2206 is used to determine the calibration coefficients in step 2208. In some examples, the audio signal m0(t) of the reference microphone is used to determine the calibration coefficients of microphones 2141 and 2142 of the microphone array of microphone module 2140. In step 2210, the calibration coefficients K1(t), ..., K n (t) is stored in the non-volatile memory associated with the microphone array (e.g., calibration coefficients K1(), ..., K n (The values ​​in parentheses are stored in the memory 2143 of the microphone module 2140).

[0143] Figure 16 shows Method 2220, which illustrates a specific operation that may be performed when determining the calibration coefficients according to various embodiments of the present invention. Specifically, in some examples, steps 2222 and 2224 of Method 2220 replace step 2208 of Method 2200 in Figure 15. In some examples, Method 2220 begins after step 2206 of Method 2200 in Figure 15. In step 2222, the calibration transfer function H1…H n This is calculated for each microphone 2141, 2142 of the microphone module 2140. Specifically, the calibration transfer function H x (f) is calculated (x=1....n), and in the equation,

[0144]

number

[0145] In some examples, the calibration transfer function is given by the sampled microphone audio signals m0(t), m1(t), ...m n (t) is used to calculate. In step 2224, H x Using the inverse Fourier transform of (f), the calibration transfer function H1…H n Using the calibration coefficients K1(), ...K nThe () is calculated. In step 2226, the calibration coefficient is stored in the non-volatile memory of the microphone module (for example, memory 2143 of microphone module 2140).

[0146] In the embodiment shown in Figure 16, M0 to M x The transfer function mapping (where x represents one of microphones 1...n) is (1) microphone M (the denominator) x (2) The time-averaged cross-correlation product of the reference microphone M02130 and the quotient of the autocorrelation product of M0 (which is the numerator) can be calculated. The calibration transfer function shown in Figure 16 is the reciprocal of this transfer function, and the phase shift term exp is obtained by comparing M0 and M x This reflects the time delay between and results in a shorter filter. (i²πfd / c) Finite Impulse Response (FIR) filter coefficient K x This is the calibration transfer function H x It can be calculated by applying the inverse Fourier transform of 2312.

[0147] Figure 17 shows Method 2240, which illustrates a specific operation that may be performed when determining the calibration coefficient according to various embodiments of the present invention. Specifically, in some embodiments, Method 2240 begins after step 2204 in Figure 15. As shown in Figure 17, Method 2240 is a multi-step procedure. In step 2242, the test signal loudspeaker is pre-calibrated. Specifically, the transfer function H L (f) can be calculated to map the loudspeaker signal S(f) to the reference microphone signal M0(f). For example:

[0148]

number

[0149] In step 2244, the calibration transfer function H x (f) is calculated (x=1...n). Specifically:

[0150]

number

[0151] In some examples, the reference microphone M0 then undergoes calibration transfer function H in step 2244. x It is not used in the calculation. For example, the reference microphone signal is H L It can be calculated as the product of (f) and S(f). Next, the calculation of the filter coefficients can be carried out as described above. Specifically, in step 2246, the calibration coefficient K x (t)(x=1…n) is H x It is determined by the inverse Fourier transform of (f)(x=1…n). In step 2248, the calibration coefficient is stored in the microphone array's memory. In yet another embodiment, the first step of calibration in method 2240 may be omitted, and the loudspeaker may be used to output a test signal s(t) (e.g., a point light source with a flat frequency response), H L (f) can be set to 1 for all frequencies.

[0152] Figure 18 shows multiple microphone modules A1...A according to various embodiments. m The diagram shows system 2400 including 2410...2420. System 2400 is shown with microphone modules A1...A in operation. m This indicates 2410...2420. Specifically, microphone module A1...A m 2410...2420 can be installed in a location selected for use. Microphone module A1...A m Modules 2410...2420 may have been calibrated beforehand, as described above with respect to Figures 14-17. During operation on system 2400, the previously performed calibration is used for modules A1...A m The microphone signals for the 2410...2420 microphones may be filtered. Specifically, calibration is performed on microphone module A1...A m The calibration coefficients may be performed first for each of the 2410...2420, and for each microphone module A1...Am The data may be stored in memories 2413, 2423, 2410...2420. In the system of Figure 18, the microphone signal processing unit 2430 may operate as an edge processor on a data interface 2450 (which may be, for example, one of the embodiments of bus 106 disclosed herein) to the microphone signal sink 2440.

[0153] Figure 19 shows a method 2500 for applying a calibration coefficient during runtime according to various embodiments. In some implementations, method 2500 may be performed by the microphone signal processing unit 2430 of Figure 18. In step 2502, the calibration coefficient K xy (x=1...n, y=1...m) is transmitted via data interface 2510 from memory 2413, 2423 to microphone module A1...A m The signals from 2410...2420 are extracted by the microphone signal processing unit 2430. In step 2504, the respective calibration coefficients K xy () Microphone signal m xy A discrete convolution of (t) is performed, and the calibrated microphone signal n xy Generate (t).

[0154]

number

[0155] In the equation, x = 1...n and y = 1...m.

[0156] In some examples, the calibration coefficient K is applied as an FIR filter. In step 2506, the original microphone signal m xy (t) is the calibrated microphone signal n in the microphone signal processing unit 2430. xy (t) is replaced. In some examples, the original microphone signal is replaced with the calibrated microphone signal located under the data interface. In step 2508, the calibrated microphone signal n xy(t) is the original microphone signal m xy Instead of (t), x=1...n, y=1...m, the data is sent to the microphone sink 2440 on the data interface 2450.

[0157] Figure 20 is an exemplary configuration showing a microphone module calibrated according to the techniques disclosed herein, which may be used in various embodiments of this disclosure. Specifically, Figure 20 shows a vehicle including a main node 2602, a first subnode 2604, a second subnode 2606, and a third subnode 2606. The main node 2602 is connected to the first subnode 2604 via bus 106, the first subnode 2604 is connected to the second subnode 2606 via bus 106, and the second subnode 2606 is connected to the third subnode 2608 via bus 106. Thus, the main node 2602, the first subnode 2604, the second subnode 2606, and the third subnode 2608 are connected in a daisy-chain configuration as described herein.

[0158] In some examples, the main node 2602 is the head unit. In some examples, digital audio signals from the second subnode 2606 and the third subnode 2608 are sent to the first subnode 2604. In various examples, any of the first subnode 2604, the second subnode 2606, and the third subnode 2608 may include an audio processing node. Similarly, the main node 2602 may include an audio processing node. In various examples, the audio processing node may be the main node, a microphone node, an amplifier node, an emergency call node, or many other types of nodes. The setting in Figure 20 is a vehicle, but the systems and techniques disclosed herein may be used in any preferred setting. In some embodiments, the bus 106 may include stranded pairs (e.g., unshielded twisted pairs).

[0159] In some embodiments, microphone module calibration may not be performed at the factory during manufacturing, but may be performed when the microphone is installed in its respective intended settings. For example, Figure 21 shows a method 2700 for microphone module calibration, which may be performed by system 100 to calibrate the microphone module in its respective operating settings, according to various embodiments of the present disclosure. For example, method 2700 may be performed in a vehicle, such as the vehicle shown in Figure 20. However, the calibration procedure in Figure 21 may be performed by system 100 in factory settings instead of operating settings, as desired. Calibration coefficients for the procedure in Figure 21 can be calculated using any suitable technique among those disclosed herein.

[0160] In step 2702, a bus system is discovered and configured. The bus system can be any type of bus system, including those described herein. In step 2704, a test signal is played from a reference speaker. In some examples, the test signal is a chirp. The reference speaker may be connected to the bus system. In some examples, the reference speaker is not connected to the bus system but is connected to the microphone system, separately. In step 2706, microphone nodes are sampled while the test signal is applied. In addition, if a measurement microphone and / or reference microphone are present, the measurement microphone and / or reference microphone are sampled in step 2706. In step 2708, the calibration coefficients for each microphone node are calculated along with any other calibration data. In step 2710, the calibration information for each microphone node is stored in each microphone node.

[0161] Figure 22 shows Method 2750 for the operation procedure of a microphone module according to various embodiments. Method 2750 may be performed by System 100 to extract and use calibration coefficients generated by any of the microphone module calibration techniques disclosed herein. Step 2752 is found and configured. The bus system can be any type of bus system, such as those described herein. Step 2754 is read from the microphone node. In some examples, the pre-stored information is stored in the non-volatile memory of each microphone node and may include calibration information and general microphone information such as vendor, product, model number, serial number, and version. Step 2756 is transferred to a node containing an audio signal processor. Step 2758 is applied to the audio signal processing node with the calibration information from the microphone. Step 2760 is played back. The audio output may be an analog or digital audio output and may be output to a speaker, amplifier, telephone, or any other audio output device.

[0162] Selected Examples

[0163] Embodiment 1 provides a system for microphone module calibration, comprising: a loudspeaker configured to reproduce a test signal; a microphone module configured to receive a test signal and generate multiple microphone array signals; a reference microphone positioned between the loudspeaker and the microphone module, configured to receive a test signal and generate a reference signal; and a calibration computer configured to process the multiple microphone array signals and the reference signal, generate a set of filter coefficients, and transmit the set of filter coefficients to the microphone array.

[0164] Example 2 provides a system according to either the earlier and / or subsequent examples, further comprising memory associated with a microphone array configured to store a set of filter coefficients.

[0165] Example 3 provides a system according to either the preceding and / or subsequent embodiments, in which the memory is positioned on a microphone array module together with the microphone array.

[0166] Embodiment 4 provides a system according to either the preceding and / or subsequent embodiments, wherein the memory is cloud-based memory accessible by a microphone array.

[0167] Embodiment 5 provides a system according to either the preceding embodiment or a subsequent embodiment, wherein the memory is further configured to store microphone information, which includes at least one of vendor information, product information, version information, model information, capability information, serial number, manufacturing information, configuration information, routing information, and authentication information.

[0168] Embodiment 6 provides a system according to either the preceding or subsequent embodiment, further comprising a plurality of memory modules, each of which is associated with each microphone of a microphone array.

[0169] Example 7 provides a system according to either the preceding and / or subsequent examples, wherein the filter coefficients include phase calibration, frequency calibration, and magnitude calibration.

[0170] Embodiment 8 provides a system according to either the preceding or subsequent embodiment, further comprising a two-wire interface, wherein the transmission of filter coefficients to the microphone array occurs via the two-wire interface.

[0171] Example 9 provides a system according to either the preceding and / or subsequent embodiments, in which each of the multiple microphone array signals is unique, and each microphone in the microphone array is associated with each subset of the set of filter coefficients.

[0172] Example 10 provides a method for microphone array calibration, comprising: reproducing a test signal with a loudspeaker; sampling the test signal with a microphone array; generating multiple microphone array signals with the microphone array; sampling the test signal with a reference microphone; generating a reference signal with the reference microphone; generating a set of filter coefficients based on the multiple microphone array signals and the reference signal; and transmitting the set of filter coefficients to the microphone array.

[0173] Example 11 provides a method according to either the earlier and / or subsequent examples, in which sampling a test with a microphone array includes sampling a test signal with each individual microphone in the microphone array.

[0174] Example 12 provides a method according to either the preceding and / or subsequent examples, wherein generating a set of filter coefficients includes generating a subset of filter coefficients for each respective microphone.

[0175] Example 13 provides a method according to either the preceding and / or subsequent examples, further comprising storing each subset of filter coefficients in each respective microphone.

[0176] Example 14 provides a method according to either the preceding and / or subsequent examples, further comprising storing a set of filter coefficients on a microphone array.

[0177] Example 15 provides a method according to either the preceding and / or subsequent embodiments, wherein transmitting a set of filter coefficients includes transmitting a set of filter coefficients via a two-wire bus.

[0178] Example 16 provides a method according to any one of the prior and / or following examples, further comprising pre-calibrating a loudspeaker using a reference microphone.

[0179] Embodiment 17 provides a self-calibrating microphone system comprising: a microphone module including a microphone that is pre-calibrated and configured to receive an audio input signal and output a raw microphone output signal; a non-volatile memory configured to store the microphone calibration coefficients of the microphone; a processor configured to receive the raw microphone signal and the microphone calibration coefficients and generate a calibrated microphone signal; and a microphone signal sink configured to receive the calibrated microphone signal from the processor and output a calibrated microphone signal.

[0180] Example 18 provides a system according to either of the preceding and / or subsequent embodiments, wherein the microphone calibration coefficient is configured for at least one of phase calibration, frequency calibration, and magnitude calibration.

[0181] Example 19 provides a system according to either the preceding and / or subsequent embodiments, wherein the processor is further configured to use microphone calibration coefficients for phase calibration of the raw microphone signal.

[0182] Example 20 provides a system according to either the preceding or subsequent embodiment, further comprising a two-wire bus, wherein the processor and microphone signal sink communicate via the two-wire bus.

[0183] Example 21 provides a system according to either the preceding and / or subsequent embodiments, wherein the processor is further configured to perform convolution of the raw microphone signal and microphone calibration coefficients to generate a calibrated microphone signal.

[0184] Example 22 includes any of the phase and frequency response calibration systems and techniques disclosed herein.

[0185] Example 23 includes the subject matter from either of the preceding and / or subsequent examples, and further includes storage of microphone array-specific calibration coefficients.

[0186] Example 24 includes the subject matter from either the preceding and / or subsequent examples, and further includes the central application of a calibration coefficient to uncalibrated microphone data from multiple microphone arrays.

[0187] Example 25 includes the subject matter of either the preceding and / or subsequent examples, and further includes replacing the original microphone signal with a calibrated microphone signal.

[0188] Example 26 includes subject matter from either of the preceding and / or subsequent examples, further specifying that the microphone array is a peripheral device in any of the two-wire communication systems disclosed herein.

[0189] Example 27 provides a method according to any one of the prior and / or following examples, wherein the microphone array includes a single microphone.

[0190] Example 28 provides a system according to either the preceding and / or subsequent examples, in which the microphone array includes a single microphone.

[0191] Example 29 provides a system according to either the preceding or subsequent embodiment, further comprising a two-wire bus, wherein the memory is located on a subnode of the network bus.

[0192] Modified forms and embodiments

[0193] As described above, several aspects and embodiments of the technology of this application have been described, but those skilled in the art will understand that various changes, modifications, and improvements will readily arise. Such changes, modifications, and improvements are intended to be within the spirit and scope of the technology described herein. For example, those skilled in the art will readily conceive of various other means and / or structures for performing the function and / or obtaining one or more of the results and / or advantages described herein, and each of such variations and / or modifications will be considered within the scope of the embodiments described herein.

[0194] Those skilled in the art will recognize many equivalents to the specific embodiments described herein, or can verify them through simple routine experimentation. Therefore, it should be understood that the embodiments described herein are merely examples, and that the inventive embodiments may be carried out in ways other than those specifically described, within the scope of the appended claims and their equivalents. In addition, any combination of two or more features, systems, articles, materials, kits, and / or methods described herein is included within the scope of this disclosure, provided that such features, systems, articles, materials, kits, and / or methods are not contradictory to each other.

[0195] The foregoing outlines the features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable a person skilled in the art (PHOSITA) to better understand various aspects of this disclosure. Certain well-understood terms, as well as the underlying art and / or standards, may be referenced without further explanation. It is expected that a PHOSITA will have, or have access to, sufficient background knowledge or information in these arts and standards to implement the teachings of this disclosure.

[0196] PHOSITA will understand that the present disclosure can be readily used as a basis for designing or modifying other processes, structures, or variations to perform the same purposes and / or achieve the same advantages as the embodiments described herein. PHOSITA will also recognize that such equivalent structures will not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present disclosure.

[0197] The embodiments described above may be implemented in any of many ways. One or more aspects and embodiments of this application involving the performance of a process or method may utilize program instructions that can be executed by a device (e.g., a computer, processor, or other device) to perform or control the performance of the process or method.

[0198] In this regard, various inventive concepts may be embodied as computer-readable storage media (or multiple computer-readable storage media) encoded in one or more programs (e.g., computer memory, one or more floppy disks, compact disks, optical disks, magnetic tapes, flash memory, field-programmable gate arrays or circuit configurations of other semiconductor devices, or other tangible computer storage media), and when one or more programs are executed on one or more computers or other processors, a method of implementing one or more of the various embodiments described above is performed.

[0199] A computer-readable medium may be transportable so that the programs stored therein can be loaded onto one or more different computers or other processors to implement various aspects of the embodiments described above. In some embodiments, the computer-readable medium may be a non-transient medium.

[0200] It should be noted that the activities discussed above, particularly specialized software programs or algorithms, can be applied to any integrated circuit involving signal processing (e.g., gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), with reference to the drawings, and some of these may be related to the processing of digitized real-time data.

[0201] In some cases, the teachings of this disclosure may be encoded into one or more tangible, non-transient, computer-readable media that, when executed, store executable instructions that instruct a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. If the teachings of this disclosure are at least partially embodied in a hardware device (such as an ASIC, IP block, or SoC), the non-transient media may include a hardware device that is hardware-programmed with logic for performing the methods or functions disclosed herein. The teachings may also be implemented in the form of register transfer level (RTL) or other hardware description languages ​​such as VHDL or Verilog, which can be used to program manufacturing processes for producing the disclosed hardware elements.

[0202] In exemplary implementations, at least some of the processing activities outlined herein may also be implemented in software. In some embodiments, one or more of these features may be implemented in hardware provided outside of the elements of the disclosed figures, or may be integrated in any suitable manner to achieve the intended function. Various components may include software (or interconnected software) that can work together to achieve operations such as those outlined herein. In yet other embodiments, these elements may include any preferred algorithms, hardware, software, components, modules, interfaces, or objects that facilitate their operation.

[0203] Any appropriately configured processor component can execute any type of instruction associated with data to achieve the operations detailed herein. Any processor disclosed herein can transform an element or article (e.g., data) from one state or thing to another. In another example, some of the activities outlined herein may be implemented with fixed logic or programmable logic (e.g., software and / or computer instructions executed by the processor), and the elements identified herein may be ASICs including some types of programmable processors, programmable digital logic (e.g., FPGAs, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), digital logic, software, code, electronic instructions, flash memory, optical discs, CD-ROMs, DVD-ROMs, magnetic or optical cards, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof.

[0204] During operation, the processor may store information in any suitable type of non-temporary storage medium (e.g., random access memory (RAM), read-only memory (ROM), FPGA, EPROM, electrically erasable programmable ROM (EEPROM), etc.), software, hardware, or, as necessary and based on specific needs, in any other suitable component, device, element, or object. Furthermore, information that is tracked, sent, received, or stored in the processor may be provided in any database, register, table, cache, queue, control list, or storage structure, based on specific needs and implementation examples, all of which may be referenced within any suitable time frame.

[0205] Any of the memory items discussed herein should be interpreted as being included in the broader definition of “memory.” Similarly, any of the potential processing elements, modules, and machines described herein should be interpreted as being included in the broader definition of “microprocessor” or “processor.” Furthermore, in various embodiments, the processors, memories, network cards, buses, storage devices, associated peripherals, and other hardware elements described herein may be implemented by processors, memories, and other associated devices configured with software or firmware for emulating or virtualizing the functions of those hardware elements.

[0206] Furthermore, it should be understood that computers can be embodied in any of several forms, including, but not limited to, rack-mount computers, desktop computers, laptop computers, or tablet computers. In addition, computers can be embedded in devices with suitable processing capabilities, including personal digital assistants (PDAs), smartphones, mobile phones, iPads®, or any other suitable portable or fixed electronic devices, although these are not generally considered computers.

[0207] Furthermore, a computer may have one or more input and output devices. These devices may, among other things, be used to present a user interface. Examples of output devices that may be used to provide a user interface include a printer or display screen for visual presentation of output, and a speaker or other sound-generating device for audible presentation of output. Examples of input devices that may be used for a user interface include a keyboard, as well as pointing devices such as a mouse, touchpad, and digitizing tablet. As another example, a computer may receive input information through speech recognition or in other audible formats.

[0208] Such computers may be interconnected by one or more networks of any preferred form, including local area networks or wide area networks such as enterprise networks, and intelligent networks (INs) or the Internet. Such networks may be based on any preferred technology, may operate according to any preferred protocol, and may include wireless or wired networks.

[0209] Computer executable instructions can take many forms, such as program modules, which are executed by one or more computers or other devices. Generally, a program module includes routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. Typically, the functions of a program module may be combined or distributed as desired in various embodiments.

[0210] The terms “program” or “software” are used herein in a general sense and refer to any type of computer code or set of computer executable instructions employed to program a computer or other processor to implement various aspects of the embodiments described above. In addition, it should be understood that, according to one aspect, one or more computer programs that, when executed, implement the method of this application do not need to reside on a single computer or processor, but can be distributed modularly among several different computers or processors to implement various aspects of this application.

[0211] Furthermore, data structures can be stored in a computer-readable medium in any preferred form. For simplicity of explanation, it can be shown that a data structure has fields that are associated through locations within the data structure. Such relationships may also be achieved by allocating storage devices for the fields that have locations in a computer-readable medium that also transmit relationships between the fields. However, relationships between information within the fields of a data structure can be established using any preferred mechanism, including the use of pointers, tags, or other mechanisms for establishing relationships between data elements.

[0212] When implemented in software, the software code can run on any suitable processor or set of processors, whether it is provided on a single computer or distributed across multiple computers.

[0213] Computer program logic that implements all or part of the functions described herein may be implemented in various forms, including, but not limited to, source code, computer executable, hardware description, and various intermediate forms (e.g., mask work, or forms generated by an assembler, compiler, linker, or locator). For example, source code may include a set of computer program instructions implemented in various programming languages, such as object code, assembly language, or high-level languages ​​like OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, Java®, or HTML, for use with various operating systems or operating environments. Source code may define and use various data structures and communication messages. Source code may be computer executable (e.g., via an interpreter), or source code may be converted to computer executable (e.g., via a converter, assembler, or compiler).

[0214] In some embodiments, any number of electrical circuits in the drawings may be mounted on a substrate of the associated electronic device. The substrate can be a general circuit board capable of housing various components of the internal electronic system of the electronic device and further providing connectors for other peripheral devices. More specifically, the substrate can provide electrical connections that enable other components of the system to communicate electrically. Any suitable processor, memory elements, etc. (including digital signal processors, microprocessors, support chipsets, etc.) can be appropriately coupled to the substrate based on specific configuration needs, processing requirements, computer design, etc.

[0215] Other components, such as external storage, additional sensors, audio / video display controllers, and peripheral devices, may be mounted to the board via cables as plug-in cards, or may be integrated into the board itself. In another exemplary embodiment, the electrical circuit of the drawing may be implemented as a standalone module (e.g., a device having associated components and circuits configured to perform a specific application or function), or as a plug-in module in application-specific hardware for an electronic device.

[0216] It should be noted that in many of the examples provided herein, interactions may be described in relation to two, three, four, or more electrical components; however, this is done for clarification and illustrative purposes only. It should be understood that the system may be established in any preferred manner. In line with similar design alternatives, any of the components, modules, and elements shown in the drawings may be combined in various possible configurations, all of which are clearly within the broad scope of this disclosure.

[0217] In some cases, referring to only a limited number of electrical components can more easily illustrate one or more functions of a given flowset. It should be understood that the electrical circuits and their teachings in the drawings are readily expandable and can accommodate more components, as well as more complex / sophisticated arrangements and configurations. Therefore, the examples provided are not intended to limit the scope or hinder the broader teaching of electrical circuits when potentially applied to countless other architectures.

[0218] Furthermore, as described, several embodiments may be embodied as one or more methods. The actions performed as part of the method may be ordered in any preferred manner. Thus, while they are shown as sequential actions in the exemplary embodiments, embodiments can be constructed in which actions are performed in a different order than those illustrated, which may include performing several actions simultaneously.

[0219] Interpretation of terms

[0220] All definitions defined and used herein should be understood to govern dictionary definitions, definitions incorporated by reference in documents, and / or the ordinary meaning of the defined terms. Unless otherwise explicitly requested, throughout this specification and the claims,

[0221] Words like "comprise" and "comprising" should be interpreted in a comprehensive sense, as opposed to an exclusive or exhaustive sense; that is, they should be interpreted as "including, but not limited to."

[0222] "Connected," "coupled," or any variation thereof means any direct or indirect connection or coupling between two or more elements, which may be physical, logical, or a combination thereof.

[0223] When used to describe this specification, the words “this specification,” “above,” “below,” and similar terms refer to this specification as a whole and not to any particular part thereof.

[0224] When "or" is used in relation to a list of two or more items, it encompasses all of the following interpretations of the word, any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0225] The singular forms "a," "an," and "the" also include the meaning of any appropriate plural form.

[0226] The terms used herein to indicate direction, such as "vertical," "transverse," "horizontal," "upward," "downward," "forward," "backward," "inward," "outward," "vertical," "transverse," "left," "right," "front," "back," "top," "bottom," "below," "above," and "under," depend on the specific direction of the apparatus described and illustrated. The subject matter described herein may assume various other directions. Therefore, these directional terms are not strictly defined and should not be interpreted narrowly.

[0227] As used herein and in the claims, the indefinite articles "a" and "an" should be understood to mean "at least one" unless explicitly indicated otherwise.

[0228] As used herein and in the claims, the phrase “and / or” should be understood to mean “either or both” of the elements thus combined, i.e., elements that exist as a combination in some cases and as separate in others. Multiple elements listed using “and / or” should be interpreted in the same way, i.e., “one or more” of the elements thus combined.

[0229] Elements other than those specifically identified by the "and / or" clause may be present at their discretion, regardless of whether they are related to those specifically identified elements. Thus, as a non-restrictive example, when used in combination with unrestrictive language such as "comprising," a reference to "A and / or B" may, in one embodiment, refer to A only (optionally including elements other than B), in another embodiment, refer to B only (optionally including elements other than A), and in yet another embodiment, refer to both A and B (optionally including other elements).

[0230] When used in the specification and claims herein, the phrase “at least one” relating to a list of one or more elements should be understood to mean at least one element selected from any one or more elements in the list of elements, and not necessarily including at least one of each element and all elements specifically listed in the list of elements, nor excluding any combination of elements in the list of elements. This definition also allows for the optional presence of elements other than those specifically identified in the list of elements referred to by the phrase “at least one,” whether related to or unrelated to those specifically identified elements.

[0231] Therefore, as a non-restrictive example, “at least one of A and B” (or equivalently, “at least one of A or B” or equivalently, “at least one of A and / or B”) may, in one embodiment, refer to A which optionally includes at least one or more elements and does not include B (and optionally includes elements other than B); in another embodiment, refer to B which optionally includes at least one or more elements and does not include A (and optionally includes elements other than A); and in yet another embodiment, refer to A which optionally includes at least one or more elements, and B which optionally includes at least one or more elements (and optionally includes other elements), etc.

[0232] As used herein, the term “between” should be inclusive unless otherwise indicated. For example, “between A and B” includes A and B unless otherwise indicated.

[0233] Furthermore, the terminology and grammar used herein are for illustrative purposes only and should not be considered limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein means to include the items and their equivalents listed thereafter, as well as any additional items.

[0234] In the claims and the above specification, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” and “composed of” should be understood as open-ended, meaning they include but are not limited to these. Only the transitional phrases “consisting of” and “consisting essentially of” are considered closed or partially closed transitional phrases, respectively.

[0235] Numerous other changes, substitutions, modifications, alterations and modifications may be apparent to those skilled in the art, and this disclosure is intended to encompass all such changes, substitutions, modifications, alterations and modifications within the scope of the appended claims.

[0236] For the United States Patent and Trademark Office (USPTO) and, additionally, to assist any reader of any patent issued in connection with this application in interpreting the claims attached herein, the Applicant hopes that the Applicant will be deemed to have (a) not intended to exercise any of the attached claims under Section 112(f) of the United States Patent Act as of the filing date of this application unless the words “means for” or “steps for” are specifically used in any particular claim, and (b) not intended to limit the Disclosure in any way not otherwise reflected in the attached claims by any statement herein.

[0237] Therefore, it should be considered that the present invention is not limited to the specific embodiments described above. Various modifications, equivalent processes, and many structures to which the present invention may be applicable will be readily apparent to those skilled in the art through a review of this disclosure. [Explanation of symbols]

[0238] 100 Systems 102 nodes 102-1 Main Node 102-2 Subnode 106 Bus 108 and peripheral devices 110 Hosts 120-node transceiver 122 transceivers 124 transceivers 126 Bus protocol circuit 127 Transceiver 128 Phase-Locked Loop (PLL) 129 transceivers 130 Voltage Regulator Circuit 131 Downstream bus interface circuit 132 Upstream bus interface circuit 136 transceivers 138 External devices 154 Control circuits 155 External devices 156 Preamble Circuit 157 External devices 158 Insertion Circuit 159 Test Circuit 160 Compression Circuit 162 Multiplexer (MUX) 164 Scramble Circuit 166 Descramble Circuit 168 Demultiplexer (DEMUX) 170 Restoration Circuit 180 Synchronized control frames 182 Preamble 184 Control Data 190 Superframe 192 Downstream transmission period 194 Upstream transmission period 196 Period of no transmission 197 Synchronized response frame 198 data slots 199 data slots 1200 placement 1202 data 1204 data 1300 device 1302 processing device 1304 memory 1306 display device 1308 audio output device 1310 another output device 1312 communication chip 1314 power supply circuit 1318 device 1320 another input device 1322 antenna 1324 audio input device 2110 calibration computer 2120 speaker 2130 reference microphone 2140 module 2140 microphone module 2141 microphone 2142 microphone 2143 memory 2143 microphone module 2200 method 2202 step 2204 step 2206 step 2208 step 2210 step 2220 method 2222 step 2224 step 2226 step 2240 method 2242 step 2244 step 2246 step 2248 step 2400 system 2413 memory 2423 memory 2430 microphone signal processing unit 2440 microphone signal sink 2450 Data Interface 2500 ways 2502 Steps 2504 steps 2506 steps 2508 steps 2510 Data Interface 2602 Main Node 2604 First subnode 2606 Second subnode 2608 Third subnode 2700 method 2702 Steps 2704 steps 2706 steps 2708 steps 2710 steps 2750 method 2752 steps 2754 steps 2756 steps 2758 steps 2760 steps

Claims

1. A system for microphone calibration, A loudspeaker configured to play a test signal, A microphone array configured to receive the aforementioned test signal and generate multiple microphone array signals, A reference microphone positioned between the loudspeaker and the microphone array, configured to receive the test signal and generate a reference signal, A calibration computer configured to process the plurality of microphone array signals and the reference signal, generate a set of filter coefficients, and transmit the set of filter coefficients to the microphone array, A system that includes these features.

2. The system according to claim 1, further comprising a memory associated with the microphone array, configured to store the set of filter coefficients.

3. The system according to claim 2, wherein the memory is positioned on a microphone array module together with the microphone array.

4. The system according to claim 2, wherein the memory is a cloud-based memory accessible by the microphone array.

5. The system according to claim 2, wherein the memory is further configured to store microphone information, which includes at least one of vendor information, product information, version information, model information, capability information, serial number, manufacturing information, configuration information, routing information, and authentication information.

6. The system according to claim 1, further comprising a plurality of memory modules, each of which is associated with each of the microphones of the microphone array.

7. The system according to claim 1, wherein the filter coefficients provide phase calibration and magnitude calibration.

8. The system according to claim 1, further comprising a two-wire interface, wherein the transmission of the filter coefficients to the microphone array occurs via the two-wire interface.

9. The system according to claim 1, wherein each of the plurality of microphone array signals is unique, and each microphone in the microphone array is associated with each subset of the set of filter coefficients.

10. A method for calibrating a microphone array, Playing a test signal through a loudspeaker, The test signal is sampled using a microphone array, The microphone array generates multiple microphone array signals, The test signal is sampled using a reference microphone, The aforementioned reference microphone generates a reference signal, Based on the plurality of microphone array signals and the reference signal, a set of filter coefficients is generated. Transmitting the set of filter coefficients to the microphone array, Methods that include...

11. The method according to claim 10, wherein sampling the test signal with the microphone array includes sampling the test signal with each microphone of the microphone array.

12. The method according to claim 11, wherein generating a set of filter coefficients includes generating a subset of filter coefficients for each respective microphone.

13. The method according to claim 12, further comprising storing each of the aforementioned subsets of filter coefficients in each respective microphone.

14. The method according to claim 10, further comprising storing the set of filter coefficients on the microphone array.

15. The method according to claim 10, wherein transmitting the set of filter coefficients includes transmitting the set of filter coefficients via a two-wire bus.

16. The method according to claim 10, further comprising pre-calibrating the loudspeaker using the reference microphone.

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