Semiconductor equipment

Abstract

To reduce the standby power or suppress the malfunction in a logic circuit performing clock gating.SOLUTION: A logic circuit includes a transistor that is turned off in a state that a potential difference exists between a source terminal and a drain terminal in a period for which a clock signal is not supplied. A channel formation region of the transistor is formed of an oxide semiconductor with reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019(atoms / cm3) or less. Thus, the leakage current of the transistor can be reduced. As a result, the standby power can be reduced and the malfunction can be suppressed in the logic circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a logic circuit. In particular, the channel formation region is composed of an oxide semiconductor. This relates to a logic circuit having a transistor. Furthermore, it relates to a semiconductor device having the logic circuit. To relate to.

[0002] In this specification, a semiconductor device is defined as a device that can function by utilizing semiconductor properties. This refers to all types of equipment, and includes electro-optical devices, semiconductor circuits, and electrical equipment, all of which are semiconductor devices. [Background technology]

[0003] Generally, Si-wafers and SOI (Silicon On Insulator) Circuits with transistors fabricated using this method have improved in terms of microfabrication and reduced operating voltage. The more you do this, the lower the power consumption becomes.

[0004] Power consumption is mainly due to the gate capacitance of the transistors, the inter-transistor and inter-circuit block capacitances. Dynamic power consumed by the charging and discharging of parasitic capacitance in connecting wiring, etc., and circuit The sum of static power consumed even when the device is not operating (hereinafter also called standby power) Yes.

[0005] One method to reduce this power consumption is a technique called clock gating. For example, see Patent Document 1). Clock gating is a method used to reduce power consumption. This is a technique that stops supplying a clock signal to a circuit during periods when that circuit is not operating. This reduces the power consumed by parasitic capacitance in the wiring that supplies the clock signal. It is possible. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2008-219882 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] Standby power is generally the power consumed by circuits that are not in operation (hereinafter referred to as non-operating circuits) and the power supply. The leakage current of an inverter (generally, the source-drain voltage when the gate-source voltage is 0V) It can be divided into the power consumed by the current flowing through it and the power consumed by the current.

[0008] While the clock gating described above can reduce dynamic power consumption, It is not possible to reduce static power consumption caused by current. Dynamic power consumption includes charging and discharging of parasitic capacitance in the wiring to which the clock signal is supplied. One example is the power consumption caused by this. Furthermore, in the circuit that performs clock gating... Therefore, the state of each element constituting the non-operating circuit is maintained. Power consumption due to current flow accounts for a high proportion of standby power. Also, transistor leakage The probability of logic circuits malfunctioning increases with current.

[0009] In view of the above-mentioned problems, one aspect of the present invention relates to a logic circuit that performs clock gating. One of the objectives is to reduce standby power consumption caused by leakage current or to suppress malfunctions. do. [Means for solving the problem]

[0010] One embodiment of the present invention relates to an impurity (hydrogen or By removing (such as water), it is a genuine or substantially genuine semiconductor, specifically a silicon semiconductor. A transistor in which a channel formation region is formed of an oxide semiconductor having a larger energy gap than silicon. It is applied to an N-type transistor in which a logic circuit has a transistor.

[0011] Specifically, the hydrogen contained in the oxide semiconductor is 5×10 19 (atoms / cm 3 ) or less , preferably 5×10 18 (atoms / cm 3 ) or less, more preferably 5×10 17 ( atoms / cm 3 ) or less, and the hydrogen or OH group contained in the oxide semiconductor is removed , and the carrier density is 5×10 14 / cm 3 or less, preferably 5×10 12 / cm 3 or less, and a logic circuit is configured by a transistor in which a channel formation region is formed of an oxide semiconductor. It is formed. It is.

[0012] The energy gap of the oxide semiconductor is >2 eV, preferably >2.5 eV, more preferably >3 eV, and impurities such as hydrogen that form donors are reduced as much as possible, and the carrier density is 5×10 / cm 14 or less, preferably 5×10 3 / cm 12 or less, and is made to be 3 like this. It is made.

[0013] By using the oxide semiconductor purified in this way for the channel formation region of the transistor, even when the channel width is 10 mm, when the drain voltage is 1 V and 10 V it is. In this configuration, when the gate voltage is in the range of -5V to -20V, the drain current is 1 × 10⁻¹⁰ -1 3 [A] It acts in such a way that the result is less than or equal to [A]. That is, the highly purified oxide semiconductor is transient By applying it to the channel formation region of the sta, leakage current can be significantly reduced. Cut.

[0014] In other words, one aspect of the present invention comprises a first period during which a clock signal is input, and the clock signal A logic circuit having a second period in which no input is received, wherein over the second period, source The transistor has a potential difference between the terminal and the drain terminal that turns off when a potential difference exists between the terminal and the drain terminal. The channel formation region of sta is when the hydrogen concentration is 5 × 10 19 (atoms / cm 3 ) The following oxidation This is a logic circuit characterized by being composed of semiconductor materials. [Effects of the Invention]

[0015] A logic circuit according to one aspect of the present invention provides a source terminal during a period when no clock signal is supplied. and has a transistor that turns off when a potential difference exists at the drain terminal. The channel-forming region of the sta is composed of an oxide semiconductor with a reduced hydrogen concentration. Specifically, the hydrogen concentration of the oxide semiconductor is 5 × 10⁻⁶. 19 (atoms / cm 3 ) Below Yes. Therefore, the leakage current of the transistor can be reduced. As a result, This reduces the standby power consumption of the logic circuit and suppresses malfunctions.

[0016] In particular, in logic circuits where clock gating is performed, the state within the logic circuit lasts for a long time. This will be maintained. In other words, a specific transistor between its source and drain terminals Such a transistor will remain switched off for an extended period of time while a potential difference exists. Applying this transistor as such has a significant effect.

[0017] Furthermore, by reducing the power consumption of the entire circuit, the logic circuit according to one embodiment of the present invention can be operated. The load on the external circuit can be reduced. This reduces the load on the logic circuit and the semiconductor having the external circuit. This will allow for functional expansion of the device. [Brief explanation of the drawing]

[0018] [Figure 1] A diagram showing an example of the logic circuit configuration described in Embodiment 1. [Figure 2] (A) A diagram showing an example configuration of the logic circuit described in Embodiment 2, and (B) A diagram showing an example of a timing chart. [Figure 3] (A) and (B) are diagrams showing example circuit configurations of the AND gate described in Embodiment 2. [Figure 4] Figure (A) shows an example of the configuration of a flip-flop, and (B) and (C) show examples of the circuit configuration of a NAND gate, as described in Embodiment 2. [Figure 5] (A) A diagram showing an example configuration of the logic circuit described in Embodiment 3, and (B) A diagram showing an example of a timing chart. [Figure 6] (A) and (B) are diagrams showing examples of the circuit configuration of the NOR gate described in Embodiment 3. [Figure 7] (A) A diagram showing an example configuration of the logic circuit described in Embodiment 4, and (B) A diagram showing an example of a timing chart. [Figure 8] Figure (A) shows an example of the configuration of a latch in the logic circuit described in Embodiment 4, and (B) and (C) show examples of the circuit configuration of an inverter. [Figure 9] A diagram showing an example of the logic circuit configuration described in Embodiment 5. [Figure 10]A diagram showing an example of the logic circuit configuration described in Embodiment 6. [Figure 11] A cross-sectional view showing an example configuration of a P-type transistor and an N-type transistor described in Embodiment 7. [Figure 12] (A) to (H) Cross-sectional views showing an example of the manufacturing process of a P-type transistor as described in Embodiment 7. [Figure 13] (A) to (G) Cross-sectional views showing an example of the manufacturing process of an N-type transistor described in Embodiment 7. [Figure 14] (A) to (D) Cross-sectional views showing an example of the manufacturing process of an N-type transistor described in Embodiment 7. [Figure 15] A cross-sectional view showing an example configuration of a P-type transistor and an N-type transistor described in Embodiment 7. [Figure 16] (A) and (B) are cross-sectional views showing examples of the configurations of the P-type transistor and N-type transistor described in Embodiment 7. [Figure 17] (A) and (B) are cross-sectional views showing examples of the configurations of the P-type transistor and N-type transistor described in Embodiment 7. [Figure 18] (A) and (B) are diagrams showing examples of the configurations of the P-type transistor and N-type transistor described in Embodiment 7. [Figure 19] (A) Plan view and (B) Cross-sectional view showing an example of the transistor configuration described in Embodiment 8. [Figure 20] (A) to (E) Cross-sectional views showing an example of the transistor fabrication process described in Embodiment 8. [Figure 21] (A) to (E) Cross-sectional views showing an example of the transistor fabrication process described in Embodiment 9. [Figure 22] (A) to (D) Cross-sectional views showing an example of the transistor fabrication process described in Embodiment 10. [Figure 23] (A) to (F) Figures showing examples of semiconductor devices described in Embodiment 11. [Figure 24] A figure showing the initial characteristics of an example of a thin-film transistor described in Example 1. [Figure 25](A), (B) Top view of an evaluation element for an example of a thin-film transistor described in Example 1. [Figure 26] (A) and (B) are figures showing the Vg-Id characteristics of an evaluation element, an example of a thin-film transistor described in Example 1. [Modes for carrying out the invention]

[0019] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention The present invention is not limited to the following description, and its form may not depart from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, The present invention is not limited to the embodiments described below.

[0020] Note that the source and drain terminals of a transistor are related to the transistor's structure and operating conditions. Because it can change depending on the factors, it is difficult to determine which is the source terminal or the drain terminal. It is difficult. Therefore, in this document, one of the source terminal and drain terminal is referred to as the first terminal. The other terminal, besides the source terminal and the drain terminal, will be referred to as the second terminal to distinguish them.

[0021] Furthermore, the size, layer thickness, or area of ​​each component shown in the drawings of each embodiment is as follows: The figures may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. It is not defined. Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification are not defined. This is added to avoid confusion regarding the constituent elements and does not mean that the number is limited. do.

[0022] (Embodiment 1) This embodiment describes an example of a logic circuit in which clock gating is performed. Specifically, the period during which a clock signal is input and the period during which a clock signal is not input are defined. An example of a logic circuit that has a clock signal and performs arithmetic processing using the clock signal is shown with reference to Figure 1. I will explain.

[0023] The logic circuit 10 shown in Figure 1 is a wiring that supplies pulse signals (PS) (hereinafter referred to as pulse signal lines). A first input terminal 11 is electrically connected to (also known as) and a data signal (Data) is supplied. A second input terminal 12 is electrically connected to the wiring (hereinafter also referred to as the data signal line), It has an output terminal 13. The logic circuit 10 receives a clock signal via a pulse signal line. It has a period during which (CK) is supplied and a period during which the clock signal is not supplied. That is, The logic circuit shown in Figure 1 is a logic circuit in which clock gating is performed. No clock signal supply means that the clock signal is not at a high or low potential. A fixed signal that changes from high level to low level and from low level to high level. This means that it will not be supplied.

[0024] Furthermore, the logic circuit 10 of this embodiment shown in Figure 1 includes a main logic circuit section 14 and a clock A state in which a potential difference exists between the source terminal and the drain terminal during a period when no signal is supplied. It has a transistor 15 that turns off when the transistor is turned off. The main logic circuit section 14 is a transistor It is composed of multiple elements, such as capacitive elements or resistive elements.

[0025] Furthermore, the channel formation region of transistor 15 has a hydrogen concentration of 5 × 10 19 (atoms / cm 3 ) Preferably 5 × 10 18 (atoms / cm 3 ) More preferably, is 5 x 10 17 (atoms / cm 3 It is composed of the following oxide semiconductors. In other words, transistor 15 reduces the hydrogen, which acts as a carrier donor, to an extremely low concentration. This transistor utilizes a highly purified oxide semiconductor applied to the channel formation region. The hydrogen concentration in the oxide semiconductor layer was measured by secondary ion mass spectrometry (SIMS). This was done using an environmental ion mass spectroscopy. .

[0026] The logic circuit of this embodiment is a logic circuit in which clock gating is performed, and the During the period when lock gating is performed (i.e., the period when no clock signal is input) It has a transistor that turns off when there is a potential difference between the source terminal and the drain terminal. The transistor has a channel formation region formed by an oxide semiconductor. The hydrogen concentration in a semiconductor is 5 × 10⁻⁶ 19 (atoms / cm 3 ) Preferably 5 × 10 18 (atoms / cm 3 ) More preferably 5 × 10 17 (atoms / cm 3 It is controlled to be below ). Therefore, the off-current of the transistor is set to 1 × 10⁻⁶. -13 [A] It is possible to reduce it to the lower level. In other words, the charge leakage through the transistor can be reduced. It can be suppressed. As a result, standby power consumption during that period can be reduced and This makes it possible to suppress malfunctions in logic circuits in between.

[0027] In particular, in logic circuits where clock gating is performed, the state within the logic circuit lasts for a long time. This will be maintained. In other words, a specific transistor between its source and drain terminals Such a transistor will remain switched off for an extended period of time while a potential difference exists. Applying this transistor as such has a significant effect.

[0028] Furthermore, by reducing the power consumption of the logic circuit, the operation of the logic circuit of this embodiment is made easier. The load on the internal circuit can be reduced. This reduces the load on the semiconductor having the logic circuit and the external circuit. This will allow for expansion of the device's functionality.

[0029] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0030] (Embodiment 2) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically For logic circuits having an AND gate and a flip-flop, refer to Figures 2 to 4. I'll explain while doing so.

[0031] <Example of logic circuit configuration> The logic circuit 200 of this embodiment shown in Figure 2(A) has a first input terminal which receives an enable signal. It is electrically connected to the wiring that supplies (EN) (hereinafter also called the enable signal line), and the second The input terminal is connected to the wiring that supplies the clock signal (CK) (hereinafter also referred to as the clock signal line). The electrically connected AND gate 201 and the first input terminal are electrically connected to the data signal line. The second input terminal is electrically connected to the output terminal of the AND gate 201, and the flip It has flop 202.

[0032] Furthermore, the flip-flop 202 in the logic circuit of this embodiment utilizes a feedback mechanism. This is a circuit that can hold 1 bit of data. Also, the output signal of flip-flop 202 The number represents the output signal of logic circuit 200.

[0033] <Example of logic circuit operation> The operation of the logic circuit shown in Figure 2(A) can be understood by referring to the timing chart shown in Figure 2(B). I will explain below while referring to the following.

[0034] During period T1, the enable signal line functions as a wire supplying a high-level signal. Therefore, the output signal (AND(Out)) of the AND gate 201 is the clock signal. (CK) is the result. In other words, the second input terminal of flip-flop 202 receives the clock signal. (CK) is input. Flip-flop 202 responds to the input clock signal (CK) It works better. Specifically, flip-flop 202 works better when the clock signal (CK) is low. The data signal (D0 or D1) is captured when the bell changes to a high level, and the clock signal The data signal is output when the CK signal changes from a high level to a low level.

[0035] During period T2, the enable signal line functions as a wire supplying a low-level signal. Therefore, the output signal (AND(Out)) of the AND gate 201 is low level. This becomes a signal. In other words, a low-level signal is sent to the second input terminal of flip-flop 202. This is input. At this time, the output signal (Out) of the logic circuit maintains the data signal (D1). ru.

[0036] During period T3, the enable signal line is again wired to supply a high-level signal. functions. That is, similar to period T1, flip-flop 202 captures the data signal (D2 or D3) when the clock signal (C K) changes from the low level to the high level, and outputs the data signal when the clock signal (CK) changes from the high level to the low level. forces it.

[0037] In the logic circuit of this embodiment, the clock signal input to flip-flop 20 2 is controlled by the enable signal (EN). That is, it is a logic circuit in which clock gating is performed on flip-flop 202.

[0038] Note that the logic circuit of this embodiment reads data when the clock signal input to flip-flop 202 changes to the high level, and holds the read data during one clock period. Therefore, the output signal (Out) of the logic circuit is temporarily held even after the elapse of period T1 or period T3 during which flip-flop 202 is operating.

[0039] <Circuit configuration example of AND gate and flip-flop> A specific circuit configuration example of AND gate 201 included in the logic circuit shown in Fig. 2(A) is shown in Figs. 3 (A) and (B), and a specific circuit configuration example of flip-flop 202 is shown in Figs. 4(A) to ( C).

[0040] The AND gate shown in Fig. 3(A) includes transistors 211 to 216. Transistors 211, 214, and 215 are P-type transistors, and trans istors 212, 213, and 216 are N-type transistors.

[0041] Transistor 211 has its gate terminal electrically connected to the enable signal line, and its first terminal It is electrically connected to the wiring that supplies the high power potential (VDD) (hereinafter also referred to as the high power potential line). It will be done.

[0042] Transistor 212 has its gate terminal connected to the enable signal line and the gate of transistor 211. The terminal is electrically connected to the terminal, and the first terminal is electrically connected to the second terminal of transistor 211. It can be done.

[0043] Transistor 213 has its gate terminal electrically connected to the clock signal line, and its first terminal is It is electrically connected to the second terminal of transistor 212, and the second terminal is at the low power supply potential (VSS) It is electrically connected to the supply wiring (hereinafter also referred to as the low power potential line).

[0044] Transistor 214 has its gate terminal connected to the clock signal line and the gate of transistor 213. The terminals are electrically connected, with the first terminal electrically connected to a high power potential line, and the second terminal is connected to a transistor. It is electrically connected to the second terminal of transistor 211 and the first terminal of transistor 212.

[0045] Transistor 215 has its gate terminal at the second terminal of transistor 211, and transistor 2 It is electrically connected to the first terminal of 12 and the second terminal of transistor 214, and the first terminal is high voltage It is electrically connected to the source potential line.

[0046] Transistor 216 has its gate terminal at the second terminal of transistor 211, and transistor 2 The first terminal of transistor 12, the second terminal of transistor 214, and the gate terminal of transistor 215 Electrically connected, the first terminal is electrically connected to the second terminal of transistor 215, and the second The terminals are electrically connected to the low power supply potential line.

[0047] Furthermore, in this AND gate, the second terminal of transistor 215 and transistor 216 The potential of the node to which the first terminal is electrically connected is the output signal of the AND gate (AND(Out It will be output as )).

[0048] Furthermore, in this specification, high power supply potential (VDD) and low power supply potential (VSS) are defined as follows: When comparing them, if the high power supply potential (VDD) is higher than the low power supply potential (VSS), then which The potential may be such that, for example, the low power supply potential (VSS) may be the ground potential or 0V. By applying various methods, it is possible to apply any positive potential as the high power supply potential (VDD).

[0049] The AND gate shown in Figure 3(B) has transistors 221 to 225. Furthermore, transistors 221 through 225 are N-type transistors. Furthermore, transistors 221 through 225 are enhancements when the threshold voltage is positive. It is a sment-type transistor.

[0050] Transistor 221 has its gate terminal and first terminal electrically connected to a high power supply potential line. .

[0051] Transistor 222 has its gate terminal electrically connected to the enable signal line, and terminal 1 This is electrically connected to the second terminal of transistor 221.

[0052] Transistor 223 has its gate terminal electrically connected to the clock signal line, and its first terminal is It is electrically connected to the second terminal of transistor 222, and the second terminal is electrically connected to the low power supply potential line. Connected.

[0053] Transistor 224 has its gate terminal and first terminal electrically connected to a high power supply potential line. .

[0054] Transistor 225 has a gate terminal that is the second terminal of transistor 221 and transistor It is electrically connected to the first terminal of 222, and the first terminal is electrically connected to the second terminal of transistor 224. They are connected, and the second terminal is electrically connected to the low power potential line.

[0055] Furthermore, in this AND gate, the second terminal of transistor 224 and transistor 225 The potential of the node to which the first terminal is electrically connected is the output signal of the AND gate (AND(Out It will be output as )).

[0056] Furthermore, transistors 221 and 224 have high current at their gate terminal and first terminal. It is an enhancement-type transistor electrically connected to the source potential line. Transistors 221 and 224 remain in the ON state regardless of the time period. Transistors 221 and 224 are used as resistive elements.

[0057] Furthermore, the first and second input terminals of the AND gate are interchangeable. That is, In the above explanation, the terminal specified to be electrically connected to the enable signal line is the clock signal A terminal defined as being electrically connected to a line and also electrically connected to a clock signal line It is possible to configure it by electrically connecting it to the bull signal line.

[0058] The flip-flop shown in Figure 4(A) consists of NAND gates 231 to 23 It has 4.

[0059] The NAND gate 231 has a first input terminal electrically connected to a data signal line, and a second The input terminal is electrically connected to the output terminal of the AND gate.

[0060] The NAND gate 232 has a first input terminal that electrically connects to the output terminal of the NAND gate 231. It is connected to the output terminal of the AND gate and the second input of the NAND gate 231, with the second terminal being the output terminal of the AND gate and the second input of the NAND gate 231. It is electrically connected to the terminal.

[0061] The NAND gate 233 has a first input terminal which is connected to the output terminal of the NAND gate 231 and NA It is electrically connected to the first input terminal of the ND gate 232.

[0062] The NAND gate 234 has a first input terminal that electrically connects to the output terminal of the NAND gate 233. The second input terminal is connected to the output terminal of the NAND gate 232, and the output The power terminal is electrically connected to the second input terminal of the NAND gate 233.

[0063] The flip-flop shown in Figure 4(A) is a delay-type flip-flop. The flip-flop in this embodiment is a delay type that uses only the Q terminal as the output terminal. Although it is a flip-flop, the Q terminal and QB terminal (output terminal of NAND gate 234) It may also have a configuration with two output terminals.

[0064] Furthermore, the flip-flop shown in Figure 4(A) is just one example, and the flip in this embodiment... The flop is not limited to this configuration. That is, the flip-flop of this embodiment is a return Any circuit configuration is acceptable as long as it can hold 1 bit of data using the return function.

[0065] Figures 4(B) and (C) show the applicable configurations for NAND gates 231 through 234. Here are some specific examples of such circuits.

[0066] The NAND gate shown in Figure 4(B) has transistors 241 to 244. Note that transistors 241 and 244 are P-type transistors, and transistor 2 42 and 243 are N-type transistors.

[0067] Transistor 241 has its gate terminal electrically connected to the first input terminal of the NAND gate. Then, the first terminal is electrically connected to the high power potential line.

[0068] Transistor 242 has a gate terminal which is the first input terminal of the NAND gate and transistor It is electrically connected to the gate terminal of transistor 241, and the first terminal is connected to the second terminal of transistor 241. It is electrically connected.

[0069] Transistor 243 has its gate terminal electrically connected to the second input terminal of the NAND gate. The first terminal is electrically connected to the second terminal of transistor 242, and the second terminal is a low power supply. It is electrically connected to the potential line.

[0070] Transistor 244 has a gate terminal which is the second input terminal of the NAND gate and a transistor The gate terminal of TA243 is electrically connected, and the first terminal is electrically connected to the high power potential line. The second terminal electrically connects to the second terminal of transistor 241 and the first terminal of transistor 242. It connects to the network.

[0071] Furthermore, in the NAND gate, the second terminal of transistor 241 and transistor 242 The potential of the node to which the first terminal and the second terminal of transistor 244 are electrically connected is NAN It is output as the output signal of the D gate.

[0072] The NAND gate shown in Figure 4(C) has transistors 251 to 253. Yes. Note that transistors 251 through 253 are N-type transistors. In addition, transistors 251 to 253 have a threshold voltage that is positive. It is a compression-type transistor.

[0073] Transistor 251 has its gate terminal and first terminal electrically connected to a high power supply potential line. .

[0074] Transistor 252 has its gate terminal electrically connected to the first input terminal of the NAND gate. The first terminal is then electrically connected to the second terminal of transistor 251.

[0075] Transistor 253 has its gate terminal electrically connected to the second input terminal of the NAND gate. The first terminal is electrically connected to the second terminal of transistor 252, and the second terminal is a low power supply. It is electrically connected to the potential line.

[0076] Furthermore, in the NAND gate, the second terminal of transistor 251 and transistor 25 The potential of the node to which the first terminal of 2 is electrically connected is output as the output signal of the NAND gate. It can be done.

[0077] Furthermore, the first and second input terminals of the NAND gate are interchangeable. The terminal specified in the above description to be electrically connected to the first input terminal of the NAND gate The child is electrically connected to the second input terminal of the NAND gate, and the second of the NAND gate The terminals defined as being electrically connected to the input terminals are electrically connected to the first input terminal of the NAND gate. It is possible to configure it to be connected to [this].

[0078] The logic circuit of this embodiment has NAND gates 231 to 234 At least one channel formation region of transistors 242, 243, 252, and 253 is acid It is composed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is 5 × 10⁻⁶. 19 (ato ms / cm 3 ) Preferably 5 × 10 18 (atoms / cm 3 ) Below are some further preferences Or 5x10 17 (atoms / cm 3 ) is controlled below. Therefore, the transition The off-current of the sta is 1 × 10 -13 It is possible to reduce it to [A] or lower. In other words, The charge leakage through the transistor during the period when clock gating is performed It can be suppressed. As a result, standby power consumption during that period can be reduced and This makes it possible to suppress malfunctions in logic circuits in between.

[0079] Furthermore, the AND gate 201 in the logic circuit of this embodiment is shown in Figure 3(B). The AND gate shown above is applied to flip-flop 202, and the NAN shown in Figure 4(C) is generated. By applying a Delay-type flip-flop constructed with a D gate, the logic All transistors that make up the circuit can be N-type transistors. N-type transistor is the above-mentioned transistor (channel formation region, hydrogen concentration 5 × 10 19 (atoms / cm 3 (The transistor is composed of the following oxide semiconductors.) As a result, it is possible to achieve low power consumption in a logic circuit that is composed only of N-type transistors. This is possible. Furthermore, by constructing the logic circuit using only N-type transistors, the manufacturing process can be streamlined. This can reduce the yield of the logic circuit and lower manufacturing costs. It can be made to happen.

[0080] Furthermore, by reducing the power consumption of the logic circuit, the operation of the logic circuit of this embodiment is made easier. The load on the internal circuit can be reduced. This reduces the load on the semiconductor having the logic circuit and the external circuit. This will allow for expansion of the device's functionality.

[0081] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0082] (Embodiment 3) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically For a logic circuit having a NOR gate and a flip-flop, see Figures 5 and 6. I'll explain while doing so.

[0083] <Example of logic circuit configuration> The logic circuit 500 of this embodiment shown in Figure 5(A) has a first input terminal which receives an enable signal. The wire is electrically connected, and the second input terminal supplies the inverted clock signal (CKB). A NOR gate 501 electrically connected to the inverting clock signal line (hereinafter also referred to as the first) The input terminal of the first is electrically connected to the data signal line, and the second input terminal of the NOR gate 501 It has a flip-flop 502 electrically connected to the output terminal.

[0084] Furthermore, the flip-flop 502 in the logic circuit of this embodiment utilizes a feedback mechanism. This is a circuit that can hold 1 bit of data. Also, the output signal of the flip-flop 502 The number represents the output signal of logic circuit 500.

[0085] <Example of logic circuit operation> The operation of the logic circuit shown in Figure 5(A) can be understood by referring to the timing chart shown in Figure 5(B). I will explain below while referring to the following.

[0086] During period T4, the enable signal line functions as a wire supplying a low-level signal. Therefore, the output signal (NOR(Out)) of the NOR gate 501 is the clock signal. (CK) is the result. In other words, the second input terminal of the flip-flop 502 receives the clock signal. (CK) is input. Flip-flop 502 responds to the input clock signal (CK) It works better. Specifically, the flip-flop 502 works better when the clock signal (CK) is low. The data signal (D4 or D5) is captured when the bell changes to a high level, and the clock signal The data signal is output when the CK signal changes from a high level to a low level.

[0087] During period T5, the enable signal line functions as a wire supplying a high-level signal. Therefore, the output signal of the NOR gate 501 (NOR(Out)) is low level. This becomes a signal. In other words, a low-level signal is sent to the second input terminal of the flip-flop 502. This is input. At this time, the output signal (Out) of the logic circuit maintains the data signal (D5). ru.

[0088] During period T6, the enable signal line is again wired to supply a low-level signal. It functions. That is, similar to period T4, flip-flop 502 captures the data signal (D6 or D7) when the clock signal (C K) changes from the low level to the high level, and outputs the data signal when the clock signal (CK) changes from the high level to the low level .

[0089] In the logic circuit of this embodiment, the clock signal input to flip-flop 50 2 is controlled by the enable signal (EN). That is, it is a logic circuit in which clock gating is performed on flip-flop 502 .

[0090] Note that the logic circuit of this embodiment reads data when the clock signal input to flip-flop 502 is at the high level, and holds the read data during one clock cycle . Therefore, the output signal (Out) of the logic circuit is temporarily held even after the elapse of period T4 or period T6 during which flip-flop 502 is operating .

[0091] <Circuit configuration example of NOR gate and flip-flop> A specific circuit configuration example of NOR gate 501 included in the logic circuit shown in FIG. 5(A) is shown in FIGS. 6 (A) and (B). Note that for flip-flop 5 02 included in the logic circuit shown in FIG. 5(A), the Delay type flip-flop shown in FIG. 4(A) can be applied[[ID=3)) . Therefore, here, for the specific circuit configuration example of flip-flop 502, the above description will be incorporated . Hereinafter, the specific circuit configuration example of NOR gate 501 will be described with reference to FIGS. 6(A) and (B)<0000%23>.

[0092] The NOR gate shown in FIG. 6(A) includes transistors 511 to 514​​ Note that transistors 511 and 512 are P-type transistors, and transistor 51 3.514 is an N-type transistor.

[0093] Transistor 511 has its gate terminal electrically connected to the enable signal line, and terminal 1 It is electrically connected to the wiring that supplies the high power potential (VDD) (hereinafter also referred to as the high power potential line). It will be done.

[0094] Transistor 512 has its gate terminal electrically connected to the inverting clock signal line, and the first terminal The child is electrically connected to the second terminal of transistor 511.

[0095] Transistor 513 has its gate terminal connected to the inverting clock signal line and the gate of transistor 512. The terminal is electrically connected, and the first terminal is electrically connected to the second terminal of transistor 512. Then, the second terminal is electrically connected to the low power supply potential line.

[0096] Transistor 514 has its gate terminal connected to the enable signal line and the gate of transistor 511. The terminal is electrically connected, and the first terminal is the second terminal of transistor 512 and the transistor The first terminal of 513 is electrically connected, and the second terminal is electrically connected to the low power supply potential line.

[0097] Furthermore, in this NOR gate, the second terminal of transistor 512 and transistor 513 The potential of the node to which the first terminal and the first terminal of transistor 514 are electrically connected is NOR gate It is output as the output signal (NOR(Out)).

[0098] The NOR gate shown in Figure 6(B) has transistors 521 to 523. Furthermore, transistors 521 through 523 are N-type transistors. Furthermore, transistors 521 through 523 are enhancements where the threshold voltage is positive. It is a sment-type transistor.

[0099] Transistor 521 has its gate terminal and first terminal electrically connected to a high power supply potential line. .

[0100] Transistor 522 has its gate terminal electrically connected to the inverting clock signal line, and the first terminal The child is electrically connected to the second terminal of transistor 521, and the second terminal is electrically connected to the low power supply potential line. It connects to the target.

[0101] Transistor 523 has its gate terminal electrically connected to the enable signal line, and terminal 1 This is electrically connected to the second terminal of transistor 521 and the first terminal of transistor 522. The second terminal is electrically connected to the low power potential line.

[0102] Furthermore, in this NOR gate, the second terminal of transistor 521 and transistor 522 The potential of the node to which the first terminal and the first terminal of transistor 523 are electrically connected is NOR gate It is output as the output signal (NOR(Out)).

[0103] Furthermore, the gate terminal and first terminal of transistor 521 are electrically connected to the high power supply potential line. It is an enhanced transistor. Therefore, transistor 521 is a period It remains in the ON state regardless. In other words, transistor 521 is used as a resistive element. It is being done.

[0104] Furthermore, the first and second input terminals of the NOR gate are commutative. That is, In the above explanation, the terminal specified to be electrically connected to the enable signal line is the inverting clock A terminal defined as being electrically connected to a signal line and also electrically connected to an inverting clock signal line. It is possible to configure this by electrically connecting it to the enable signal line.

[0105] The logic circuit of this embodiment is a trace circuit in which the channel formation region is made of an oxide semiconductor. It has an radiator. The hydrogen concentration of the oxide semiconductor is 5 × 10 19 (atoms / cm 3 ) Preferably 5 × 10 18 (atoms / cm 3 ) More preferably 5 × 1 0 17 (atoms / cm 3 ) is controlled below this level. Therefore, the off-power of the transistor is controlled below this level. Flow 1 x 10 -13 It is possible to reduce it to [A] or lower. In other words, clock games To suppress charge leakage through the transistor during the period in which the tuning is performed. This can be achieved. As a result, standby power consumption during that period can be reduced and the discussion during that period can be reduced. This makes it possible to suppress malfunctions in the circuitry.

[0106] Furthermore, the NOR gate 501 in the logic circuit of this embodiment is shown in Figure 6(B). The NOR gate shown is applied to the flip-flop 502, and the NAN gate shown in Figure 4(C) is generated. By applying a Delay-type flip-flop constructed with a D gate, the logic All transistors that make up the circuit can be N-type transistors. N-type transistor is the above-mentioned transistor (channel formation region, hydrogen concentration 5 × 10 19 (atoms / cm 3(The transistor is composed of the following oxide semiconductors.) As a result, it is possible to achieve low power consumption in a logic circuit that is composed only of N-type transistors. This is possible. Furthermore, by constructing the logic circuit using only N-type transistors, the manufacturing process can be streamlined. This can reduce the yield of the logic circuit and lower manufacturing costs. It can be made to happen.

[0107] Furthermore, by reducing the power consumption of the logic circuit, the operation of the logic circuit of this embodiment is made easier. The load on the internal circuit can be reduced. This reduces the load on the semiconductor having the logic circuit and the external circuit. This will allow for expansion of the device's functionality.

[0108] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0109] (Embodiment 4) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically This refers to a logic circuit having a latch and a flip-flop, with reference to Figures 7 and 8. I will explain.

[0110] <Example of logic circuit configuration> The logic circuit 600 of this embodiment shown in Figure 7(A) has a first input terminal which receives an enable signal. The wire is electrically connected, and the second input terminal is electrically connected to the inverting clock signal line. The first input terminal of the Chi 601 is electrically connected to the data signal line, and the second input terminal is connected to the RAT. It has a flip-flop 602 electrically connected to the output terminal of the 601.

[0111] Furthermore, the flip-flop 602 in the logic circuit of this embodiment utilizes a feedback mechanism. This is a circuit that can hold 1 bit of data. Also, the output signal of the flip-flop 602 The number represents the output signal of logic circuit 600.

[0112] Furthermore, the latch 601 of this embodiment can latch data in any way. This configuration is also acceptable. Here, when a high-level signal is supplied to the first input terminal, the second A circuit that latches and outputs the inverted signal of the signal input to the input terminal is applied to latch 601. ru.

[0113] <Example of logic circuit operation> Refer to the timing chart shown in Figure 7(B) for the operation of the logic circuit shown in Figure 7(A). I will explain below while referring to the following.

[0114] During period T7, the enable signal line functions as a wire supplying a high-level signal. At this time, the output signal of latch 601 (Latch(Out)) is the clock signal (C K) is the result. In other words, the second input terminal of the flip-flop 602 receives the clock signal (C A clock signal (CK) is input. The flip-flop 602 responds to the input clock signal (CK) It works. Specifically, the flip-flop 602 operates when the clock signal (CK) is at a low level. The data signal (D8 or D9) is captured when it changes to a high level, and the clock signal ( The data signal is output when CK changes from a high level to a low level.

[0115] During period T8, the enable signal line functions as a wire supplying a low-level signal. At this time, the output signal (Latch(Out)) of latch 601 remains at a low level. In other words, a low-level signal is input to the second input terminal of the flip-flop 602. This occurs. At this time, the output signal (Out) of the logic circuit maintains the data signal (D9).

[0116] During period T9, the enable signal line is again wired to supply a high-level signal. It functions in this way. In other words, similar to period T7, flip-flop 602 receives the clock signal (C The data signal (D10 or D11) is taken when K) changes from a low level to a high level. In addition, when the clock signal (CK) changes from a high level to a low level, the data signal Outputs.

[0117] In the logic circuit of this embodiment, the flip-flop 60 is activated by the enable signal (EN). The clock signal (CK) input to 2 is controlled. In other words, the flip-flop 602 controls... In contrast, this is a logic circuit where clock gating is performed.

[0118] In this embodiment, the logic circuit receives the clock signal input to the flip-flop 602. When the signal level is high, data is read, and the read data is held for one clock cycle. Therefore, the output signal (Out) of the logic circuit is when the flip-flop 602 is operating. It remains temporarily retained even after the period T7 or period T9 has elapsed.

[0119] <Examples of latch and flip-flop circuit configurations> Figure 8(A) shows a specific circuit configuration example of the latch 601 in the logic circuit shown in Figure 7(A). As shown in (C). Note that the flip-flop 602 in the logic circuit shown in Figure 7(A) It is possible to apply the Delay-type flip-flop shown in Figure 4(A). Therefore, here, regarding the specific circuit configuration example of the flip-flop 602, the description above will be incorporated herein. Below, the specific circuit configuration example of the latch 601 will be described with reference to FIGS. 8( (A) to (C).

[0120] The latch shown in FIG. 8(A) includes a transistor 611, an inverter 612, and an inverter 613. Note that the transistor 611 is an N-type transistor.

[0121] The gate terminal of the transistor 611 is electrically connected to the enable signal line, and the first terminal is electrically connected to the inverted clock signal line.

[0122] The input terminal of the inverter 612 is electrically connected to the second terminal of the transistor 611 .

[0123] The input terminal of the inverter 613 is electrically connected to the output terminal of the inverter 612, and the output terminal is electrically connected to the second terminal of the transistor 611 and the input terminal of the inverter 612 .

[0124] In this latch, the output signal of the inverter 612 is output as the output signal of the latch (Latch (Out)).

[0125] FIGS. 8(B) and (C) show specific examples of circuits applicable to the inverter 612 and the inverter 613.

[0126] The inverter shown in FIG. 8(B) includes a transistor 621 and a transistor 622 . Note that the transistor 621 is a P-type transistor, and the transistor 622 is an N-type transistor.

[0127] Transistor 621 has its gate terminal electrically connected to the input terminal of the inverter, and the first The terminal is electrically connected to the high-power potential line.

[0128] Transistor 622 has its gate terminal connected to the input terminal of the inverter and transistor 621. The gate terminal is electrically connected, and the first terminal is electrically connected to the second terminal of transistor 621. The second terminal is then electrically connected to the low power supply potential line.

[0129] Furthermore, in this inverter, the second terminal of transistor 621 and transistor 622 The potential of the node to which the first terminal is electrically connected is output as an output signal.

[0130] The inverter shown in Figure 8(C) has transistors 631 and 632. Furthermore, transistors 631 and 632 are N-type transistors. Transistors 631 and 632 are enhancements where the threshold voltage is positive. It is a ment-type transistor.

[0131] Transistor 631 has its gate terminal and first terminal electrically connected to a high power supply potential line. .

[0132] Transistor 632 has its gate terminal electrically connected to the input terminal of the inverter, and the first The terminal is electrically connected to the second terminal of transistor 631, and the second terminal is electrically connected to the low power supply potential line. They are connected electrically.

[0133] Furthermore, in this inverter, the second terminal of transistor 631 and transistor 632 The potential of the node to which the first terminal is electrically connected is output as an output signal.

[0134] In the above description, the case where the transistor 611 is an N-type transistor has been described. However, the transistor 611 can also be a P-type transistor. In this case, by inverting the enable signal, it is possible to perform the same operation as the above operation. The logic circuit of this embodiment includes a transistor whose channel formation region is formed of an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is controlled to be 5×10 (atoms / cm 19 ) or less, preferably 5×10 3 (atoms / cm ) or less, and more preferably 5×1 18 (atoms / cm 3 ) or less. Therefore, the off-current of the transistor can be reduced to 1×10 17 (atoms / cm 3 ) or less. That is, it is possible to suppress the leakage of charges through the transistor during the period when clock gating is performed. As a result, it is possible to reduce the standby power during that period and suppress the malfunction of the logic circuit during that period.

[0135] -13 [A] or less. [[ID=3l]]

[0136] Furthermore, as the latch 601 included in the logic circuit of this embodiment, a latch composed of the inverter shown in FIG. 8(C) is applied, and as the flip-flop 602, a Delay type flip-flop composed of the NAND gate shown in FIG. 4(C ) is applied. By doing so, all the transistors constituting the logic circuit can be N-type transistors. These N-type transistors are the above transistors (the channel formation region has a hydrogen concentration of 5×10 (atoms / cm 19 ) or less, preferably 5×10 3 (atoms / cm 19 ) or less, and more preferably 5×1 3 (atoms / cm 18) Transistors composed of the following oxide semiconductors By using (zistar), it is a logic circuit composed only of N-type transistors, It is possible to reduce power consumption. Also, the logic circuit can be constructed using only N-type transistors. This reduces the manufacturing process and improves the yield of the logic circuit. It can reduce manufacturing costs.

[0137] Furthermore, by reducing the power consumption of the logic circuit, the operation of the logic circuit of this embodiment is made easier. The load on the internal circuit can be reduced. This reduces the load on the semiconductor having the logic circuit and the external circuit. This will allow for expansion of the device's functionality.

[0138] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0139] (Embodiment 5) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically For a logic circuit having an AND gate and multiple flip-flops, refer to Figure 9. I'll explain while doing so.

[0140] The logic circuit 800 of this embodiment shown in Figure 9 includes an AND gate 801 and a flip-flop It has a group of flip-flops 805 that includes 802-804.

[0141] The AND gate 801 has a first input terminal electrically connected to an enable signal line, and a second input terminal. The input terminal is electrically connected to the clock signal line.

[0142] The flip-flop 802 has its first input terminal electrically connected to a data signal line, and its second The input terminal of the AND gate 801 is electrically connected to the output terminal of the AND gate 801.

[0143] Flip-flop 803 has its first input terminal connected to the output terminal of flip-flop 802. The two input terminals are electrically connected, and the second input terminal is electrically connected to the output terminal of the AND gate 801. .

[0144] Flip-flop 804 has its first input terminal connected to the output terminal of flip-flop 803. The two input terminals are electrically connected, and the second input terminal is electrically connected to the output terminal of the AND gate 801. .

[0145] Note that the output signal of the flip-flop 804 is the same as the output signal (Out) of the logic circuit 800. Yes.

[0146] Furthermore, the flip-flops 802 to 804 in the logic circuit of this embodiment provide feedback. This is a circuit that can hold 1 bit of data using [a specific method / technique]. For example, the Dela shown in Figure 4. A Y-type flip-flop can be applied.

[0147] In the logic circuit of this embodiment, the enable signal (EN) activates the flip-flop group 8 The clock signal input to 05 is controlled. In other words, it controls the flip-flop group 805. This is a logic circuit where clock gating is performed.

[0148] Furthermore, the second and subsequent flip-flops included in the 805 flip-flop group are the first The input terminal is electrically connected to the output terminal of the preceding flip-flop. In the form of a logic circuit, the data signal is input during the period when a clock signal is input. ) is a shift register that sequentially shifts the flip-flops.

[0149] The logic circuit of this embodiment is a trace circuit in which the channel formation region is made of an oxide semiconductor. It has an radiator. The hydrogen concentration of the oxide semiconductor is 5 × 10 19 (atoms / cm 3 ) Preferably 5 × 10 18 (atoms / cm 3 ) More preferably 5 × 1 0 17 (atoms / cm 3 ) is controlled below this level. Therefore, the off-power of the transistor is controlled below this level. Flow 1 x 10 -13 It is possible to reduce it to [A] or lower. In other words, clock games To suppress charge leakage through the transistor during the period in which the tuning is performed. This can be achieved. As a result, standby power consumption during that period can be reduced and the discussion during that period can be reduced. This makes it possible to suppress malfunctions in the circuitry.

[0150] Furthermore, the logic circuit of this embodiment includes an AND gate 801 and a group of flip-flops. All of the transistors that make up the 805 can be N-type transistors. The N-type transistor is the above-mentioned transistor (the channel formation region has a hydrogen concentration of 5 × 10 1 9 (atoms / cm 3 (The transistor is composed of the following oxide semiconductors.) This allows for low power consumption in a logic circuit composed solely of N-type transistors. It is possible to construct the logic circuit using only N-type transistors. This can reduce the number of defects, improve the yield of the logic circuit, and lower manufacturing costs. It can be reduced.

[0151] Furthermore, by reducing the power consumption of the logic circuit, the operation of the logic circuit of this embodiment is made easier. The load on the internal circuit can be reduced. This reduces the load on the semiconductor having the logic circuit and the external circuit. This will allow for expansion of the device's functionality.

[0152] In this embodiment, a logic circuit having three flip-flops is shown. However, the number of flip-flops in the logic circuit of this embodiment is not limited to three. In other words, the logic circuit of this embodiment includes a first flip-flop to the nth (where n is a natural number) This also includes logic circuits having a flip-flop. A flip-flop of type k (where n is a natural number less than or equal to n) has a first input terminal that is the k-1 flip-flop. The output terminal of the top is electrically connected, and the output terminal of the AND gate 801 is connected to the second input terminal. It is electrically connected.

[0153] Furthermore, in this embodiment, the first input terminal of the second and subsequent flip-flops is connected to the previous stage's flip-flop. The diagram shows a configuration in which the output signal of a lip-flop is input, but the logic circuit of this embodiment The configuration is not limited to this configuration. For example, a flip-flop can be accessed from outside the logic circuit 800. The configuration may also involve inputting a signal to the first input terminal of the flip-flop. Other flip-flops besides the one in front, such as those electrically connected to the output terminal of the flip-flop in the preceding stage. It may also be configured to be electrically connected to the output terminal of a flip-flop. The first input terminal of the flip-flop is not directly connected to the output terminal of the other flip-flop, but rather in between It may also be routed through other circuits.

[0154] Furthermore, the circuit configuration of the multiple flip-flops in the logic circuit of this embodiment is common. It is not necessary to do so; the circuit configuration may be changed for each flip-flop depending on the application.

[0155] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0156] (Embodiment 6) In this embodiment, an example of the logic circuit shown in Embodiment 1 will be described. Specifically For a logic circuit having an AND gate and multiple flip-flops, see Figure 10. I'll explain while doing so.

[0157] The logic circuit 900 of this embodiment shown in Figure 10 includes a flip-flop 901 and an AND gate. A control unit 903 including a 902 and a flip-flop having flip-flops 904-906 It has a lop group 907.

[0158] The flip-flop 901 receives a first data signal (Data1) at its first input terminal. The wiring (hereinafter also referred to as the first data signal line) is electrically connected, and the second input terminal is It is electrically connected to the clock signal line.

[0159] The AND gate 902 has a first input terminal that electrically connects to the output terminal of the flip-flop 901. The second input terminal is connected to the enable signal line.

[0160] The flip-flop 904 receives a second data signal (Data2) at its first input terminal. The wiring (hereinafter also referred to as the second data signal line) is electrically connected, and the second input terminal is It is electrically connected to the output terminal of the AND gate 902.

[0161] Flip-flop 905 has its first input terminal connected to the output terminal of flip-flop 904. The two input terminals are electrically connected, and the second input terminal is electrically connected to the output terminal of the AND gate 902. .

[0162] Flip-flop 906 has its first input terminal connected to the output terminal of flip-flop 905. The two input terminals are electrically connected, and the second input terminal is electrically connected to the output terminal of the AND gate 902. .

[0163] The output signal of the flip-flop 906 is the same as the output signal (Out) of the logic circuit 900. Yes.

[0164] Furthermore, the flip-flops 901, 904-906 in the logic circuit of this embodiment are This circuit can hold one bit of data by utilizing feedback. For example, as shown in Figure 4. A delay-type flip-flop can be applied.

[0165] The logic circuit of this embodiment is configured by a first data signal (Data1) and a clock signal. The output signal of the flip-flop 901, which is controlled by the flip-flop, and the enable signal (EN) The clock signal input to the flip-flop group 907 is controlled. This is a logic circuit that performs clock gating on the flop group 907.

[0166] Furthermore, the second and subsequent flip-flops included in the flip-flop group 907 are the first The input terminal is electrically connected to the output terminal of the preceding flip-flop. The logic circuit in this configuration receives a second data signal (D) during the period when a clock signal is input. ata2) is a shift register that sequentially shifts the flip-flops.

[0167] The logic circuit of this embodiment is a trace circuit in which the channel formation region is made of an oxide semiconductor. It has an radiator. The hydrogen concentration of the oxide semiconductor is 5 × 10 19 (atoms / cm 3 ) Preferably 5 × 10 18 (atoms / cm 3 ) More preferably 5 × 1 0 17 (atoms / cm 3 ) is controlled below this level. Therefore, the off-power of the transistor is controlled below this level. Flow 1 x 10 -13 It is possible to reduce it to [A] or lower. In other words, clock games To suppress charge leakage through the transistor during the period in which the tuning is performed. This can be achieved. As a result, standby power consumption during that period can be reduced and the discussion during that period can be reduced. This makes it possible to suppress malfunctions in the circuitry.

[0168] Furthermore, the logic circuit of this embodiment includes a control unit 903 and a flip-flop group 907 All of the transistors that make up this can be N-type transistors. The transistor is the above transistor (the channel formation region has a hydrogen concentration of 5 × 10 19 (a toms / cm 3 (The transistor will be composed of the following oxide semiconductors.) Furthermore, to achieve low power consumption while using logic circuits composed solely of N-type transistors. This is possible. In addition, by constructing the logic circuit using only N-type transistors, the manufacturing process can be streamlined. This can reduce the amount of material used, improve the yield of the logic circuit, and lower manufacturing costs. It is possible.

[0169] Furthermore, by reducing the power consumption of the logic circuit, the operation of the logic circuit of this embodiment is made easier. The load on the internal circuit can be reduced. This reduces the load on the semiconductor having the logic circuit and the external circuit. This will allow for expansion of the device's functionality.

[0170] In this embodiment, the flip-flop group 907 has three flip-flops. This is shown, but the flip-flops of the flip-flop group 907 in this embodiment The number of flip-flops is not limited to three. In other words, the logic circuit of this embodiment includes flip-flops. The theory that a flip-flop group has the first to the nth (where n is a natural number) flip-flops. This also includes logic circuits. Furthermore, the kth (where k is a natural number less than or equal to n) of the flip-flop group is also included. The flip-flop of ) has a first input terminal that is connected to the output terminal of the k-1 flip-flop. It is electrically connected to the output terminal of the AND gate 902, and the second input terminal is electrically connected to the output terminal of the AND gate 902. .

[0171] Furthermore, in this embodiment, the flip-flops of the flip-flop group 907 from the second stage onward This diagram shows a configuration in which the output signal of the preceding flip-flop is input to the first input terminal of the flip-flop. However, the configuration of the flip-flop group in this embodiment is not limited to this configuration. Alternatively, a signal may be input to the flip-flop from outside the logic circuit 900. Furthermore, the first input terminal of the flip-flop is electrically connected to the output terminal of the flip-flop two stages prior. Configurations that are electrically connected to the output terminals of flip-flops other than the preceding stage, such as being directly connected. It may also be the case that the first input terminal of one flip-flop is connected to another flip-flop It may be connected via other circuits rather than directly to the output terminal of the device.

[0172] Furthermore, the circuit configuration of the multiple flip-flops in the logic circuit of this embodiment is common. It is not necessary to do so; the circuit configuration may be changed for each flip-flop depending on the application.

[0173] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0174] (Embodiment 7) This embodiment shows an example of a transistor in the logic circuit shown in Embodiments 1 to 6. This will be explained. Specifically, the P-type transistor in the logic circuit is a semiconductor. A transistor formed using a substrate containing the material is applied, and as an N-type transistor, acid This example demonstrates the application of transistors formed using ionized semiconductors.

[0175] <Example Configuration> Figure 11 shows the P-type transistor and N-type transistor included in the logic circuit of this embodiment. vinegar.

[0176] The P-type transistor 160 shown in Figure 11 is provided on a substrate 100 containing semiconductor material. A channel-forming region 116 and a pair of impurities arranged so as to sandwich the channel-forming region 116 Regions 114a, 114b and a pair of high-concentration impurity regions 120a, 120b (these are (Also simply called the impurity region) and the gate insulating layer provided on the channel formation region 116 108a, gate electrode layer 110a provided on gate insulating layer 108a, and impurity region The source electrode layer 130a is electrically connected to 114a, and the impurity region 114b is electrically connected It has a subsequent drain electrode layer 130b.

[0177] Furthermore, a sidewall insulating layer 118 is provided on the side surface of the gate electrode layer 110a. Furthermore, in areas that do not overlap with the sidewall insulating layer 118 of the substrate 100 containing semiconductor material It has a pair of high-concentration impurity regions 120a and 120b, and the pair of high-concentration impurity regions 120 A pair of metallic compound regions 124a and 124b exist on a and 120b. Also, the substrate 1 An element isolation insulating layer 106 is provided on 00 so as to surround the transistor 160, Interlayer insulating layers 126 and 128 are provided so as to cover the transistor 160. The source electrode layer 130a and the drain electrode layer 130b are interlayer insulating layer 126 and interlayer Through an opening formed in the insulating layer 128, one of the pair of metal compound regions 124a and 124b It is electrically connected to the other side. In other words, the source electrode layer 130a is connected to the metal compound region 124 It is electrically connected to the high-concentration impurity region 120a and the impurity region 114a via a, and The rain electrode layer 130b is connected to the high-concentration impurity region 120b via the metal compound region 124b. It is electrically connected to the impurity region 114b.

[0178] Furthermore, the lower layer of the N-type transistor 164, which will be described later, is made of the same material as the gate insulating layer 108a. An insulating layer 108b made of the same material as the gate electrode layer 110a, and an electrode layer 110b made of the same material as the gate electrode layer 110a, Furthermore, the electrode layer 130 is made of the same material as the source electrode layer 130a and the drain electrode layer 130b. c is provided.

[0179] The N-type transistor 164 shown in Figure 11 has a gate electrode provided on the interlayer insulating layer 128. Layer 136d, gate insulating layer 138 provided on gate electrode layer 136d, gate insulating An oxide semiconductor layer 140 provided on layer 138, and provided on the oxide semiconductor layer 140, The source electrode layer 142a is electrically connected to the oxide semiconductor layer 140, and the drain electrode It has layer 142b.

[0180] Here, the gate electrode layer 136d is connected to the insulating layer 132 formed on the interlayer insulating layer 128. It is provided to be embedded. Also, similar to the gate electrode layer 136d, a P-type transistor The electrode layer 136a in contact with the source electrode layer 130a and the drain electrode layer 1 An electrode layer 136b is formed in contact with 30b. Also, an electrode layer in contact with electrode layer 130c 136c is formed.

[0181] Furthermore, on top of the transistor 164, a portion of the oxide semiconductor layer 140 is in contact with the transistor. A protective insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode layer 142a An opening is provided that extends to the drain electrode layer 142b, and through this opening, - Electrode layer 150d in contact with electrode layer 142a, electrode layer 1 in contact with drain electrode layer 142b 50e is formed. Also, similar to electrode layer 150d and electrode layer 150e, gate insulation Through the openings provided in layer 138, protective insulating layer 144, and interlayer insulating layer 146, the electrode layer 13 Electrode layer 150a in contact with 6a, electrode layer 150b in contact with electrode layer 136b, and electrode layer 13 An electrode layer 150c is formed in contact with 6c.

[0182] Here, the oxide semiconductor layer 140 is purified to a high degree by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5 × 10⁻⁶. 19 (atoms / cm 3 ) or less. Note that the hydrogen concentration of the oxide semiconductor layer 140 is 5 × 10 18 (atoms / cm 3 It is preferable that it be less than or equal to 5 × 10 17 (atoms / cm 3 ) is below It is more desirable that the hydrogen concentration is sufficiently reduced and the oxide semiconductor layer 140 is purified. By using this method, a transistor 164 with extremely excellent off-current characteristics can be obtained. For example, if the drain voltage Vd is +1V or +10V, and the gate voltage Vg is - In the range of 5V to -20V, the off-current is 1 × 10⁻¹⁰ -13 [A] is less than or equal to this. By applying an oxide semiconductor layer 140 in which the hydrogen concentration has been sufficiently reduced and purified, The off-current of transistor 164 can be reduced. The hydrogen concentration in 40 was determined by secondary ion mass spectrometry (SIMS). This was measured using Mass Spectroscopy.

[0183] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152 Electrode layers 154a, 154b, 154c, and 154d are provided so that they can be inserted. It is being removed. Furthermore, electrode layer 154a is in contact with electrode layer 150a, and electrode layer 154b is It is in contact with electrode layer 150b, and electrode layer 154c is in contact with electrode layer 150c and electrode layer 150d. They are in contact, and electrode layer 154d is in contact with electrode layer 150e.

[0184] The source electrode layer 130a of the P-type transistor 160 shown in this embodiment is the upper layer region The electrode layers 136a, 150a, and 154a provided in the region are electrically connected. Therefore, the source electrode layer 130a of the P-type transistor 160 is made of these conductive layers. By appropriately forming the electrodes of the N-type transistor 164 provided in the upper region It is possible to electrically connect to any of the layers. Also, the P-type transistor has Similarly, for the drain electrode layer 130b, an N-type transistor 16 is provided in the upper region. It is possible to electrically connect to any of the electrode layers of 4. Note that Figure 11 shows Although not shown in the diagram, the gate electrode layer 110a of the P-type transistor 160 is located in the upper region Electrically, through the electrode layer provided therein, one of the electrode layers of the N-type transistor 164 is electrically connected. It is also possible to configure it to connect to targets.

[0185] Similarly, the source electrode layer 142a of the N-type transistor 164 shown in this embodiment is It is electrically connected to electrode layers 130c and 110b provided in the lower layer region. Therefore, the source electrode layer 142a of the N-type transistor 164 appropriately forms these conductive layers. As a result, the gate electrode layer 110a of the P-type transistor 160 provided in the lower region It is possible to electrically connect to the source electrode layer 130a or the drain electrode layer 130b. Although not shown in Figure 11, the gate current of the N-type transistor 164 is The electrode layer 136d or the drain electrode layer 142b, via the electrode layer provided in the lower region, P It is also possible to configure it to be electrically connected to one of the electrode layers of the type transistor 160. Cut.

[0186] Multiple P-type transistors 160 and N-type transistors 164 are provided as described above. The logic circuits shown in Embodiments 1 to 6 can be constructed accordingly. All of the N-type transistors 164 in the logic circuit are formed using oxide semiconductors. It is not necessary to use a transistor; the characteristics required for each transistor can be changed as appropriate. This is possible. For example, as an N-type transistor that requires high-speed operation, the semiconductor material can be It is required to apply transistors formed using a substrate containing the material and to reduce leakage current. As an N-type transistor, a transistor formed using an oxide semiconductor is applied. It is possible.

[0187] <Example of manufacturing process> Next, we will describe an example of a method for fabricating P-type transistor 160 and N-type transistor 164. Let me explain. Below, we will first refer to Figure 12 for the method of fabricating the P-type transistor 160. The explanation will proceed, followed by the method for fabricating the N-type transistor 164, as shown in Figures 13 and 1. I will explain this while referring to section 4.

[0188] First, prepare a substrate 100 containing semiconductor material (see Figure 12(A)). The substrate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates can be applied. Yes, it is possible. Here, a single-crystal silicon substrate is used as the substrate 100 containing semiconductor material. An example of a combination is shown below. Generally, an "SOI substrate" is a substrate with silicon on its insulating surface. This refers to a substrate having a semiconductor layer, but in this specification, etc., a silicon layer is provided on the insulating surface. This concept is used to include substrates with a semiconductor layer made of materials other than condensate. Furthermore, the semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The OI substrate has a configuration in which a semiconductor layer is provided on an insulating substrate such as a glass substrate, with an insulating layer in between. This is also included.

[0189] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 12(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of materials such as silicon nitride can be used. Before and after, in order to control the threshold voltage of the semiconductor device, an n-type conductivity is imparted. Pure elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of silicon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. It is possible to have p-type conductivity. Also, examples of impurities that impart p-type conductivity include boron and aluminum. Aluminum, gallium, and other materials can be used.

[0190] Next, etching is performed using the protective layer 102 as a mask, and the protective layer 102 covers the following Remove a portion of the substrate 100 in the area that is not present (the exposed area). This separates the substrate. A semiconductor region 104 is formed (see Figure 12(B)). This etching process involves dry etching. Etching is preferred, but wet etching may also be used. Etching gas The etching solution can be appropriately selected depending on the material to be etched.

[0191] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer in the region, an element isolation insulating layer 106 is formed (Figure 12(B)). (See reference). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. This is done. As a method for removing the insulating layer, CMP (Chemical Mechanical) is used. There are polishing processes such as polishing and etching, but which of these It may be used after the formation of the semiconductor region 104, or after the formation of the element isolation insulating layer 106. Next, the protective layer 102 is removed.

[0192] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0193] The insulating layer will later become the gate insulating layer, and is produced using methods such as CVD or sputtering. The resulting silicon oxide, silicon nitride, silicon nitride, hafnium oxide, and aluminum oxide are obtained. A single-layer or multi-layer structure of a film containing nium, tantalum oxide, etc. is preferable. By oxidizing and nitriding the surface of the semiconductor region 104 through plasma treatment and thermal oxidation treatment, The above insulating layer may be formed. High-density plasma treatment may be performed using, for example, He, Ar, Kr, The process is carried out using a mixture of noble gases such as Xe, oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen. It is possible to do so. Also, the thickness of the insulating layer is not particularly limited, but for example, 1 nm or more and 100 nm or more. It can be reduced to less than nm.

[0194] The layer containing conductive material is made of metals such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using materials. Also, semiconductor materials such as polycrystalline silicon containing conductive materials. A layer containing a conductive material may be formed using the material. The formation method is not particularly limited, and includes vapor deposition, Various film deposition methods such as CVD, sputtering, and spin coating can be used. In this embodiment, an example is given where a layer containing a conductive material is formed using a metal material. This will be shown.

[0195] Subsequently, the layers containing the insulating layer and conductive material are selectively etched to form the gate insulating layer 10 8a forms a gate electrode layer 110a (see Figure 12(C)).

[0196] Next, an insulating layer 112 is formed to cover the gate electrode layer 110a (see Figure 12(C)). Then, boron (B) or aluminum (Al) is added to the semiconductor region 104 to form a shallow junction. This forms a pair of impurity regions 114a and 114b of varying depths (see Figure 12(C)). Here, boron and aluminum are added to form a p-type transistor, but n-type transistors... When forming a ranzista, impurity elements such as phosphorus (P) and arsenic (As) are added. That is fine. Furthermore, the formation of a pair of impurity regions 114a and 114b results in the semiconductor region 104 A channel formation region 116 is formed below the gate insulating layer 108a (see Figure 12(C)). (See image). Here, the concentration of added impurities can be set as appropriate, but the semiconductor device is highly When it is further miniaturized, it is desirable to increase its concentration. Also, here, the insulating layer The process involves forming a pair of impurity regions 114a and 114b after forming 112. However, the process involves forming a pair of impurity regions 114a and 114b, followed by forming an insulating layer 112. That's also acceptable.

[0197] Next, the sidewall insulating layer 118 is formed (see Figure 12(D)). The insulating layer 118 is formed after the insulating layer is formed so as to cover the insulating layer 112, and anisotropy is applied to the insulating layer. By applying a high-performance etching process, it can be formed in a self-aligned manner. During this process, the insulating layer 112 is partially etched, and the upper surface of the gate electrode layer 110a is paired with it. It is best to expose the upper surfaces of the impurity regions 114a and 114b.

[0198] Next, gate electrode layer 110a, pair of impurity regions 114a, 114b, sidewall An insulating layer is formed so as to cover the insulating layer 118, etc. Then, a pair of impurity regions 114a, Boron (B) and aluminum (Al) are added to a portion of 114b to create a pair of highly concentrated It forms degree impurity regions 120a and 120b (see Figure 12(E)). Here too, N-type trabeculae When forming a radiator, impurity elements such as phosphorus (P) or arsenic (As) can be added. Good. After that, remove the above insulating layer, gate electrode layer 110a, sidewall insulating layer 11 8. Form a metal layer 122 so as to cover a pair of high-concentration impurity regions 120a, 120b, etc. (See Figure 12(E)). The metal layer 122 is formed by vacuum deposition, sputtering, or spin coating. It can be formed using various film deposition methods such as the method. The metal layer 122 is in the semiconductor region 10 It is formed using a metal material that reacts with the semiconductor material constituting 4 to form a low-resistance metal compound. This is desirable. Examples of such metallic materials include titanium, tantalum, and tungsten. Examples include nickel, cobalt, and platinum.

[0199] Next, heat treatment is applied to react the metal layer 122 with the semiconductor material. This creates a pair A pair of metal compound regions 124a, 124 are adjacent to the high-concentration impurity regions 120a, 120b. b is formed (see Figure 12(F)). Note that polycrystalline silicon is used as the gate electrode layer 110a. When using materials such as gold, the portion of the gate electrode layer 110a that comes into contact with the metal layer 122 should also be gold. A genus compound region will be formed.

[0200] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. It is possible to use other heat treatment methods, but chemical reactions related to the formation of metal compounds are possible. To improve the controllability of the response, it is necessary to use a method that enables very short heat treatment times. Desirable. Note that the above-mentioned metal compound region is formed by the reaction between the metal material and the semiconductor material. This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the element's characteristics. After forming the compound regions 124a and 124b, the metal layer 122 is removed.

[0201] Next, an interlayer insulating layer 126 is formed to cover each of the components formed by the above process. Layer 128 is formed (see Figure 12(G)). The interlayer insulating layer 126 and interlayer insulating layer 128 are acid Silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, acid It can be formed using materials containing inorganic insulating materials such as tantalum oxide. It is also possible to form it using organic insulating materials such as acrylic. It has a two-layer structure consisting of an interlayer insulating layer 126 and an interlayer insulating layer 128, but the configuration of the interlayer insulating layer is as follows Not limited. After the formation of the interlayer insulating layer 128, its surface may be treated with CMP or etching. It is desirable to flatten it out by doing so.

[0202] Subsequently, openings extending to a pair of metal compound regions 124a and 124b are made in the interlayer insulating layer. An opening is formed, and a source electrode layer 130a and a drain electrode layer 130b are formed in the opening. See Figure 12(H). The source electrode layer 130a and the drain electrode layer 130b are, for example, open After forming a conductive layer in the area including the mouth using methods such as PVD or CVD, etching and This can be formed by removing a portion of the conductive layer using methods such as CMP. Cut.

[0203] Furthermore, when forming the source electrode layer 130a and the drain electrode layer 130b, the surface It is desirable to process it so that it becomes flat. For example, a titanium film or nitride in the region including the opening. When forming a tungsten film by embedding it in the opening after forming a thin titanium film: Then, through subsequent CMP (Chemical Polishing), unwanted tungsten, titanium, titanium nitride, etc. are removed. In both cases, the flatness of the surface can be improved. Thus, the source electrode layer 130a And by planarizing the surface including the drain electrode layer 130b, a good result can be obtained in subsequent processes. This makes it possible to form suitable electrodes, wiring, insulating layers, semiconductor layers, and so on.

[0204] In this case, the source electrode layer 1 is in contact with the pair of metal compound regions 124a and 124b. Although only 30a and the drain electrode layer 130b are shown, in this process, as wiring Form a functional electrode layer (for example, electrode layer 130c in Figure 11) together. This can be done. It can be used as the source electrode layer 130a and the drain electrode layer 130b. There are no particular limitations on the materials used; various conductive materials can be used. For example, molybdenum Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium Conductive materials such as luminescent material can be used.

[0205] As a result, a P-type transistor 160 is formed using a substrate 100 containing semiconductor material. Furthermore, electrodes, wiring, insulating layers, etc. may be formed after the above process. As a structure, a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers is adopted. This allows us to provide highly integrated logic circuits. Furthermore, in the same process as described above... Therefore, it is also possible to form an N-type transistor using a substrate 100 containing semiconductor material. Yes. That is, in the process described above, the impurity element added to the semiconductor region is phosphorus (P). By changing to impurity elements such as arsenic (As), an N-type transistor can be formed. It is possible.

[0206] Next, using Figures 13 and 14, an N-type transistor 164 is placed on the interlayer insulating layer 128. The manufacturing process will be explained. Figures 13 and 14 show each of the interlayer insulating layers 128. This shows the manufacturing process for seed electrode layers and N-type transistors such as 164. The P-type transistor 160 and other components located at the bottom of ZISTA 164 have been omitted.

[0207] First, interlayer insulating layer 128, source electrode layer 130a, drain electrode layer 130b, electrode layer 1 An insulating layer 132 is formed on 30c (see Figure 13(A)). The insulating layer 132 is processed by PVD or C It can be formed using methods such as the VD method. Also, silicon oxide, silicon nitride, and nitriding can be used. Includes inorganic insulating materials such as silicon dioxide, hafnium oxide, aluminum oxide, and tantalum oxide. It can be formed using materials.

[0208] Next, the insulating layer 132 is made of source electrode layer 130a, drain electrode layer 130b, and An opening is formed that extends to the electrode layer 130c. At this time, the gate electrode layer 136d is later formed. An opening is also formed in the area to be treated. Then, a conductive layer 13 is embedded in the above-mentioned opening. Form 4 (see Figure 13(B)). The above opening is made by etching using a mask or other method. The mask can be formed by methods such as exposure using a photomask. It is possible to do this. Etching methods include wet etching and dry etching. Either method can be used, but from the viewpoint of microfabrication, dry etching is preferable. The conductive layer 134 can be formed using film deposition methods such as PVD or CVD. Materials that can be used to form the conductive layer 134 include molybdenum, titanium, and cyanoacrylate. Conductive materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium. Examples include material properties, alloys of these materials, and compounds (such as nitrides).

[0209] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, C After forming a thin titanium nitride film using the VD method, a tungsten film was then embedded in the opening. A method for forming it can be applied. Here, the titanium film formed by the PVD method is The oxide film at the interface is reduced, and the lower electrode layer (here, source electrode layer 130a, drain electrode layer) It has the function of reducing contact resistance with (130b, electrode layer 130c, etc.). The titanium nitride film formed therein has a barrier function that suppresses the diffusion of conductive materials. After forming a barrier film using titanium or titanium nitride, a copper film is formed by a plating method. That's good too.

[0210] After forming the conductive layer 134, the conductive layer is further processed using methods such as etching and CMP. By removing a portion of 134 and exposing the insulating layer 132, electrode layer 136a, electrode layer 136b, An electrode layer 136c and a gate electrode layer 136d are formed (see Figure 13(C)). A portion of the electrode layer 134 is removed to form electrode layer 136a, electrode layer 136b, electrode layer 136c, and gate. When forming the electrode layer 136d, it is desirable to process the surface so that it becomes flat. As shown, insulating layer 132, electrode layer 136a, electrode layer 136b, electrode layer 136c, gate electrode By planarizing the surface of the polar layer 136d, good electrodes, wiring, and insulation can be achieved in subsequent processes. This makes it possible to form marginal layers, semiconductor layers, and the like.

[0211] Next, insulating layer 132, electrode layer 136a, electrode layer 136b, electrode layer 136c, gate electrode A gate insulating layer 138 is formed to cover layer 136d (see Figure 13(D)). The insulating layer 138 can be formed using methods such as CVD or sputtering. The gate insulating layer 138 consists of silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide nitride, and aluminum oxide. It is preferable to form the product to contain elements such as nium, hafnium oxide, and tantalum oxide. The gate insulating layer 138 may be a single layer or a multilayer structure. For example, Using plasma CVD with silane (SiH4), oxygen, and nitrogen as the gases, oxidation A gate insulating layer 138 made of silicon nitride can be formed. Thickness of the gate insulating layer 138 The wavelength is not particularly limited, but for example, it can be between 10 nm and 500 nm. In the case of the structure, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less, and a first If a second gate insulating layer with a thickness of 5 nm to 300 nm is laminated on the gate insulating layer, It is suitable.

[0212] Furthermore, by removing impurities, the oxide semiconductor is converted to type i or substantially converted to type i. Highly purified oxide semiconductors are extremely sensitive to interface states and interface charges, When such an oxide semiconductor is used in the oxide semiconductor layer, the interface with the gate insulating layer is heavy This is essential. In other words, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high This will require a higher level of quality.

[0213] For example, high-density plasma CVD using μ-wave (2.45 GHz) is a dense and dielectric-resistant method. It is suitable in that it can form a high-quality gate insulating layer 138 with high purity. The close contact between the semiconductor layer and the high-quality gate insulating layer reduces interface states and improves interface characteristics. Because it can be made into something good.

[0214] Of course, if it can form a good insulating layer as a gate insulating layer, then it can be made highly pure. Even when using an oxide semiconductor layer, other methods such as sputtering and plasma CVD are used. The method can be applied. In addition, the film quality and interface properties can be modified by heat treatment after formation. An insulating layer may be applied. In any case, the film quality of the gate insulating layer 138 is good. In addition to being favorable, it reduces the interface state density with the oxide semiconductor layer, allowing for the formation of a good interface. You just need to form that.

[0215] Furthermore, 85℃, 2×10 6 (V / cm), 12-hour gate bias thermal stress test In the BT test, if impurities are added to the oxide semiconductor, the impurities and oxides will react. The bonds between the semiconductor's main components are broken by a strong electric field (B: bias) and high temperature (T: temperature). Therefore, the generated uncoupled hands induce a drift in the threshold voltage (Vth).

[0216] In contrast, impurities in oxide semiconductors, especially hydrogen and water, are eliminated as much as possible, as described above. By improving the interface characteristics with the gate insulating layer, stable transients are achieved even under BT testing. It is possible to obtain stars.

[0217] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching is performed using a mask. The oxide semiconductor layer is processed by methods such as G to form island-shaped oxide semiconductor layers 140. (See Figure 13(E)).

[0218] Examples of oxide semiconductor layers include In-Ga-Zn-O systems, In-Sn-Zn-O systems, and In- Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Z nO series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn -O-based and Zn-O-based oxide semiconductor layers, particularly amorphous oxide semiconductor layers, are preferred. In this embodiment, an In-Ga-Zn-O-based metal oxide layer is used as the oxide semiconductor layer. Using a GET, an amorphous oxide semiconductor layer will be formed by sputtering. By adding silicon to an amorphous oxide semiconductor layer, its crystallization can be suppressed. Therefore, for example, using a target containing 2% to 10% by weight of SiO2, acid A synthetic semiconductor layer may be formed.

[0219] For example, an acid can be used as a target for fabricating an oxide semiconductor layer by sputtering. Metal oxide targets, mainly composed of zinc oxide, can be used. In addition, Metal oxide targets containing Ga and Zn (composition ratio: In2O3:Ga2O3) :ZnO=1:1:1[mol], In:Ga:Zn=1:1:0.5[atom]) It is also possible to use metal oxide targets containing In, Ga, and Zn. And In:Ga:Zn=1:1:1[atom], or In:Ga:Zn=1:1: A target having a composition ratio of 2 atoms may also be used. (Metal oxide target) The filling rate is 90% or more and 100% or less, preferably 95% or more (for example, 99.9%). By using a metal oxide target with a high packing density, a dense oxide semiconductor layer is formed. It will be done.

[0220] The formation atmosphere for oxide semiconductor layers includes a noble gas atmosphere (typically argon), an oxygen atmosphere, Alternatively, a mixed atmosphere of a noble gas (typically argon) and oxygen is preferable. In terms of composition, for example, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present in amounts of several ppm (desirable). It is preferable to use a high-purity gas that has been reduced to a level of approximately a few ppb.

[0221] During the formation of the oxide semiconductor layer, the substrate is held in a processing chamber that is kept under reduced pressure, and the substrate The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming an oxide semiconductor layer while heating, the impurity concentration contained in the oxide semiconductor layer is reduced. This can reduce the amount of sputtering damage. Sputtered gas, from which hydrogen and water have been removed while removing residual moisture from the room, is introduced, and metal oxidation is performed. To form an oxide semiconductor layer using an object as a target. To remove residual moisture in the processing chamber. It is preferable to use an adsorption-type vacuum pump. For example, a cryopump or an ion pump. A titanium sublimation pump can be used. In addition, as an exhaust means, A cryopump may be used to add a cold trap to the pump. The treated chamber is used to process, for example, hydrogen atoms, water (H2O), and other compounds containing hydrogen atoms (preferably... Since compounds containing carbon atoms are exhausted, oxide semiconductors formed in the processing chamber are affected. The concentration of impurities in the body layer can be reduced.

[0222] Formation conditions include, for example, a distance of 100 mm between the substrate and the target, and a pressure of 0. 6 Pa, DC power 0.5 kW, atmosphere oxygen (oxygen flow rate 100%) The following conditions can be applied. Furthermore, if a pulsed DC power supply is used, The amount of powdery material (also called particles or dust) generated during film formation can be reduced, and the film thickness distribution can be made uniform. Therefore, it is preferable. The thickness of the oxide semiconductor layer is preferably 2 nm or more and 200 nm or less. The thickness should be between 5 nm and 30 nm. Note that the appropriate thickness will vary depending on the oxide semiconductor material used. Therefore, the thickness should be selected appropriately depending on the material being used.

[0223] Furthermore, before forming the oxide semiconductor layer by sputtering, argon gas is introduced... Reverse sputtering is performed to generate rasma, and dust adhering to the surface of the gate insulating layer 138 is removed. It is preferable to remove it. Here, reverse sputtering is the process in which sputtering is performed. Instead of colliding ions with the target, we can instead collide ions with the treatment surface. Therefore, it refers to a method of modifying the surface. It involves colliding ions with the treated surface. This involves applying a high-frequency voltage to the processing surface in an argon atmosphere to generate plasma near the substrate. There are methods such as using nitrogen, helium, or oxygen instead of an argon atmosphere. That's good too.

[0224] For etching the above oxide semiconductor layer, dry etching and wet etching are both possible. You may use this. Of course, you can also use both in combination. To enable etching, etching conditions (etching gas and etching solution, Set the etching time, temperature, etc. as appropriate.

[0225] Etching gases used in dry etching include, for example, chlorine-containing gases (chlorine-based gases). For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), and carbon tetrachloride. Examples include (CCl4, etc.). Also, fluorine-containing gases (fluorinated gases, for example, tetrafluoride). Carbon (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoromethane (CH4) F3, etc., hydrogen bromide (HBr), oxygen (O2), and these gases with helium (He) Gases to which noble gases such as argon (Ar) have been added may also be used.

[0226] As for dry etching methods, parallel plate type RIE (Reactive Ion Etc The hing method, or ICP (Inductively Coupled Plasma): A conductively coupled plasma etching method can be used. It is possible to etch the material into the desired shape. As such, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the substrate-side electrode) The amount of power used, the electrode temperature on the substrate, etc., should be set as appropriate.

[0227] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid. These can be used. In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's okay to be there.

[0228] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. This allows for the dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment is The temperature should be between 300°C and 750°C, preferably between 400°C and below the strain point of the substrate. The substrate is introduced into an electric furnace using a resistance heating element, and the oxide semiconductor layer 140 is exposed to a nitrogen atmosphere. The oxide semiconductor layer 140 is subjected to a heat treatment at 450°C for 1 hour under ambient air conditions. This prevents re-introduction of water or hydrogen without contact with the material.

[0229] Furthermore, heat treatment equipment is not limited to electric furnaces; it also includes heat conduction from a heated medium such as gas, and This may be a device that heats the object to be processed by thermal radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Angle) for Thermal Annealing devices, etc. A neal device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high pressure A device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as mercury lamps. The GRTA apparatus is a device that performs heat treatment using high-temperature gas. The gas used is: Inert gases such as argon or nitrogen, which do not react with the material being treated during heat treatment, are used. A gaseous substance is used.

[0230] For example, as a first heat treatment, the base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The board is placed in the inert gas, heated for several minutes, and then the board is removed from the inert gas during the GRTA process. It is also possible to do so. Using GRTA treatment makes high-temperature heat treatment possible in a short time. Because this is a heat treatment, it can be applied even under temperature conditions that exceed the strain point of the substrate.

[0231] Furthermore, the first heat treatment mainly uses nitrogen or a noble gas (helium, neon, argon, etc.). It is desirable to perform this in an atmosphere that is free from water, hydrogen, etc. If so, the purity of the nitrogen, or noble gas such as helium, neon, or argon, introduced into the heat treatment device , 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, Furthermore, the impurity concentration shall be 1 ppm or less, preferably 0.1 ppm or less.

[0232] Depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize. It may undergo crystallization and become microcrystalline or polycrystalline. For example, if the crystallization rate is 90% or higher, or 8 In some cases, a microcrystalline oxide semiconductor layer with 0% or more crystalline material may be formed. Also, the conditions of the first heat treatment, Depending on the material of the oxide semiconductor layer, it can become an amorphous oxide semiconductor layer that does not contain crystalline components. In some cases, it may be the case.

[0233] Furthermore, microcrystals (particle size 1 nm) can be placed on amorphous oxide semiconductors (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer contains a mixture of elements up to 20 nm (typically between 2 nm and 4 nm). In some cases, this may be the case.

[0234] Furthermore, by arranging microcrystals within an amorphous material, the electrical properties of the oxide semiconductor layer can be changed. It is also possible to use an In-Ga-Zn-O metal oxide target. When forming an oxide semiconductor layer, an electrically anisotropic In2Ga2ZnO7 crystal is used. By forming oriented microcrystalline regions, the electrical properties of the oxide semiconductor layer are altered. It is possible.

[0235] More specifically, for example, if the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer By orienting the elements in a specific direction, the conductivity in a direction parallel to the surface of the oxide semiconductor layer is directed. This can improve the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer. These microcrystalline regions suppress the penetration of impurities such as water and hydrogen into the oxide semiconductor layer. To have the ability.

[0236] The oxide semiconductor layer having the above-mentioned microcrystalline portion is an oxide semiconductor layer obtained by GRTA treatment. It can be formed by surface heating. Also, the Zn content is insulated from In or Ga. By using a sputtering target smaller than the required volume, it is possible to form the material more favorably. .

[0237] The first heat treatment of the oxide semiconductor layer 140 involves processing the island-shaped oxide semiconductor layer 140. It can also be performed on the oxide semiconductor layer before the first heat treatment. In that case, after the first heat treatment, a heating device The substrate is removed from the machine, and then the photolithography process is performed.

[0238] Furthermore, is the above heat treatment effective in dehydrating and dehydrogenating the oxide semiconductor layer 140? These processes can also be called dehydration or dehydrogenation. The chemical treatment involves forming an oxide semiconductor layer, then adding a source electrode layer and a drain on the oxide semiconductor layer 140. After laminating the electrode layers, or forming a protective insulating layer on the source electrode layer and drain electrode layer. This can be done at times such as after. The dehydrogenation treatment can be performed multiple times, not just once.

[0239] Next, the source electrode layer 142a and the drain electrode are brought into contact with the oxide semiconductor layer 140. Form layer 142b (see Figure 13(F)). Source electrode layer 142a and drain electrode layer 142b forms a conductive layer so as to cover the oxide semiconductor layer 140, and then selects the conductive layer. It can be formed by etching the target.

[0240] The conductive layer is produced using PVD methods such as sputtering, and CVD methods such as plasma CVD. It can be formed using the method. Furthermore, aluminum and chromium can be used as materials for the conductive layer. Elements selected from copper, tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above. Alloys containing the following components can be used: manganese, magnesium, zirconium, bellflower. Materials selected from one or more of lylium and thorium may be used. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, Materials consisting of one or more elements selected from candium may be used. The layers may be a single-layer structure or a laminated structure of two or more layers. For example, silicon A single-layer structure of an aluminum film containing, a two-layer structure in which a titanium film is laminated on an aluminum film, Examples include a three-layer structure in which a titanium film, an aluminum film, and another titanium film are stacked.

[0241] Here, the exposure used during mask formation for etching includes ultraviolet light, KrF laser light, and Ar It is preferable to use F laser light.

[0242] The channel length (L) of the transistor is measured from the lower end of the source electrode layer 142a to the drain electrode This is determined by the distance from the lower end of layer 142b. Note that the channel length (L) is less than 25 nm. When performing full exposure, extremely short wavelengths of ultra-ultraviolet light (Extreme) with wavelengths ranging from a few nanometers to several tens of nanometers are used. Exposure for mask formation is performed using ultra-ultraviolet light. It has high resolution and a large depth of field. Therefore, the channel length of the transistors that are formed later (L) can also be set to between 10nm and 1000nm, allowing for faster circuit operation speeds. It can be transformed.

[0243] Furthermore, during etching of the conductive layer, care must be taken to ensure that the oxide semiconductor layer 140 is not removed. Adjust the materials and etching conditions as appropriate. Therefore, in this process, a portion of the oxide semiconductor layer 140 is etched, and grooves (concave) are formed. It may also become an oxide semiconductor layer having a portion.

[0244] Also, between the oxide semiconductor layer 140 and the source electrode layer 142a, or the oxide semiconductor layer 140 An oxide conductive layer may be formed between the and the drain electrode layer 142b. - The metal layer for forming the electrode layer 142a and the drain electrode layer 142b is continuous It is possible to form (continuous film deposition) the oxide conductive layer in the source region or drain region. It can function as a region. By providing such an oxide conductive layer, the source region or drain region can be configured. This allows for lower resistance in the Ω region, enabling high-speed operation of the transistor.

[0245] Furthermore, in order to reduce the number of masks used and the number of processes, the transmitted light will have multiple intensities. A resist mask is formed using a multi-gradation mask, which is an optical mask, and this is used for etching. The process may be carried out. The resist mask formed using a multi-gradation mask has multiple thicknesses. This results in a stepped shape, and the shape can be further deformed by ashing. It can be used in multiple etching processes to process different patterns. The multi-level mask allows for registrations corresponding to at least two different patterns. A mask can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding mask can be formed. Since the photography process can also be reduced, the process can be simplified.

[0246] Furthermore, after the above-mentioned process, plasma treatment using gases such as N2O, N2, or Ar is performed. It is preferable to perform the following. The surface of the exposed oxide semiconductor layer by the plasma treatment Water and other substances adhering to it are removed. Additionally, plasma treatment is performed using a mixed gas of oxygen and argon. You may do so.

[0247] Next, a protective insulating layer 1 that contacts a portion of the oxide semiconductor layer 140 without being exposed to the atmosphere. Forms 44 (see Figure 13(G)).

[0248] The protective insulating layer 144 is prepared by methods such as sputtering, which can cause impurities such as water and hydrogen to be mixed into the protective insulating layer 144. It can be formed by appropriately using methods to prevent this from happening. Furthermore, its thickness is at least 1 nm. This concludes the explanation. Materials that can be used for the protective insulating layer 144 include silicon oxide and silicon nitride. These include silicon oxide nitride and silicon oxide nitride. Furthermore, their structure can be a single-layer structure. A laminated structure is also acceptable. The substrate temperature when forming the protective insulating layer 144 should be above room temperature or 300°C. It is preferable to keep the temperature below °C, and the atmosphere should be a noble gas atmosphere (typically argon) or an oxygen atmosphere. A gas or a mixed atmosphere of a noble gas (typically argon) and oxygen is preferred.

[0249] If hydrogen is present in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer 140, Hydrogen extracts oxygen from the oxide semiconductor layer 140, and so on, and the oxide semiconductor layer 14 The back channel side of 0 may become less resistant, potentially leading to the formation of parasitic channels. Therefore, the protective insulating layer 144 is formed in a way that minimizes hydrogen content. It is important not to use it.

[0250] Furthermore, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The oxide semiconductor layer 140 and the protective insulating layer 144 do not contain hydrogen, hydroxyl groups, or water. This is for the purpose of doing so.

[0251] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, by using cryopumps, ion pumps, and titanium sublimation pumps. This is preferable. Furthermore, as an exhaust means, a turbo pump with a cold trap added is preferable. It may be present. The treatment chamber, which is evacuated using a cryopump, contains, for example, hydrogen atoms and water (H Because compounds containing hydrogen atoms, such as 2O, are removed, the protective insulation formed in the processing chamber is The concentration of impurities in the marginal layer 144 can be reduced.

[0252] The sputtering gas used when forming the protective insulating layer 144 includes hydrogen, water, hydroxyl groups, and This process removes impurities such as hydrides to a level of several ppm (preferably several ppb). It is preferable to use a high-purity gas.

[0253] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. It is desirable to perform the process at temperatures between 0°C and 400°C, for example, between 250°C and 350°C. Next, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, This can reduce variations in the electrical characteristics of the transistors.

[0254] Furthermore, heat treatment is performed in air at a temperature between 100°C and 200°C for a period of 1 hour to 30 hours. This is also acceptable. This heat treatment may be carried out by heating while maintaining a constant heating temperature, or from room temperature to 100°C. The process involves repeatedly raising the temperature to a heating temperature of 200°C or lower, and then lowering it from the heating temperature back to room temperature. This may be done. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment is performed under reduced pressure. This procedure may be performed instead of the second heat treatment, or before or after the second heat treatment.

[0255] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Figure 14(A)). The intervening insulating layer 146 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnix oxide It can be formed using materials containing inorganic insulating materials such as fluorine. After formation, the surface is planarized by methods such as CMP or etching. desirable.

[0256] Next, electrodes are applied to the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. Layer 136a, electrode layer 136b, electrode layer 136c, source electrode layer 142a, drain electrode layer An opening is formed that extends to 142b, and a conductive layer 148 is formed to be embedded in the opening. (See Figure 14(B)). The above-mentioned opening is formed by methods such as etching using a mask. This can be done. The mask can be formed by methods such as exposure using a photomask. Yes, it is possible. For etching, either wet etching or dry etching can be used. While this is also possible, from the viewpoint of microfabrication, dry etching is preferable. (Conductive) Layer 148 can be formed using film deposition methods such as PVD or CVD. Conductive layer Materials that can be used to form 148 include molybdenum, titanium, chromium, and tantalum. Conductive materials such as aluminum, tungsten, copper, neodymium, and scandium, Examples include alloys and compounds (such as nitrides).

[0257] Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then CVD is applied. After forming a thin titanium nitride film using the method, a tungsten film is formed to fill the opening. A method can be applied. Here, the titanium film formed by the PVD method is at the interface. The oxide film is reduced, and the lower electrode (here, electrode layer 136a, electrode layer 136b, electrode layer 13 6c, function to reduce contact resistance with source electrode layer 142a and drain electrode layer 142b) It has the following properties. Furthermore, the titanium nitride that is formed thereafter acts as a barrier to suppress the diffusion of conductive materials. It has the function of forming a barrier film made of titanium or titanium nitride, followed by a plating process. A copper film may be formed by this method.

[0258] After forming the conductive layer 148, a part of the conductive layer 14 8 is removed using methods such as etching or CMP to expose the interlayer insulating layer 146, and the electrode layers 150a, electrode layer 150b, electrode layer 150c, electrode layer 150d, and electrode layer 150e are formed (see FIG. 14(C)). In addition, when removing a part of the conductive layer 148 to form the electrode layers 150a, electrode layer 150b, electrode layer 150 c, electrode layer 150d, and electrode layer 150e, it is desirable to process so that the surface becomes flat. Thus, by planarizing the surfaces of the interlayer insulating layer 146, electrode layer 150a, electrode layer 150b, electrode layer 150c, electrode layer 150d, and electrode layer 150e, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. Furthermore, an insulating layer 152 is formed, openings reaching the electrode layers 150a, electrode layer 150b, electrode layer 150c, electrode layer 150d, and electrode layer 150e are formed in the insulating layer 152, and after forming a conductive layer so as to fill the openings, a part of the conductive layer is removed using methods such as etching or CMP to expose the insulating layer 152, and the electrode layers 154a, electrode layer 154b, electrode layer 1

[0259] 54c, and electrode layer 154d are formed (see FIG. 14(D)). This process is the same as the case of forming the electrode layer 150a [[ID=2y]] etc., so details are omitted. When the N-type transistor 164 is fabricated by the method as described above, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 (atoms / cm ) or less, and the off-current of the N-type transistor 1 64 is 1×10

[0260] [A] or less at room temperature. Such excellent 19 (atoms / cm 3 ) -13 The characteristic N-type transistor 164 is applied to the logic circuits shown in Embodiments 1 to 6. Therefore, reducing the standby power consumption of the logic circuit and suppressing malfunctions of the logic circuit It will become possible.

[0261] <Variation> Figures 15 to 18 show modified configurations of the N-type transistor 164. In Figures 1 through 18, the configuration of transistor 160 is the same as that shown in Figure 11.

[0262] Figure 15 shows a gate electrode layer 136d beneath an oxide semiconductor layer 140, and a source electrode layer 142a and the drain electrode layer 142b are in contact on the lower surface of the oxide semiconductor layer 140. The N-type transistor 164 with the following configuration is shown.

[0263] A major difference between the configuration shown in Figure 15 and the configuration shown in Figure 11 is the source electrode layer 142a and The connection point between the drain electrode layer 142b and the oxide semiconductor layer 140 is one example. In the configuration shown in Figure 11, the source electrode layer 1 is located on the upper surface of the oxide semiconductor layer 140. In contrast to contact with 42a and the drain electrode layer 142b, in the configuration shown in Figure 15, the oxide On the lower surface of the semiconductor layer 140, the source electrode layer 142a and the drain electrode layer 142b It comes into contact with the other electrode layer, insulating layer, etc. Due to this difference in contact, the arrangement of other electrode layers, insulating layers, etc. is different. This is how it is. The details of each component are the same as in Figure 11.

[0264] Specifically, the N-type transistor 164 shown in Figure 15 is provided on the interlayer insulating layer 128. A gate electrode layer 136d and a gate insulating layer 138 provided on the gate electrode layer 136d , Source electrode layer 142a and drain electrode layer 142 provided on gate insulating layer 138 b and the oxide semiconductor in contact with the upper surfaces of the source electrode layer 142a and the drain electrode layer 142b It has a body layer 140 and an oxide semiconductor layer 14 on top of the N-type transistor 164. A protective insulating layer 144 is provided to cover 0.

[0265] Figure 16 shows an N-type transient having a gate electrode layer 136d on an oxide semiconductor layer 140. Figure 16(A) shows the source electrode layer 142a and the drain electrode layer. 142b is in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 140. This figure shows an example of the configuration, and Figure 16(B) shows the source electrode layer 142a and the drain electrode layer 14 2b is configured to be in contact with the oxide semiconductor layer 140 on the upper surface of the oxide semiconductor layer 140. An example is shown in the figure.

[0266] The main difference between the configuration shown in Figure 11 or Figure 15 and the configuration shown in Figure 16 is the oxide semiconductor layer 1 The point is that the gate electrode layer 136d is located on top of 40. Also, the configuration shown in Figure 16(A) and Figure The main difference in the configuration shown in 16(B) is the source electrode layer 142a and the drain electrode layer 14 Whether 2b is in contact with the lower or upper surface of the oxide semiconductor layer 140, That is the point. And due to these differences, the arrangement of other electrode layers, insulating layers, etc. They are different. The details of each component are the same as in Figure 11, etc.

[0267] Specifically, the N-type transistor 164 shown in Figure 16(A) is provided on the interlayer insulating layer 128. The source electrode layer 142a and drain electrode layer 142b are cut, and the source electrode layer 142a and The oxide semiconductor layer 140 is in contact with the upper surface of the drain electrode layer 142b, and the oxide semiconductor layer A gate insulating layer 138 provided on 140, and an oxide semiconductor layer 1 on the gate insulating layer 138 It has a gate electrode layer 136d in a region that overlaps with 40.

[0268] Furthermore, the N-type transistor 164 shown in Figure 16(B) is provided on the interlayer insulating layer 128. An oxide semiconductor layer 140 and a portion provided in contact with the upper surface of the oxide semiconductor layer 140 Source electrode layer 142a and drain electrode layer 142b, oxide semiconductor layer 140, source electrode A gate insulating layer 138 provided on the electrode layer 142a and the drain electrode layer 142b, and A gate electrode layer 13 is provided in the region where it overlaps with the oxide semiconductor layer 140 on the insulating layer 138. It has 6d and .

[0269] In addition, the configuration shown in Figure 16 omits some components compared to the configuration shown in Figure 11, etc. This may occur (for example, electrode layer 150a or electrode layer 154a). In this case, the manufacturing process This also has the secondary effect of simplifying the process. Of course, even in the configuration shown in Figure 11, It goes without saying that non-essential components can be omitted.

[0270] Figure 17 shows the case where the device size is relatively large, and below the oxide semiconductor layer 140 An N-type transistor 164 having a gate electrode layer 136d is shown. In this case, the surface The requirements for flatness and coverage are relatively lenient, so wiring and electrodes are not kept out It is not necessary to form it so that it is embedded in the margin layer. For example, patterning after the formation of the conductive layer By doing so, it is possible to form a gate electrode layer 136d, etc.

[0271] The main difference between the configuration shown in Figure 17(A) and the configuration shown in Figure 17(B) is the source electrode layer 1 42a and the drain electrode layer 142b are located on the lower or upper surface of the oxide semiconductor layer 140. The question is which of these situations will lead to contact. And, due to these differences, other The arrangement of the electrode layer, insulating layer, etc., differs. Details of each component are shown in the diagram. It is similar to 11, etc.

[0272] Specifically, the N-type transistor 164 shown in Figure 17(A) is provided on the interlayer insulating layer 128. The gate electrode layer 136d is cut, and the gate insulating layer 1 provided on the gate electrode layer 136d 38 and the source electrode layer 142a and drain electrode layer provided on the gate insulating layer 138 142b and the oxidation in contact with the upper surface of the source electrode layer 142a and the drain electrode layer 142b It has a material semiconductor layer 140.

[0273] Furthermore, the N-type transistor 164 shown in Figure 17(B) is provided on the interlayer insulating layer 128. A gate electrode layer 136d and a gate insulating layer 138 provided on the gate electrode layer 136d an oxide semiconductor is provided in the region that overlaps with the gate electrode layer 136d on the gate insulating layer 138. A body layer 140 and a source electrode layer provided in contact with the upper surface of the oxide semiconductor layer 140. It has 142a and a drain electrode layer 142b.

[0274] Furthermore, in the configuration shown in Figure 17, the number of components is reduced compared to the configuration shown in Figure 11, etc. It may be omitted. In this case, too, the effect of simplifying the manufacturing process can be achieved.

[0275] Figure 18 shows the case where the device size is relatively large, with the oxide semiconductor layer 140 on top of An N-type transistor 164 having a gate electrode layer 136d is shown. In this case as well, the table The requirements for surface flatness and coverage are relatively lenient, so wiring and electrodes, etc. It is not necessary to form it so as to be embedded in the insulating layer. For example, after the conductive layer is formed, the patterning By performing this process, it is possible to form the gate electrode layer 136d and other components.

[0276] The main difference between the configuration shown in Figure 18(A) and the configuration shown in Figure 18(B) is the source electrode layer 1 42a and the drain electrode layer 142b are located on the lower or upper surface of the oxide semiconductor layer 140. The question is which of these situations will lead to contact. And, due to these differences, other The arrangement of the electrode layer, insulating layer, etc., differs. Details of each component are shown in the diagram. It is similar to 11, etc.

[0277] Specifically, the N-type transistor 164 shown in Figure 18(A) is provided on the interlayer insulating layer 128. The source electrode layer 142a and drain electrode layer 142b are cut, and the source electrode layer 142a and The oxide semiconductor layer 140 is in contact with the upper surface of the drain electrode layer 142b, and the source electrode layer 1 42a, drain electrode layer 142b, and gate insulation provided on oxide semiconductor layer 140 A region is provided in which layer 138 and the oxide semiconductor layer 140 on the gate insulating layer 138 overlap. It has a gate electrode layer 136d.

[0278] Furthermore, the N-type transistor 164 shown in Figure 18(B) is provided on the interlayer insulating layer 128. An oxide semiconductor layer 140 and a portion provided in contact with the upper surface of the oxide semiconductor layer 140 Source electrode layer 142a and drain electrode layer 142b, source electrode layer 142a, drain The electrode layer 142b and the gate insulating layer 138 provided on the oxide semiconductor layer 140, A gate electrode layer 13 is provided in the region where it overlaps with the oxide semiconductor layer 140 on the insulating layer 138. It has 6d and .

[0279] Furthermore, in the configuration shown in Figure 18, the number of components is reduced compared to the configuration shown in Figure 11, etc. It may be omitted. In this case, too, the effect of simplifying the manufacturing process can be achieved.

[0280] In this embodiment, an N-type transistor 164 is stacked on top of a P-type transistor 160 to form Although an example of this has been explained, the structure of the P-type transistor 160 and the N-type transistor 164 The results are not limited to this. For example, a P-type transistor and an N-type transistor on the same plane. A transistor can be formed. Furthermore, a P-type transistor 160 and an N-type transistor It is also acceptable to superimpose Ta164 on it.

[0281] The above-mentioned N-type transistor 164 is an N-type transistor found in the logic circuits shown in Embodiments 1 to 6. By applying this to a transistor, charge leakage through the thin-film transistor is suppressed. This can be controlled. As a result, the standby power consumption of logic circuits can be reduced and the malfunction of logic circuits can be controlled. This makes it possible to suppress the growth.

[0282] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0283] (Embodiment 8) This embodiment shows an example of a transistor in the logic circuit shown in Embodiments 1 to 6. This will be explained. Specifically, the channel formation region is made up of an oxide semiconductor. Let's describe an example of a film transistor.

[0284] One embodiment of the thin-film transistor and its fabrication method is shown in Figures 19 and 20. I will explain.

[0285] Figures 19(A) and (B) show examples of the planar and cross-sectional structures of a thin-film transistor. The thin-film transistor 460 shown in A) and (B) is a thin-film transistor with a top gate structure. be.

[0286] Figure 19(A) is a plan view of the thin-film transistor 460 with a top gate structure, and Figure 19( B) is a cross-sectional view along the line D1-D2 in Figure 19(A).

[0287] The thin-film transistor 460 has an insulating layer 457 on a substrate 450 having an insulating surface, source Electrode layer or drain electrode layer 465a (465a1, 465a2), oxide semiconductor layer 462 Source electrode layer or drain electrode layer 465b, wiring layer 468, gate insulating layer 452, gate It includes an electrode layer 461 (461a, 461b), and a source electrode layer or drain electrode layer 465 a(465a1, 465a2) is electrically connected to wiring layer 464 via wiring layer 468. It is also present. In addition, although not shown in the diagram, the source electrode layer or drain electrode layer 465b is also gate insulating. An opening in layer 452 is electrically connected to the wiring layer.

[0288] The thin-film transistor 460 is fabricated on the substrate 450 using Figures 20(A) to (E) below. I will explain the process.

[0289] First, an insulating layer 457, which will serve as the base film, is formed on a substrate 450 having an insulating surface.

[0290] In this embodiment, the insulating layer 457 is formed by a silicon oxide layer using a sputtering method. The substrate 450 is transported to the processing room, where it is subjected to a spa treatment containing high-purity oxygen from which hydrogen and moisture have been removed. A tatta gas is introduced and a silicon target or quartz (preferably synthetic quartz) is used on the substrate 4 A silicon oxide layer is formed on 50 as an insulating layer 457. The sputtering gas used is... Oxygen or a mixture of oxygen and argon can be used.

[0291] For example, using quartz (preferably synthetic quartz) with a purity of 6N, and a substrate temperature of 108°C, The distance between the substrate and the target (TS distance) is 60 mm, the pressure is 0.4 Pa, and the high-frequency current is set to 60 mm. Power source 1.5kW, oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = A silicon oxide layer is deposited by RF sputtering under a 1:1 atmosphere. The film thickness is 10 The size is set to 0 nm. Note that instead of quartz (preferably synthetic quartz), the silicon target is oxidized. It can be used as a target for depositing a recon layer.

[0292] In this case, it is preferable to form the insulating layer 457 while removing residual moisture in the processing chamber. This is to ensure that the insulating layer 457 does not contain hydrogen, hydroxyl groups, or moisture. The treatment chamber, which is evacuated using an iodine pump, contains compounds that include hydrogen atoms, such as water (H2O). Because compounds containing impurities are exhausted from the treatment chamber, the impurities contained in the insulating layer 457 formed in the treatment chamber are removed. The concentration can be reduced.

[0293] The sputtering gas used when forming the insulating layer 457 is hydrogen, water, hydroxyl groups, or hydrides. It is preferable to use high-purity gas from which impurities have been removed to a level of several ppm or several ppb. It seems so.

[0294] Furthermore, the insulating layer 457 may also have a laminated structure, for example, a silicon nitride layer from the substrate 450 side, Nitride insulating layers such as silicon nitride layer, aluminum nitride layer, and aluminum nitride layer. Alternatively, a laminated structure with the above-mentioned oxide insulating layer may be used.

[0295] For example, a layer containing high-purity nitrogen from which hydrogen and moisture have been removed between the silicon oxide layer and the substrate. A putter gas is introduced and a silicon nitride layer is deposited using a silicon target. In this case, Similarly to the silicon oxide layer, the silicon nitride layer is processed while removing residual moisture in the processing chamber. It is preferable to form a film.

[0296] Next, a conductive layer is formed on the insulating layer 457, and then the conductive layer is formed by the first photolithography process. A resist mask is formed on the film, and selective etching is performed to remove the source electrode layer or drain After forming electrode layers 465a1 and 465a2, remove the resist mask (Figure 20(A (See reference). The source electrode layer or drain electrode layer 465a1, 465a2 is divided in the cross-sectional view. As shown, it is a continuous film. Note that the formed source electrode layer and drain electrode A tapered shape at the edges of the layer is preferable because it improves the coverage of the gate insulating layer laminated on top. It's nice.

[0297] The materials for the source electrode layer or drain electrode layer 465a1, 465a2 are Al, Cr , elements selected from Cu, Ta, Ti, Mo, W, or elements containing the above elements Examples include alloys or alloys combining the elements mentioned above. Also, manganese, magnesium A material selected from one or more of the following: thorium, zirconium, beryllium, and thorium. It may be used. Furthermore, the conductive layer may be a single-layer structure or a multi-layer structure of two or more layers. For example... For example, a single-layer structure of an aluminum layer containing silicon, or a titanium layer laminated on top of the aluminum layer. It has a two-layer structure: a Ti layer, and an aluminum layer stacked on top of the Ti layer, and then another Ti layer on top of that. Examples include a three-layer structure in which an i-layer is formed. Also, titanium (Ti), tantalum ( Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Nd (Neodymium) Layers, alloy layers, and combinations of one or more elements selected from Sc (scandium) are also available. Alternatively, a nitride layer may be used.

[0298] In this embodiment, the source electrode layer or drain electrode layer 465a1, 465a2 is spa A titanium layer with a thickness of 150 nm is formed using the tarring method.

[0299] Next, on the insulating layer 457 and the source electrode layer or drain electrode layers 465a1, 465a2 Then, an oxide semiconductor layer with a thickness of 2 nm to 200 nm is formed.

[0300] Next, the material is processed into island-shaped oxide semiconductor layers 462 by a second photolithography process. (See Figure 20(B)). In this embodiment, an In-Ga-Zn-O metal oxide target is used. An oxide semiconductor layer is formed by sputtering using [a specific method].

[0301] The substrate is held in a processing chamber maintained under reduced pressure, and while removing residual moisture from the processing chamber, hydrogen is used. Then, a sputtering gas from which moisture has been removed is introduced, and a metal oxide is used as the target for the substrate 450. An oxide semiconductor layer is deposited on top. To remove residual moisture in the processing chamber, an adsorption-type vacuum is used. It is preferable to use a pump. For example, a cryopump, an ion pump, or a titanium subpump. It is preferable to use an acceleration pump. Furthermore, as an exhaust means, a turbo pump is used. A gold trap may also be added. The treatment chamber, which has been evacuated using a cryopump, For example, compounds containing hydrogen atoms such as water (H2O) (more preferably compounds containing carbon atoms) Because substances such as [unclear] are exhausted, the concentration of impurities in the oxide semiconductor layer formed in the processing chamber increases. The temperature can be reduced. Furthermore, the substrate may be heated during oxide semiconductor layer deposition.

[0302] The sputtering gas used when depositing oxide semiconductor layers is hydrogen, water, hydroxyl groups, or hydrides. Using high-purity gas from which impurities such as these have been removed to a few ppm or a few ppb is possible. preferable.

[0303] An example of film deposition conditions is a substrate temperature of room temperature and a distance of 60 mm between the substrate and the target. Pressure 0.4 Pa, DC power supply 0.5 kW, oxygen and argon (oxygen flow rate 15 scc) The conditions applied are under an atmosphere with an argon flow rate of 30 sccm. Using a power supply reduces the amount of powdery material (also called particles or dust) generated during film formation. This is preferable because it also results in a uniform film thickness distribution. The oxide semiconductor layer is preferably 5 nm or more and 30 nm thick. The thickness should be less than or equal to nm. Note that the appropriate thickness varies depending on the oxide semiconductor material used. You can then choose the appropriate thickness.

[0304] In this embodiment, a solution of phosphoric acid, acetic acid, and nitric acid is used as the etching solution. The oxide semiconductor layer is processed into island-shaped oxide semiconductor layers 462 by an etching method.

[0305] In this embodiment, the oxide semiconductor layer 462 is subjected to a first heat treatment. The temperature shall be between 400°C and 750°C, preferably between 400°C and below the substrate's strain point. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer is subjected to After heating at 450°C for 1 hour under a nitrogen atmosphere, without exposure to air, acid This first heat treatment prevents the re-imposition of water and hydrogen into the oxide semiconductor layer, thereby obtaining an oxide semiconductor layer. This allows for dehydration or dehydrogenation of the oxide semiconductor layer 462.

[0306] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction from heat sources such as resistance heating elements or The device may include an apparatus that heats the object to be processed by thermal radiation. For example, GRTA(Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal) RTA (Rapid Thermal A A nneal apparatus can be used. For example, as the first heat treatment, 650°C~7 The substrate is moved into an inert gas heated to a high temperature of 0°C and heated for several minutes, and then the substrate GRTA may be performed by moving the material and releasing it from an inert gas heated to a high temperature. Using this method allows for high-temperature heat treatment in a short amount of time.

[0307] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the solution does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device. or the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferred It is preferable to keep the concentration below 0.1 ppm.

[0308] Furthermore, depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor The layers may crystallize, becoming microcrystalline or polycrystalline.

[0309] Furthermore, the first heat treatment of the oxide semiconductor layer is the oxidation before processing into an island-shaped oxide semiconductor layer. This can also be done on a semiconductor layer. In that case, after the first heat treatment, the substrate is removed from the heating device. The material is removed and the photolithography process is performed.

[0310] Heat treatments that have the effect of dehydrating and dehydrogenating oxide semiconductor layers are used for oxide semiconductor layers. After film formation, source electrodes and drain electrodes are further stacked on the oxide semiconductor layer, and then the source This may be done either after forming a gate insulating layer on the electrode and the drain electrode.

[0311] Next, a conductive layer is formed on the insulating layer 457 and the oxide semiconductor layer 462, and the third photo A resist mask is formed on the conductive layer by a lithography process, and selective etching is performed. After forming the source electrode layer or drain electrode layer 465b and the wiring layer 468, the resist mass Remove the 'K' (see Figure 20(C)). Source electrode layer or drain electrode layer 465b, wiring layer 468 is made of the same materials and processes as the source electrode layer or drain electrode layer 465a1, 465a2. That's how you should form it.

[0312] In this embodiment, the source electrode layer or drain electrode layer 465b and the wiring layer 468 are made of spa A titanium layer with a thickness of 150 nm is formed by the tarring method. In this embodiment, the source electrode Layer or drain electrode layer 465a1, 465a2 and source electrode layer or drain electrode layer 465 This is an example where the same titanium layer is used in b, so source electrode layer or drain electrode layer 465a1, 46 5a2 and the source electrode layer or drain electrode layer 465b have a selectivity ratio in etching. No. Therefore, the source electrode layer or drain electrode layer 465a1, 465a2 is the source electrode. To prevent etching during etching of the layer or drain electrode layer 465b, A wiring layer 468 is placed on the source electrode layer or drain electrode layer 465a2 that is not covered by the body layer 462. It is provided. Source electrode layer or drain electrode layer 465a1, 465a2 and source electrode layer or The drain electrode layer 465b and a different material having a high selectivity ratio in the etching process are used. When used, protect the source electrode layer or drain electrode layer 465a2 during etching. The wiring layer 468 does not necessarily have to be provided.

[0313] Furthermore, during the etching of the conductive film, the oxide semiconductor layer 462 is not removed. The materials and etching conditions are adjusted as appropriate.

[0314] In this embodiment, a Ti layer is used as the conductive film, and the oxide semiconductor layer 462 is In-G Using an α-Zn-O oxide semiconductor, ammonia peroxide (ammonia) is used as the etchant. Use a mixture of water and hydrogen peroxide solution.

[0315] In the third photolithography process, only a portion of the oxide semiconductor layer 462 is etched. It may also be formed as an oxide semiconductor layer having grooves (recesses). Alternatively, an inkjet resist mask for forming the drain electrode layer 465b and the wiring layer 468. It may also be formed by the inkjet method. If the resist mask is formed by the inkjet method, it will be a photomask. Because it does not use a component, manufacturing costs can be reduced.

[0316] Next, insulating layer 457, oxide semiconductor layer 462, source electrode layer or drain electrode layer 46 5a1, 465a2, source electrode layer or drain electrode layer 465b, and on wiring 468 A 452 insulating layer is formed.

[0317] The gate insulating layer 452 is formed using a plasma CVD method or a sputtering method, etc. silicon oxide layer, silicon nitride layer, silicon oxide nitride layer, silicon oxide nitride layer, Alternatively, a single or multilayer aluminum oxide layer may be applied. Note that the gate insulating layer 4 To prevent a large amount of hydrogen from being contained in 52, the gate insulating layer is made using the sputtering method. It is preferable to deposit 452. When depositing the silicon oxide layer by sputtering. For this process, a silicon target or a quartz target is used as the target, and sputtering gas This is carried out using oxygen or a mixture of oxygen and argon.

[0318] The gate insulating layer 452 is a source electrode layer or drain electrode layer 465a1, 465a2, A silicon oxide layer and a silicon nitride layer are laminated from the electrode layer or drain electrode layer 465b side. It can also be structured as follows. In this embodiment, the pressure is 0.4 Pa and the high-frequency power supply is 1.5 kW. , oxygen and argon atmosphere (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1) A silicon oxide layer with a thickness of 100 nm is formed by RF sputtering under gas pressure.

[0319] Next, a resist mask is formed by a fourth photolithography step, and selectively etched Chining is performed to remove a portion of the gate insulation layer 452, creating an opening 423 that reaches the wiring layer 468. (See Figure 20(D)). Although not shown, when forming the opening 423, the source electrode layer or An opening reaching the drain electrode layer 465b may be formed. In this embodiment, the source electrode The opening to the layer or drain electrode layer 465b is formed after further lamination of the interlayer insulating layer, and electrical This example shows how to form a wiring layer for direct connection in an opening.

[0320] Next, after forming a conductive layer on the gate insulating layer 452 and the opening 423, the fifth photolithography The gate electrode layer 461 (461a, 461b) and the wiring layer 464 are formed by the sography process. The resist mask may also be formed by an inkjet method. Since the inkjet method does not require the use of a photomask, manufacturing costs can be reduced.

[0321] Furthermore, the gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of molybdenum. Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, Scandinavian A single layer or laminate of metallic materials such as um, or alloy materials mainly composed of these, can be applied. Cut.

[0322] In this embodiment, the gate electrode layer 461 (461a, 461b) and the wiring layer 464 are made of A titanium layer with a thickness of 150 nm is formed using the puttering method.

[0323] Next, a second heat treatment (preferably) is performed under an inert gas atmosphere or an oxygen gas atmosphere. The process is carried out at a temperature of 200°C to 400°C (for example, 250°C to 350°C). The second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. Alternatively, this may be done after forming a protective insulating layer or a planar insulating layer on the thin-film transistor 460.

[0324] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may be done. This heat treatment may be performed by heating while maintaining a constant heating temperature, or from room temperature, 1 The process involves raising the temperature to a heating temperature between 00°C and 200°C, and then lowering the temperature from the heating temperature back to room temperature multiple times. This process may be repeated. Furthermore, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. It is also acceptable to perform the heat treatment under reduced pressure, which can shorten the heating time.

[0325] In the above process, the concentrations of hydrogen, water, hydride, and hydroxide are reduced in the oxide semiconductor layer 4. A thin-film transistor 460 having 62 can be formed (see Figure 20(E)).

[0326] Furthermore, a protective insulating layer and a planarizing insulating layer for planarization are provided on the thin-film transistor 460. It is also possible to use a gate insulating layer 452, a protective insulating layer, or a planar insulating layer. An opening is formed that reaches the source electrode layer or drain electrode layer 465b, and the source electrode layer is placed in the opening. Alternatively, a wiring layer is formed that is electrically connected to the drain electrode layer 465b.

[0327] As described above, when forming an oxide semiconductor layer, residual moisture in the reaction atmosphere is removed. This makes it possible to reduce the concentration of hydrogen and hydrides in the oxide semiconductor layer. This allows for the stabilization of the oxide semiconductor layer.

[0328] The thin-film transistors described above are the transistors in the logic circuits shown in Embodiments 1 to 6. By applying this to the transistor, charge leakage through the thin-film transistor is suppressed. This can be achieved. As a result, the power consumption (standby power) of logic circuits can be reduced and errors in logic circuits can be corrected. This makes it possible to suppress the action.

[0329] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0330] (Embodiment 9) This embodiment shows an example of a transistor in the logic circuit shown in Embodiments 1 to 6. This will be explained. Specifically, the channel formation region is made up of an oxide semiconductor. Let's describe an example of a film transistor.

[0331] One embodiment of the thin-film transistor and its fabrication method according to this embodiment will be explained with reference to Figure 21. ru.

[0332] Figures 21(A) to (E) show examples of cross-sectional structures of thin-film transistors. The thin-film transistor 390 shown in (E) is a bottom-gate structure and is an inverse staggered thin-film transistor. Also called a film transistor.

[0333] Furthermore, thin-film transistor 390 is explained using a single-gate thin-film transistor. However, if necessary, a thin film transient with a multi-gate structure having multiple channel formation regions It is possible to form a sta.

[0334] The thin-film transistor 390 is fabricated on the substrate 394 using Figures 21(A) to (E) below. I will explain the process.

[0335] First, a conductive layer is formed on a substrate 394 having an insulating surface, and then a first photolithograph is used. The gate electrode layer 391 is formed by the following process. The ends of the formed gate electrode layer 391 are A super-shaped configuration is preferable because it improves the coverage of the gate insulating layer laminated on top. The resist mask may be formed by an inkjet method. Since this method eliminates the need for photomasks, manufacturing costs can be reduced.

[0336] There are no major restrictions on the substrates that can be used for the substrate 394 having an insulating surface, however few At the very least, it must have sufficient heat resistance to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass can be used.

[0337] Furthermore, for glass substrates, if the subsequent heat treatment temperature is high, the strain point will be 730°C or higher. It is best to use the above. Also, for the glass substrate, for example, aluminosilicate glass, Glass materials such as aluminoborosilicate glass and bariumborosilicate glass are used. Generally, by including more barium oxide (BaO) compared to boron oxide, Practical heat-resistant glass can be obtained. For this reason, a glass substrate containing more BaO than B2O3 is used. It is preferable to use

[0338] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. An insulating substrate may be used. Other materials such as crystallized glass can also be used. Furthermore, plastic substrates and the like can be used as appropriate.

[0339] An insulating layer serving as the base film may be provided between the substrate 394 and the gate electrode layer 391. This has the function of preventing the diffusion of impurity elements from the substrate 394, and the silicon nitride layer, oxide One or more films selected from a silicon nitride layer, a silicon nitride layer, or a silicon oxide nitride layer It can be formed by a laminated structure.

[0340] Furthermore, the gate electrode layer 391 is made of molybdenum, titanium, chromium, tantalum, and tungsten. Metal materials such as stainless steel, aluminum, copper, neodymium, scandium, or materials with these as their main components A single layer or laminate of the alloy material can be applied.

[0341] For example, as a two-layer stacked structure of the gate electrode layer 391, molybdenum on an aluminum layer A two-layer laminated structure in which layers are stacked, a two-layer structure in which a molybdenum layer is stacked on a copper layer, on a copper layer A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated, and the titanium nitride layer and molybdenum A two-layer structure in which a tungsten layer and a tungsten layer are stacked, or a tungsten nitride layer and a tungsten layer are stacked. A two-layer structure is preferred. As for a three-layer laminated structure, a tungsten layer or a nitride layer is preferred. A stenescent layer and an aluminum-silicon alloy layer or an aluminum-titanium alloy layer It is preferable to have a structure in which a titanium nitride layer or a titanium layer is laminated. A conductive layer having light-transmitting properties can also be used to form the gate electrode layer. Examples of such materials include translucent conductive oxides.

[0342] Next, a gate insulating layer 397 is formed on the gate electrode layer 391.

[0343] The gate insulating layer 397 is formed using plasma CVD or sputtering. silicon oxide layer, silicon nitride layer, silicon oxide nitride layer, silicon oxide nitride layer, Alternatively, a single or multilayer aluminum oxide layer may be applied. Note that the gate insulating layer 3 To prevent excessive hydrogen from being present in 97, the gate insulating layer is made using the sputtering method. It is preferable to deposit 397. When depositing a silicon oxide layer by sputtering. For this process, a silicon target or a quartz target is used as the target, and sputtering gas This is carried out using oxygen or a mixture of oxygen and argon.

[0344] The gate insulating layer 397 consists of a silicon nitride layer and a silicon oxide layer, viewed from the gate electrode layer 391 side. A layered structure can also be used. For example, sputtering can be used as the first gate insulating layer. By law, a silicon nitride layer (SiN) with a thickness of 50 nm to 200 nm. y (y>0) The first gate insulating layer is then layered with a second gate insulating layer with a thickness of 5 nm to 300 nm. silicon oxide layer (SiO x (x>0)) are stacked to form a gate insulating layer with a thickness of 100 nm and do.

[0345] Furthermore, hydrogen, hydroxyl groups, and moisture are present in the gate insulating layer 397 and the oxide semiconductor layer 393 as much as possible. To prevent contamination, as a pretreatment before film formation, in the preheating chamber of the sputtering apparatus A substrate 394 on which the gate electrode layer 391 is formed, or a substrate up to the gate insulating layer 397 is formed. The substrate 394 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 394 and exhaust the waste. It is preferable to do so. The preheating temperature is preferably 100°C to 400°C. The temperature is between 150°C and 300°C. The exhaust means provided in the preheating chamber is a cryopone. P is preferred. Note that this preheating process can be omitted. Also, this preheating is Before forming the oxide insulating layer 396, the source electrode layer 395a and the drain electrode layer 395b The same procedure may be performed on the substrate 394 formed by the same method.

[0346] Next, an oxide semiconductor layer 3 with a thickness of 2 nm to 200 nm is placed on the gate insulating layer 397. Forms 93 (see Figure 21(A)).

[0347] Furthermore, before depositing the oxide semiconductor layer 393 by sputtering, argon gas was used. Inverted sputtering is performed to generate plasma, and the material is deposited on the surface of the gate insulating layer 397. It is preferable to remove any debris. Reverse sputtering is a process where voltage is not applied to the target side. Under an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form a plasma near the substrate. This is a method for modifying the surface. Note that nitrogen, helium, and oxygen can be used instead of an argon atmosphere. You may also use the following:

[0348] The oxide semiconductor layer 393 is deposited by sputtering. In-Ga-Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-G a-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, Zn-O system oxides A semiconductor is used. In this embodiment, the oxide semiconductor layer 393 is made of an In-Ga-Zn-O system. The film is deposited by sputtering using an oxide target. Furthermore, the oxide semiconductor layer 3 93 is under a noble gas (typically argon) atmosphere, under an oxygen atmosphere, or under a noble gas (typically It can be formed by sputtering in an argon and oxygen atmosphere. Furthermore, when using the sputtering method, the saturates the saturates containing 2% to 10% by weight of SiO2. Film deposition may also be performed using a GET device.

[0349] As a target for fabricating oxide semiconductor layer 393 by sputtering, A metal oxide target with lead as the main component can be used. Other examples of target materials include metal oxide targets containing In, Ga, and Zn (composition ratio) As such, In2O3:Ga2O3:ZnO=1:1:1[mol], In:Ga:Zn= A ratio of 1:1:0.5 [atom] can be used. Also, it contains In, Ga, and Zn. As a metal oxide target, In:Ga:Zn=1:1:1[atom], or In A target with a composition ratio of :Ga:Zn=1:1:2[atom] can also be used. The filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more. It is 9.9%. By using a metal oxide target with a high packing density, the deposited oxide film is formed. The semiconductor layer becomes a dense layer.

[0350] The substrate is held in a processing chamber under reduced pressure, and the substrate is brought to a temperature between room temperature and 400°C. Heat it up. Then, while removing residual moisture in the processing chamber, the sputter is treated to remove hydrogen and moisture. A gas is introduced, and an oxide semiconductor layer 393 is formed on the substrate 394 using a metal oxide as the target. To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, using cryopumps, ion pumps, and titanium sublimation pumps. It is preferable to add a cold trap to the turbopump as an exhaust means. It may also be a material. The treatment chamber, which has been evacuated using a cryopump, may contain, for example, water (H2O). Compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) are exhausted. Therefore, the concentration of impurities in the oxide semiconductor layer deposited in the processing chamber can be reduced. By performing sputter deposition while removing residual moisture in the processing chamber using a cryopump, The substrate temperature when depositing the oxide semiconductor layer 393 can be set to room temperature or higher and less than 400°C. Cut.

[0351] One example of film deposition conditions is a distance of 100 mm between the substrate and the target, and a pressure of 0.6 P. a. The following conditions apply: DC power supply of 0.5kW, and an oxygen atmosphere (oxygen flow rate ratio of 100%). It is done. Furthermore, when using a pulsed DC power supply, the powdery substance (partition) generated during film formation is produced. This is preferable because it reduces debris (also called dust) and results in a more uniform film thickness distribution. The body layer is preferably 5 nm to 30 nm in thickness. Note that the oxide semiconductor material used may vary. The appropriate thickness varies depending on the material, so you should select the appropriate thickness according to the material.

[0352] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and There is the DC sputtering method, and further, pulsed DC sputtering, which applies a pulsed bias. There is also the sputtering method. RF sputtering is mainly used when depositing an insulating layer, and DC sputtering. The tarring method is mainly used for depositing metal layers.

[0353] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to deposit films by simultaneously discharging different materials.

[0354] Furthermore, a sputtering method using a magnetron sputtering system equipped with a magnetic mechanism inside the chamber is also used. ECR uses a tater device or plasma generated using microwaves instead of glow discharge. There are sputtering machines that use the sputtering method.

[0355] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering occur during film deposition. Reactive sputtering involves chemically reacting gaseous components to form thin film compounds. There are also bias sputtering methods, which involve applying voltage to the substrate during film deposition.

[0356] Next, the oxide semiconductor layer is transformed into island-shaped oxide semiconductor layers by a second photolithography process. Process into 399 (see Figure 21(B)). Also, form island-shaped oxide semiconductor layers 399. A resist mask may be formed by an inkjet method. Since the wet process does not require the use of a photomask, manufacturing costs can be reduced.

[0357] Furthermore, when forming contact holes in the gate insulating layer 397, the process involves oxide semiconductor This can be performed when layer 399 is formed.

[0358] Note that the etching of the oxide semiconductor layer 393 here can be done using either dry etching or wet etching. Etching is also an option, or both methods can be used.

[0359] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (C) Cl4) etc. are preferred.

[0360] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (S) F6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc., hydrogen bromide (HB r), oxygen (O2), and noble gases such as helium (He) and argon (Ar) can be added to these gases. Gases with added substances, etc., can be used.

[0361] As for dry etching methods, parallel plate type RIE (Reactive Ion Etc The hing method, or ICP (Inductively Coupled Plasma): A conductively coupled plasma etching method can be used. The desired processing shape can be etched. To enable etching, the etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The amount of power being applied, the electrode temperature on the substrate, etc., are adjusted as appropriate.

[0362] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid. These can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0363] Furthermore, the etching solution after wet etching is washed together with the etched material. The material is removed. The waste liquid of the etching solution containing the removed material is purified, and the contained material The waste liquid after etching may be reused. Indium contained in the oxide semiconductor layer can be extracted from the waste liquid after etching. By recovering and reusing materials such as these, resources can be used effectively and costs can be reduced. ru.

[0364] To enable etching to the desired shape, etching conditions (etching) are adjusted according to the material. Adjust the etching solution, etching time, temperature, etc. as appropriate.

[0365] Furthermore, before forming the conductive layer in the next step, reverse sputtering is performed to form the oxide semiconductor layer 399 and the gate It is preferable to remove any resist residue or other material adhering to the surface of the insulating layer 397.

[0366] Next, a conductive layer is formed on the gate insulating layer 397 and the oxide semiconductor layer 399. The conductive layer can be formed by sputtering or vacuum deposition. As for the material of the conductive layer, Al, Elements selected from Cr, Cu, Ta, Ti, Mo, and W, or elements containing the above elements as components. Examples include alloys or alloy layers combining the elements mentioned above. Also, manganese, magnesium Selected from one or more of the following: nesium, zirconium, beryllium, and thorium Materials may be used. Furthermore, the metal conductive layer may be a single layer or a laminated structure of two or more layers. Good. For example, a single-layer structure of an aluminum layer containing silicon, or a titanium layer on top of an aluminum layer. A two-layer structure is formed by stacking a Ti layer and an aluminum layer stacked on top of the Ti layer. Furthermore, a three-layer structure in which a Ti layer is stacked on top of it can be mentioned. Also, a titanium (T) layer can be added to Al. i) Tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), One or more elements selected from Nd (neodymium) and Sc (scandium) are used in combination. A layer, alloy layer, or nitride layer may be used.

[0367] A third photolithography step forms a resist mask on the conductive layer, and selectively... After performing a stirring to form the source electrode layer 395a and the drain electrode layer 395b, the resistor Remove the tomask (see Figure 21(C)).

[0368] For exposure during resist mask formation in the third photolithography step, ultraviolet light or KrF Laser light or ArF laser light is used. Adjacent source electrode layers on oxide semiconductor layer 399 The gap width between the lower end and the lower end of the drain electrode layer determines the thin film transistor that is later formed. The channel length L is determined. Note that if exposure is performed with a channel length L less than 25 nm, Extreme ultraviolet light (Ultraviolet) has extremely short wavelengths, ranging from a few nanometers to tens of nanometers. Exposure during the resist mask formation process in the third photolithography step is performed using et). Exposure with ultra-ultraviolet light yields high resolution and a large depth of field. Therefore, the thin film that is subsequently formed... It is also possible to set the channel length L of the lampistor to between 10 nm and 1000 nm. The circuit operation speed can be increased, and since the off-current value is extremely small, power consumption can also be reduced. It is possible.

[0369] Furthermore, during etching of the conductive layer, the oxide semiconductor layer 399 is not removed. The materials and etching conditions are adjusted as appropriate.

[0370] In this embodiment, a Ti layer is used as the conductive film, and the oxide semiconductor layer 399 is In-G Using an α-Zn-O oxide semiconductor, ammonia peroxide (ammonia) is used as the etchant. Use a mixture of water and hydrogen peroxide solution.

[0371] In the third photolithography process, only a portion of the oxide semiconductor layer 399 is etched. It may also be formed as an oxide semiconductor layer having grooves (recesses). A resist mask for forming drain electrode layer 395a and drain electrode layer 395b is formed by inkjet method. It may also be formed by an inkjet method. If the resist mask is formed by an inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0372] Furthermore, in order to reduce the number of photomasks and processes used in the photolithography process, A resist formed by a multi-gradation mask, which is an exposure mask where the light that passes through it has multiple intensities. The etching process may be performed using a mask. A resist formed using a multi-gradation mask. The mask has a shape with multiple film thicknesses, and its shape can be further deformed by etching. Because it can do this, it can be used in multiple etching processes to process different patterns. Therefore, a single multi-tone mask can be used to create at least two different patterns. A corresponding resist mask can be formed. Therefore, the number of exposure masks can be reduced. Furthermore, the corresponding photolithography process can also be reduced, thus simplifying the overall process.

[0373] Oxidation exposed by plasma treatment using gases such as N2O, N2, or Ar Adsorbed water and other substances adhering to the surface of the semiconductor layer may be removed. Also, a mixture of oxygen and argon may be used. Plasma treatment may be performed using gas.

[0374] When plasma treatment is performed, the acid comes into contact with a portion of the oxide semiconductor layer without coming into contact with the atmosphere. A oxide insulating layer 396 is formed (see Figure 21(D)). In this embodiment, the oxide semiconductor layer In the region where 399 does not overlap with the source electrode layer 395a and the drain electrode layer 395b, acid The oxide semiconductor layer 399 and the oxide insulating layer 396 are formed in contact with each other.

[0375] In this embodiment, the oxide insulating layer 396 is an island-shaped oxide semiconductor layer 399, source The substrate 394, on which the electrode layer 395a and drain electrode layer 395b have been formed, is heated to room temperature or above 100°C. The material is heated to a temperature below a certain level, and a sputtered gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced. A silicon oxide layer containing defects is deposited using a silicon target.

[0376] For example, a silicon target with a purity of 6N and doped with boron (resistance value 0.0 Using a Ωcm resistor, the distance between the substrate and the target (TS distance) was set to 89 mm, and the pressure was 0 0.4 Pa, 6 kW DC power supply, under an oxygen (100% oxygen flow rate) atmosphere, pulse D A silicon oxide layer is deposited using the C sputtering method. The film thickness is set to 300 nm. To form a silicon oxide layer, use quartz (preferably synthetic quartz) instead of a silicon target. It can be used as a target. Furthermore, oxygen or oxygen and... This is done using a mixed gas of argon and bisulfite.

[0377] In this case, the oxide insulating layer 396 is formed while removing residual moisture in the processing chamber. This is preferable. Hydrogen, hydroxyl groups, or water are present in the oxide semiconductor layer 399 and the oxide insulating layer 396. This is to ensure that it is not included.

[0378] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, by using cryopumps, ion pumps, and titanium sublimation pumps. This is preferable. Furthermore, as an exhaust means, a turbo pump with a cold trap added is preferable. It may be present. The treatment chamber, which is evacuated using a cryopump, contains, for example, water (H2O). Since compounds containing elementary atoms and other compounds are exhausted, oxide insulation films formed in the processing chamber are affected. The concentration of impurities in layer 396 can be reduced.

[0379] Furthermore, as the oxide insulating layer 396, instead of the silicon oxide layer, a silicon oxide nitride layer, acid An aluminum oxide layer or an aluminum oxide nitride layer can also be used.

[0380] Furthermore, with the oxide insulating layer 396 and the oxide semiconductor layer 399 in contact, at 100°C to 4°C Heat treatment may be performed at 0°C. The oxide insulating layer 396 in this embodiment has many defects. Because it contains hydrogen, water, and hydroxyl contained in the oxide semiconductor layer 399, this heat treatment removes them. Impurities such as ions or hydrides are diffused into the oxide insulating layer 396, and in the oxide semiconductor layer 399 This makes it possible to further reduce the amount of impurities contained in the material.

[0381] In the above process, the oxide semiconductor layer 3 in which the concentration of hydrogen, water, hydroxyl groups, or hydrides is reduced is obtained. A thin-film transistor 390 having 92 can be formed (see Figure 21(E)).

[0382] As described above, when forming an oxide semiconductor layer, residual moisture in the reaction atmosphere is removed. This makes it possible to reduce the concentration of hydrogen and hydrides in the oxide semiconductor layer. This allows for the stabilization of the oxide semiconductor layer.

[0383] A protective insulating layer may be provided on the oxide insulating layer. In this embodiment, the protective insulating layer 398 is It is formed on the oxide insulating layer 396. The protective insulating layer 398 is a silicon nitride layer, an acid nitride layer. A silicon oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer is used.

[0384] As a protective insulating layer 398, the substrate 394, which has an oxide insulating layer 396 formed on it, is heated to 100°C~ Sputtered gas containing high-purity nitrogen, from which hydrogen and moisture have been removed, is introduced after heating to a temperature of 400°C. A silicon nitride layer is formed using an embedded silicon target. In this case as well, oxidation Similar to the material insulating layer 396, the protective insulating layer 398 is formed while removing residual moisture in the processing chamber. It is preferable.

[0385] When forming the protective insulating layer 398, the temperature during film formation of the protective insulating layer 398 is 100°C to 400°C. By heating the substrate 394, hydrogen or moisture contained in the oxide semiconductor layer is eliminated by the oxide insulation. It can be diffused into the margin layer. In this case, heat treatment is performed after the formation of the oxide insulating layer 396. It is not necessary to do so.

[0386] A silicon oxide layer is formed as the oxide insulating layer 396, and a silicon nitride layer is formed as the protective insulating layer 398. When stacking layers, the silicon oxide layer and the silicon nitride layer are processed in the same processing chamber. Thin films can be deposited using a silicon target. First, a sputtering gas containing oxygen is introduced. Then, a silicon oxide layer is formed using a silicon target installed in the processing chamber, and then Switching the sputtering gas to a nitrogen-containing sputtering gas and using the same silicon target... A silicon oxide layer is formed. The silicon oxide layer and the silicon nitride layer are continuously formed without exposure to the atmosphere. Because it can be formed in this way, impurities such as hydrogen and moisture are adsorbed onto the surface of the silicon oxide layer. This can prevent the following. In this case, the silicon oxide layer is formed as the oxide insulating layer 396. After completing the process, a silicon nitride layer is laminated as a protective insulating layer 398, and then it is incorporated into the oxide semiconductor layer. Heat treatment (temperature 100°C to 40°C) to diffuse hydrogen or moisture into the oxide insulating layer It is recommended to perform the procedure at 0°C.

[0387] After forming the protective insulating layer, further exposure to air at a temperature between 100°C and 200°C for 1 to 30 hours. The following heat treatment may be performed. This heat treatment can be performed by maintaining a constant heating temperature. Okay, raising the temperature from room temperature to a heating temperature of 100°C to 200°C, and from the heating temperature back to room temperature. The cooling process up to this point may be repeated multiple times. Alternatively, this heat treatment can be applied to the oxide insulating layer. The process may be carried out under reduced pressure before formation. Heating under reduced pressure shortens the heating time. This can be done. This heat treatment makes it possible to obtain a thin-film transistor that is normally off. Yes, it is possible. Therefore, the reliability of semiconductor devices can be improved.

[0388] Furthermore, when forming an oxide semiconductor layer on the gate insulating layer to serve as a channel formation region, By removing residual moisture in the atmosphere, the concentration of hydrogen and hydrides in the oxide semiconductor layer can be reduced. This can be reduced.

[0389] The above process uses a liquid crystal display panel, an electroluminescent display panel, and electronic ink. Used in the manufacture of backplanes (substrates on which thin-film transistors are formed) for display devices and the like. This is possible. Since the above process is carried out at a temperature of 400°C or less, the thickness will be 1 mm or less. Therefore, it can also be applied to manufacturing processes that use glass substrates with sides exceeding 1 meter. Since all processes can be carried out at processing temperatures below 400℃, it is possible to manufacture display panels. It saves a lot of energy from having to expend it.

[0390] The thin-film transistors described above are the transistors in the logic circuits shown in Embodiments 1 to 6. By applying this to the transistor, charge leakage through the thin-film transistor is suppressed. This makes it possible to reduce the standby power consumption of logic circuits and suppress malfunctions of logic circuits. It becomes possible to do so.

[0391] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0392] (Embodiment 10) This embodiment shows an example of a transistor in the logic circuit shown in Embodiments 1 to 6. This will be explained. Specifically, the channel formation region is made up of an oxide semiconductor. Let's describe an example of a film transistor.

[0393] One embodiment of the thin-film transistor and its fabrication method according to this embodiment will be explained with reference to Figure 22. ru.

[0394] Figures 22(A) to (D) show examples of cross-sectional structures of thin-film transistors. Figure 22(D) shows The thin-film transistor 360 shown is called a channel-protected type (also called a channel-stopped type). It is one of the bottom-gate structures and is also called an inverse staggered thin-film transistor.

[0395] Furthermore, thin-film transistor 360 is explained using a single-gate thin-film transistor. However, if necessary, a thin film transient with a multi-gate structure having multiple channel formation regions It can also form a sta.

[0396] The thin-film transistor 360 is fabricated on the substrate 320 using Figures 22(A) to (D) below. I will explain the process.

[0397] First, a conductive layer is formed on a substrate 320 having an insulating surface, and then a first photolithograph is used. The gate electrode layer 361 is formed by the following process. The resist mask is then prepared using an inkjet method. It may also be formed by an inkjet method. If the resist mask is formed by an inkjet method, a photomask is used. Therefore, manufacturing costs can be reduced.

[0398] Furthermore, the gate electrode layer 361 can be made of molybdenum, titanium, chromium, tantalum, and tungsten. Metal materials such as stainless steel, aluminum, copper, neodymium, scandium, or materials with these as their main components A single layer or laminate of the alloy material can be applied.

[0399] Next, a gate insulating layer 322 is formed on the gate electrode layer 361.

[0400] In this embodiment, the gate insulating layer 322 is made with a thickness of 100 nm by plasma CVD. The following silicon oxide nitride layer is formed.

[0401] Next, an oxide semiconductor layer with a thickness of 2 nm or more and 200 nm or less is placed on the gate insulating layer 322. The material is formed and then processed into island-shaped oxide semiconductor layers by a second photolithography process. In this configuration, an In-Ga-Zn-O-based metal oxide target is used as the oxide semiconductor layer. The film is then deposited by sputtering.

[0402] In this case, the oxide semiconductor layer is formed while removing residual moisture in the processing chamber. This is preferable, as it prevents hydrogen, hydroxyl groups, or moisture from being contained in the oxide semiconductor layer.

[0403] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, by using cryopumps, ion pumps, and titanium sublimation pumps. This is preferable. Furthermore, as an exhaust means, a turbo pump with a cold trap added is preferable. It may be present. The treatment chamber, which is evacuated using a cryopump, contains, for example, water (H2O). Because compounds containing elementary atoms are exhausted, they are contained in the oxide semiconductor layer formed in the processing chamber. The concentration of impurities can be reduced.

[0404] The sputtering gas used when depositing oxide semiconductor layers is hydrogen, water, hydroxyl groups, or hydrides. Using high-purity gas from which impurities such as these have been removed to a few ppm or a few ppb is possible. preferable.

[0405] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C to 750°C, preferably 400°C or higher, to reduce substrate strain. The temperature should be below the 0.0 point. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor... The conductive layer was subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere, and then exposed to air. Without doing so, the re-importation of water and hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 332 is obtained. (See Figure 22(A)).

[0406] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar. The Zuma treatment removes adsorbed water and other substances adhering to the surface of the exposed oxide semiconductor layer. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0407] Next, an oxide insulating layer is formed on the gate insulating layer 322 and the oxide semiconductor layer 332. Afterward, a resist mask is formed by a third photolithography process, and then selective etching is performed. After performing the necessary steps to form the oxide insulating layer 366, the resist mask is removed.

[0408] In this embodiment, a silicon oxide layer with a thickness of 200 nm is sputtered as the oxide insulating layer 366. The film is deposited using the following method. The substrate temperature during film deposition should be between room temperature and 300°C. In this form, the temperature is set to 100°C. For the deposition of silicon oxide layers by sputtering, a rare gas (typically) Under an argon atmosphere, under an oxygen atmosphere, or a mixture of a noble gas (typically argon) and oxygen. It can be carried out under atmospheric conditions. Also, silicon dioxide target or A silicon target can be used. For example, a silicon target can be used to extract oxygen and nitrogen. A silicon oxide layer can be formed by sputtering under an ambient atmosphere.

[0409] In this case, the oxide insulating layer 366 is formed while removing residual moisture in the processing chamber. This is preferable. Hydrogen, hydroxyl groups, or water are present in the oxide semiconductor layer 332 and the oxide insulating layer 366. This is to ensure that it is not included.

[0410] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, by using cryopumps, ion pumps, and titanium sublimation pumps. This is preferable. Furthermore, as an exhaust means, a turbo pump with a cold trap added is preferable. It may be present. The treatment chamber, which is evacuated using a cryopump, contains, for example, water (H2O). Since compounds containing elementary atoms and other compounds are exhausted, oxide insulation films formed in the processing chamber are affected. The concentration of impurities in layer 366 can be reduced.

[0411] The sputtering gas used when forming the oxide insulating layer 366 is hydrogen, water, hydroxyl group or hydrogen By using high-purity gas from which impurities such as monoxides have been removed to a level of several ppm or several ppb. This is preferable.

[0412] Next, a second heat treatment (preferably) is performed under an inert gas atmosphere or an oxygen gas atmosphere. You may also perform the procedure at temperatures between 200°C and 400°C, for example between 250°C and 350°C. A second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, A portion of the oxide semiconductor layer (channel formation region) is heated while in contact with the oxide insulating layer 366. It can be done.

[0413] In this embodiment, an oxide insulating layer 366 is further provided, and a portion of the oxide semiconductor is exposed. The body layer 332 is heat-treated under nitrogen, an inert gas atmosphere, or under reduced pressure. Oxide insulating layer The region of the exposed oxide semiconductor layer 332 that is not covered by 366 is nitrogen, inert Heating treatment under a gaseous atmosphere or reduced pressure results in an oxygen-deficient state, leading to lower resistance, i.e., N-type. It can be transformed. For example, by heating it at 250°C for 1 hour under a nitrogen atmosphere.

[0414] Heat treatment of an oxide semiconductor layer 332 provided with an oxide insulating layer 366 under a nitrogen atmosphere As a result, the exposed region of the oxide semiconductor layer 332 has low resistance, while the region with different resistance (Figure 22) (B) is an oxide semiconductor layer 362 having the shaded region and the white region.

[0415] Next, on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366, After forming the conductive layer, a resist mask is formed by a fourth photolithography step, and After selective etching is performed to form the source electrode layer 365a and the drain electrode layer 365b, Remove the resist mask (see Figure 22(C)).

[0416] The materials for the source electrode layer 365a and the drain electrode layer 365b are Al, Cr, Cu, An element selected from Ta, Ti, Mo, and W, or an alloy containing the above elements, Examples include alloy layers combining the elements mentioned above. Furthermore, metal conductive layers can also be single-layer structures. It may also be a laminated structure of two or more layers.

[0417] Through the above process, the oxide semiconductor layer after film formation undergoes dehydration or dehydrogenation. The heat treatment for the transformation process simultaneously lowers the resistance of the oxide semiconductor layer, i.e., it becomes N-type. By forming an oxide insulating layer in contact with the oxide semiconductor layer, a portion of the oxide semiconductor layer can be selected. A selectively oxygen-rich state is created. As a result, a channel formation region overlaps with the gate electrode layer 361. 363 becomes type I. At this time, the carrier density is at least compared to the channel formation region 363. The degree is high, and there is a high-resistance source region 364a that overlaps with the source electrode layer 365a, and at least one channel Compared to the Nell formation region 363, the carrier density is higher and overlaps with the drain electrode layer 365b, resulting in a high resistance The anti-drain region 364b is formed self-aligned. Through the above process, the thin-film transistor 3 60 is formed.

[0418] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat it while maintaining the heating temperature, or you may heat it from room temperature to a heating temperature of 100°C to 200°C. The process of raising the temperature to a certain degree and then lowering it from the heating temperature back to room temperature may be repeated multiple times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. This process shortens the heating time. This heat treatment removes the oxide semiconductor layer To obtain a thin-film transistor that is normally off by incorporating hydrogen into the oxide insulating layer. This allows for improved reliability of semiconductor devices.

[0419] Furthermore, the oxide semiconductor superimposed on the drain electrode layer 365b (and source electrode layer 365a) By forming a high-resistance drain region 364b (and a high-resistance source region 364a) in the layer This can improve the reliability of thin-film transistors. Specifically, high resistance By forming the rain region 364b, the high-resistance drain region 364b is created from the drain electrode layer. Furthermore, the structure is designed so that the conductivity can be changed in steps in the channel formation region 363. This is possible. Therefore, wiring that supplies a high power supply potential VDD to the drain electrode layer 365b is connected. When operating continuously, a high electric field is generated between the gate electrode layer 361 and the drain electrode layer 365b. Even when applied, the high-resistance drain region acts as a buffer, making localized electric field concentration less likely to occur. This allows for a configuration that improves the pressure resistance of the inverter.

[0420] Source electrode layer 365a, drain electrode layer 365b, protective insulating layer on oxide insulating layer 366 Form 323. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride layer. (See Figure 22(D)).

[0421] Furthermore, the source electrode layer 365a, drain electrode layer 365b, and oxide insulating layer 366 are further An oxide insulating layer may be formed, and a protective insulating layer 323 may be laminated on the oxide insulating layer.

[0422] The thin-film transistors described above are the transistors in the logic circuits shown in Embodiments 1 to 6. By applying this to the transistor, charge leakage through the thin-film transistor is suppressed. This makes it possible to reduce the standby power consumption of logic circuits and suppress malfunctions of logic circuits. It becomes possible to do so.

[0423] Note that the contents of this embodiment or a part thereof may be the contents of other embodiments or parts thereof. It is possible to freely combine a part of this or the contents of other embodiments or parts of said contents. ru.

[0424] (Embodiment 11) In this embodiment, an example of a semiconductor device equipped with the logic circuit obtained in the above embodiment is provided. This will be explained using Figure 23. Note that the logic circuit according to the above embodiment is described as moving the logic circuit. The external circuits that cause the operation are integrated together and mounted on a circuit board, etc., inside each semiconductor device It will be installed in [the vehicle].

[0425] Figure 23(A) shows a notebook-type personal computer having the logic circuit described above. This is a diagram showing the main unit 2201, housing 2202, display unit 2203, keyboard 2204, etc. That's how it's structured.

[0426] Figure 23(B) shows a personal digital assistant (PDA) having the logic circuit described above. The main unit 2211 includes a display unit 2213, an external interface 2215, and operation buttons 22 There are 14 buttons, etc. Additionally, a stylus 2212 is provided as an accessory for operation.

[0427] Figure 23(C) shows an example of an electronic paper having the logic circuit described above, specifically an e-book 22 Figure 20. The e-book 2220 consists of two enclosures: enclosure 2221 and enclosure 2223. It is composed of a body. Housings 2221 and 2223 are integrated by shaft portion 2237. The shaft portion 2237 is used as the axis for opening and closing operations. Furthermore, eBook 2220 can be used just like a paper book.

[0428] The display unit 2225 is incorporated into the casing 2221, and the display unit 2227 is incorporated into the casing 2223. It is included. Display units 2225 and 2227 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2225 in Figure 23(C)), and on the left An image can be displayed on the display unit (display unit 2227 in Figure 23(C)).

[0429] Furthermore, Figure 23(C) shows an example in which the housing 2221 is equipped with an operating section, etc. The enclosure 2221 is equipped with a power supply 2231, operation keys 2233, speaker 2235, etc. It is located on the same surface as the display unit of the casing. Pages can be advanced using operation key 2233. The configuration may also include a keyboard and a pointing device. On the side, there are external connection terminals (earphone jack, USB terminal, or AC adapter and USB terminal). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. It may also be considered complete. Furthermore, the e-book 2220 has a configuration that gives it the functionality of an electronic dictionary. You may do so.

[0430] Furthermore, the e-book 2220 may be configured to transmit and receive information wirelessly. The system will be configured to purchase and download desired book data from an e-book server. It is also possible.

[0431] Furthermore, electronic paper can be applied to any field that displays information. It is possible. For example, in addition to ebooks, posters, in-vehicle advertisements such as trains, and credit cards This can be applied to displays on various types of cards, such as credit cards.

[0432] Figure 23(D) shows a mobile phone having the logic circuit described above. The machine consists of two enclosures, enclosure 2240 and enclosure 2241. Enclosure 2241 is Display panel 2242, speaker 2243, microphone 2244, pointing It includes a device 2246, a camera lens 2247, an external connection terminal 2248, and the like. Furthermore, the housing 2240 includes a solar cell 2249 for charging the mobile phone, and external memory. It is equipped with slot 2250, etc. The antenna is also built into the housing 2241. ru.

[0433] The display panel 2242 has a touch panel function, and the image displayed in Figure 23(D) is The multiple operation keys 2245 are indicated by dotted lines. Note that this mobile phone is solar-powered. A boost circuit is implemented to increase the voltage output by the RU2249 to the voltage required for each circuit. In addition to the above configuration, there is also a configuration that incorporates a contactless IC chip, a small recording device, etc. It is also possible.

[0434] The display panel 2242 changes its orientation as appropriate depending on the usage mode. Since the camera lens 2247 is located on the same plane as the 2242, video calls are possible. Yes. Speaker 2243 and microphone 2244 are not limited to voice calls, but also television broadcasts. It is capable of speaking, recording, and playing back. Furthermore, the casings 2240 and 2241 slide apart. As shown in Figure 23(D), it can be changed from an unfolded state to an overlapping state, and can be used on a mobile phone. Suitable miniaturization is possible.

[0435] External connection terminal 2248 can be connected to various cables such as AC adapters and USB cables. It allows for charging and data communication. Also, the external memory slot 2250 is marked By inserting recording media, it can handle the storage and transfer of larger amounts of data. In addition to the above functions... Furthermore, it may also be equipped with infrared communication functions, television reception functions, etc.

[0436] Figure 23(E) shows a digital camera having the logic circuit described above. The barrel camera consists of the main unit 2261, display unit (A) 2267, eyepiece 2263, and operation switch 2 It consists of components such as 264, a display unit (B) 2265, and a battery 2266.

[0437] Figure 23(F) shows a television device having the logic circuit described above. In John device 2270, the display unit 2273 is incorporated into the housing 2271. Display unit 2 273 makes it possible to display video. Note that here, stand 2275 This configuration provides better support for the casing 2271.

[0438] The television device 2270 is operated using the control switches on the housing 2271, or a separate control unit. This can be done using the remote control unit 2280. The remote control unit 2280 has an operating key -2279 allows you to control the channel and volume, and the information is displayed on the display unit 2273. The video can be controlled. Furthermore, the remote control unit 2280 can control the remote control operation. A display unit 2277 that displays information output from the unit 2280 may also be provided.

[0439] Furthermore, it is preferable that the television equipment 2270 be configured to include a receiver, modem, and the like. The receiver can receive general television broadcasts. Also, via a modem... By connecting to a wired or wireless communication network, one-way communication (from the sender to the receiver) is possible. Information communication is conducted either by the recipient or in both directions (between the sender and recipient, or between recipients). It is possible to do so. [Examples]

[0440] In this example, the measurement of the off-current at the evaluation element (also called TEG) is described below. I will reveal it.

[0441] Figure 24 shows 200 thin-film transistors with L / W = 3 μm / 50 μm connected in parallel, effective In terms of performance, it shows the initial characteristics of a thin-film transistor with L / W = 3 μm / 10000 μm. A top view is shown in Figure 25(A), and an enlarged top view of a part of it is shown in Figure 25(B). The area enclosed by the dotted line in B) is a single layer of thin film with L / W = 3 μm / 50 μm and Lov = 1.5 μm. This is a thin-film transistor. To measure the initial characteristics of the thin-film transistor, the substrate temperature was set to room temperature and The source-drain voltage (hereinafter referred to as drain voltage or Vd) is set to 10V, The gate-gate voltage (hereinafter referred to as gate voltage or Vg) can be changed from -20V to +20V. The change in source-drain current (hereinafter referred to as drain current or Id) when this modification is performed. The characteristics, specifically the Vg-Id characteristics, were measured. Note that in Figure 24, Vg was measured from -20V to +5V. It is shown within the range of [this].

[0442] As shown in Figure 24, a thin-film transistor with a channel width W of 10,000 μm has a Vd of 1V And at 10V the off current is 1 × 10 -13 [A] The following applies to measuring instruments (semiconductors) Parameter analyzer, Agilent 4156C (manufactured by Agilent Corporation) resolution It is below (100 fA).

[0443] The method for fabricating the measured thin-film transistor will be explained.

[0444] First, a silicon nitride layer is formed on the glass substrate as an underlayer by the CVD method, and then the silicon nitride layer A silicon oxide nitride layer was formed on top. A gate electrode layer was formed on the silicon oxide nitride layer by sputtering. A tungsten layer was formed. Here, the tungsten layer was selectively etched to form the gate. An electrode layer was formed.

[0445] Next, a 100 nm thick oxide nitride layer is applied to the gate electrode layer as a gate insulating layer by CVD. A silicon layer was formed.

[0446] Next, an In-Ga-Zn-O oxide semiconductor layer is applied to the gate insulating layer by sputtering. Using a GET (molar ratio, In2O3:Ga2O3:ZnO=1:1:2), thickness 5 A 0 nm oxide semiconductor layer was formed. Then, the oxide semiconductor layer was selectively etched, Island-shaped oxide semiconductor layers were formed.

[0447] Next, the oxide semiconductor layer was subjected to a first process in a clean oven under a nitrogen atmosphere at 450°C for 1 hour. Heat treatment was performed.

[0448] Next, a titanium layer (thickness 15) is placed on the oxide semiconductor layer as the source electrode layer and the drain electrode layer. A 0 nm layer was formed by sputtering. Here, the source electrode layer and drain electrode layer were selected. The thin film transistor is etched precisely, and the channel length L of one thin film transistor is 3 μm, and the channel width W is 5 By setting the thickness to 0 μm and connecting 200 units in parallel, the effective ratio of L / W becomes 3 μm / 10000 μm. I made it happen.

[0449] Next, a protective insulating layer is created in contact with the oxide semiconductor layer using reactive sputtering. A silicon oxide layer was formed with a thickness of 300 nm. Here, the silicon oxide layer, which is the protective layer, was selectively treated. By cutting, openings were formed on the gate electrode layer, source electrode layer, and drain electrode layer. Following this, a second heat treatment was performed at 250°C for 1 hour under a nitrogen atmosphere.

[0450] Then, before measuring the Vg-Id characteristics, the samples were heated at 150°C for 10 hours.

[0451] Through the above process, a bottom-gate type thin film transistor was fabricated.

[0452] As shown in FIG. 24, the thin film transistor is about 1×10 -13 [A], because the hydrogen concentration in the oxide semiconductor layer could be sufficiently reduced in the above fabrication process. The hydrogen concentration in the oxide semiconductor layer is 5×10 19 (atoms / cm 3 ) or less, preferably 5 ×10 18 (atoms / cm 3 ) or less, more preferably 5×10 17 (atoms / cm 3 ) or less. The measurement of the hydrogen concentration in the oxide semiconductor layer is performed by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy).

[0453] In addition, although an example using an In-Ga-Zn-O-based oxide semiconductor was shown, it is not particularly limited, and other oxide semiconductor materials, for example, In-Sn-Zn-O-based, Sn-Ga-Zn-O-based, A l-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, In-Sn-O-based , Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based, etc., can be used. In addition, as the oxide semiconductor material, an In-Al-Zn-O-based material mixed with 2.5 to 10 wt% of AlOx or an In-Zn-O -based material mixed with 2.5 to 10 wt% of SiOx can also be used.

[0454] In addition, the carrier density of the oxide semiconductor layer measured by a carrier measurement instrument is 5×10 14 / cm 3More preferably 5 × 10 12 / cm 3 More preferably, silicon True carrier density: 1.45 × 10⁻⁶ 10 / cm 3 It is equivalent to or less than that. That is, The carrier density of an oxide semiconductor layer can be made to be as close to zero as possible.

[0455] Furthermore, the channel length L of the thin-film transistor can be set to be between 10 nm and 1000 nm. It is possible, the circuit's operating speed can be increased, and because the off-current value is extremely small, it is even more energy-efficient. It can also be made more energy-efficient.

[0456] Furthermore, in the off state of a thin-film transistor, the oxide semiconductor layer can be considered an insulator in the circuit. Design can be performed.

[0457] Next, the temperature characteristics of the off-current for the thin-film transistors fabricated in this embodiment were evaluated. Temperature characteristics are considered in relation to the environmental resistance and performance maintenance of the final product in which thin-film transistors are used. This is an important consideration. Naturally, the smaller the amount of change, the better, as it allows for greater freedom in product design. To increase.

[0458] Temperature characteristics were measured using a constant temperature bath at -30, 0, 25, 40, 60, 80, 100, and 12 The substrates on which thin-film transistors were formed at each temperature of 0°C were kept at a constant temperature, and the drain voltage The Vg-Id characteristics were obtained by varying the voltage (6V) and gate voltage from -20V to +20V.

[0459] Figure 26(A) shows the Vg-Id characteristics measured at each of the above temperatures, superimposed. Figure 26(B) shows an enlarged view of the off-current region enclosed by the dotted line. The curve at the right end, indicated by the arrow, is the curve obtained at -30°C, and the curve at the left end is the curve obtained at 120°C. The curve showing the gain lies somewhere in between. The temperature dependence of the on-current is almost negligible. On the other hand, As is also clear in the enlarged view of Figure 26(B), the off-current occurs when the gate voltage is close to 20V. Except for the surrounding area, the measurement was near the resolution of the instrument at all temperatures, 1 × 10⁻⁶. -12 [A] is below Furthermore, temperature dependence is not observed. That is, even at a high temperature of 120°C, the off-current is 1 × 1 0 -12 [A] The following conditions must be met, and the effective channel width W must be 10,000 μm. Considering this, it can be seen that the off-current is very small.

[0460] Thin-film transistors using highly purified oxide semiconductors exhibit a significant temperature dependence of the off-current. It hardly ever appears. This is because the energy gap of the oxide semiconductor is 3 eV or more, and intrinsic This is due to the extremely low number of carriers. Furthermore, the source and drain regions are degenerate. This state is indeed a factor in the lack of temperature dependence. (Operation of thin-film transistors) This is mostly due to carriers injected into the oxide semiconductor from a degenerate source region. Yes, and the above characteristics (no temperature dependence of off-current) are due to the lack of temperature dependence of the carrier density. It can explain this.

[0461] A logic circuit was constructed using thin-film transistors with extremely low off-current values. In such cases, the standby power consumption of the logic circuit is reduced or malfunctions of the logic circuit are suppressed. It is possible. [Explanation of Symbols]

[0462] 10 Logic Circuits 11 input terminals 12 Input terminals 13 Output terminals 14 Main logic circuit section 15 transistors 100 circuit boards 102 Protective layer 104 Semiconductor field 106 element isolation insulating layer 108a Gate Insulation Layer 108b Insulating layer 110a Grid cell layer 110b Electrode layer 112 Insulating layer 114a Impurity region 114b Impurity region 116 Channel formation region 118 Sidewall insulation layer 120a High concentration impurity region 120b High concentration impurity region 122 Metal layer 124a Metal compound area 124b Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode layer 130b Drain electrode layer 130c electrode layer 132 Insulating layer 134 Conductive layer 136a Electrode layer 136b Electrode layer 136c electrode layer 136d Gate layer 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode layer 142b Drain electrode layer 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a electrode layer 150b electrode layer 150c electrode layer 150d electrode layer 150e electrode layer 152 Insulating layer 154a Electrode layer 154b Electrode layer 154c electrode layer 154d electrode layer 160 transistors 164 transistors 200 Logic Circuits 201 AND Gate 202 Flip-flops 211 transistors 212 transistors 213 transistors 214 transistors 215 transistors 216 transistors 221 transistors 222 transistors 223 Transistors 224 transistors 225 transistors 231 NAND gate 232 NAND gates 233 NAND gates 234 NAND gates 241 transistors 242 transistors 243 transistors 244 transistors 251 transistors 252 transistors 253 transistors 320 circuit boards 322 Gate Insulation Layer 323 Protective insulating layer 332 Oxide semiconductor layer 360 Thin-Film Transistors 361 Grid control layer 362 Oxide semiconductor layer 363 Channel formation region 364a Source area 364b Drain area 365a Source electrode layer 365b Drain electrode layer 366 Oxide insulating layer 390 Thin-Film Transistors 391 Grid gate layer 392 Oxide semiconductor layer 393 Oxide semiconductor layer 394 circuit boards 395a Source electrode layer 395b Drain electrode layer 396 Oxide insulating layer 397 Gate Insulation Layer 398 Protective insulating layer 399 Oxide semiconductor layer 423 Aperture 450 circuit boards 452 Gate Insulation Layer 457 Insulating layer 460 Thin-Film Transistors 461 Guard Layer 461a Guardgate layer 461b Guard gate layer 462 Oxide semiconductor layer 464 Wiring layer 465a Source electrode layer or drain electrode layer 465a1 Source electrode layer or drain electrode layer 465a2 Source electrode layer or drain electrode layer 465b Source electrode layer or drain electrode layer 468 Wiring layer 500 Logic Circuits 501 NOR Gate 502 Flip-flops 511 transistors 512 transistors 513 Transistors 514 transistors 521 Transistors 522 transistors 523 Transistors 600 Logic Circuits 601 Latch 602 Flip-flops 611 transistors 612 Inverter 613 Inverter 621 Transistors 622 transistors 631 transistors 632 transistors 800 Logic Circuits 801 AND Gate 802 Flip-flops 803 Flip-flop 804 Flip-flops 805 Flip-Flop Group 900 Logic Circuits 901 Flip-Flop 902 AND gate 903 Control Unit 904 Flip-flops 905 Flip-flops 906 Flip-flops 907 Flip-Flop Group 2201 Main Unit 2202 enclosure 2203 Display section 2204 Keyboard 2211 Main Unit 2212 Stylus 2213 Display section 2214 Operation Buttons 2215 External Interface 2220 eBooks 2221 enclosure 2223 Casing 2225 Display section 2227 Display section 2231 Power supply 2233 Operation Keys 2235 Speaker 2237 Shaft 2240 enclosure 2241 enclosure 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Keys 2246 Pointing device 2247 Camera Lens 2248 External connection terminal 2249 solar cells 2250 External Memory Slots 2261 Main Unit 2263 Eyepiece 2264 Operation switch 2265 Display section (B) 2266 Battery 2267 Display section (A) 2270 Television equipment 2271 enclosure 2273 Display section 2275 Stand 2277 Display section 2279 Operation Keys 2280 Remote Control Unit

Claims

1. A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, A semiconductor device in which one of the source and drain of the first transistor and the other of the source and drain of the second transistor are electrically connected, A first conductive layer having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A second conductive layer having the same material as the first conductive layer, A first insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the second conductive layer, A third conductive layer having a region located above the first insulating layer and functioning as the gate electrode of the second transistor, A fourth conductive layer having a region located above the first insulating layer and made of the same material as the third conductive layer, An oxide semiconductor layer having a region that overlaps with the third conductive layer and having a channel formation region for the second transistor, A second insulating layer having a region located between the oxide semiconductor layer and the third conductive layer, and a region in contact with the fourth conductive layer, A third insulating layer having a region located above the oxide semiconductor layer, A fifth conductive layer having a region in contact with the upper surface of the third insulating layer and electrically connected to one of the source and drain of the second transistor, A sixth conductive layer having a region in contact with the upper surface of the third insulating layer and electrically connected to one of the source and drain of the first transistor, A seventh conductive layer having a region in contact with the upper surface of the third insulating layer and electrically connected to the other of the source and drain of the first transistor, A semiconductor device wherein the fifth conductive layer is electrically connected to the second conductive layer via the fourth conductive layer.

2. A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, A semiconductor device in which one of the source and drain of the first transistor and the other of the source and drain of the second transistor are electrically connected, A first conductive layer having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor, A second conductive layer having the same material as the first conductive layer, A first insulating layer having a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the second conductive layer, A third conductive layer having a region located above the first insulating layer and functioning as the gate electrode of the second transistor, A fourth conductive layer having a region located above the first insulating layer and made of the same material as the third conductive layer, An oxide semiconductor layer having a region that overlaps with the third conductive layer and having a channel formation region for the second transistor, A second insulating layer having a region located between the oxide semiconductor layer and the third conductive layer, and a region in contact with the fourth conductive layer, A third insulating layer having a region located above the oxide semiconductor layer, A fifth conductive layer having a region in contact with the upper surface of the third insulating layer and electrically connected to one of the source and drain of the second transistor, A sixth conductive layer having a region in contact with the upper surface of the third insulating layer and electrically connected to one of the source and drain of the first transistor, A seventh conductive layer having a region in contact with the upper surface of the third insulating layer and electrically connected to the other of the source and drain of the first transistor, The fifth conductive layer is electrically connected to the second conductive layer via the fourth conductive layer. A semiconductor device wherein the fifth conductive layer, the sixth conductive layer, and the seventh conductive layer are made of the same material.

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