Multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor (100) comprises: a capacitor body (1) in which a plurality of dielectric layers (2), a plurality of first internal electrodes (3), and a plurality of second internal electrodes (4) are stacked; a first via conductor (5) provided in the capacitor body (1) and electrically connected to the plurality of first internal electrodes (3); a second via conductor (6) provided in the capacitor body (1) and electrically connected to the plurality of second internal electrodes (4); a first external electrode (11) provided on at least one of a first main surface (1a) and a second main surface (1b) opposing each other in a stacking direction among the surfaces of the capacitor body (1), the first external electrode (11) being connected to the first via conductor (5); a second external electrode (12) provided on at least one main surface of the capacitor body (1) and connected to the second via conductor (6); and a first metal layer (21) provided on a side surface of the capacitor body (1) and electrically connected to the first via conductor (5).

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] There are known multilayer capacitors with reduced ESL (equivalent series inductance) by thickening the current flow path, shortening the current flow path, canceling out the magnetic fields generated by currents with different polarities, etc. Patent Document 1 discloses an example of a multilayer capacitor with reduced ESL. [[ID=D13]]

[0003] The multilayer capacitor disclosed in Patent Document 1 includes a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated. The capacitor body is provided with a plurality of first via conductors electrically connected to the plurality of first internal electrodes and extending to one main surface of the capacitor body, and a plurality of second via conductors electrically connected to the plurality of second internal electrodes and extending to one main surface of the capacitor body. On one main surface of the capacitor body, a plurality of first external electrodes electrically connected to the plurality of first via conductors respectively, and a plurality of second external electrodes electrically connected to the plurality of second via conductors respectively are provided.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Here, when manufacturing the multilayer capacitor described in Patent Document 1 mentioned above, a method can be considered in which the first external electrode and the second external electrode are formed by a rotary plating process. In the barrel plating method, which is an example of a rotary plating method, for example, a large number of capacitor bodies and a large number of conductive media are placed in a rotatable barrel, and the barrel is rotated in a plating solution and current is applied, thereby forming plating on the plating formation region of the surface of the capacitor body in which the first via conductor and the second via conductor are exposed. The conductive media is, for example, a metal sphere. According to the rotary plating method, it is possible to form the first external electrode and the second external electrode on the surface of a large number of capacitor bodies in a single plating process, and to form a large number of multilayer capacitors at once.

[0006] However, because the area on the surface of the capacitor body where the first via conductor and the second via conductor are exposed is small, there is a possibility that during the plating process, the conductive media may not come into contact with the plating formation area, resulting in no plating film being formed, or that a multilayer capacitor may be manufactured in which the plating film is not sufficiently formed.

[0007] The present invention aims to solve the above problems and to provide a multilayer ceramic capacitor that can more reliably form external electrodes by rotary plating. [Means for solving the problem]

[0008] The multilayer ceramic capacitor of the present invention is A capacitor body comprising multiple dielectric layers, multiple first internal electrodes, and multiple second internal electrodes stacked together, A first via conductor is provided inside the capacitor body and is electrically connected to the plurality of first internal electrodes, A second via conductor is provided inside the capacitor body and is electrically connected to the plurality of second internal electrodes, A first external electrode is provided on at least one of the first and second main surfaces of the capacitor body, which are opposite to the stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode, and is connected to the first via conductor. A second external electrode is provided on at least one main surface of the capacitor body and is connected to the second via conductor, A first metal layer is provided on the side surface of the capacitor body, which is a surface other than the first main surface and the second main surface, and is electrically connected to the first via conductor. It is characterized by being equipped with [the following features].

[0009] A multilayer ceramic capacitor in another aspect of the present invention is A capacitor body comprising multiple dielectric layers, multiple first internal electrodes, and multiple second internal electrodes stacked together, A first via conductor is provided inside the capacitor body and is electrically connected to the plurality of first internal electrodes, A second via conductor is provided inside the capacitor body and is electrically connected to the plurality of second internal electrodes, A first external electrode is provided on at least one of the first and second main surfaces of the capacitor body, which are opposite to the stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode, and is connected to the first via conductor. A second external electrode is provided on at least one main surface of the capacitor body and is connected to the second via conductor, A first metal layer is provided on the side surface of the capacitor body, which is a surface other than the first main surface and the second main surface, and is electrically connected to the first via conductor. A second metal layer is provided on the side surface of the capacitor body and is electrically connected to the second via conductor, It is characterized by being equipped with [the following features]. [Effects of the Invention]

[0010] According to the multilayer ceramic capacitor of the present invention, a first metal layer electrically connected to a first via conductor is provided on the side surface of the capacitor body, which allows for more reliable formation of external electrodes by rotary plating. That is, during rotary plating, plating can be applied to the plating region not only when the conductive medium comes into contact with the plating region where the first via conductor is exposed, but also when the conductive medium comes into contact with the first metal layer, thus enabling more reliable formation of the first external electrodes.

[0011] Furthermore, according to another aspect of the present invention, a multilayer ceramic capacitor is provided on the side surface of the capacitor body, with a first metal layer electrically connected to a first via conductor and a second metal layer electrically connected to a second via conductor. This allows for more reliable formation of external electrodes by rotary plating. Specifically, during rotary plating, plating can be applied to the plating region not only when the conductive media contacts the plating region where the first and second via conductors are exposed, but also when the conductive media contacts the first and second metal layers. This ensures more reliable formation of the first and second external electrodes. [Brief explanation of the drawing]

[0012] [Figure 1] (a) is a schematic top view showing a multilayer ceramic capacitor in the first embodiment of the present invention, and (b) is a schematic bottom view showing a multilayer ceramic capacitor in the first embodiment. [Figure 2] Figure 1 is a side view of the multilayer ceramic capacitor as seen in the direction of arrow Y1. [Figure 3] Figure 1 is a schematic cross-sectional view showing the structure of a multilayer ceramic capacitor when cut along the line III-III. [Figure 4] (a) is a schematic plan view showing the first internal electrode, and (b) is a schematic plan view showing the second internal electrode. [Figure 5](a) to (d) are partial enlarged views schematically showing various examples of the positional relationship between the second metal layer and the second connection layer, and (e) to (h) are partial enlarged views schematically showing examples of the shape of the second connection layer corresponding to (a) to (d) respectively. [Figure 6] It is a side view schematically showing a state where the multilayer ceramic capacitor in the first embodiment is mounted on a mounting substrate. [Figure 7] (a) is a plan view schematically showing a first internal electrode when the first connection layer and the second connection layer are provided in one layer respectively, and (b) is a plan view schematically showing a second internal electrode when the first connection layer and the second connection layer are provided in one layer respectively. [Figure 8] (a) is a plan view schematically showing the first internal electrode and the first connection layer when the first connection layer is provided in the layer where the first internal electrode is provided but the second connection layer is not provided, and (b) is a plan view schematically showing the second internal electrode and the second connection layer when the second connection layer is provided in the layer where the second internal electrode is provided but the first connection layer is not provided. [Figure 9] It is a flowchart for explaining an example of a method for manufacturing a multilayer ceramic capacitor. [Figure 10] (a) is a top view schematically showing the multilayer ceramic capacitor in the second embodiment, and (b) is a bottom view schematically showing the multilayer ceramic capacitor in the second embodiment. [Figure 11] It is a side view when the multilayer ceramic capacitor shown in FIG. 10 is viewed in the direction of arrow Y2. [Figure 12] (a) is a plan view schematically showing the first internal electrode of the multilayer ceramic capacitor in the second embodiment, and (b) is a plan view schematically showing the second internal electrode. [Figure 13] (a) is a top view schematically showing the multilayer ceramic capacitor in the third embodiment, and (b) is a bottom view schematically showing the multilayer ceramic capacitor. [Figure 14](a) is a schematic plan view showing the first internal electrode of the multilayer ceramic capacitor in the third embodiment, and (b) is a schematic plan view showing the second internal electrode. [Figure 15] (a) is a schematic top view showing a multilayer ceramic capacitor in the fourth embodiment, and (b) is a schematic bottom view showing a multilayer ceramic capacitor. [Figure 16] Figure 15 is a side view of the multilayer ceramic capacitor as seen in the direction of arrow Y3. [Figure 17] (a) is a schematic plan view showing the first internal electrode of the multilayer ceramic capacitor in the fourth embodiment, and (b) is a schematic plan view showing the second internal electrode. [Figure 18] A modified example of the multilayer ceramic capacitor in the fourth embodiment is shown below: (a) is a schematic plan view showing the first internal electrode and the first connecting layer in a case where the first connecting layer is provided in the layer where the first internal electrode is provided, but the second connecting layer is not provided; and (b) is a schematic plan view showing the second internal electrode and the second connecting layer in a case where the second connecting layer is provided in the layer where the second internal electrode is provided, but the first connecting layer is not provided. [Figure 19] This is a schematic top view of a multilayer ceramic capacitor showing another arrangement pattern of external electrodes when the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is odd. [Figure 20] (a) and (b) are schematic top views of multilayer ceramic capacitors, respectively, showing alternative arrangement patterns of external electrodes when the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd. [Figure 21] (a) and (b) are schematic top views of a multilayer ceramic capacitor showing alternative arrangement patterns of external electrodes when the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is even. [Modes for carrying out the invention]

[0013] The features of the present invention will be specifically described below with reference to embodiments of the present invention. <First Embodiment> Figure 1(a) is a schematic top view of the multilayer ceramic capacitor 100 in the first embodiment of the present invention, and Figure 1(b) is a schematic bottom view of the multilayer ceramic capacitor 100 in the first embodiment. Here, the first main surface 1a of the capacitor body 1, which will be described later, is called the top surface, and the second main surface 1b is called the bottom surface. Figure 2 is a side view of the multilayer ceramic capacitor 100 shown in Figure 1 when viewed in the direction of arrow Y1. Figure 3 is a schematic cross-sectional view showing the structure when the multilayer ceramic capacitor 100 shown in Figure 1 is cut along the line III-III.

[0014] The multilayer ceramic capacitor 100 comprises a capacitor body 1, a first via conductor 5, a second via conductor 6, a first external electrode 11, a second external electrode 12, and a first metal layer 21. The multilayer ceramic capacitor 100 in this embodiment further comprises a second metal layer 22. Furthermore, the multilayer ceramic capacitor 100 in this embodiment further comprises a first connecting layer 31 and a second connecting layer 32.

[0015] As shown in Figure 3, the capacitor body 1 has a structure in which multiple dielectric layers 2, multiple first internal electrodes 3, and multiple second internal electrodes 4 are stacked. More specifically, the capacitor body 1 has a structure in which multiple first internal electrodes 3 and second internal electrodes 4 are alternately stacked via the dielectric layers 2.

[0016] The material of the dielectric layer 2 is arbitrary and can consist of, for example, a ceramic material mainly composed of BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3. These main components may also contain minor components in smaller amounts than the main components, such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds.

[0017] The shape of the capacitor body 1 is arbitrary. In this embodiment, the capacitor body 1 has a rectangular parallelepiped shape as a whole. A rectangular parallelepiped shape as a whole means a shape that is not a perfect rectangular parallelepiped, for example, a shape in which the corners or edges of the rectangular parallelepiped are rounded, or a shape in which there are irregularities on the surface of the rectangular parallelepiped, but which has six surfaces and can be considered as a rectangular parallelepiped as a whole. Therefore, the capacitor body 1 comprises a first main surface 1a, a second main surface 1b, a first side surface 1c, a second side surface 1d, a third side surface 1e, and a fourth side surface 1f.

[0018] The first main surface 1a and the second main surface 1b of the capacitor body 1 are surfaces that are opposite to the stacking direction T of the dielectric layer 2, the first internal electrode 3, and the second internal electrode 4. The first side surface 1c to the fourth side surface 1f of the capacitor body 1 constitute four side surfaces of the capacitor body 1 other than the first main surface 1a and the second main surface 1b. The first side surface 1c is opposite to the third side surface 1e, and the second side surface 1d is opposite to the fourth side surface 1f. In this embodiment, the first side surface 1c to the fourth side surface 1f of the capacitor body 1 are perpendicular to the first main surface 1a and the second main surface 1b, respectively, but they do not have to be perpendicular.

[0019] The dimensions of the capacitor body 1 are arbitrary. For example, a rectangular capacitor body 1 viewed from above in the stacking direction T can have a vertical dimension of 0.3 mm to 3.0 mm, a horizontal dimension of 0.3 mm to 3.0 mm, and a dimension in the stacking direction T of 50 μm to 200 μm. The dimension of the capacitor body 1 in the stacking direction T refers to the thickness of the capacitor body 1.

[0020] Figure 4(a) is a schematic plan view showing the first internal electrode 3, and Figure 4(b) is a schematic plan view showing the second internal electrode 4. Figures 4(a) and (b) also show the dielectric layer 2, the first via conductor 5, and the second via conductor 6. In addition, Figure 4(a) also shows the second connecting layer 32, which will be described later, and Figure 4(b) also shows the first connecting layer 31, which will be described later.

[0021] As shown in Figures 4(a) and (b), in this embodiment, the shape of the dielectric layer 2 when viewed in the stacking direction T is rectangular. The shape of the first internal electrode 3 when viewed in the stacking direction T is not rectangular. Specifically, as shown in Figure 4(a), the first internal electrode 3 has a shape like a rectangle with a pair of corners removed. The shape of the removed corners is, for example, rectangular. Also, the shape of the second internal electrode 4 when viewed in the stacking direction T is not rectangular. Specifically, as shown in Figure 4(b), the second internal electrode 4 has a shape like a rectangle with a pair of corners removed. The shape of the removed corners is, for example, rectangular. However, the shape of the first internal electrode 3 is not limited to the shape shown in Figure 4(a), nor is the shape of the second internal electrode 4 limited to the shape shown in Figure 4(b).

[0022] The material of the first internal electrode 3 and the second internal electrode 4 is arbitrary; for example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals, can be used. The first internal electrode 3 and the second internal electrode 4 may also contain the same ceramic material as the dielectric ceramic contained in the dielectric layer 2 as a co-material. In that case, the proportion of the co-material contained in the first internal electrode 3 and the second internal electrode 4 is, for example, 20 vol% or less.

[0023] The thickness of the first internal electrode 3 and the second internal electrode 4 is arbitrary and can be, for example, between 0.3 μm and 1.0 μm. The number of layers of the first internal electrode 3 and the second internal electrode 4 is arbitrary. For example, the total number of layers of the first internal electrode 3 and the second internal electrode 4 can be between 10 and 150 layers.

[0024] In the multilayer ceramic capacitor 100, capacitance is formed when the first internal electrode 3 and the second internal electrode 4 face each other via the dielectric layer 2.

[0025] The first via conductor 5 and the second via conductor 6 are provided inside the capacitor body 1. In this embodiment, as shown in Figure 1, a plurality of first via conductors 5 and a plurality of second via conductors 6 are provided in a matrix arrangement. More specifically, four via conductors, including two first via conductors 5 and two second via conductors 6, are provided at positions corresponding to the four corners of the rectangular capacitor body 1 in a plan view in the stacking direction T. However, the arrangement of the first via conductors 5 and the second via conductors 6 is not limited to a matrix arrangement. Also, the number of first via conductors 5 and the number of second via conductors 6 are not limited to two, but can be any number.

[0026] As shown in Figure 3, the first via conductor 5 is provided inside the capacitor body 1 in such a manner that it extends in the stacking direction T from the first main surface 1a toward the second main surface 1b of the capacitor body 1, and is electrically connected to a plurality of first internal electrodes 3. The first via conductor 5 is spaced apart from the second internal electrodes 4 and is insulated from the second internal electrodes 4.

[0027] As shown in Figure 3, the second via conductor 6 is provided inside the capacitor body 1 in such a manner that it extends in the stacking direction T from the first main surface 1a toward the second main surface 1b of the capacitor body 1, and is electrically connected to a plurality of second internal electrodes 4. The second via conductor 6 is spaced apart from the first internal electrodes 3 and is insulated from the first internal electrodes 3.

[0028] As shown in Figure 3, the first via conductor 5 and the second via conductor 6 are not exposed on the second main surface 1b of the capacitor body 1, but they may be exposed.

[0029] The material of the first via conductor 5 and the second via conductor 6 is arbitrary; for example, metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals, can be used.

[0030] The shapes of the first via conductor 5 and the second via conductor 6 are arbitrary, for example, cylindrical. In that case, the diameters of the first via conductor 5 and the second via conductor 6 are, for example, approximately 30 μm to 150 μm.

[0031] The first external electrode 11 is provided on at least one of the main surfaces of the capacitor body 1, namely the first main surface 1a and the second main surface 1b, and is connected to the first via conductor 5. In this embodiment, the first via conductor 5 is exposed on the first main surface 1a of the capacitor body 1, and the first external electrode 11 is provided on the first main surface 1a of the capacitor body 1. More specifically, the first external electrode 11 is provided at a position that overlaps with the first via conductor 5 in the stacking direction T. The number of first external electrodes 11 is the same as the number of first via conductors 5, which is two in the example shown in Figure 1. However, the number of first external electrodes 11 is not limited to two. As described above, since the first via conductor 5 is electrically connected to a plurality of first internal electrodes 3, the first external electrode 11 is electrically connected to a plurality of first internal electrodes 3.

[0032] The second external electrode 12 is provided on at least one main surface of the capacitor body 1 and is connected to the second via conductor 6. In this embodiment, the second via conductor 6 is exposed on the first main surface 1a of the capacitor body 1, and like the first external electrode 11, the second external electrode 12 is provided on the first main surface 1a of the capacitor body 1. More specifically, the second external electrode 12 is provided at a position that overlaps with the second via conductor 6 in the stacking direction T. The number of second external electrodes 12 is the same as the number of second via conductors 6, which is two in the example shown in Figure 1. However, the number of second external electrodes 12 is not limited to two. As described above, since the second via conductor 6 is electrically connected to a plurality of second internal electrodes 4, the second external electrode 12 is electrically connected to a plurality of second internal electrodes 4.

[0033] Furthermore, the first via conductor 5 and the second via conductor 6 may also be exposed on the second main surface 1b of the capacitor body 1, and the first external electrode 11 and the second external electrode 12 may also be provided on the second main surface 1b.

[0034] The materials of the first external electrode 11 and the second external electrode 12 are arbitrary. In this embodiment, the first external electrode 11 and the second external electrode 12 are plated electrodes formed by a rotary plating process. Examples of materials that make up the plated electrodes include Cu, Ni, Sn, etc. The plated electrodes may consist of a single layer or multiple layers.

[0035] The first metal layer 21 is provided on one of the sides of the surface of the capacitor body 1 and is electrically connected to the first via conductor 5. In this embodiment, as shown in Figure 1, the first metal layer 21 is provided at the corners spanning from the first side surface 1c to the second side surface 1d, and at the corners spanning from the third side surface 1e to the fourth side surface 1f of the capacitor body 1. However, the position where the first metal layer 21 is provided is not limited to the position shown in Figure 1.

[0036] The second metal layer 22 is provided on one of the sides of the surface of the capacitor body 1 and is electrically connected to the second via conductor 6. In this embodiment, as shown in Figure 1, the second metal layer 22 is provided at the corners spanning from the second side surface 1d to the third side surface 1e of the capacitor body 1, and at the corners spanning from the fourth side surface 1f to the first side surface 1c. However, the position where the second metal layer 22 is provided is not limited to the position shown in Figure 1.

[0037] The materials of the first metal layer 21 and the second metal layer 22 are arbitrary. In this embodiment, the first metal layer 21 and the second metal layer 22 are plated layers formed by a rotary plating process. Examples of materials constituting the plated layers include Cu, Ni, Sn, etc. The plated layers may consist of a single layer or multiple layers.

[0038] In the multilayer ceramic capacitor 100 of this embodiment, a first connecting layer 31 for electrically connecting the first via conductor 5 and the first metal layer 21, and a second connecting layer 32 for electrically connecting the second via conductor 6 and the second metal layer 22 are provided inside the capacitor body 1. The first connecting layer 31 and the second connecting layer 32 have a planar shape that extends in a direction perpendicular to the stacking direction T.

[0039] In this embodiment, the first connecting layer 31 is provided in the same layer as the second internal electrode 4, as shown in Figure 4(b). The first connecting layer 31 may be provided in all of the layers on which the second internal electrode 4 is provided, or it may be provided in only some of the layers. The second connecting layer 32 is provided in the same layer as the first internal electrode 3, as shown in Figure 4(a). The second connecting layer 32 may be provided in all of the layers on which the first internal electrode 3 is provided, or it may be provided in only some of the layers.

[0040] As shown in Figure 4(b), the first connecting layer 31 is in contact with the first via conductor 5 but is spaced apart from the second internal electrode 4. As shown in Figure 4(a), the second connecting layer 32 is in contact with the second via conductor 6 but is spaced apart from the first internal electrode 3.

[0041] The shapes of the first connecting layer 31 and the second connecting layer 32 are arbitrary. In this embodiment, as shown in Figure 4(b), the first connecting layer 31 has a quarter-circular shape. Also, as shown in Figure 4(a), the second connecting layer 32 has a quarter-circular shape.

[0042] The materials of the conductive first connecting layer 31 and the second connecting layer 32 are arbitrary; for example, the same material as the first internal electrode 3 and the second internal electrode 4 can be used.

[0043] In the manufacturing process of the multilayer ceramic capacitor 100, the first connecting layer 31 and the second connecting layer 32 are exposed on the side surface of the capacitor body 1 before the first metal layer 21 and the second metal layer 22 are provided. The first metal layer 21 is provided in such a manner that it covers the first connecting layer 31 that is exposed on the side surface of the capacitor body 1. The second metal layer 22 is provided in such a manner that it covers the second connecting layer 32 that is exposed on the side surface of the capacitor body 1.

[0044] The shape of the first metal layer 21 can be changed by changing the shape of the portion of the first connecting layer 31 that is exposed on the side surface of the capacitor body 1. Similarly, the shape of the second metal layer 22 can be changed by changing the shape of the portion of the second connecting layer 32 that is exposed on the side surface of the capacitor body 1.

[0045] Figure 5(a) is a schematic enlarged section showing the positional relationship between the second metal layer 22 and the second connecting layer 32 of the multilayer ceramic capacitor 100 shown in Figures 1 to 3. Figures 5(b), (c), and (d) are schematic enlarged sections showing the positional relationship between the second metal layer 22 and the second connecting layer 32 with a different shape than that shown in Figure 5(a). Figures 5(e) to (h) are schematic enlarged sections showing examples of the shape of the second connecting layer 32 corresponding to Figures 5(a) to (d). Figures 5(e) to (h) also show parts of the dielectric layer 2, the first internal electrode 3, and the second via conductor 6.

[0046] The configuration shown in Figure 5(b) has a smaller area of ​​the second metal layer 22 compared to the configuration shown in Figure 5(a). As can be seen by comparing Figures 5(e) and 5(f), the area of ​​the second metal layer 22 can be reduced by reducing the area of ​​the portion of the second connecting layer 32 that is exposed on the side surface of the capacitor body 1. The same applies to the first metal layer 21 and the first connecting layer 31, although the figures are omitted.

[0047] In the configuration shown in Figure 5(c), two second metal layers 22 are provided on one side surface of the capacitor body 1. The two second metal layers 22 are provided at positions spaced apart from each other. Figure 5(c) shows a state where two second metal layers 22 are provided on the first side surface 1c of the capacitor body 1, but a similar configuration can be achieved by providing two second metal layers 22 on the second side surface 1d, the third side surface 1e, and the fourth side surface 1f. To realize such a configuration, the second connecting layer 32 has a shape that is exposed at two locations on one side surface of the capacitor body 1, as shown in Figure 5(g). The first metal layer 21 and the first connecting layer 31 are similar, although the figures are omitted. Note that the number of first metal layers 21 and second metal layers 22 provided on one side surface of the capacitor body 1 is not limited to two, and there may be three or more.

[0048] In the configuration shown in Figure 5(d), the second metal layer 22 is provided only in the region of the capacitor body 1's side surface that is on the first main surface 1a side, where the first external electrode 11 and the second external electrode 12 are provided. That is, when the side surface of the capacitor body 1 is divided into the region on the first main surface 1a side and the region on the second main surface 1b side, the second metal layer 22 is provided only in the region on the first main surface 1a side. In this case, the second connecting layer 32 only needs to be provided in the layer on the first main surface 1a side in the stacking direction T. Note that, as shown in Figure 5(h), the shape of the second connecting layer 32 can be the same as the shape of the second connecting layer 32 shown in Figure 5(b).

[0049] As will be described later, when mounting the multilayer ceramic capacitor 100 in this embodiment onto a mounting substrate, the first metal layer 21 and the second metal layer 22 can also be joined to the land electrodes of the mounting substrate via solder. According to the configuration shown in Figure 5(d), the first metal layer 21 and the second metal layer 22 are not provided in areas where soldering is not performed when mounting the multilayer ceramic capacitor 100, thus simplifying the configuration and reducing manufacturing costs.

[0050] In the multilayer ceramic capacitor 100 of this embodiment, a first metal layer 21 electrically connected to the first via conductor 5 and a second metal layer 22 electrically connected to the second via conductor 6 are provided on the side surface of the capacitor body 1, so that the formation of external electrodes by rotary plating can be performed more reliably. As will be described later, during rotary plating, plating can be applied to the plating formation region not only when the conductive medium comes into contact with the plating formation region on the surface of the capacitor body 1 where the first via conductor 5 and the second via conductor 6 are exposed, but also when the conductive medium comes into contact with the first metal layer 21 and the second metal layer 22, so that the first external electrode 11 and the second external electrode 12 can be formed more reliably.

[0051] Furthermore, with the multilayer ceramic capacitor 100 in this embodiment, stable mounting is possible when mounting to a mounting substrate by bonding not only the first external electrode 11 and the second external electrode 12, but also the first metal layer 21 and the second metal layer 22 to the land electrodes of the mounting substrate.

[0052] Figure 6 is a schematic side view showing the multilayer ceramic capacitor 100 in this embodiment mounted on a mounting substrate 200. The first external electrode 11 and the second external electrode 12 of the multilayer ceramic capacitor 100 are each joined to the land electrode 210 of the mounting substrate 200 via solder 220. In addition, the first metal layer 21 and the second metal layer 22 provided on the side surface of the capacitor body 1 are each joined to the land electrode 210 of the mounting substrate 200 via solder 220. Since the first metal layer 21 and the second metal layer 22 are also joined to the land electrode 210 of the mounting substrate 200 in addition to the first external electrode 11 and the second external electrode 12, more stable mounting is possible.

[0053] Furthermore, since the first metal layer 21 and the second metal layer 22 are joined to the land electrodes 210 of the mounting substrate 200 via solder 220, it becomes possible to visually confirm whether or not the multilayer ceramic capacitor 100 is mounted.

[0054] (Modification 1 of the first embodiment) As shown in Figures 4(a) and 4(b), the first connection layer 31 and the second connection layer 32 are alternately provided on different layers, but it is also possible to configure the system so that the first connection layer 31 and the second connection layer 32 are provided on the same layer.

[0055] Figure 7(a) shows a schematic plan view of the first internal electrode 3 when the first connecting layer 31 and the second connecting layer 32 are provided on the same layer, and Figure 7(b) shows a schematic plan view of the second internal electrode 4. In Figures 7(a) and (b), the dielectric layer 2, the first via conductor 5, the second via conductor 6, the first connecting layer 31, and the second connecting layer 32 are also shown.

[0056] As shown in Figure 7(a), the layer on which the first internal electrode 3 is provided also has a first connecting layer 31 along with a second connecting layer 32. The first connecting layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connecting layer 31 is not in direct contact with the first internal electrode 3.

[0057] As shown in Figure 7(b), the layer on which the second internal electrode 4 is provided also has a second connecting layer 32 along with the first connecting layer 31. The second connecting layer 32 is in contact with the second via conductor 6 and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connecting layer 32 is not in direct contact with the second internal electrode 4.

[0058] In this configuration example, compared to the configuration examples shown in Figures 4(a) and (b), the number of first connecting layers 31 connecting the first via conductor 5 and the first metal layer 21, and the number of second connecting layers 32 connecting the second via conductor 6 and the second metal layer 22 are increased. Therefore, the electrical connection between the first via conductor 5 and the first metal layer 21 via the first connecting layers 31, and the electrical connection between the second via conductor 6 and the second metal layer 22 via the second connecting layers 32 become more reliable, and the first external electrode 11 and the second external electrode 12 can be formed more reliably when formed by rotary plating.

[0059] Furthermore, because the first connecting layer 31 is not in direct contact with the first internal electrode 3, it is possible to suppress the intrusion of plating solution from the outside into the inside during manufacturing, and also to suppress the intrusion of moisture and other substances from the outside into the inside of the finished product. In other words, in a configuration where the first connecting layer 31 is in direct contact with the first internal electrode 3, plating solution and moisture and other substances can easily intrude into the inside from the outside of the capacitor body 1 via the first connecting layer 31 and the first internal electrode 3. However, because the first connecting layer 31 is separated from the first internal electrode 3, the intrusion of plating solution and moisture and other substances into the inside can be suppressed. Similarly, because the second connecting layer 32 is not in direct contact with the second internal electrode 4, it is possible to suppress the intrusion of plating solution and moisture and other substances from the outside into the inside of the capacitor body 1.

[0060] Furthermore, when comparing the configurations shown in Figures 4(a) and 4(b) with those shown in Figures 7(a) and 7(b), the internal electrodes and the connecting layer are completely separated within a single layer. Therefore, the configurations shown in Figures 4(a) and 4(b) can more effectively suppress the intrusion of plating solution, moisture, etc., from the outside to the inside of the capacitor body 1.

[0061] (Modification 2 of the first embodiment) In the configuration shown in Figures 4(a) and (b), the second connecting layer 32 is provided on the layer where the first internal electrode 3 is provided, and the first connecting layer 31 is provided on the layer where the second internal electrode 4 is provided. However, it is also possible to have a configuration where the first connecting layer 31 is provided on the layer where the first internal electrode 3 is provided, and the second connecting layer 32 is provided on the layer where the second internal electrode 4 is provided. In that case, a schematic plan view showing the first internal electrode 3 and the first connecting layer 31 is shown in Figure 8(a), and a schematic plan view showing the second internal electrode 4 and the second connecting layer 32 is shown in Figure 8(b). In Figures 8(a) and (b), the dielectric layer 2, the first via conductor 5, and the second via conductor 6 are also shown.

[0062] As shown in Figure 8(a), the first connecting layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connecting layer 31 is not in direct contact with the first internal electrode 3. As shown in Figure 8(a), the second connecting layer 32 is not provided in the layer on which the first internal electrode 3 is provided.

[0063] As shown in Figure 8(b), the second connecting layer 32 is in contact with the second via conductor 6 and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connecting layer 32 is not in direct contact with the second internal electrode 4. As shown in Figure 8(b), the first connecting layer 31 is not provided in the layer where the second internal electrode 4 is provided.

[0064] According to the configuration shown in Figures 8(a) and 8(b), the number of first connecting layers 31 and second connecting layers 32 can be reduced by approximately half compared to the configuration shown in Figures 7(a) and 7(b). This suppresses the intrusion of plating solution from the outside into the inside during manufacturing, and also suppresses the intrusion of moisture and other substances from the outside into the inside of the finished product. In other words, on the side surface of the capacitor body 1, the positions where the first connecting layers 31 and second connecting layers 32 are exposed are susceptible to the intrusion of plating solution and moisture into the inside. However, the reduced number of first connecting layers 31 and second connecting layers 32 suppresses the intrusion of plating solution and moisture into the inside. The same is true for the configuration shown in Figures 4(a) and 4(b).

[0065] (Manufacturing method for multilayer ceramic capacitors) An example of a manufacturing method for the multilayer ceramic capacitor 100 described above will be explained with reference to the flowchart shown in Figure 9.

[0066] In step S1 of Figure 9, a ceramic green sheet, a conductive paste for the internal electrodes, and a conductive paste for the connecting layer are prepared. A known ceramic green sheet can be used; for example, it can be obtained by coating a ceramic slurry containing ceramic powder, a resin component, and a solvent onto a substrate and drying it.

[0067] The conductive paste for the internal electrodes is a conductive paste for forming the first internal electrode 3 and the second internal electrode 4, and known conductive pastes can be used. The conductive paste for the internal electrodes comprises particles made of a metal or its precursor, such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, and a solvent. The conductive paste for the internal electrodes may further contain a resin component that acts as a dispersant or binder.

[0068] The conductive paste for the connecting layer is a conductive paste for forming the first connecting layer 31 and the second connecting layer 32, and for example, the same conductive paste as the conductive paste for the internal electrodes can be used. However, a different conductive paste from the conductive paste for the internal electrodes may be used as the conductive paste for the connecting layer.

[0069] In step S2, following step S1, conductive paste for internal electrodes and conductive paste for connecting layers are applied to the prepared ceramic green sheet by printing or other methods. The conductive paste for internal electrodes is applied to the positions where the first internal electrode 3 and the second internal electrode 4 will be formed. The conductive paste for connecting layers is applied to the positions where the first connecting layer 31 and the second connecting layer 32 will be formed. Here, electrode patterns and connecting layer patterns are formed that enable the simultaneous manufacture of multiple multilayer ceramic capacitors 100.

[0070] In step S3, following step S2, a mother laminate is fabricated by stacking multiple ceramic green sheets coated with conductive paste for internal electrodes and conductive paste for the connecting layer. When fabricating the mother laminate, ceramic green sheets without electrode patterns and connecting layer patterns may be placed on the outside in the stacking direction. Here, the mother laminate is fabricated by stacking multiple ceramic green sheets and then pressing them in the stacking direction. The pressing method is arbitrary; for example, a rigid press or a hydrostatic press can be used.

[0071] In step S4, following step S3, a plurality of through-holes extending in the stacking direction are formed in the mother laminate, and the formed plurality of through-holes are filled with conductive paste for via conductors. The through-holes can be formed by any method, for example, by a laser. The conductive paste for via conductors is a conductive paste for forming the first via conductor 5 and the second via conductor 6, and comprises particles made of a metal or its precursor, such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, and a solvent. The conductive paste for via conductors may further contain a resin component that acts as a dispersant or binder.

[0072] In step S5, following step S4, the mother stack is cut to separate it into multiple unfired chips. The mother stack can be cut by methods such as press cutting, dicing, or laser cutting.

[0073] In step S6, following step S5, the capacitor body 1 is manufactured by firing the unfired chip. The first main surface 1a of the manufactured capacitor body 1 has the first via conductor 5 and the second via conductor 6 exposed, and the first connecting layer 31 and the second connecting layer 32 exposed on the side surface.

[0074] In step S7, following step S6, a first external electrode 11 and a second external electrode 12 are formed on the surface of the capacitor body 1. Here, the first external electrode 11 and the second external electrode 12 are formed by a plating process using barrel plating, which is an example of a rotary plating method. Specifically, a number of capacitor bodies 1 and a number of conductive media are placed in a rotatable barrel, and the barrel is rotated in a plating solution while current is applied, thereby plating is applied to the plating formation region of the first main surface 1a of the capacitor body 1 where the first via conductor 5 and the second via conductor 6 are exposed. The conductive media are, for example, metal spheres. The first external electrode 11 and the second external electrode 12, which are plated electrodes, are formed by the formation of a plating film in the plating formation region.

[0075] Furthermore, by the rotary plating method, a plating film is formed on the side surface of the capacitor body 1 where the first connecting layer 31 and the second connecting layer 32 are exposed, thereby forming the first metal layer 21 and the second metal layer 22, which are the plating layers.

[0076] The plating film in the plating formation region is formed not only when the conductive media comes into contact with the first via conductor 5 and the second via conductor 6 exposed on the first main surface 1a of the capacitor body 1 and current is passed through, but also when the conductive media comes into contact with the first connecting layer 31 and the second connecting layer 32 exposed on the side surface of the capacitor body 1 and current is passed through, and when the conductive media comes into contact with the first metal layer 21 and the second metal layer 22 formed on the side surface of the capacitor body 1 by the plating process and current is passed through. Therefore, the first external electrode 11 and the second external electrode 12 can be formed more reliably by the rotary plating method.

[0077] As described above, in the multilayer ceramic capacitor 100 of this embodiment, the first metal layer 21 and the second metal layer 22 are provided in positions that span two sides of the capacitor body 1. Therefore, compared to a configuration in which the first metal layer 21 and the second metal layer 22 are provided on only one side of the capacitor body 1, the conductive media has more opportunities to come into contact with the first metal layer 21 and the second metal layer 22 during rotary plating, thus enabling more reliable formation of the first external electrode 11 and the second external electrode 12.

[0078] A multilayer ceramic capacitor 100 can be obtained by the manufacturing method described above. <Second Embodiment> In the multilayer ceramic capacitor 100 of the first embodiment, the number of first external electrodes 11 and second external electrodes 12 are each two, but as described above, the number is not limited to two.

[0079] Figure 10(a) is a schematic top view of the multilayer ceramic capacitor 100A in the second embodiment, and Figure 10(b) is a schematic bottom view of the multilayer ceramic capacitor 100A. Figure 11 is a side view of the multilayer ceramic capacitor 100A shown in Figure 10, viewed in the direction of arrow Y2.

[0080] In the multilayer ceramic capacitor 100A of the second embodiment, six first external electrodes 11 and six second external electrodes 12 are provided. The total of 12 external electrodes, including the first external electrodes 11 and the second external electrodes 12, are arranged in a matrix. Here, four external electrodes are arranged in the row direction (horizontal direction in the figure) and three in the column direction (vertical direction in the figure), but the number of external electrodes in the row direction is not limited to four, nor is the number of external electrodes in the column direction limited to three.

[0081] As shown in Figure 10(a), the first external electrode 11 and the second external electrode 12 are arranged alternately in the row direction, and either only the first external electrode 11 or only the second external electrode 12 are arranged in the column direction. However, the arrangement pattern of the first external electrode 11 and the second external electrode 12 is not limited to the arrangement pattern shown in Figure 10(a).

[0082] Figure 12(a) is a schematic plan view showing the first internal electrode 3, and Figure 12(b) is a schematic plan view showing the second internal electrode 4. Figures 12(a) and (b) also show the dielectric layer 2, the first via conductor 5, and the second via conductor 6. In addition, Figure 12(a) also shows the first connecting layer 31, and Figure 12(b) also shows the second connecting layer 32.

[0083] The first internal electrode 3 has multiple first through holes 3a formed therein for inserting the second via conductor 6. The second internal electrode 4 has multiple second through holes 4a formed therein for inserting the first via conductor 5.

[0084] As shown in Figure 12(b), the first via conductor 5, which is positioned to overlap with the second internal electrode 4 in the stacking direction T, passes through the second through hole 4a formed in the second internal electrode 4 and is insulated from the second internal electrode 4. Also, as shown in Figure 12(a), the second via conductor 6, which is positioned to overlap with the first internal electrode 3 in the stacking direction T, passes through the first through hole 3a formed in the first internal electrode 3 and is insulated from the first internal electrode 3.

[0085] As shown in Figure 12(a), the first connecting layer 31 is provided in the layer on which the first internal electrode 3 is provided. The first connecting layer 31 is in contact with the first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connecting layer 31 is not in direct contact with the first internal electrode 3. As shown in Figure 12(a), the second connecting layer 32 is not provided in the layer on which the first internal electrode 3 is provided.

[0086] As shown in Figure 12(b), the second connecting layer 32 is provided in the layer where the second internal electrode 4 is provided. The second connecting layer 32 is in contact with the second via conductor 6 and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connecting layer 32 is not in direct contact with the second internal electrode 4. As shown in Figure 12(b), the first connecting layer 31 is not provided in the layer where the second internal electrode 4 is provided.

[0087] In this embodiment, the multilayer ceramic capacitor 100A, like the multilayer ceramic capacitor 100 in the first embodiment, is provided with a first metal layer 21 electrically connected to the first via conductor 5 and a second metal layer 22 electrically connected to the second via conductor 6 on the side surface of the capacitor body 1. This allows for more reliable formation of the first external electrode 11 and the second external electrode 12 by rotary plating.

[0088] <Third Embodiment> In the multilayer ceramic capacitor 100 in the first embodiment and the multilayer ceramic capacitor 100A in the second embodiment described above, a first metal layer 21 and a second metal layer 22 are provided on the side surface of the capacitor body 1, but it is also possible to have a configuration in which only the first metal layer 21 is provided.

[0089] Figure 13(a) is a schematic top view showing the multilayer ceramic capacitor 100B in the third embodiment, and Figure 13(b) is a schematic bottom view showing the multilayer ceramic capacitor 100B in the third embodiment.

[0090] In the third embodiment, the multilayer ceramic capacitor 100B is provided with five first external electrodes 11 and four second external electrodes 12. The total of nine external electrodes, including the first external electrodes 11 and the second external electrodes 12, are arranged in a matrix. Here, three external electrodes are arranged in the row direction and three in the column direction, but the number of external electrodes in the row direction is not limited to three, nor is the number of external electrodes in the column direction limited to three.

[0091] In this embodiment, the first external electrode 11 is provided at the four corners and the center of the nine arrangement positions in a 3x3 grid, while the second external electrode 12 is provided at the other positions.

[0092] The multilayer ceramic capacitor 100B in this embodiment includes a first metal layer 21 provided on the side surface of the capacitor body 1, but does not include a second metal layer. In this embodiment, the first metal layer 21 is provided at four locations: the corner spanning from the first side surface 1c to the second side surface 1d, the corner spanning from the second side surface 1d to the third side surface 1e, the corner spanning from the third side surface 1e to the fourth side surface 1f, and the corner spanning from the fourth side surface 1f to the first side surface 1c. However, the locations where the first metal layer 21 is provided are not limited to the above-described locations, nor is the number of first metal layers 21 limited to four.

[0093] Figure 14(a) is a schematic plan view showing the first internal electrode 3, and Figure 14(b) is a schematic plan view showing the second internal electrode 4. Figures 14(a) and (b) also show the dielectric layer 2, the first via conductor 5, the second via conductor 6, and the first connecting layer 31.

[0094] The first internal electrode 3 has multiple first through holes 3a formed therein for inserting the second via conductor 6. The second internal electrode 4 has a second through hole 4a formed therein for inserting the first via conductor 5.

[0095] As shown in Figure 14(b), the first via conductor 5, which is positioned to overlap with the second internal electrode 4 in the stacking direction T, passes through the second through hole 4a formed in the second internal electrode 4 and is insulated from the second internal electrode 4. Also, as shown in Figure 14(a), the second via conductor 6, which is positioned to overlap with the first internal electrode 3 in the stacking direction T, passes through the first through hole 3a formed in the first internal electrode 3 and is insulated from the first internal electrode 3.

[0096] As shown in Figures 14(a) and (b), the first connecting layer 31 is provided in both the layer where the first internal electrode 3 is provided and the layer where the second internal electrode 4 is provided. The first connecting layer 31 is provided at the four corners of the rectangular dielectric layer 2 when viewed in the stacking direction T. The first connecting layer 31 is in contact with the nearest first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connecting layer 31 is not in direct contact with the first internal electrode 3.

[0097] In this embodiment, the multilayer ceramic capacitor 100B is provided on the side surface of the capacitor body 1, with a first metal layer 21 electrically connected to the first via conductor 5. This makes it possible to more reliably form the first external electrode 11 by rotary plating.

[0098] <Fourth Embodiment> As described above, in the multilayer ceramic capacitor 100B of the third embodiment, a total of nine external electrodes are arranged in a matrix, and only the first metal layer 21 is provided on the side surface of the capacitor body 1.

[0099] In contrast, in the multilayer ceramic capacitor 100C of the fourth embodiment, a total of nine external electrodes are arranged in a matrix, and a first metal layer 21 and a second metal layer 22 are provided on the side surface of the capacitor body 1.

[0100] Figure 15(a) is a schematic top view of the multilayer ceramic capacitor 100C in the fourth embodiment, and Figure 15(b) is a schematic bottom view of the multilayer ceramic capacitor 100C. Figure 16 is a side view of the multilayer ceramic capacitor 100C shown in Figure 15, viewed in the direction of arrow Y3.

[0101] Similar to the multilayer ceramic capacitor 100B in the third embodiment, the multilayer ceramic capacitor 100C in the fourth embodiment is also provided with five first external electrodes 11 and four second external electrodes 12. As shown in Figure 15(a), the arrangement positions of the multiple first external electrodes 11 and the multiple second external electrodes 12 are the same as those of the multilayer ceramic capacitor 100B in the third embodiment.

[0102] The placement of the first metal layer 21 is the same as in the multilayer ceramic capacitor 100B in the third embodiment. That is, the first metal layer 21 is provided at four locations in the corners that span two sides of the capacitor body 1.

[0103] In this embodiment, the second metal layer 22 is provided between two first metal layers 21 on each of the first side surface 1c, second side surface 1d, third side surface 1e, and fourth side surface 1f of the capacitor body 1. That is, as shown in Figure 16, the second metal layer 22 provided on the first side surface 1c of the capacitor body 1 is located between two first metal layers 21 provided on the first side surface 1c. Similarly, the second metal layer 22 provided on the second side surface 1d of the capacitor body 1 is located between two first metal layers 21 provided on the second side surface 1d. The second metal layer 22 provided on the third side surface 1e of the capacitor body 1 is located between two first metal layers 21 provided on the third side surface 1e. The second metal layer 22 provided on the fourth side surface 1f of the capacitor body 1 is located between two first metal layers 21 provided on the fourth side surface 1f.

[0104] Figure 17(a) is a schematic plan view showing the first internal electrode 3, and Figure 17(b) is a schematic plan view showing the second internal electrode 4. Figures 17(a) and (b) also show the dielectric layer 2, the first via conductor 5, the second via conductor 6, the first connecting layer 31, and the second connecting layer 32.

[0105] The first internal electrode 3 has multiple first through holes 3a formed therein for inserting the second via conductor 6. The second internal electrode 4 has a second through hole 4a formed therein for inserting the first via conductor 5.

[0106] As shown in Figure 17(b), the first via conductor 5, which is positioned to overlap with the second internal electrode 4 in the stacking direction T, passes through the second through hole 4a formed in the second internal electrode 4 and is insulated from the second internal electrode 4. Also, as shown in Figure 17(a), the second via conductor 6, which is positioned to overlap with the first internal electrode 3 in the stacking direction T, passes through the first through hole 3a formed in the first internal electrode 3 and is insulated from the first internal electrode 3.

[0107] As shown in Figures 17(a) and (b), the first connecting layer 31 and the second connecting layer 32 are provided in the layer where the first internal electrode 3 is provided and the layer where the second internal electrode 4 is provided, respectively. The first connecting layer 31 is provided at the corners of the rectangular dielectric layer 2 when viewed in the stacking direction T. The first connecting layer 31 is in contact with the nearest first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connecting layer 31 is not in direct contact with the first internal electrode 3.

[0108] As shown in Figures 17(a) and (b), the second connecting layer 32 is provided at the center of each of the four sides of the rectangular dielectric layer 2 when viewed in the stacking direction T. The second connecting layer 32 is in contact with the nearest second via conductor 6 and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connecting layer 32 is not in direct contact with the second internal electrode 4.

[0109] In the fourth embodiment, the multilayer ceramic capacitor 100C, like the multilayer ceramic capacitor 100 in the first embodiment, is provided with a first metal layer 21 electrically connected to the first via conductor 5 and a second metal layer 22 electrically connected to the second via conductor 6 on the side surface of the capacitor body 1. This allows for more reliable formation of the first external electrode 11 and the second external electrode 12 by rotary plating.

[0110] (Modification of the fourth embodiment) In the configuration shown in Figures 17(a) and (b), the first connecting layer 31 and the second connecting layer 32 are provided in the layer where the first internal electrode 3 is provided and the layer where the second internal electrode 4 is provided, respectively. However, it is also possible to have a configuration in which the first connecting layer 31 is provided in the layer where the first internal electrode 3 is provided and the second connecting layer 32 is provided in the layer where the second internal electrode 4 is provided. In that case, a schematic plan view showing the first internal electrode 3 and the first connecting layer 31 is shown in Figure 18(a), and a schematic plan view showing the second internal electrode 4 and the second connecting layer 32 is shown in Figure 18(b). In Figures 18(a) and (b), the dielectric layer 2, the first via conductor 5, and the second via conductor 6 are also shown. The number and arrangement of the first via conductor 5 and the second via conductor 6 are the same as those shown in Figure 17.

[0111] As shown in Figure 18(a), the first connecting layer 31 is in contact with the nearest first via conductor 5 and is electrically connected to the first internal electrode 3 via the first via conductor 5. The first connecting layer 31 is not in direct contact with the first internal electrode 3. The position of the first connecting layer 31 when viewed in the stacking direction T is the same as the position shown in Figure 17(a). As shown in Figure 18(a), the second connecting layer 32 is not provided in the layer where the first internal electrode 3 is provided.

[0112] As shown in Figure 18(b), the second connecting layer 32 is in contact with the nearest second via conductor 6 and is electrically connected to the second internal electrode 4 via the second via conductor 6. The second connecting layer 32 is not in direct contact with the second internal electrode 4. The position of the second connecting layer 32 when viewed in the stacking direction T is the same as the position shown in Figure 17(b). As shown in Figure 18(b), the first connecting layer 31 is not provided in the layer where the second internal electrode 4 is provided.

[0113] According to the configuration shown in Figures 18(a) and (b), the number of first connecting layers 31 and second connecting layers 32 can be reduced by about half compared to the configuration shown in Figures 17(a) and (b). This suppresses the intrusion of plating solution from the outside into the inside during manufacturing, and also suppresses the intrusion of moisture and other substances from the outside into the inside of the finished product. In other words, on the side surface of the capacitor body 1, the positions where the first connecting layer 31 and second connecting layer 32 are exposed are susceptible to the intrusion of plating solution and moisture into the inside. However, the reduced number of first connecting layers 31 and second connecting layers 32 suppresses the intrusion of plating solution and moisture into the inside.

[0114] The present invention is not limited to the embodiments described above, and various applications and modifications can be made within the scope of the invention. For example, the characteristic configurations described in each embodiment and its modified form can be combined as appropriate.

[0115] The arrangement patterns of the multiple external electrodes arranged in a matrix are not limited to the arrangement patterns of the embodiments and modifications described above. For example, if the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is odd, the arrangement pattern shown in Figure 19 can also be used. In the arrangement pattern shown in Figure 19, the same type of external electrodes are arranged in the row direction, and the first external electrode 11 and the second external electrode 12 are arranged alternately in the column direction. However, the first external electrode 11 and the second external electrode 12 may be arranged alternately in the row direction, and the same type of external electrode may be arranged in the column direction. In the arrangement pattern shown in Figure 19, as with the arrangement pattern shown in Figure 13, the only external electrode provided on the side surface of the capacitor body 1 is the first external electrode 11.

[0116] When the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd, the arrangement patterns shown in Figures 20(a) and (b) can also be used. In the arrangement pattern shown in Figure 20(a), the first external electrodes 11 and the second external electrodes 12 are arranged alternately in the row direction, and the first external electrodes 11 and the second external electrodes 12 are also arranged alternately in the column direction. In the arrangement pattern shown in Figure 20(b), the same type of external electrodes are arranged in the row direction, and the first external electrodes 11 and the second external electrodes 12 are arranged alternately in the column direction. In the arrangement pattern shown in Figure 20(a), the first metal layer 21 and the second metal layer 22 are provided on the side surface of the capacitor body 1, while in the arrangement pattern shown in Figure 20(b), only the first metal layer 21 is provided on the side surface of the capacitor body 1. Furthermore, even when the number of external electrodes in the row direction is odd and the number of external electrodes in the column direction is even, it is possible to arrange the external electrodes in the same arrangement pattern as when the number of external electrodes in the row direction is even and the number of external electrodes in the column direction is odd.

[0117] When the number of external electrodes is greater than 2 rows and 2 columns, and the number of external electrodes in the row direction is even, and the number of external electrodes in the column direction is even, the arrangement patterns shown in Figures 21(a) and (b) can be used. In the arrangement pattern shown in Figure 21(a), the first external electrode 11 and the second external electrode 12 are arranged alternately in the row direction, and the first external electrode 11 and the second external electrode 12 are also arranged alternately in the column direction. In the arrangement pattern shown in Figure 21(b), the same type of external electrode is arranged in the row direction, and the first external electrode 11 and the second external electrode 12 are arranged alternately in the column direction. However, the first external electrode 11 and the second external electrode 12 may be arranged alternately in the row direction, and the same type of external electrode may be arranged in the column direction. In the arrangement patterns shown in Figures 21(a) and (b), the first metal layer 21 and the second metal layer 22 are provided on the side surface of the capacitor body 1, respectively.

[0118] When mounting the multilayer ceramic capacitor 100 onto a mounting substrate, the first metal layer 21 and the second metal layer 22 may be configured not to be joined to the land electrodes of the mounting substrate. In that case, the first metal layer 21 and the second metal layer 22 are not practically necessary for the finished product, so they may be covered with resin or the like.

[0119] In the multilayer ceramic capacitors of the embodiments and their variations described above, a first connecting layer 31 is provided inside the capacitor body 1 to electrically connect the first via conductor 5 and the first metal layer 21. However, the first connecting layer 31 may be omitted, and the first via conductor 5 and the first metal layer 21 may be electrically connected by a first internal electrode 3. In that case, the shape of the first internal electrode 3 may be made to extend to the side surface of the capacitor body 1. Similarly, in a multilayer ceramic capacitor equipped with a second metal layer 22, the second connecting layer 32 may be omitted, and the second via conductor 6 and the second metal layer 22 may be electrically connected by a second internal electrode 4.

[0120] The multilayer ceramic capacitor in this application is as follows: <1> A capacitor body comprising multiple dielectric layers, multiple first internal electrodes, and multiple second internal electrodes stacked together, A first via conductor is provided inside the capacitor body and is electrically connected to the plurality of first internal electrodes, A second via conductor is provided inside the capacitor body and is electrically connected to the plurality of second internal electrodes, A first external electrode is provided on at least one of the first and second main surfaces of the capacitor body, which are opposite to the stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode, and is connected to the first via conductor. A second external electrode is provided on at least one main surface of the capacitor body and is connected to the second via conductor, A first metal layer is provided on the side surface of the capacitor body, which is a surface other than the first main surface and the second main surface, and is electrically connected to the first via conductor. A multilayer ceramic capacitor characterized by having the following features.

[0121] <2> The capacitor further comprises a first connecting layer provided inside the capacitor body, which electrically connects the first via conductor and the first metal layer. <1> The multilayer ceramic capacitor described above.

[0122] <3> A capacitor body comprising multiple dielectric layers, multiple first internal electrodes, and multiple second internal electrodes stacked together, A first via conductor is provided inside the capacitor body and is electrically connected to the plurality of first internal electrodes, A second via conductor is provided inside the capacitor body and is electrically connected to the plurality of second internal electrodes, A first external electrode is provided on at least one of the first and second main surfaces of the capacitor body, which are opposite to the stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode, and is connected to the first via conductor. A second external electrode is provided on at least one main surface of the capacitor body and is connected to the second via conductor, A first metal layer is provided on the side surface of the capacitor body, which is a surface other than the first main surface and the second main surface, and is electrically connected to the first via conductor. A second metal layer is provided on the side surface of the capacitor body and is electrically connected to the second via conductor, A multilayer ceramic capacitor characterized by having the following features.

[0123] <4> A first connecting layer is provided inside the capacitor body and electrically connects the first via conductor and the first metal layer, A second connecting layer is provided inside the capacitor body and electrically connects the second via conductor and the second metal layer, Features further equipped <3> The multilayer ceramic capacitor described above.

[0124] <5> The first metal layer and the second metal layer are each provided at a corner that spans the two sides of the capacitor body. <3> or <4> The multilayer ceramic capacitor described above.

[0125] <6> The capacitor body has four sides, The first metal layer and the second metal layer are provided at four locations in the corners spanning the two sides of the capacitor body, and the other metal layer is provided at a position between the two first metal layers on each of the four sides. <3> ~ <5> A multilayer ceramic capacitor as described in any one of the following:

[0126] <7> The first connecting layer is provided in the layer where the second internal electrode is provided. The second connecting layer is provided in the layer in which the first internal electrode is provided. <4> The multilayer ceramic capacitor described above.

[0127] <8> The first connecting layer and the second connecting layer are provided in the layer where the first internal electrode is provided and the layer where the second internal electrode is provided, respectively. <4> The multilayer ceramic capacitor described above.

[0128] <9> The first connecting layer is provided in the layer in which the first internal electrode is provided. The second connecting layer is provided in the layer on which the second internal electrode is provided. <4> The multilayer ceramic capacitor described above.

[0129] <10> The first connecting layer is in contact with the first via conductor, but not with the first internal electrode. The second connecting layer is in contact with the second via conductor but not with the second internal electrode. <8> or <9> The multilayer ceramic capacitor described above.

[0130] <11> The aforementioned first metal layer is a plating layer. The first external electrode and the second external electrode are characterized by being plated electrodes. <1> ~ <10> A multilayer ceramic capacitor as described in any one of the following: [Explanation of Symbols]

[0131] 1 Capacitor body, 2 Dielectric layer, 3 First internal electrode, 3a First through hole, 4 Second internal electrode, 4a Second through hole, 5 First via conductor, 6 Second via conductor, 11 First external electrode, 12 Second external electrode, 21 First metal layer, 22 Second metal layer, 31 First connection layer, 32 Second connection layer, 100, 100A, 100B, 100C Multilayer ceramic capacitor, 200 Connection substrate, 210 Land electrode, 220 Solder.

Claims

1. A capacitor body comprising multiple dielectric layers, multiple first internal electrodes, and multiple second internal electrodes stacked together, A first via conductor is provided inside the capacitor body and is electrically connected to the plurality of first internal electrodes, A second via conductor is provided inside the capacitor body and is electrically connected to the plurality of second internal electrodes, A first external electrode is provided on at least one of the first and second main surfaces of the capacitor body, which are opposite to the stacking direction of the dielectric layer, the first internal electrode, and the second internal electrode, and is connected to the first via conductor. A second external electrode is provided on at least one main surface of the capacitor body and is connected to the second via conductor, A first metal layer is provided on the side surface of the capacitor body, which is a surface other than the first main surface and the second main surface, and is electrically connected to the first via conductor. A second metal layer is provided on the side surface of the capacitor body and is electrically connected to the second via conductor, Equipped with, A multilayer ceramic capacitor in which the first metal layer and the second metal layer are each provided at a corner portion spanning the two sides of the capacitor body.

2. A first connecting layer is provided inside the capacitor body and electrically connects the first via conductor and the first metal layer, A second connecting layer is provided inside the capacitor body and electrically connects the second via conductor and the second metal layer, The multilayer ceramic capacitor according to claim 1, further comprising the features described above.

3. The capacitor body has four sides, The multilayer ceramic capacitor according to claim 1, characterized in that one of the first metal layer and the second metal layer is provided at four positions in the corners spanning the two sides of the capacitor body, and the other metal layer is provided at a position between the two first metal layers on each of the four sides.

4. The capacitor body has four sides, The multilayer ceramic capacitor according to claim 2, characterized in that one of the first metal layer and the second metal layer is provided at four positions in the corners spanning the two sides of the capacitor body, and the other metal layer is provided at a position between the two first metal layers on each of the four sides.

5. The first connecting layer is provided in the layer in which the second internal electrode is provided. The multilayer ceramic capacitor according to claim 2, characterized in that the second connecting layer is provided in the layer in which the first internal electrode is provided.

6. The multilayer ceramic capacitor according to claim 2, characterized in that the first connecting layer and the second connecting layer are provided in the layer where the first internal electrode is provided and the layer where the second internal electrode is provided, respectively.

7. The first connecting layer is provided in the layer in which the first internal electrode is provided. The multilayer ceramic capacitor according to claim 2, characterized in that the second connecting layer is provided in the layer on which the second internal electrode is provided.

8. The first connecting layer is in contact with the first via conductor, but not with the first internal electrode. The multilayer ceramic capacitor according to claim 6, characterized in that the second connecting layer is in contact with the second via conductor but not with the second internal electrode.

9. The first connecting layer is in contact with the first via conductor but is not in contact with the first internal electrode. The multilayer ceramic capacitor according to claim 7, characterized in that the second connecting layer is in contact with the second via conductor but not with the second internal electrode.

10. The first metal layer is a plating layer, The multilayer ceramic capacitor according to any one of claims 1 to 9, characterized in that the first external electrode and the second external electrode are plated electrodes.

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