Method for manufacturing laminates and patterned substrates, electronic devices and mounting devices

Abstract

A laminate 100 according to the present invention comprises an insulating layer 10, a conductor layer 30 that is provided on the insulating layer 10, and an etching delay layer 20 that is provided on one surface and / or the other surface of the conductor layer 30. The conductor layer 30 and the etching delay layer 20 are not patterned.

Description

Technical Field

[0001] The present invention relates to a laminate having an insulating layer and a conductor layer, a method for manufacturing the laminate, an electronic device, and a mounting device.

Background Art

[0002] Conventionally, a laminate in which a conductor layer is provided on an insulating layer has been known. As an example, in Patent Document 1, a copper-clad laminate having an insulating layer made of polyimide and a first copper foil layer laminated and provided on one surface of the insulating layer made of polyimide has been proposed. [[ID=I3]]

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When etching the conductor layer in a laminate including a copper-clad laminate, the etching rate in the conductor layer located on the upper side becomes faster than the etching rate in the conductor layer located on the lower side, and patterning in which the upper side is shorter than the lower side tends to be formed. When the upper side becomes shorter than the lower side in the cross-sectional shape of the conductor layer, there may occur a problem that the designed current amount does not flow through the conductor layer. [[ID=ID=37]]

[0005] The present invention provides a laminate, a method for manufacturing the laminate, an electronic device, and a mounting device that can reduce the amount by which the length of one side on the side opposite to the insulating layer becomes shorter than the length of the other side on the insulating layer side in the cross-sectional shape of the conductor layer.

Means for Solving the Problems

[0006] [Concept I] The laminate according to the present invention is an insulating layer, and A conductive layer provided in the insulating layer, An etching delay layer provided on one side, the other side, or both sides of the conductor layer, Equipped with, The conductor layer and the etching delay layer do not need to be patterned.

[0007] [Concept 2] In a laminate according to Concept 1, The etching delay layer may be provided over substantially the entire surface of one side of the conductor layer.

[0008] [Concept 3] In a laminate according to either concept 1 or 2, An oxide layer may be provided between the insulating layer and the conductive layer.

[0009] [Concept 4] In a laminate based on any one of concepts 1 to 3, The aforementioned conductive layer is a layer mainly composed of copper, The etching delay layer may be a layer mainly composed of an alloy containing nickel, titanium, zinc, silver, tin, iron, gold, aluminum, stainless steel, tungsten, platinum, chromium, lead, or cobalt.

[0010] [Concept 5] In a laminate according to any one of concepts 1 to 4, The thickness of the etching delay layer may be 1 / 2 to 1 / 1000 of the thickness of the conductor layer.

[0011] [Concept 6] In a laminate according to Concept 5, The thickness of the etching delay layer may be 1 / 2 to 1 / 10 of the thickness of the conductor layer.

[0012] [Concept 7] In a laminate based on any one of concepts 1 to 6, The etching delay layer may be provided on both sides of the conductive layer.

[0013] [Concept 8] In the laminate according to any one of Concepts 1 to 7, the conductor layer may have a thickness of 100 μm or more.

[0014] [Concept 9] In the laminate according to any one of Concepts 1 to 8, an oxide layer may be provided on both one side and the other side of the conductor layer.

[0015] [Concept 10] The method for manufacturing a patterned substrate according to the present invention includes: a step of preparing a laminate having an insulating layer, a conductor layer provided on the insulating layer, and an etching delay layer provided on one side or both one side and the other side of the conductor layer; a step of patterning the conductor layer and the etching delay layer by performing etching on the substrate to be processed; and may include.

[0016] [Concept 11] The electronic device according to the present invention includes: a laminate according to any one of Concepts 1 to 9; and electronic components provided on the laminate. and may include.

[0017] [Concept 12] The mounting device according to the present invention may include the electronic device described in Concept 11. [Advantages of the Invention]

[0018] When adopting a mode in which an etching delay layer is provided on one side of the conductor layer in an unpatterned laminate, the amount by which the length (upper side length) of one side on the side opposite to the insulating layer in the cross-sectional shape of the conductor layer becomes shorter than the length (lower side length) of the other side on the insulating layer side can be reduced, and the cross-sectional shape of the conductor layer can be made closer to a rectangular shape or a square shape. [Brief Description of the Drawings]

[0019]

[0019] [Figure 1] Figure 1 is a lateral cross-sectional view of a laminate according to an example of the first embodiment of the present invention. [Figure 2] Figure 2(a) is a side cross-sectional view of a laminate according to another example of the first embodiment of the present invention, and Figure 2(b) is a side cross-sectional view of a laminate according to yet another example of the first embodiment of the present invention. [Figure 3] Figure 3 is a side cross-sectional view showing a configuration in which a portion of the conductive layer is pressed into the insulating layer before patterning. [Figure 4] Figure 4 is a lateral cross-sectional view showing a configuration in which a portion of the patterned conductive layer is pressed into the insulating layer. [Figure 5] Figure 5 is a lateral cross-sectional view showing a configuration in which the entire side surface of the conductor layer before patterning is pressed into the insulating layer. [Figure 6] Figure 6 is a lateral cross-sectional view showing a configuration in which the entire side surface of the patterned conductive layer is pressed into the insulating layer. [Figure 7] Figure 7 is a side cross-sectional view showing an embodiment having an oxidation-reduction layer, in which a portion of the patterned conductive layer is pressed into the insulating layer. [Figure 8] Figure 8 is a lateral cross-sectional view showing an embodiment having an oxidation-reduction layer, in which the entire side surface of the patterned conductive layer is pressed into the insulating layer. [Figure 9] Figure 9(a) is a side cross-sectional view showing a laminate with an etching delay layer; Figure 9(b) is a side cross-sectional view showing the state after the etching delay layer has been patterned following Figure 9(a); Figure 9(c) is a side cross-sectional view showing the state after the conductive layer has been patterned following Figure 9(b); Figure 9(d) is a side cross-sectional view showing the state after the etching delay layer has been removed following Figure 9(c); and Figure 9(e) is a side cross-sectional view showing the state after the conductive layer has been pressed into the insulating layer following Figure 9(d). [Figure 10] Figure 10(a) is a side cross-sectional view showing an example of a configuration for generating a redox layer, and Figure 10(b) is a side cross-sectional view showing a configuration having a first redox layer and a second redox layer. [Figure 11] Figure 11 is a side cross-sectional view showing an example of a configuration in which etching is performed after a portion of the conductive layer has been pressed in. [Figure 12] Figure 12(a) is a side cross-sectional view illustrating an etching process when no etching delay layer is provided, and Figure 12(b) is a side cross-sectional view illustrating an etching process when an etching delay layer is provided. [Figure 13] Figure 13(a) is a side cross-sectional view showing how the conductor layer is pressed into the insulating layer after the etching delay layer is removed; Figure 13(b) is a side cross-sectional view corresponding to Figure 13(a), showing how the oxidation-reduction layer is provided on the lower and side surfaces of the conductor layer; and Figure 13(c) is a side cross-sectional view corresponding to Figure 13(a), showing how the oxidation-reduction layer is provided on the lower, side, and upper surfaces of the conductor layer. [Figure 14] Figure 14 is a lateral cross-sectional view showing an embodiment in which an oxidation-reduction layer with an uneven shape is provided. [Figure 15A] Figure 15A is a lateral cross-sectional view of a laminate according to an example of a second embodiment of the present invention. [Figure 15B] Figure 15B(a) is a side cross-sectional view of a laminate according to another example of the second embodiment of the present invention, and Figure 15B(b) is a side cross-sectional view of a laminate according to yet another example of the second embodiment of the present invention. [Figure 16] Figure 16(a) is a side cross-sectional view of a laminate according to an example of a third embodiment of the present invention; Figure 16(b) is a side cross-sectional view of a laminate showing an example in which an oxidation-reduction layer is provided in the third embodiment of the present invention; Figure 16(c) is a side cross-sectional view of a laminate showing another example in which an oxidation-reduction layer is provided; and Figure 16(d) is a side cross-sectional view of a laminate according to yet another example in which an oxidation-reduction layer is provided. [Figure 17] Figure 17 shows an example of an electronic device that may be provided by the present invention. [Figure 18] Figure 18 is a side cross-sectional view showing an example of a multilayer substrate that may be used in the present invention. [Figure 19]Figure 19 is a lateral cross-sectional view showing an example of a double-sided plate that may be used in the present invention. [Modes for carrying out the invention]

[0020] First Embodiment "composition" The laminate 100 according to this embodiment may have an insulating layer 10, a conductive layer 30 provided on the insulating layer 10, and an etching delay layer 20 provided on one side of the conductive layer 30 (the upper side in Figure 1), as shown in Figure 1. The conductive layer 30 and the etching delay layer 20 do not have to be patterned. In other words, the laminate 100 may be in its pre-etched state. The laminate 100 provided in this embodiment may be a printed circuit board, a metal-clad laminate such as a copper-clad laminate (CCL), etc. The conductive layer 30 may be provided on both sides of the insulating layer 10, making it a double-sided board (see Figure 19).

[0021] The conductor layer 30 may be provided over substantially the entire surface of one side of the insulating layer 10, and the etching delay layer 20 may be provided over substantially the entire surface of one side of the conductor layer 30. Providing the conductor layer 30 over substantially the entire surface of one side of the insulating layer 10 means that, in a plan view from one side (the upper side of Figure 1), the conductor layer 30 covers 95% or more of the area of ​​the insulating layer 10, and the area of ​​the insulating layer 10 not covered by the conductor layer 30 is 5% or less. Similarly, providing the etching delay layer 20 over substantially the entire surface of one side of the conductor layer 30 means that, in a plan view from one side (the upper side of Figure 1), the etching delay layer 20 covers 95% or more of the area of ​​the conductor layer 30, and the area of ​​the conductor layer 30 not covered by the etching delay layer 20 is 5% or less.

[0022] The conductive layer 30 may be a metal foil, metal plating, rolled sheet, etc. The conductive layer 30 may be a copper layer made of copper. The conductive layer 30 may be made of a material other than copper, for example, gold, silver, aluminum, or an alloy containing these metals. The conductive layer 30 may be a metal mainly composed of copper. In this application, "main component" means being contained in an amount exceeding 50% by weight. The thickness of the conductive layer 30 may be 100 μm or more, or 150 μm or more. The thickness of the conductive layer 30 may be 500 μm or less, or 300 μm or less.

[0023] The etching delay layer 20 may be a nickel layer made of nickel. The etching delay layer 20 may be made of any material that delays etching, and may be made of a material other than nickel, but from the viewpoint of versatility and cost, it is beneficial to use nickel. The etching delay layer 20 may be made of a material mainly composed of nickel. Alternatively, the etching delay layer 20 may be made of a material mainly composed of titanium, zinc, silver, tin, iron, gold, aluminum, stainless steel, tungsten or platinum, or an alloy containing two or more of these.

[0024] It is beneficial for the thickness of the etching delay layer 20 to be in the range of 1 / 2 to 1 / 1000 of the thickness of the conductive layer 30. Generally speaking, when the thickness of the conductive layer 30 increases, the ratio of the thickness of the etching delay layer 20 becomes relatively smaller.

[0025] The etching delay layer 20 may be removed after the etching process is completed. In this case, the laminate 100 having the etched and patterned conductive layer 30 will not have the etching delay layer 20.

[0026] The insulating layer 10 may be composed of, for example, resin, glass, ceramic, etc. The insulating layer 10 may be a mixture of two or more insulating materials. For example, the insulating layer 10 may contain fibrous or granular insulators. The insulating layer 10 may be a semi-cured sheet (prepreg) obtained by impregnating a substrate such as paper or glass fiber with resin and drying it. The insulating layer 10 may contain a thermal conductive material such as silicon nitride. A semi-cured state is a state in which the material has not completely hardened and is still deformable.

[0027] The insulating layer 10 may be made of a thermosetting resin, an ultraviolet curing resin, or the like. A thermoplastic resin may also be used as the insulating layer 10 if it has a certain level of heat resistance. The thermosetting resin may be made of a polyimide resin, an epoxy resin, a phenolic resin, a cyanate resin, or the like. The thermoplastic resin may have a heat distortion temperature of 50 degrees Celsius or higher.

[0028] A redox layer 40 may be provided between the insulating layer 10 and the conductive layer 30. The redox layer 40 may have an uneven surface on the side facing the insulating layer 10 (see Figure 14).

[0029] The oxidation-reduction layer 40 may contain oxides of the materials constituting the conductive layer 30. Furthermore, the oxidation-reduction layer 40 may have an uneven or irregular shape in whole or in part. The uneven shape may have a cross-section that is approximately triangular, approximately rectangular, approximately semicircular, or approximately circular, or it may have a mesh-like shape resembling intertwined fibers. The uneven shape can be configured in a variety of shapes. In this embodiment, "approximately XX shape" means that it is roughly XX shape to someone skilled in the art.

[0030] As shown in Figure 2(a), the redox layer 40 may be provided between the conductive layer 30 and the etching delay layer 20. The redox layer 40 may be provided on one side of the conductive layer 30, the other side (see Figure 2(a)), or both sides (see Figure 2(b)).

[0031] The redox layer 40 may contain copper oxide as its main component. The copper oxide may contain cuprous oxide, cupric oxide, or both cuprous oxide and cupric oxide. Here, "main component" means that it is contained in an amount exceeding 50% by weight.

[0032] As shown in Figure 10(b), the redox layer 40 may have a first redox layer 41 and a second redox layer 42 provided on the insulating layer 10 side of the first redox layer 41. When the redox layer 40 is made of copper oxide, for example, the first redox layer 41 may contain cuprous oxide (Cu2O) and the second redox layer 42 may contain cuprous oxide (CuO). Alternatively, the first redox layer 41 may be made of cuprous oxide (Cu2O) and the second redox layer 42 may be made of cuprous oxide (CuO).

[0033] The redox layer 40 may consist solely of copper oxide. In other words, the entire redox layer 40 may be composed of copper oxide. In this case, the redox layer 40 will consist of an oxidized layer (oxide layer). The copper oxide may be cuprous oxide (Cu2O), cupric oxide (CuO), or both cuprous oxide and cupric oxide. As the oxidation reaction progresses, cuprous oxide becomes cupric oxide, so the mixing ratio of cuprous oxide and cupric oxide may be adjusted by adjusting the processing time with the processing solution 120 (see Figure 10(a)) in the container 110.

[0034] The insulating layer 10 may be in a semi-cured state. Part or all of the patterned conductor layer 30 may be embedded in the semi-cured insulating layer 10 by pressing it in (see Figures 3 to 6). When embedding the conductor layer 30 in the insulating layer 10, a pressing force may be applied to the conductor layer 30, but the method is not limited to this, and the conductor layer 30 may be embedded in the insulating layer 10 by its own weight. When the conductor layer 30 is embedded in the insulating layer 10, the patterned conductor layer 30 may be embedded in the insulating layer 10 (see Figures 4 and 6), or the conductor layer 30 may be embedded in the insulating layer 10 before patterning (see Figures 3 and 5). Furthermore, in the configuration in which the etching delay layer 20 is removed, the entire conductor layer 30, including one side surface (top surface), may be completely embedded inside the insulating layer 10 (see Figures 13(a)-(c)).

[0035] Figure 13(b) shows an embodiment in which the redox layer 40 is provided over the entire bottom and side surfaces of the conductor layer 30, but the redox layer 40 is not provided on the top surface where the etching delay layer 20 was previously located. This embodiment can be achieved by performing an etching process, then carrying out a redox reaction or oxidation reaction of the conductor layer 30, and then removing the etching delay layer 20. On the other hand, if an etching process is performed and the etching delay layer 20 is removed, and then a redox reaction or oxidation reaction of the conductor layer 30 is carried out, the redox layer 40 will be formed over the entire surface of the conductor layer 30 (see Figure 13(c)).

[0036] After embedding part or all of the patterned conductive layer 30 into the semi-cured insulating layer 10 by pressing it in, the insulating layer 10 may be cured by applying heat or irradiating it with ultraviolet light. If a thermoplastic resin is used as the insulating layer 10, the insulating layer 10 may be cured by allowing it to cool or by cooling.

[0037] In an embodiment where the redox layer 40 is provided, the redox layer 40 may be provided in the region that extends into the insulating layer 10, and may not be provided in the region (side surface) exposed from the insulating layer 10 (see Figure 7). This embodiment can be created by removing the region of the redox layer 40 that protrudes from the insulating layer 10 from the redox layer 40 that has been generated on the entire side surface of the conductor layer 30. Alternatively, the redox layer 40 may be provided on the entire side surface of the conductor layer 30, and the entire conductor layer 30 and the redox layer 40 may be provided within the insulating layer 10 (see Figure 8).

[0038] ≪Manufacturing process≫ An example of a processing step using the laminate according to this embodiment will be explained with reference to Figure 9.

[0039] A laminate 100 is prepared having an insulating layer 10, a conductive layer 30 provided on the insulating layer 10, and an etching delay layer 20 provided on one side of the conductive layer 30 (see Figure 9(a)).

[0040] Next, the conductive layer 30 and the etching delay layer 20 are patterned by etching the laminate 100 while it is masked as appropriate (see Figures 9(b) and 9(c)). Note that the etching solution used to pattern the etching delay layer 20 (first etching solution) and the etching solution used to pattern the conductive layer 30 (second etching solution) may be liquids with different components.

[0041] For example, the etching delay layer 20 is patterned with the first etching solution while appropriately masked (see Figure 9(b)). Then, the conductive layer 30 is patterned with the second etching solution while appropriately masked (see Figure 9(c)).

[0042] After etching is complete, the etching delay layer 20 is removed using a chemical solution (a removal solution or a second etching solution to remove the etching delay layer 20) (see Figure 9(d)).

[0043] Afterward, part or all of the patterned conductor layer 30 is pressed into the semi-cured insulating layer 10 (see Figure 9(e)).

[0044] Next, the insulating layer 10, which is in a semi-cured state, is allowed to cool or is cooled to cure it. As a result, a laminated board 100 is produced in which a portion of the conductive layer 30 is embedded in the insulating layer 10.

[0045] The above description uses an embodiment in which the conductor layer 30 is pressed into the semi-cured insulating layer 10 after the etching delay layer 20 has been removed, but the invention is not limited to this embodiment. For example, the etching delay layer 20 may be removed after the conductor layer 30 has been pressed into the semi-cured insulating layer 10. Alternatively, etching may be performed after the conductor layer 30 has been pressed into the semi-cured insulating layer 10, then the etching delay layer 20 may be removed, and then the insulating layer 10 may be cured. In this case as well, as a portion of the conductor layer 30 is removed by etching, the semi-cured insulating layer 10 moves to match the height, and an insulating layer 10 with equal height in the area where the conductor layer 30 is not provided, as shown in Figure 9(e), can be obtained. However, the invention is not limited to this embodiment, and by curing the semi-cured insulating layer 10 earlier, laminates 100 with different heights of insulating layers 10 may be produced, as shown in Figure 11. In the embodiment shown in Figure 11, the insulating layer 10 has a recessed shape where the conductor layer 30 was present.

[0046] "effect" Next, we will explain the effects of this embodiment, which has the configuration described above, focusing on those that have not yet been explained.

[0047] When an etching delay layer 20 is provided on one side of the conductor layer 30, and a laminate is used in which neither the conductor layer 30 nor the etching delay layer 20 is patterned, the cross-sectional shape of the conductor layer 30 can be made closer to a rectangular or square shape. During etching, the conductor layer 30 located on the upper side is etched more than the conductor layer 30 located on the lower side, resulting in a pattern where the upper edge is shorter than the lower edge (see Figure 12(a)). In this regard, by providing an etching delay layer 20 on one side of the conductor layer 30, the etching rate of the conductor layer 30 located on the upper side can be slowed down, and as a result, the shape of the patterned conductor layer 30 can be made closer to a rectangular or square shape (see Figure 12(b)).

[0048] In this embodiment, since the focus is on the etching process, it is important to note that the conductive layer 30 and the etching delay layer 20 are not patterned. Generally, attempts are made to reduce costs by increasing the etching speed and shortening the processing time, but in this embodiment, the disadvantage of slower processing time is accepted in order to make the conductive layer 30 closer to a rectangular or square shape, which is based on an idea that is completely opposite to that of a typical person skilled in the art.

[0049] This embodiment is advantageous because it allows a current close to the design value to flow by making the conductor layer 30 closer to a rectangular or square shape. In other words, when designing, calculations are made assuming that the conductor pattern of copper, etc., has a rectangular or square cross-section, but in reality, the cross-section of the conductor pattern of copper, etc., is trapezoidal, so a different current flows than the amount used in the design value. This embodiment is advantageous because it can improve this point.

[0050] As the thickness of the conductor layer 30 increases, the upper edge of the cross-section of the conductor layer 30 tends to become shorter than the lower edge, making it beneficial to adopt the configuration of this embodiment. In particular, for conductor layers 30 with a thickness of 100 μm or more (typically thick copper type conductor layers), the difference in the shape of the conductor layer 30 between the case where the etching delay layer 20 is provided and the case where the etching delay layer 20 is not provided becomes significant. For this reason, adopting this embodiment is beneficial when using a conductor layer 30 with a thickness of 100 μm or more.

[0051] The etching rate on one side (the upper side) can be adjusted by adjusting the thickness of the etching delay layer 20. This is particularly beneficial when the thickness of the etching delay layer 20 is 1 / 10 or more of the thickness of the conductive layer 30, and even more beneficial when it is 1 / 5 or more.

[0052] Second Embodiment Next, a second embodiment of the present invention will be described.

[0053] As shown in Figure 15A, in this embodiment, the etching delay layer 20 is provided on both one side and the other side of the conductor layer 30. The other configurations are the same as in the first embodiment, and any configuration described in the first embodiment can be adopted. The same reference numerals are used to describe the components described in the first embodiment. In this embodiment, the etching delay layer 20 provided on one side (upper side) of the conductor layer 30 is also called the first etching delay layer 20a, and the etching delay layer 20 provided on the other side (lower side) of the conductor layer 30 is also called the second etching delay layer 20b.

[0054] By providing a second etching delay layer 20b on the other side, the height of the bottom surface of the conductor layer 30 can be increased. As a result, the conductor layer 30 can be positioned in a location where the etching solution does not stagnate (the etching solution does not circulate) and the etching effect is reduced, rather than being positioned in a location where the etching solution flows smoothly and an etching effect can be expected. Therefore, it is possible to prevent the etching rate of the conductor layer 30 located on the insulating layer 10 side (lower side) from slowing down, and the cross-sectional shape of the conductor layer 30 located between the first etching delay layer 20a and the second etching delay layer 20b can be made closer to a rectangular or square shape.

[0055] From the perspective of raising the height of the bottom surface of the conductor layer 30, it is beneficial for the thickness of the second etching delay layer 20b to be 1 / 5 or more of the thickness of the conductor layer 30. By adopting a second etching delay layer 20b with such a thickness, the conductor layer 30 can be prevented from being located on the lower side where the etching process is less likely to proceed.

[0056] The thickness of the first etching delay layer 20a and the thickness of the second etching delay layer 20b may be different, and the thickness of the second etching delay layer 20b may be twice or more the thickness of the first etching delay layer 20a. For example, the thickness of the first etching delay layer 20a may be 1 / 10 or more of the thickness of the conductive layer 30, and the thickness of the second etching delay layer 20b may be 1 / 5 or more of the thickness of the conductive layer 30.

[0057] The first etching delay layer 20a and the second etching delay layer 20b may be made of the same material (e.g., nickel), but they may also be made of different materials.

[0058] If the insulating layer 10 is in a semi-cured state, the conductive layer 30 may be pressed in so that approximately (80% or more) of the second etching delay layer 20b is embedded within the insulating layer 10. Alternatively, the conductive layer 30 may be pressed in so that the entire second etching delay layer 20b is embedded within the insulating layer 10. Such pressing may be performed after patterning has been carried out.

[0059] As shown in Figures 15B(a) and (b), the redox layer (oxide layer) 40 may be provided between the conductor layer 30 and the etching delay layer 20. The redox layer 40 may be provided on one side of the conductor layer 30, the other side (see Figure 15B(a)), or both sides (see Figure 15B(b)).

[0060] Third Embodiment Next, a third embodiment of the present invention will be described.

[0061] As shown in Figure 16(a), in this embodiment, the etching delay layer 20 (second etching delay layer 20b) is provided on the other side of the conductor layer 30. The other configurations are the same as in the first embodiment, and any configuration described in the first and second embodiments can be adopted. The same reference numerals are used to describe the components described in the first or second embodiment.

[0062] Unlike the first and second embodiments, in this embodiment, the etching delay layer 20 (first etching delay layer 20a) is not provided on one side, but only on the other side. Even in this configuration, for the reasons explained in the second embodiment, the cross-sectional shape of the conductive layer 30 can be made closer to a rectangular or square shape.

[0063] As shown in Figure 16(b), the redox layer (oxide layer) 40 may be provided between the conductor layer 30 and the etching delay layer 20. The redox layer 40 may be provided on one side of the conductor layer 30 (see Figure 16(c)), the other side (see Figure 16(c)), or both sides (see Figure 16(d)).

[0064] ≪Multilayer board≫ A multilayer substrate in which multiple laminates as shown in the first to third embodiments are stacked may be used. An etching delay layer 20 and / or an oxidation-reduction layer 40 may be provided for each of the conductive layers 30.

[0065] Figure 18 shows a configuration in which multiple laminates shown in Figure 2(a) are stacked, but it is not limited to this. A configuration in which multiple laminates shown in any of Figures 1, 2(b), 15A, 15B(a), 15B(b), 16(a), 16(b), 16(c), and 16(d) are stacked may be adopted, or a multilayer substrate may be adopted in which multiple laminates consisting of two or more configurations from any of Figures 1, 2(a), 2(b), 15A, 15B(a), 15B(b), 16(a), 16(b), 16(c), and 16(d) are stacked. A configuration in which the configuration of the outermost (topmost) laminate differs from the configuration of the other laminates (laminated plates located inside) may be adopted.

[0066] The descriptions of the embodiments and the disclosure of the drawings described above are merely examples for illustrating the invention described in the claims, and the invention described in the claims is not limited by the descriptions of the embodiments or the disclosure of the drawings described above.

[0067] In the above-described embodiment, electronic components 210 such as semiconductor elements, capacitors, and resistors are placed on the laminate 100, and the electronic components are sealed with a sealing resin 220 to provide an electronic device 200 (see Figure 17). Such an electronic device may be incorporated into any mounting device such as automobiles, airplanes, ships, helicopters, personal computers, and home appliances. [Explanation of symbols]

[0068] 10 Insulating layer 20 Etching delay layer 30 Conductor Layers 100 Laminate

Claims

1. Insulating layer and, A conductive layer having a thickness exceeding 100 μm is provided on one side of the insulating layer, An etching delay layer provided on one side of the conductor layer, Equipped with, The conductor layer and the etching delay layer are not patterned. The etching retardation layer is a layer mainly composed of zinc, silver, tin, gold, aluminum, platinum, or lead, or an alloy containing two or more of these. A laminate in which the thickness of the etching delay layer is less than 1 / 60 and 1 / 1000 or more of the thickness of the conductor layer.

2. The laminate according to claim 1, further comprising an oxide layer provided on the other side of the conductor layer.

3. The laminate according to claim 1 or 2, further comprising an oxide layer provided on one side of the conductor layer.

4. The laminate according to any one of claims 1 to 3, wherein the etching delay layer is provided over substantially the entire surface of one side of the conductor layer.

5. The laminate according to any one of claims 1 to 4, wherein the conductive layer is a layer mainly composed of copper.

6. The laminate according to any one of claims 1 to 5, wherein an oxide layer is provided on both one and the other side of the conductor layer.

7. The laminate according to any one of claims 1 to 6, wherein the insulating layer is in a semi-cured state.

8. A step of preparing a laminate according to any one of claims 1 to 7, A step of patterning the conductive layer and the etching delay layer by etching the laminate, A method for manufacturing a patterned substrate, comprising:

9. A laminate according to any one of claims 1 to 7, Electronic components provided on the laminated board, An electronic device equipped with [a specific feature / feature].

10. A mounting apparatus equipped with the electronic device described in claim 9.

Images