Masking agent for high dielectric constant thin films, selective region deposition method using the same, and semiconductor substrates and semiconductor devices manufactured therefrom.

Abstract

The present invention relates to a masking agent for a high dielectric constant thin film, a selective area deposition method using the same, and a semiconductor substrate and a semiconductor device manufactured therefrom. The present invention has an effect of providing a masking agent for a high dielectric constant thin film, which can manufacture a patterned thin film by an atomic layer deposition method without a patterning process, and can significantly reduce impurities, a selective area deposition method using the same, and a semiconductor substrate and a semiconductor device manufactured therefrom.

Description

Technical Field

[0001] The present invention relates to a masking agent for a high dielectric constant thin film, a selective area deposition method using the same, and a semiconductor substrate and a semiconductor device manufactured therefrom. More specifically, the present invention relates to a masking agent for a high dielectric constant thin film capable of manufacturing a thin film having a pattern formed by an atomic layer deposition method without performing a patterning process and significantly reducing impurities, a selective area deposition method using the same, and a semiconductor substrate and a semiconductor device manufactured therefrom.

Background Art

[0002] Semiconductor processes are required because metal, semiconductor, or insulator thin films are used in various fields such as semiconductor devices, integrated circuits, solar cells, liquid crystal display devices, and organic light emitting diodes.

[0003] In order to selectively deposit a film on a complex surface composed of joints of various materials, the above semiconductor process is repeated in an etching - deposition - polishing (CMP) process.

[0004] Regarding the above deposition, research is actively conducted to deposit a high - quality thin film at a relatively low temperature using an atomic layer deposition method (ALD) that controls the reaction mechanism.

[0005] In the ALD process, the surface environment of the substrate is adjusted step by step to form a self - saturated unit atomic film raw material, and a reaction occurs on the surface. Due to the property of forming a self - saturated raw material, not only can the thickness be adjusted in atomic units, but also a perfect conformal thin film can be deposited even when forming a surface with a very complex shape by the surface movement of the raw material precursor. The density of the deposited thin film is high, and the deposition temperature can be lowered.

[0006] Recently, with the miniaturization and three - dimensionalization of semiconductor patterns, there has been a situation of facing structural parts that are difficult to form by conventional techniques.

[0007] To overcome this, there is a need to develop 'selective deposition technology' that selectively deposits specific components only in the necessary areas.

[0008] Selective deposition can be classified into two types: active, where the precursor goes to the desired site, and passive, where unwanted areas are shielded, such as molecular layers or photoresists.

[0009] Of these, the active type has the disadvantage of low substrate selectivity, so the passive type is necessary to achieve high step heights.

[0010] Passive-type photoresist systems are developed using a wet process to create permanent molecular layer photoresists. One example is a technique involving immersion in a thiol solution, but the disadvantages of wet stripping make it unsuitable for use in vapor deposition processes.

[0011]

[0012] [Prior art document]

[0013] [Patent]

[0014] (Patent Document 1) Korean Published Patent No. 2019-0140104 [Overview of the Initiative] [Problems that the invention aims to solve]

[0015] To solve the problems of the conventional technology described above, the present invention aims to provide a masking agent for high dielectric constant thin films that can perform dry removal-molecular layer-photoresist at each deposition cycle using the masking agent, thereby passivating surfaces where the masking agent has not grown, and coating only the surfaces where the masking agent has grown with a precursor, a selective deposition method using the same, and a semiconductor substrate and semiconductor device manufactured therefrom.

[0016] All of the above and other objectives of the present invention can be achieved by the present invention as described below. [Means for solving the problem]

[0017] To achieve the above objective, the present invention provides a masking agent for high dielectric constant thin films, characterized by selective adsorption onto the surface having a dielectric constant of 4.0 or higher on a composite substrate having one or more surfaces having a dielectric constant of 4.0 or higher.

[0018]

[0019] Furthermore, this invention

[0020] A step of preparing a composite substrate having one or more surfaces on the substrate with a dielectric constant (k) of less than 4.0 and one or more surfaces with a dielectric constant of 4.0 or more; and

[0021] The present invention provides a region-selective deposition method, characterized by comprising the step of loading the substrate into a chamber, and then using the masking agent for high dielectric constant thin films, precursor compound, and reaction gas of claim 1 to provide a stepped pattern or stack in which the deposition thickness on a surface with a dielectric constant (k) of less than 4.0 due to the masking agent for high dielectric constant thin films and the deposition thickness on a surface with a dielectric constant (k) of 4.0 or more are in the range of 1:2 to 20.

[0022]

[0023] The present invention also provides a selective area deposition method, which includes a step of injecting the masking agent for high dielectric constant thin films described above into a chamber and injecting it onto the surface of a substrate loaded (loaded).

[0024]

[0025] The present invention also provides a semiconductor substrate, which includes a step pattern or stack manufactured by the selective area deposition method described above.

[0026]

[0027] The present invention also provides a semiconductor device including the semiconductor substrate described above.

[0028] The semiconductor substrate may be a low resistive metal gate interconnects, a high aspect ratio 3D metal-insulator-metal capacitor, a DRAM trench capacitor, a 3D gate-all-around (GAA), or a 3D NAND.

Effects of the Invention

[0029] According to the present invention, a step pattern or stack can be manufactured without performing a patterning process, and there is an effect of providing a selective deposition area on a substrate having a complex structure by controlling the thin film growth rate.

[0030] Also, during the formation of the thin film, process by-products are more effectively reduced, corrosion and deterioration are prevented, and the crystallinity of the thin film is improved, thereby improving the electrical characteristics of the thin film. <00001Furthermore, during thin film formation, process by-products are reduced, improving step coverage and thin film density, which in turn provides a selective region deposition method utilizing this property, and a semiconductor substrate manufactured therefrom. [Brief explanation of the drawing]

[0032] [Figure 1] This is a schematic cross-sectional view showing the stacking thickness of SiO2 deposited when a pattern area on a wafer, where two or more film materials are exposed using a stage heater at a temperature of 300 to 400°C, is deposited with a total of four types of thin films: SiO2, HfO2, ZrO2, and SiN, and then SiO2 is directly deposited on top of each thin film.

[0033] [Figure 2] This is a schematic cross-sectional view showing the stacking thickness of SiO2 deposited when a pattern area on a wafer, where two or more film materials are exposed using a stage heater at a temperature of 300 to 400°C, is deposited with a total of four types of thin films: SiO2, HfO2, ZrO2, and SiN, and then SiO2 is directly deposited on top of each thin film.

[0034] [Figure 3] This figure shows the reduction rate of the deposition rate at different deposition temperatures when HfO2 is deposited using a masking agent for high dielectric constant thin films, depending on whether or not a masking agent for high dielectric constant thin films is used.

[0035] [Figure 4] This figure shows the reduction rate of the deposition rate at different deposition temperatures when SiO2 is deposited using a masking agent for high dielectric constant thin films, depending on whether or not a masking agent for high dielectric constant thin films is used. [Figure 5] This figure shows the reduction rate of the deposition rate at different deposition temperatures when SiO2 is deposited using a masking agent for high dielectric constant thin films, depending on whether or not a masking agent for high dielectric constant thin films is used. [Modes for carrying out the invention]

[0036] The following describes in detail the masking agent for high dielectric constant thin films described herein, the selective region deposition method using the same, and the semiconductor substrate manufactured therefrom.

[0037] As used in this invention, the term "high dielectric constant" refers to a dielectric constant (k) of 4.0 or higher, unless otherwise specified.

[0038] As used in this invention, the term "composite substrate" refers to a material having one or more surfaces with a dielectric constant (k) of less than 4.0 and one or more surfaces with a dielectric constant of 4.0 or more, unless otherwise specified.

[0039]

[0040] To achieve the above objective, the present invention provides a masking agent for high dielectric constant thin films, characterized by selective adsorption onto the surface having a dielectric constant of 4.0 or higher on a composite substrate having one or more surfaces having a dielectric constant of 4.0 or higher.

[0041] In the composite substrate, the surface having a dielectric constant (k) of less than 4.0 may be one selected from Si and SiO2.

[0042] In the composite substrate, the surface having a dielectric constant (k) of 4.0 or higher may be represented by MO2, M2O3, MN, or M3N4 (where M is a metal).

[0043] In the composite substrate, the surface having a dielectric constant (k) of 4.0 or higher may be one selected from Al2O3, ZrO2, HfO2, La2O3, Si3N4, TiN, TaN, GaN, AlN, and BN.

[0044] When the adsorption selectivity for a surface with a dielectric constant (k) less than 4.0 is denoted as a, and the adsorption selectivity for a surface with a dielectric constant of 4.0 or more is denoted as b, the following equation 1 may be satisfied.

[0045] [Formula 1]

[0046] a <b<2a

[0047] The masking agent for high dielectric constant thin films may be a compound whose deposition thickness on a surface with a dielectric constant (k) of 4.0 or higher is in the range of 0.1 to 0.4 Å per cycle.

[0048] The masking agent for high dielectric constant thin films may be a compound whose deposition thickness on a surface with a dielectric constant (k) of less than 4.0 is in the range of 0.6 to 1.5 Å per cycle.

[0049] The dielectric constant (k) used in this invention may be based on a value known in the art (measured at 20°C).

[0050] The masking agent for high dielectric constant thin films that satisfies the aforementioned deposition thickness may be a compound having a tertiary structure or a linear carbonate structure.

[0051] The masking agent for high dielectric constant thin films may preferably contain one or more compounds selected from linear compounds having three or more elemental species with lone pairs of electrons.

[0052] The linear compound having three or more elemental species with lone pairs of electrons may be a compound represented by the following chemical formula 1.

[0053] [Chemical formula 1]

[0054] [ka]

[0055] (In the above chemical formula 1, R'' is hydrogen, a C1 to C5 alkyl group, a C1 to C5 alkene group, or a C1 to C5 alkoxy group,

[0056] The aforementioned B is -OH, -OCH3, -OCH2CH3, -CH2CH3, -SH, -SCH3, or -SCH2CH3.

[0057] The masking agent for high dielectric constant thin films may have a refractive index (measured at 20 to 25°C) of 1.365 to 1.48, 1.366 to 1.47, 1.367 to 1.46, 1.365 to 1.41, or 1.41 to 1.46.

[0058]

[0059] The masking agent for high dielectric constant thin films may contain one or more compounds selected from the compounds represented by the following chemical formulas 1-1 to 1-3.

[0060] [Chemical formulas 1-1 to 1-3]

[0061] [ka]

[0062] The masking agent for high dielectric constant thin films may be solid or liquid under conditions of 20°C and 1 bar.

[0063]

[0064] Furthermore, this invention

[0065] A step of preparing a composite substrate having one or more surfaces on the substrate with a dielectric constant (k) of less than 4.0 and one or more surfaces with a dielectric constant of 4.0 or more; and

[0066] The present invention provides a region-selective deposition method, characterized by comprising the step of loading the substrate into a chamber, and then using the masking agent for high dielectric constant thin films, precursor compound, and reaction gas of claim 1 to provide a stepped pattern or stack in which the deposition thickness on a surface with a dielectric constant (k) of less than 4.0 due to the masking agent for high dielectric constant thin films and the deposition thickness on a surface with a dielectric constant (k) of 4.0 or more are in the range of 1:2 to 20.

[0067] The deposition thickness of the high dielectric constant thin film masking agent on a surface with a dielectric constant (k) of less than 4.0 may be in the range of 0.1 to 0.4 Å per cycle.

[0068] The deposition thickness of the masking agent for high dielectric constant thin films on a surface with a dielectric constant (k) of less than 4.0 may be in the range of 0.6 to 1.5 Å per cycle.

[0069] The substrate may be formed from among the hafnium-based thin film, silicon-based thin film, aluminum-based thin film, copper thin film, and tungsten thin film.

[0070] The hafnium-based thin film may also be made of hafnium oxide.

[0071] The silicon-based thin film may be silicon nitride or silicon oxide.

[0072] The aluminum-based thin film may also be aluminum oxide.

[0073] In this case, the substrate may be selected from titanium nitride, hafnium oxide, silicon oxide, or silicon nitride as needed.

[0074]

[0075] The aforementioned region-selective deposition method may be carried out by ALD, CVD, PEALD, or PECVD.

[0076] The precursor compound that provides the surface having a dielectric constant of 4.0 or higher may be a molecule consisting of a central metal that forms Si3N4, Al2O3, TiO2, Ta2O5, HfO2, ZrO2, La2O3, Gd2O3, Er2O3, Nd2O3, PrO2, CeO2, Y2O3, HfSiO2, α-LaAlO3, SrTiO3, etc.

[0077] The lower substrate of the composite substrate may be selected from SiN, SiO2, HfO, Al2O3, Cu, and W.

[0078] The reaction gas may contain oxygen, nitrogen, or sulfur.

[0079] The deposition temperature may be in the range of 50 to 700°C.

[0080]

[0081] Furthermore, the present invention provides a selective region deposition method characterized by including the step of injecting the aforementioned high dielectric constant thin film masking agent into a chamber and injecting it onto the loaded substrate surface.

[0082]

[0083] The selected region deposition method may include: ia) vaporizing the masking agent for the high dielectric constant thin film to form a shielding region on the surface of the substrate loaded into the chamber; ib) primary purging of the inside of the chamber with a purge gas; ii-a) vaporizing the raw material precursor for the target film and adsorbing it onto the region outside the shielding region; ii-b) secondary purging of the inside of the chamber with a purge gas; iii-a) vaporizing the raw material precursor for the non-target film and adsorbing it onto the region outside the shielding region; iii-b) tertiary purging of the inside of the chamber with a purge gas; iv-a) supplying a reaction gas into the inside of the chamber; and iv-b) quaternary purging of the inside of the chamber with a purge gas.

[0084] Prior to steps ii-a) and ii-b), steps iii-a) and iii-b) may be performed, and if necessary, steps ii-a) and iii-a), and steps ii-b) and iii-b) may be performed simultaneously.

[0085] Furthermore, steps iii-a) and iii-b) may be performed before steps ii-a) and ii-b), and steps ia) and ib) may be performed afterward. If necessary, steps ii-a) and iii-a), and steps ii-b) and iii-b) may be performed simultaneously before steps ia) and ib) are performed.

[0086] The chamber may be an ALD chamber, a CVD chamber, a PEALD chamber, or a PECVD chamber.

[0087] The masking agent or raw material precursor for the high dielectric constant thin film may include a step of plasma post-treatment after vaporization and injection.

[0088] The amount of purge gas introduced into the chamber may be 10 to 100,000 times the volume of masking agent for high dielectric constant thin films introduced.

[0089] The reaction gas, the masking agent for high dielectric constant thin films, and the raw material precursor may be transferred into the chamber by VFC, DLI, or LDS.

[0090] The substrate loaded into the chamber is heated to 50 to 400°C, and the ratio of the amount (mg / cycle) of the masking agent for high dielectric constant thin films to the raw material precursor added to the chamber may be 1:1.5 to 1:20.

[0091] The reaction gas may be a reducing agent, a nitriding agent, or an oxidizing agent.

[0092]

[0093] * The aforementioned selective region deposition method may also involve a deposition temperature of 50 to 700°C.

[0094] The thin film for selective atomic layer deposition may be a low dielectric constant thin film, a high dielectric constant thin film, or a metal film.

[0095]

[0096] Furthermore, the present invention provides a semiconductor substrate characterized by including a step pattern or stack manufactured by the selective region deposition method described above.

[0097] The aforementioned stepped pattern or stack may have a multilayer structure of two or three or more layers.

[0098] The stepped pattern or stack does not remain on the hafnium-based thin film, silicon-based thin film, aluminum-based thin film, copper thin film, or tungsten thin film, and may contain 1% or less of carbon, silicon, and halogen compounds.

[0099] The stepped pattern or stack may be used for applications such as an insulator, dielectric film, diffusion barrier, or electrode.

[0100]

[0101] Furthermore, the present invention provides a semiconductor device including the aforementioned semiconductor substrate.

[0102] The semiconductor substrate may be a low-resistive metal gate interconnect, a high-aspect-ratio 3D metal-insulator-metal (MIM) capacitor, a DRAM trench capacitor, a 3D gate-all-around (GAA) or 3D NAND.

[0103]

[0104] According to the present invention, stepped patterns or stacks can be manufactured without performing a patterning process, and the thin film growth rate can be controlled to provide selective deposition regions on substrates with complex structures.

[0105] Furthermore, during thin film formation, process by-products are more effectively reduced, preventing corrosion and degradation, and improving the crystallinity of the thin film, thereby improving its electrical properties.

[0106] Furthermore, during thin film formation, process by-products are reduced, improving step coverage and thin film density, which in turn provides a selective region deposition method utilizing this property, and a semiconductor substrate manufactured therefrom.

[0107]

[0108] Preferred embodiments and drawings are provided below to aid in understanding the present invention. The embodiments and drawings below are merely illustrative of the present invention, and it will be obvious to those skilled in the art that various changes and modifications are possible within the scope of the present invention and the technical concept, and such variations and modifications will naturally fall within the scope of the attached claims.

[0109]

[0110] [Examples]

[0111] Example 1 and Comparative Examples 1 to 2

[0112] The combinations shown in Table 1 below were selected for use in the experiment, including the masking agent for high dielectric constant thin films, raw material precursor, reaction gas, deposition temperature, flow rate, purging, deposition conditions, and cycle conditions (masking agent injection - purging - precursor injection - purging - reaction gas injection - purging).

[0113] [Table 1]

[0114] In Table 1 above, CpHf is an abbreviation for CpHf(NMe2)3, BTBAS is an abbreviation for [Bis(t-butylamino)Silane], and 3DMAS is an abbreviation for Tris(dimethylamino)silane.

[0115] The experiment was conducted as follows using the combinations shown in Table 1 above.

[0116] Specifically, as a high dielectric constant thin film masking agent, we prepared a compound represented by the following chemical formula 1-1.

[0117] [Chemical formula 1-1]

[0118] [ka]

[0119] Furthermore, CpHf, BTBAS, and 3DMAS were used as precursors, and ozone (oxygen 1m) was used as the reaction gas. 3 Each sample was prepared with ozone at a concentration of 200g per sample.

[0120]

[0121] Example 1

[0122] The masking agent for high dielectric constant thin films was placed in a canister and supplied at room temperature to a vaporizer heated to 150°C at a flow rate of 0.2 g / min using an LMFC (Liquid Mass Flow Controller). The masking agent, vaporized into a vapor phase in the vaporizer, was introduced into the deposition chamber with the substrate loaded for 1 second, and then argon gas was supplied at 3000 sccm for 2 seconds to perform an argon purge. At this time, the pressure in the reaction chamber was controlled to 2 Torr.

[0123] Next, the precursor compound CpHf was placed in a canister and injected into the chamber for 1 second through a VFC (vapor flow controller). After that, argon gas was supplied at 3000 sccm for 2 seconds to perform an argon purge. At this time, the pressure inside the reaction chamber was controlled to 2 Torr.

[0124] Next, 1000 sccm of ozone was introduced into the reaction chamber as a reactive gas for 3 seconds, followed by argon purging for 3 seconds. During this time, the substrate on which the thin film was to be formed was heated under the temperature conditions shown in Table 1.

[0125] This process was repeated 200 to 400 times to form a 10 nm thick self-limiting atomic layer thin film.

[0126]

[0127] Comparative Examples 1 to 5

[0128] Except for not using a masking agent for high dielectric constant thin films in Example 1, the same process as in Example 1 was repeated using the materials and conditions shown in Table 1.

[0129]

[0130] Experimental Example 1

[0131] For each of the thin films obtained in Example 1 and Comparative Examples 1 to 5, the deposition rate reduction rate (D / R reduction rate), SIMS C impurities, and step coverage were measured using the method described below, and are shown in Figures 3 to 5 below.

[0132] * Evaporation rate reduction rate (D / R (dep. rate) reduction rate): This refers to the ratio of the reduction in deposition rate after the introduction of the thin film shielding material compared to the D / R before the introduction of the shielding material to react with the activated surface. It was calculated as a percentage using the measured A / cycle value.

[0133] The deposition rate was calculated by dividing the thickness of the fabricated thin film, measured using an ellipsometer (a device that measures optical properties such as thickness and refractive index of a thin film by utilizing the polarization characteristics of light), by the number of cycles, thereby calculating the thickness of the thin film deposited per cycle. Specifically, the calculation was performed using Equation 1 below.

[0134] [Formula 1]

[0135] Deposition rate (D / R) = Thickness of deposited thin film / Number of deposition cycles

[0136] * SIMS (Secondary-ion mass spectrometry) C impurities: When the thin film was penetrated axially by ion sputtering and the substrate surface layer was less contaminated, the C impurity value was confirmed using a SIMS graph, taking into account the C impurity content (counts) when the sputtering time was 50 seconds.

[0137] * Step Coverage (%): The step coverage was calculated by measuring the TEM of specimens horizontally cut at a position 100 nm below the top (left diagram) and a position 100 nm above the bottom (right diagram) of the thin films deposited on a substrate with a complex structure and an aspect ratio of 22:1 according to Example 1 and Comparative Examples 1 to 5.

[0138] Specifically, a deposition process was carried out on a substrate with a complex structure having an aspect ratio of 22:1, with an upper diameter of 90 nm, a lower diameter of 65 nm, and a via hole depth of approximately 2000 nm, using diffusion-improving material application conditions. Then, to confirm the thickness uniformity and step coverage of the deposited material inside the vertically formed via holes, specimens were prepared by horizontally cutting the substrate at positions 100 nm from the top downwards and 100 nm from the bottom upwards, and measurements were taken using an electron transmission microscope (TEM).

[0139]

[0140] Additional Example 1

[0141] Thin films were obtained by depositing HfO2 on a Si substrate by performing the same steps as in Example 1 and Comparative Example 1 in separate regions, depending on whether or not a masking agent for high dielectric constant thin films was used.

[0142] The reduction rates in deposition rates at different deposition temperatures between the application area of ​​Example 1 and the application area of ​​Comparative Example 1 of the thin film were calculated and are shown in Figure 3 below.

[0143] As can be seen from Figure 3 below, in Example 1, where the masking agent for high dielectric constant thin films selected in the present invention was applied to a surface with a dielectric constant (k) of 4.0 or higher, it was confirmed that the deposition rate (D / R) showed a significant improvement compared to Comparative Example 1, in which the masking agent for high dielectric constant thin films was not used.

[0144]

[0145] Additional Comparative Example 1

[0146] The same procedure as in Additional Example 1 was followed. Except that the same steps as in Comparative Example 2 were performed instead of Example 1, and the same steps as in Comparative Example 3 were performed instead of Comparative Example 1, the same steps as in Additional Example 1 were repeated to obtain a thin film in which SiO2 was deposited, depending on whether or not a masking agent for high dielectric constant thin films was used.

[0147] The reduction rates in deposition rates at different deposition temperatures between the application region of Comparative Example 2 and the application region of Comparative Example 3 for the thin film were calculated and are shown in Figure 4 below.

[0148] As can be seen from Figure 4 below, in Comparative Example 2, where the masking agent for high dielectric constant thin films selected in the present invention was applied to a surface with a dielectric constant (k) of less than 4.0, no improvement in the reduction rate of the deposition rate (D / R) was observed compared to Comparative Example 3, where the masking agent for high dielectric constant thin films was not applied.

[0149]

[0150] Additional Comparative Example 2

[0151] The same procedure as in Additional Example 1 was followed. Except that the same steps as in Comparative Example 4 were performed instead of Example 1, and the same steps as in Comparative Example 5 were performed instead of Comparative Example 1, the same steps as in Additional Example 1 were repeated to obtain a thin film in which SiO2 was deposited, depending on whether or not a masking agent for high dielectric constant thin films was used.

[0152] The reduction rates of deposition rates at different deposition temperatures between the application region of Comparative Example 4 and the application region of Comparative Example 5 for the thin film were calculated and are shown in Figure 5 below.

[0153] As can be seen from Figure 5 below, Comparative Example 4, in which the masking agent for high dielectric constant thin films selected in the present invention was applied to a surface with a dielectric constant (k) of less than 4.0, showed no improvement in the reduction rate of the deposition rate (D / R) compared to Comparative Example 5, in which the masking agent for high dielectric constant thin films was not applied.

[0154]

[0155] <Experimental Example 2>

[0156] Table 2 below summarizes the deposition rate reduction rates at a deposition temperature of 400°C, as shown in the deposition rate reduction rate graphs for each deposition temperature in Figures 3 to 5 mentioned above.

[0157] [Table 2]

[0158] As can be seen from Additional Example 1 in Table 2 above, it was confirmed that the reduction in deposition rate between Example 1, in which the masking agent for high dielectric constant thin films according to the present invention was applied to a surface with a dielectric constant (k) of 4.0 or higher, and Comparative Example 1, in which the masking agent for high dielectric constant thin films was not applied to the same surface, reached 88%.

[0159] On the other hand, as can be seen from Additional Comparative Example 2 in Table 2, the reduction in deposition rate between Comparative Example 2, in which the masking agent for high dielectric constant thin films according to the present invention was applied to a surface with a dielectric constant (k) of less than 4.0, and Comparative Example 3, in which the masking agent for high dielectric constant thin films was not applied to the same surface, was only 1%.

[0160] Furthermore, as can be seen from Additional Comparative Example 3 in Table 2, it was confirmed that the reduction in deposition rate between Comparative Example 4, in which the masking agent for high dielectric constant thin films according to the present invention was applied to a surface with a dielectric constant (k) of less than 4.0, and Comparative Example 5, in which the masking agent for high dielectric constant thin films was not applied to the said surface, was only 2%.

[0161]

[0162] Therefore, by using a masking agent for high dielectric constant thin films, the present invention effectively enables selective deposition technology in which dry removal, molecular layer formation, and photoresist formation are performed after each deposition cycle, allowing the surface where the masking agent has not grown to passivate, and the precursor is applied only to the surface where the masking agent has grown. This makes it suitable for providing a variety of semiconductor substrates and semiconductor devices.

Claims

1. A masking agent for high dielectric constant thin films, characterized in that it selectively adsorbs onto the surface having a dielectric constant of 4.0 or higher on a composite substrate having one or more surfaces having a dielectric constant of 4.0 or higher, wherein the composite substrate has one or more surfaces having a dielectric constant of 4.0 or higher. Surfaces with a dielectric constant (k) of less than 4.0 are Si and SiO ２ The surface is one or more selected from the above, and the dielectric constant (k) is 4.0 or higher. ２ M ２ O ３ , MN or M ３ N ４ (Here, M is a metal), and the masking agent for high dielectric constant thin films is characterized in that it is a compound having a linear carbonate structure.

2. In the composite substrate, the surface with a dielectric constant (k) of 4.0 or more is Al ２ O ３ , ZrO ２ , HfO ２ , La ２ O ３ , Si ３ N ４ , TiN, TaN, GaN, AlN, and BN, and the masking agent for a high dielectric constant thin film according to claim 1, characterized in that it is one or more selected therefrom.

3. A masking agent for high dielectric constant thin films according to claim 1, where a is the adsorption selectivity for a surface with a dielectric constant (k) less than 4.0, and b is the adsorption selectivity for a surface with a dielectric constant of 4.0 or more, and the following formula 1 is satisfied. [Formula 1] a < b < 2a

4. The masking agent for high dielectric constant thin films according to claim 1, characterized in that the masking agent for high dielectric constant thin films is a compound represented by the following chemical formula 1. [Chemical formula 1] 【Chemistry 1】 (In the above chemical formula 1, R'' is hydrogen, a C1 to C5 alkyl group, a C1 to C5 alkene group, or a C1 to C5 alkoxy group, The aforementioned B is -OCH ３ or -OCH ２ CH ３ (That is the case.)

5. A step of preparing a composite substrate having one or more surfaces on the substrate with a dielectric constant (k) of less than 4.0 and one or more surfaces with a dielectric constant of 4.0 or more; and The step of loading the substrate into the chamber, and then using the masking agent for high dielectric constant thin films, precursor compound, and reaction gas of claim 1, to provide a stepped pattern or stack without a patterning step, wherein the deposition thickness on a surface with a dielectric constant (k) of less than 4.0 due to the masking agent for high dielectric constant thin films and the deposition thickness on a surface with a dielectric constant (k) of 4.0 or more are in the range of 1:2 to 20; Surfaces with a dielectric constant (k) of less than 4.0 are Si and SiO ２ The surface is one or more selected from the above, and the dielectric constant (k) is 4.0 or higher. ２ M ２ O ３ , MN or M ３ N ４ A region-selective deposition method characterized by (where M is a metal).

6. The region-selective deposition method according to claim 5, characterized in that the region-selective deposition method is performed by ALD, CVD, PEALD, or PECVD.

7. The region-selective deposition method according to claim 5, characterized in that the precursor compound is independently selected from among Ti-based compounds, Hf-based compounds, and Si-based compounds.

8. The region-selective deposition method according to claim 5, characterized in that the deposition temperature is within the range of 50 to 700°C.

9. A semiconductor substrate characterized by including a step pattern or stack manufactured by the region-selective deposition method of claim 5.

10. The semiconductor substrate according to claim 9, characterized in that the stepped pattern or stack has a multilayer structure of two or three or more layers.

11. A semiconductor device comprising a semiconductor substrate according to claim 9.

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