Field emission element and method for manufacturing the same

Abstract

A method for manufacturing a field emission device is disclosed, which includes the steps of forming a primary epitaxial layer on a substrate, forming a plurality of secondary epitaxial structures on the primary epitaxial layer, forming an emitter electrode layer and a dielectric layer located on the primary epitaxial layer between the emitter electrode layer and the plurality of secondary epitaxial structures, sequentially forming a protective layer, an insulating layer, a gate electrode layer, and a planarization layer on the dielectric layer and the plurality of secondary epitaxial structures, etching the planarization layer to expose the dielectric layer and some of the gate electrode layers in some of the secondary epitaxial structures, etching and removing some of the protective layer, the insulating layer, and the exposed gate electrode layer in some of the secondary epitaxial structures to expose some of the secondary epitaxial structures, forming a gate connection electrode layer on the exposed gate electrode layer in the dielectric layer, and forming an anode facing the exposed secondary epitaxial structures and spaced a predetermined distance from the exposed secondary epitaxial structures.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and specifically relates to a field emission device and a method for manufacturing the same.

Background Art

[0002] A field emission device (FE) is a vacuum transistor based on the field emission phenomenon. It has high radiation resistance and no scattered electron transport, thus meeting the usage requirements in harsh environments and high-frequency electronic devices. Currently, silicon (Si)-based field emission devices are the most developed. In order to reduce the operating voltage of the FE, generally a sharp tip form is required or the distance between the gate electrode and the emitter electrode needs to be reduced. Group III nitride semiconductor materials can adjust their electron affinity (for example, by doping Al into GaN, the adjustment of the Al composition can be controlled), and it is easy to achieve n-type doping. Therefore, it is considered that the performance of the field emission device can be further improved and the on-voltage can be reduced. First, with the reduction of the electron affinity, electrons can tunnel more easily from the surface of the semiconductor into the vacuum, so the device has a lower operating voltage.

[0003] Currently, there is little research on field emission devices based on group III nitrides. For the reported devices, as a result, the on-voltage is generally greater than 100V. Since the characteristic size of the field emission device is generally less than 100 nm, its manufacturing process often depends on state-of-the-art lithography and etching technologies such as electron beam lithography and wet digital etching technology. The main existing problems are low current density, low device stability, high manufacturing difficulty, and low on-chip uniformity, etc.

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to solve the technical problems existing in the above prior art, the present invention provides a field emission device and a method for manufacturing the same. [Means for solving the problem]

[0005] A method for manufacturing a field emission element according to one embodiment of the present invention includes the steps of: forming a primary epitaxial layer on a substrate; forming a plurality of secondary epitaxial structures on the primary epitaxial layer, wherein there is a gap between adjacent secondary epitaxial structures; forming an emitter electrode layer and a dielectric layer located between the emitter electrode layer and the plurality of secondary epitaxial structures on the primary epitaxial layer; sequentially forming a laminated protective layer, an insulating layer, a gate electrode layer and a planarization layer on the dielectric layer and the plurality of secondary epitaxial structures; and forming the planarization layer The process includes the steps of: performing an etching process to expose the dielectric layer and a portion of the gate electrode layer in a portion of the secondary epitaxial structure; etching and removing a protective layer, insulating layer, and a portion of the exposed gate electrode layer in a portion of the secondary epitaxial structure to expose a portion of the secondary epitaxial structure; forming a gate connection electrode layer on the exposed gate electrode layer in the dielectric layer; and forming an anode that faces the exposed secondary epitaxial structure and has a predetermined distance between it and the exposed secondary epitaxial structure.

[0006] In one example of the manufacturing method according to the above embodiment, the plurality of secondary epitaxial structures are arranged in an array and are secondary epitaxial bumps exhibiting a frustoconical or truncated square shape.

[0007] In an example of a manufacturing method according to the above embodiment, the plurality of secondary epitaxial structures are arranged sequentially at intervals and are secondary epitaxial protrusions whose length-extending direction is perpendicular to the arrangement direction.

[0008] In one example of the manufacturing method according to the above embodiment, the predetermined distance is 1 to 10 mm.

[0009] In an example of a manufacturing method according to one embodiment described above, before forming an emitter electrode layer and a dielectric layer located between the emitter electrode layer and a plurality of secondary epitaxial structures on the primary epitaxial layer, the manufacturing method further includes a step of forming a depletion region between the side surface and the depletion layer by forming a depletion layer on the upper surface and side surface of the secondary epitaxial structure.

[0010] In one example of a manufacturing method according to the above embodiment, the manufacturing method further includes a step of forming a buffer layer on the substrate before forming a primary epitaxial layer on the substrate, and the epitaxial layer is formed on the buffer layer.

[0011] In an example of a manufacturing method according to one aspect described above, the method for forming a plurality of secondary epitaxial structures on the primary epitaxial layer specifically includes the steps of: forming a mask layer on the primary epitaxial layer; forming a plurality of via holes arranged in an array on the mask layer by performing a patterning process on the mask layer; forming a plurality of secondary epitaxial structures on the primary epitaxial layer exposed by each of the via holes; and removing the remaining mask layer.

[0012] In an example of a manufacturing method according to one aspect described above, the method for forming a plurality of secondary epitaxial structures on the primary epitaxial layer specifically includes the steps of: forming a mask layer on the primary epitaxial layer; forming a plurality of via holes on the mask layer by performing a patterning process on the mask layer, which are arranged sequentially at intervals and whose length-extending direction is perpendicular to the arrangement direction; forming a plurality of secondary epitaxial structures by performing secondary epitaxial on the primary epitaxial layer exposed by each of the via holes; and removing the remaining mask layer.

[0013] A method for manufacturing a field emission element according to another embodiment of the present invention includes the steps of sequentially forming a laminated primary epitaxial layer and an aluminum oxide layer on a substrate, forming a plurality of via holes by patterning the aluminum oxide layer, forming a plurality of secondary epitaxial structures on the primary epitaxial layer exposed by the via holes, forming an emitter electrode layer and a dielectric layer located between the emitter electrode layer and the plurality of secondary epitaxial structures on the primary epitaxial layer, and forming a laminated insulating layer on the dielectric layer, the plurality of secondary epitaxial structures and the remaining aluminum oxide layer. The process includes the steps of sequentially forming a gate electrode layer and a planarization layer; performing an etching treatment on the planarization layer to expose the dielectric layer and a portion of the gate electrode layer in a portion of the secondary epitaxial structure; etching and removing a portion of the insulating layer in a portion of the secondary epitaxial structure and a portion of the exposed gate electrode layer to expose a portion of the secondary epitaxial structure; forming a gate connection electrode layer on the exposed gate electrode layer in the dielectric layer; and forming an anode that faces the exposed secondary epitaxial structure and has a predetermined distance between it and the exposed secondary epitaxial structure.

[0014] According to another embodiment of the present invention, a field emission element manufactured by the above manufacturing method is provided. [Effects of the Invention]

[0015] As a beneficial effect, the field emission element and its manufacturing method of the present invention can provide element performance with low on-voltage and high gain. Since etching is not required when forming the primary epitaxial layer and secondary epitaxial structure, and they are formed directly by epitaxial deposition, the on-chip uniformity of the element is improved, the production efficiency of the element is improved, and the reliability of the element is improved. [Brief explanation of the drawing]

[0016] The description of the embodiments of the present invention, as well as other aspects, features, and advantages, will become clearer by explaining as follows while referring to the drawings. [Figure 1A] It is a manufacturing process diagram of a method for manufacturing a field emission device according to an embodiment of the present invention. [Figure 1B] It is a manufacturing process diagram of a method for manufacturing a field emission device according to an embodiment of the present invention. [Figure 1C] It is a manufacturing process diagram of a method for manufacturing a field emission device according to an embodiment of the present invention. [Figure 1D] It is a manufacturing process diagram of a method for manufacturing a field emission device according to an embodiment of the present invention. [Figure 1E] It is a manufacturing process diagram of a method for manufacturing a field emission device according to an embodiment of the present invention. [Figure 1F] It is a manufacturing process diagram of a method for manufacturing a field emission device according to an embodiment of the present invention. [Figure 1G] It is a manufacturing process diagram of a method for manufacturing a field emission device according to an embodiment of the present invention. [Figure 1H] It is a manufacturing process diagram of a method for manufacturing a field emission device according to an embodiment of the present invention. [Figure 2A] It is a manufacturing process diagram for manufacturing a secondary epitaxial structure according to an embodiment of the present invention. [Figure 2B] It is a manufacturing process diagram for manufacturing a secondary epitaxial structure according to an embodiment of the present invention. [Figure 2C] It is a manufacturing process diagram for manufacturing a secondary epitaxial structure according to an embodiment of the present invention. [Figure 2D] It is a manufacturing process diagram for manufacturing a secondary epitaxial structure according to an embodiment of the present invention. [Figure 2E] It is a manufacturing process diagram for manufacturing a secondary epitaxial structure according to another embodiment of the present invention. [Figure 2F] It is a manufacturing process diagram for manufacturing a secondary epitaxial structure according to another embodiment of the present invention. [Figure 2G] It is a manufacturing process diagram for manufacturing a secondary epitaxial structure according to another embodiment of the present invention. [Figure 2H] It is a manufacturing process diagram for manufacturing a secondary epitaxial structure according to another embodiment of the present invention. [Figure 3] It is a perspective view showing the configuration of a secondary epitaxial structure according to an embodiment of the present invention. [Figure 4] It is a perspective view showing the configuration of a secondary epitaxial structure according to another embodiment of the present invention. [Figure 5] It is a schematic diagram of a depletion region according to an embodiment of the present invention.

Embodiments for Carrying out the Invention

[0017] Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments described herein. On the contrary, these embodiments are provided to enable those skilled in the art to understand various modifications suitable for various embodiments of the present invention and specific expected applications by explaining the principles of the present invention and its actual applications.

[0018] As used herein, the terms "comprising" and its variants are open terms and mean "including but not limited to". Terms such as "based on" and "according to" mean "at least partially based on" and "at least partially according to". The terms "one embodiment" and "an embodiment" mean "at least one embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first", "second", etc. may refer to different objects or the same object. Hereinafter, other definitions may be included explicitly or implicitly. Unless specified from the context, the definition of a term is consistent throughout the specification.

[0019] Figures 1A to 1H are manufacturing process diagrams of a method for manufacturing a field emission device according to an embodiment of the present invention.

[0020] As shown in Figure 1A, in manufacturing step 1, the laminated buffer layer 2 and the primary epitaxial layer 3 are manufactured sequentially on the substrate 1. In other embodiments, the buffer layer 2 may be omitted, and the primary epitaxial layer 3 may be manufactured directly on the substrate.

[0021] Here, the buffer layer 2 may be made of GaN or AlGaN, and the primary epitaxial layer 3 may be made of unintentionally doped GaN (U-GaN), etc.

[0022] As shown in Figure 1B, in manufacturing step 2, multiple secondary epitaxial structures 5 are formed on the primary epitaxial layer 3, with spacing between adjacent secondary epitaxial structures 5.

[0023] Here, the secondary epitaxial structure 5 may be manufactured using GaN or AlGaN, etc. Furthermore, the secondary epitaxial structure 5 can be doped with N-type material. In this embodiment, the specific formation process of the secondary epitaxial structure 5 is shown in Figures 2A to 2D and will be described in detail below.

[0024] Figures 2A to 2D are manufacturing process diagrams for producing a secondary epitaxial structure according to an embodiment of the present invention.

[0025] First, as shown in Figure 2A, a mask layer 4 is formed on the primary epitaxial layer 3. Here, the material of the mask layer 4 may be silica (SiO2) or the like.

[0026] Next, as shown in Figure 2B, a patterning process is performed on the mask layer 4 to form a plurality of via holes 41 arranged in an array on the mask layer 4. The via holes 41 expose the corresponding portion of the primary epitaxial layer 3 below them. Here, the upper view in Figure 2B is a side view of the patterned mask layer 4, and the lower left view and lower right view are plan views of two different patterns of the patterned mask layer 4.

[0027] Next, as shown in Figure 2C, a plurality of secondary epitaxial structures 5 are formed by performing secondary epitaxial treatment on the primary epitaxial layer 3 exposed by each of the via holes 41.

[0028] Finally, remove the remaining mask layer 4 as shown in Figure 2D.

[0029] The multiple secondary epitaxial structures 5 formed by the manufacturing processes shown in Figures 2A to 2D are arranged in an array and are secondary epitaxial bumps exhibiting a frustoconical or truncated square pyramidal shape (shown in Figure 3). In this case, the angle between the side surface of the secondary epitaxial structure 5 and the plane on which the primary epitaxial layer 3 is located may be, for example, between 58° and 60°.

[0030] Figures 2E to 2H are manufacturing process diagrams for producing a secondary epitaxial structure according to another embodiment of the present invention.

[0031] First, as shown in Figure 2E, a mask layer 4 is formed on the primary epitaxial layer 3. Here, the material of the mask layer 4 may be silica (SiO2) or the like.

[0032] Next, as shown in Figure 2F, a patterning process is performed on the mask layer 4 to form a plurality of via holes 42 that are sequentially spaced apart on the mask layer 4 and whose length extension direction is perpendicular to the arrangement direction. The via holes 42 expose the corresponding portion of the primary epitaxial layer 3 below them. Here, the left side of Figure 2F is a side view of the patterned mask layer 4, and the right side is a plan view of the patterned mask layer 4.

[0033] Next, as shown in Figure 2G, a secondary epitaxial layer 3 exposed by each of the via holes 41 is subjected to secondary epitaxial treatment to form a plurality of secondary epitaxial structures 5'.

[0034] Finally, remove the remaining mask layer 4 as shown in Figure 2H.

[0035] The multiple secondary epitaxial structures 5′ formed by the manufacturing process shown in Figures 2E to 2H are arranged sequentially at intervals, and are secondary epitaxial protrusions whose length-extending direction is perpendicular to the arrangement direction (shown in Figure 4). Furthermore, the cross-sectional shape of the above secondary epitaxial protrusions is an isosceles trapezoid.

[0036] Furthermore, if the material of mask layer 4 is, for example, aluminum oxide (Al2O3), the steps in Figures 2D and 2H may be omitted. In other words, the remaining mask layer 4 may be present, and its specific function will be explained below.

[0037] After the completion of manufacturing process 2 and before performing manufacturing process 3, the manufacturing method according to an embodiment of the present invention further includes forming a depletion layer 14 on the upper and side surfaces of the secondary epitaxial structure 5, as shown in Figure 5, thereby forming a depletion region between the side surface and the depletion layer 14. The depletion layer 14 may be epitaxial p-GaN, and because the epitaxial velocity of the thin, inclined side surface is much greater than the epitaxial velocity of the upper surface, the thickness of the p-GaN on the upper surface can be ignored, and its impact on the performance of the device is very small. In this way, a depletion region is obtained on the side surface, the actual size of the upper surface can be further reduced, and the leakage current of the device can be significantly reduced by the depletion region formed on the side surface.

[0038] In this embodiment, the size of the top surface (width from left to right on the page) may be less than 50 nm.

[0039] As shown in Figure 1C, in manufacturing step 3, an emitter electrode layer 6 and a dielectric layer 7 located between the emitter electrode layer 6 and the plurality of secondary epitaxial structures 5 are formed on the primary epitaxial layer 3.

[0040] Here, the emitter electrode layer 6 may be composed of a Ti / Al / Ni / Au multilayer metal layer, and the dielectric layer 7 may be composed of an aluminum layer and a silica layer laminated and covering the aluminum layer.

[0041] As shown in Figure 1D, in manufacturing step 4, a protective layer 8, an insulating layer 9, a gate electrode layer 10, and a planarization layer 11 are sequentially formed on the dielectric layer 7 and the plurality of secondary epitaxial structures 5.

[0042] Here, the protective layer 8 may be formed of aluminum oxide. The insulating layer 9 and the planarizing layer 11 may be formed of tetraethyl orthosilicate (TEOS). The gate electrode layer 10 may be made of metallic chromium (Cr).

[0043] In another embodiment of the present invention, as described above, if the material of the mask layer 4 is, for example, aluminum oxide (Al2O3), the protective layer 8 may be omitted. In this case, in the manufacturing step 4, the insulating layer 9, gate electrode layer 10, and planarization layer 11 are sequentially formed on the dielectric layer 7, the plurality of secondary epitaxial structures 5, and the remaining aluminum trioxide layer 4.

[0044] As shown in Figure 1E, in manufacturing step 5, the dielectric layer 7 and a portion of the gate electrode layer 10 in a portion of the secondary epitaxial structure 5 are exposed by etching the planarization layer 11.

[0045] As shown in Figure 1F, in manufacturing step 6, a portion of the secondary epitaxial structure 5 is exposed by etching and removing a portion of the protective layer 8, insulating layer 9, and exposed gate electrode layer 10 of a portion of the secondary epitaxial structure 5.

[0046] In another embodiment of the present invention, if the material of the mask layer 4 is, for example, aluminum oxide (Al2O3), as described above, the protective layer 8 may be omitted. In this case, in the manufacturing step 6, a portion of the secondary epitaxial structure 5 is exposed by etching and removing a portion of the insulating layer 9 and a portion of the exposed gate electrode layer 10 in a portion of the secondary epitaxial structure 5.

[0047] As shown in Figure 1G, in manufacturing step 7, a gate connection electrode layer 12 is formed on the exposed gate electrode layer 10 in the dielectric layer 7.

[0048] Here, the gate connection electrode layer 12 may be composed of a Ni / Au multilayer metal layer.

[0049] As shown in Figure 1H, in manufacturing step 8, an anode 13 is formed facing the exposed secondary epitaxial structure 5 and having a predetermined distance between it and the exposed secondary epitaxial structure 5. In one example, the predetermined distance d AE The size is 1-10 mm.

[0050] In Figure 1H, the anode 13 is shown hanging, but in the actual process, the anode 13 is supported by a support member. For example, when packaging, in order to achieve a facing arrangement between the anode 13 and the secondary epitaxial structure 5, the anode 13 may be formed on the inner wall of the package, facing the members from the substrate 1 to the gate connection electrode layer 12.

[0051] According to yet another embodiment of the present invention, a field emission element manufactured by the above manufacturing method is further provided.

[0052] Based on the above, the field emission elements and their manufacturing methods according to each embodiment of the present invention can provide element performance characterized by low on-voltage and high gain. Since etching is not required when forming the primary epitaxial layer and secondary epitaxial structure, and they are formed directly by epitaxial deposition, the on-chip uniformity of the element is improved, the production efficiency of the element is improved, and the reliability of the element is improved.

[0053] The above describes specific embodiments of the present invention. Other embodiments are within the scope of the appended claims.

[0054] Terms used herein, such as “exemplary,” “example,” etc., mean “used as an example, illustration, or representation,” and do not mean “preferred” or “superior” to other embodiments. For the purpose of providing an understanding of the described technology, specific embodiments include specific details. However, these technologies can be carried out even without these specific details. In some embodiments, known structures and apparatus are shown in block diagram form to avoid difficulty in understanding the concepts of the described embodiments.

[0055] Although preferred embodiments of the present invention have been described in detail above with reference to the drawings, the embodiments of the present invention are not limited to the specific details of the embodiments described above. Various simple modifications can be made to the technical means of the embodiments of the present invention within the scope of the technical idea of ​​the embodiments of the present invention, and all of these simple modifications fall within the scope of protection of the embodiments of the present invention.

[0056] The above description of the contents of this specification is provided so that those skilled in the art can implement or use the contents of this specification. To those skilled in the art, various modifications made to the contents of this specification are obvious and allow the general principles defined herein to be applied to other modifications without departing from the scope of protection of the contents of this specification. Accordingly, the contents of this specification are not limited to the examples and designs described herein, but correspond to the broadest scope that fits the principles and novelty features disclosed herein.

Claims

1. A process of forming a primary epitaxial layer on a substrate, A step of forming a plurality of secondary epitaxial structures in the primary epitaxial layer, wherein there is a gap between adjacent secondary epitaxial structures, The process of forming an emitter electrode layer and a dielectric layer located between the emitter electrode layer and a plurality of secondary epitaxial structures on the primary epitaxial layer, The process involves sequentially forming a protective layer, an insulating layer, a gate electrode layer, and a planarization layer on the dielectric layer and the plurality of secondary epitaxial structures, A step of performing an etching treatment on the planarization layer to expose the dielectric layer and a portion of the gate electrode layer in a portion of the secondary epitaxial structure, A step of exposing a portion of the secondary epitaxial structure by etching and removing a portion of the protective layer, insulating layer, and exposed gate electrode layer in a portion of the secondary epitaxial structure, A step of forming a gate connection electrode layer on the gate electrode layer exposed in the dielectric layer, A method for manufacturing a field emission element, characterized by comprising the step of forming an anode that faces the exposed secondary epitaxial structure and has a predetermined distance between it and the exposed secondary epitaxial structure.

2. The manufacturing method according to claim 1, characterized in that the plurality of secondary epitaxial structures are arranged in an array and are secondary epitaxial bumps exhibiting a frustoconical or truncated square shape.

3. The manufacturing method according to claim 1, characterized in that the plurality of secondary epitaxial structures are arranged sequentially at intervals and are secondary epitaxial protrusions whose length-extending direction is perpendicular to the arrangement direction.

4. The manufacturing method according to claim 1, characterized in that the predetermined distance is 1 to 10 mm.

5. Before forming the emitter electrode layer and the dielectric layer located between the emitter electrode layer and the plurality of secondary epitaxial structures on the primary epitaxial layer, The manufacturing method according to claim 1, further comprising the step of forming a depletion region between the side surface and the depletion layer by forming a depletion layer on the upper surface and side surface of the secondary epitaxial structure.

6. Before forming the primary epitaxial layer on the substrate, The manufacturing method according to claim 1, further comprising the step of forming a buffer layer on a substrate, wherein the primary epitaxial layer is formed on the buffer layer.

7. The step of forming a plurality of secondary epitaxial structures in the primary epitaxial layer is, specifically, The process of forming a mask layer on the primary epitaxial layer, The process involves applying a patterning process to the mask layer to form a plurality of via holes arranged in an array on the mask layer, A step of forming a plurality of secondary epitaxial structures by performing secondary epitaxial on the primary epitaxial layer exposed by each of the via holes, The manufacturing method according to claim 1, further comprising the step of removing the remaining mask layer.

8. The step of forming a plurality of secondary epitaxial structures in the primary epitaxial layer is, specifically, The process of forming a mask layer on the primary epitaxial layer, The process involves applying a patterning process to the mask layer to form a plurality of via holes arranged in an array on the mask layer, A step of forming a plurality of secondary epitaxial structures by performing secondary epitaxial on the primary epitaxial layer exposed by each of the via holes, The manufacturing method according to claim 2, further comprising the step of removing the remaining mask layer.

9. The step of forming a plurality of secondary epitaxial structures in the primary epitaxial layer is, specifically, The process of forming a mask layer on the primary epitaxial layer, The process of forming a plurality of via holes in the mask layer by performing a patterning process on the mask layer, wherein the via holes are arranged sequentially at intervals and the length extension direction is perpendicular to the arrangement direction, A step of forming a plurality of secondary epitaxial structures by performing secondary epitaxial on the primary epitaxial layer exposed by each of the via holes, The manufacturing method according to claim 1, further comprising the step of removing the remaining mask layer.

10. The step of forming a plurality of secondary epitaxial structures in the primary epitaxial layer is, specifically, The process of forming a mask layer on the primary epitaxial layer, The process of forming a plurality of via holes in the mask layer by performing a patterning process on the mask layer, wherein the via holes are arranged sequentially at intervals and the length extension direction is perpendicular to the arrangement direction, A step of forming a plurality of secondary epitaxial structures by performing secondary epitaxial on the primary epitaxial layer exposed by each of the via holes, The manufacturing method according to claim 3, further comprising the step of removing the remaining mask layer.

11. The process involves sequentially forming a stacked primary epitaxial layer and an aluminum oxide layer on a substrate, The process involves forming multiple via holes by applying a patterning treatment to the aluminum oxide layer, A step of forming a plurality of secondary epitaxial structures in the primary epitaxial layer exposed by the via holes, The process of forming an emitter electrode layer and a dielectric layer located between the emitter electrode layer and a plurality of secondary epitaxial structures on the primary epitaxial layer, The process involves sequentially forming an insulating layer, a gate electrode layer, and a planarization layer on the dielectric layer, the plurality of secondary epitaxial structures, and the remaining aluminum oxide layer, A step of performing an etching treatment on the planarization layer to expose the dielectric layer and a portion of the gate electrode layer in a portion of the secondary epitaxial structure, A step of exposing a portion of the secondary epitaxial structure by etching and removing a portion of the insulating layer and the exposed gate electrode layer in a portion of the secondary epitaxial structure, A step of forming a gate connection electrode layer on the gate electrode layer exposed in the dielectric layer, A method for manufacturing a field emission element, characterized by comprising the step of forming an anode that faces the exposed secondary epitaxial structure and has a predetermined distance between it and the exposed secondary epitaxial structure.

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