Signal bridging using unimplemented processor interconnects

Abstract

Signal bridging using an unimplemented processor interconnect includes communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) of a circuit board and the processor interconnect, communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect of the circuit board and a peripheral interface, and communicatively coupling the BSP to the peripheral interface via one or more third signal paths within the apparatus.

Description

Background Art

[0001] In a system capable of supporting multiple processors, some system configurations include an unimplemented processor interface. When a processor interface such as a socket is unimplemented, the application processor is not mounted on the processor interface. As a result, the ability of the system to access peripheral interfaces or other components of the motherboard that should have been coupled to the mounted application processor is reduced.

Brief Description of the Drawings

[0002] [Figure 1] FIG. is a block diagram of an exemplary circuit board for signal bridging using unimplemented processor interconnects according to some embodiments. [Figure 2] FIG. is a flowchart of an exemplary method for signal bridging using unimplemented processor interconnects according to some embodiments. [Figure 3] FIG. is a flowchart of an exemplary method for signal bridging using unimplemented processor interconnects according to some embodiments. [Figure 4] FIG. is a flowchart of an exemplary method for signal bridging using unimplemented processor interconnects according to some embodiments. [Figure 5] FIG. is a flowchart of an exemplary method for signal bridging using unimplemented processor interconnects according to some embodiments. [Figure 6] FIG. is a flowchart of an exemplary method for signal bridging using unimplemented processor interconnects according to some embodiments.

Modes for Carrying Out the Invention

[0003] In some embodiments, a signal bridging method using an unimplemented processor interconnect includes: communicatingly coupling the device to a plurality of first signal paths between a bootstrap processor (BSP) on a circuit board and the processor interconnect; communicatingly coupling the device to a plurality of second signal paths between the processor interconnect on a circuit board and a peripheral interface; and communicatingly coupling the BSP to a peripheral interface via one or more third signal paths within the device.

[0004] In some embodiments, the device includes a printed circuit board, and one or more third signal paths each include a conductive trace. In some embodiments, the device, when mounted on a processor interconnect of the circuit board, communicatively couples a BSP to a peripheral interface. In some embodiments, the device includes one or more other peripheral interfaces, and the method further includes communicatively coupling one or more other peripheral interfaces to the BSP via one or more fourth signal paths in the device. In some embodiments, the device includes one or more built-in peripheral devices, and the method further includes communicatively coupling one or more built-in peripheral device interfaces to the BSP via one or more fourth signal paths in the device. In some embodiments, the method further includes terminating one or more of the first signal paths via one or more signal terminators in the device. In some embodiments, the method further includes communicatively coupling two or more of the first signal paths via one or more loopback connections in the device.

[0005] In some embodiments, a device for signal bridging using an unimplemented processor interconnect carries out the steps of: communicatingly coupling the device to a plurality of first signal paths between a bootstrap processor (BSP) on a circuit board and a processor interconnect; communicatingly coupling the device to a plurality of second signal paths between a processor interconnect on a circuit board and a peripheral interface; and communicatingly coupling the BSP to a peripheral interface via one or more third signal paths within the device.

[0006] In some embodiments, the device includes a printed circuit board, and one or more third signal paths each include a conductive trace. In some embodiments, the device, when mounted on a processor interconnect of the circuit board, communicatively couples the BSP to a peripheral interface. In some embodiments, the device further includes one or more other peripheral interfaces and one or more fourth signal paths that communicatively couple one or more of the other peripheral interfaces to the BSP. In some embodiments, the device further includes one or more built-in peripheral devices and one or more fourth signal paths configured to communicatively couple one or more built-in peripheral devices to the BSP. In some embodiments, the device further includes one or more signal terminators that terminate one or more of the first signal paths. In some embodiments, the device further includes one or more loopback connections configured to couple two or more of the first signal paths.

[0007] In some embodiments, a circuit board for signal bridging using an unimplemented processor interconnect includes a bootstrap processor, a peripheral interface, a processor interconnect, and a device mounted on the processor interconnect, the device performing steps including: communicatingly coupling the device to a plurality of first signal paths between the bootstrap processor (BSP) of the circuit board and the processor interconnect; communicatingly coupling the device to a plurality of second signal paths between the processor interconnect of the circuit board and the peripheral interface; and communicatingly coupling the BSP to the peripheral interface via one or more third signal paths within the device.

[0008] In some embodiments, the device includes a printed circuit board, and one or more third signal paths each include a conductive trace. In some embodiments, the device, when mounted on a processor interconnect of the circuit board, communicatively couples the BSP to a peripheral interface. In some embodiments, the device further includes one or more other peripheral interfaces and one or more fourth signal paths that communicatively couple one or more of the other peripheral interfaces to the BSP. In some embodiments, the device further includes one or more built-in peripheral devices and one or more fourth signal paths configured to communicatively couple one or more built-in peripheral devices to the BSP. In some embodiments, the device further includes one or more signal terminators that terminate one or more of the first signal paths. In some embodiments, the device further includes one or more loopback connections configured to couple two or more of the first signal paths.

[0009] In some multiprocessor systems, the motherboard includes multiple processor interconnects that can accommodate application processors. Examples of such interconnects include processor slots or sockets that form mechanical and electrical connections between the installed application processors and the motherboard. Depending on the system configuration, some processor interconnects may not have installed application processors. Such processor interconnects are considered "uninstalled." For example, a customer might want to include only two application processors on a motherboard capable of supporting up to four, in order to reduce costs.

[0010] If a motherboard includes peripheral interfaces (e.g., input / output (I / O) connections or interfaces for peripheral devices), some motherboards may include direct connections between the peripheral interfaces and the processor interconnect. This allows the mounted peripheral devices to communicate with the mounted application processor. If the processor interconnect coupled to a peripheral interface is not implemented (e.g., without the mounted application processor), the system cannot fully utilize any of the peripheral devices coupled to that interface. For example, the peripheral interface may be unusable, or the peripheral devices may process data at a slower speed than if the application processor were implemented on the peripheral interface.

[0011] Signal bridging using unimplemented processor interconnects addresses performance issues caused by unimplemented processor interconnects. Figure 1 is a block diagram of a non-limiting exemplary circuit board 100 for signal bridging using unimplemented processor interconnects. The exemplary circuit board 100 can be implemented in various computing devices, including servers, network devices, mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, etc. In some embodiments, the circuit board 100 is a motherboard on which the main components of the computing system, including processors, memory, peripheral components, etc., are mounted. In one example, the circuit board 100 includes a printed circuit board (PCB) with conductive traces that facilitate communication between components coupled to the circuit board 100.

[0012] The exemplary circuit board 100 includes a bootstrap processor (BSP). BSP 120 is a processor designated to perform the initial processes for starting up a multiprocessor system. For example, when the multiprocessor system starts up with first received power, BSP 102 loads and executes boot code from a predefined memory address. BSP 102 then executes the boot code, initializes other memory (e.g., Dynamic Random Access Memory, DRAM) and performs other boot operations in addition to initializing the application processor 104. The application processor 104 is a processor that is given the task of execution processes after the initial boot process handled by BSP 102. For example, the application processor 104 may perform operations related to the execution of an operating system, software, and interaction with peripheral devices. Both BSP 102 and the application processor 104 include, as can be understood, single-core processors, multi-core processors, or other processors.

[0013] The circuit board 100 also includes a plurality of processor interconnects 106a, 106b. The processor interconnects 106a, b are components that provide mechanical and electrical connections between mounted processors (e.g., application processors 104) and the circuit board 100. For example, electrical connections are formed between connection points of the application processor 104, such as pins, pads, or bumps, and connection points of the processor interconnects 106a, b, such as conductive pads, surfaces, or pinholes. Mechanical connections are formed between the application processors 104a, b and the circuit board 100 using latches, clips, or other mechanical interlocking mechanisms. The processor interconnect 106b enables the mounting of the application processor 104 onto the circuit board 100. If the processor interconnect 106b allows for the mounting of the processor 104 without requiring soldering, this provides the ability to add and remove the application processor 104 from the circuit board 100 as desired or as mandated by design considerations. In some embodiments, it is understood that processor interconnects 106a,b include interconnects that require processors or devices (described later) to be mounted using soldering. In this exemplary circuit board 100, one or more application processors 104 are mounted on one or more processor interconnects 106a, but no application processors 104 are mounted on processor interconnect 106b. In other words, processor interconnect 106b is unmounted.

[0014] The circuit board 100 also includes one or more peripheral interfaces 108a. The peripheral interfaces 108a are input / output connections, ports, slots, etc., that provide additional functionality for the system including the circuit board 100 by mounting peripheral devices. Such peripheral interfaces 108a enable various system configurations and functions using interchangeable peripheral devices. The peripheral interfaces 108a also enable cabling or interconnection to other circuit boards or other components of the system. For example, the peripheral interfaces 108a include peripheral component interconnect express (PCIe) slots, Serial AT Attachment (SATA) ports, Universal Serial Bus (USB) ports, etc. Exemplary peripheral devices that can be mounted on the peripheral interfaces 108a include graphics processing units (GPUs), network interface cards (NICs), and storage controllers.

[0015] The peripheral interface 108a is communicatively coupled to the processor interconnect 106b using one or more signal paths 110a. The signal paths 110a are conductive material paths that enable signal transmission between the processor interconnect 106b and the peripheral interface 108a. For example, the signal paths 110a include conductive traces of copper or another conductive material within the dielectric material (e.g., polyamide or other dielectric material suitable for PCBs) that constitutes the circuit board 100. In other examples, the signal paths 110a include buses, wiring, or other conductive paths for signals between the peripheral interface 108a and the processor interconnect 106b. When an application processor 104 is mounted on the processor interconnect 106b, the mounted processor 104 can communicate with peripheral devices mounted on the peripheral interface 108a via the signal paths 110a.

[0016] As described above, the processor interconnect 106b is not implemented. For example, a user configuring a system including the circuit board 100 might choose not to purchase a separate application processor 104 to be mounted on the processor interconnect 106b as a cost-saving measure. Because the processor interconnect 106b is not implemented, the application processor 104 cannot interact with the peripheral interfaces 108a and 108b, limiting or eliminating the capabilities of any peripheral device inserted into the peripheral interface 108a.

[0017] Instead, the device 112 is inserted into the processor 106b. In some embodiments, the device 112 includes a printed circuit board made of a dielectric material (e.g., polyamide). The device 112 enables electrical coupling to the circuit board 100 by including connection points to the processor interconnect 106b. Specific types of connection points in the device 112 correspond to the connection mechanisms used by the application processor 104 if the application processor 104 were inserted into the processor interconnect 106b. In other words, the device 112 has a dual electrical connection mechanism between the application processor 104 and the processor interconnect 106b. For example, if the processor interconnect 106b includes holes for the pins of the application processor 104, the device 112 includes the pins as connection points. If the processor interconnect 106b uses conductive pads or bumps to form a connection with the application processor 104, the device 112 includes the appropriate pads or bumps.

[0018] The circuit board 100 also includes a signal path 110b between the processor interconnect 106b and the BSP 102. In some embodiments, the signal path 110b includes conductive traces, buses, wiring, or other conductive paths within the circuit board 100, as can be understood. The signal path 110b is communicatively coupled to the input / output area of ​​the BSP 102, enabling the BSP 102 to provide outputs or receive inputs via the signal path 110b. If an application processor 104 is mounted on the processor interconnect 106b, the mounted application processor 104 can communicate with the BSP 102 via these signal paths 110b. Alternatively, if a device 112 is mounted on the processor interconnect 106b, the connection points of the device 112 form a communicative coupling to the signal path 110a (between the processor interconnect 106b and peripheral interface 108a) and a communicative coupling to the signal path 110b (between the processor interconnect 106b and the BSP 102).

[0019] Device 112 also includes signal paths 110c. For example, if device 112 is a printed circuit board, signal paths 110c include conductive traces (e.g., copper traces) within the PCB. One or more of the signal paths 110c bridge or conductively couple the connection points of device 112 that connect device 112 to the processor interconnect 106b. If device 112 is mounted on the processor interconnect 106b, signal paths 110c function to bridge signal path 110a (between the processor interconnect 106b and peripheral interface 108a) to signal path 110b (between the processor interconnect 106b and BSP 102). Thus, device 112 conductively couples peripheral interface 108a to BSP 102 by bridging signal paths 110a and 110b.

[0020] By coupling peripheral interface 108a to BSP102, peripheral devices mounted on peripheral interface 108a can communicate with BSP102 via device 112. The mounted peripheral devices can then use BSP102 instead of the unimplemented application processor 104, supporting the operation of the peripheral devices. Thus, performance loss caused by the unimplemented processor interconnect 106b is reduced or eliminated.

[0021] In some embodiments, the device 112 consists of passive components. For example, in some embodiments, the device 112 consists of a PCB, a signal path 110c, and a connection point to the processor interconnect 106b. In other embodiments, the device 112 includes active components such as buffers, multiplexers, signal adjusters, and individual logic (e.g., components that provide functions other than physical structure or signal conduction). In some embodiments, the device 112 provides additional functionality beyond bridging the signal path between the BSP 102 and the peripheral interface 108a. For example, in some embodiments, the device 112 itself includes additional peripheral interfaces 108b. For example, the device 112 includes additional PCIe slots, SATA connections, etc., to expand the number of peripheral interfaces 108a available on the circuit board 100, or to interconnect with additional interfaces or devices (e.g., via cabling). Such a peripheral interface 108b is communicably coupled to the processor interconnect 106b via the signal path 110c, thereby forming a signal path from the BSP 102 to the peripheral interface 108b via the signal paths 110b and 110c.

[0022] In some embodiments, device 112 includes an on-board peripheral device 114. The on-board peripheral device 114 is a peripheral device whose functional components are included in device 112 or are components of device 112 without involving the use of the mediation peripheral interfaces 108a, b. For example, device 112 includes one or more on-board GPUs, NICs, storage devices, or other on-board devices that further expand the functions available to circuit board 100 as can be understood. Such an on-board peripheral device 114 forms a signal path from BSP 102 to the on-board peripheral device 114 via signal paths 110b and 110c by being communicably coupled to the processor interconnect 106b via signal path 110c.

[0023] In some embodiments, device 112 includes a terminator 116. The terminator 116 terminates signals from BSP 102. For example, the terminator 116 prevents signal reflections, distortions, or other signal characteristics by matching the characteristic impedance of signal path 110b. For example, assume that BSP 102 provides an output signal to the processor interconnect 106b via signal path 110b. Further, assume that these output signals do not need to be bridged to the peripheral interface 108a or provided to another component. Instead, these signals are conveyed to the terminator 116. In some embodiments, the terminator 116 includes a passive terminator such as a resistor. In other embodiments, the terminator 116 includes an active terminator such as a voltage controller. Such a voltage controller affects the resistance applied to the signal from BSP 102 by controlling the voltage applied to the resistor.

[0024] In some embodiments, device 112 includes a loopback connection 118. The loopback connection 118 is a signal path within device 112 that conductively couples two signal paths 110b. Therefore, an output signal from BSP 102 via the first signal path 110b is received as an input signal by BSP 102 via the second signal path 110b.

[0025] In some embodiments, the use of the terminator 116, the loopback connection 118, and combinations thereof within the apparatus 112 is determined by the BSP 102 or the processor interconnect 106b used in cooperation with the apparatus 112. For example, in the case where a certain output signal is not terminated, a certain model of the BSP 102 may malfunction inaccurately. As another example, in the case where a certain output signal is not looped back as an input signal, a certain model of the BSP 102 may malfunction inaccurately. Therefore, those skilled in the art will understand that the specific configurations of the terminator 116, the loopback connection 118, and combinations thereof will vary according to the design considerations of the corresponding BSP 102 or the processor interconnect 106b.

[0026] The BSP 102 of the circuit board 100 potentially communicates with various peripheral devices (either as peripheral devices mounted on the peripheral interfaces 108a, b or as built-in peripheral devices 114), and in some embodiments, the BSP 102 can be configured to use any one of a plurality of signaling protocols (e.g., SATA, PCIe, Ethernet (registered trademark), etc.) according to the specific devices that communicate with the BSP 102. In some embodiments, configuring the BSP 102 to use a specific signaling protocol includes configuring the BSP 102 via a Unified Extensible Firmware Interface (UEFI) or a Basic Input / Output System (BIOS). For example, a specific UEFI or BIOS configuration results in the device using a specific signaling protocol used by the BSP 102. Upon system boot, the UEFI or BIOS configures the BSP 102 to use a specific signaling protocol. Therefore, the specific signaling protocol used is changed by reconfiguring the UEFI or BIOS.

[0027] In other embodiments, the device 112 includes code or data stored in memory, which is read by the BSP 102. The BSP 102 configures itself to communicate using a specific protocol indicated in the stored code or data. In further embodiments, the specific signaling protocol used by the BSP 102 is determined by a specific configuration of the terminator 116, the loopback connection 118, or a combination thereof. Thus, the specific signaling protocol used by the BSP 102 is changed by reconfiguring the arrangement of the terminator 116, the loopback connection 118, or a combination thereof.

[0028] As described above, the device 112 makes the BSP 102 accessible to peripheral devices in place of the unimplemented application processor 104. This mitigates some or all of the performance and functionality loss associated with the unimplemented processor interconnect 106b. Since the device 112 is made of less expensive materials than the application processor 104 (e.g., printed circuit board vs. complex silicon chip), the functionality is restored at minimal cost compared to implementing another application processor 104. Furthermore, if the device 112 includes additional peripheral interfaces 108b or peripheral devices 114, the device 112 provides additional peripheral devices with functionality that would not have been available if the application processor 104 had been implemented in the processor interconnect 106b.

[0029] Those skilled in the art will understand that the configuration of the circuit board 100 is merely illustrative and that other configurations are possible. For example, although not shown in the illustrative circuit board 100, those skilled in the art will understand that in some embodiments the circuit board 100 includes additional components. Such additional components may include, as can be understood, an additional processor interconnect with an application processor 104 mounted, an unmounted processor interconnect, a processor interconnect with an additional device 112 mounted, or other interconnects. In some embodiments, such additional components may include, as can be understood, an additional peripheral interface 108a, a peripheral device 114, a terminator 116, or other components.

[0030] For further explanation, Figure 2 shows a flowchart illustrating an exemplary method for signal bridging using an unimplemented processor interconnect, which includes coupling a device 112 to a plurality of first signal paths 110b between a bootstrap processor (BSP) 102 on a circuit board 100 and a processor interconnect 106b. In some embodiments, the circuit board 100 includes a printed circuit board (PCB), and the plurality of first signal paths 110b include conductive traces within the circuit board 100. For example, the first signal paths 110b include conductive traces of copper or another conductive material etched or traced in a dielectric material such as polyamide. The conductive traces provide a conductive passage for signal transmission between the BSP 102 and the processor interconnect 106b. In other examples, the first signal paths 110b include buses, wiring or other conductive paths, as can be understood. The processor interconnect 106b includes, for example, a processor socket or processor socket. In some embodiments, the circuit board 100 is the motherboard in a multiprocessor computing system. Therefore, in some embodiments, the processor interconnect 106b is one of several processor interconnects 106a, b. In some embodiments, one or more application processors 104 are mounted on the processor interconnect 106a, but the processor interconnect 106b does not have an application processor 104 mounted on it. In other words, the processor interconnect 106b is unimplemented.

[0031] Communicative coupling of the device 112 to a plurality of first signal paths 110b 202 includes mounting the device 112 on the processor interconnect 106b. Mounting the device 112 on the processor interconnect 106b includes forming mechanical and electrical couplings between the device 112 and the circuit board 100 via the processor interconnect 106b. For example, clips, clamps, or other mechanical interconnects of the processor interconnect 106b mechanically coupling the device 112 to the circuit board 100 prevents the device 112 from detaching from the processor interconnect 106b and maintains the electrical coupling.

[0032] In some embodiments, the apparatus 112 includes a printed circuit board (PCB) for providing a structure for accommodating one or more connection points to the processor interconnect 106b, as well as additional components described in more detail below. The apparatus 112 is electrically coupled to the PCB 100 using one or more connection points. A particular type of connection point in the apparatus 112 corresponds to a connection mechanism used by the application processor 104, if the application processor 104 were inserted into the processor interconnect 106b. In other words, the apparatus 112 has a dual electrical connection mechanism between the application processor 104 and the processor interconnect 106b. For example, if the processor interconnect 106b includes holes for the pins of the application processor 104, the apparatus 112 includes the pins as connection points. If the processor interconnect 106b uses conductive pads or bumps to form a connection with the application processor 104, the apparatus 112 includes appropriate pads or bumps. Therefore, the device 112 is communicably coupled to multiple first signal paths 110b by coupling the connection points of the device 112 to the processor interconnect 106b, in a state in which the processor interconnect 106b is communicably coupled to the first signal path 110b. The signal paths 110b are communicably coupled to the input / output areas of the BSP 102, thereby enabling the BSP 102 to provide output or receive input via the signal paths 110b. In this way, multiple signal paths are formed between the BSP 102 and the device 112.

[0033] Furthermore, the method shown in Figure 2 includes connecting the device to a plurality of second signal paths 110a between the processor interconnect 106b and the peripheral interface 108a of the circuit board 100 in a communicative manner. The peripheral interface 108a is an input / output connection, port, slot, etc., which provides additional functionality to the system including the circuit board 100 by mounting peripheral devices. In one example, the peripheral interface 108a includes a PCIe (Peripheral Component Interconnection Express) slot, a Serial AT Attachment (SATA) port, a Universal Serial Bus (USB) port, etc. Exemplary peripheral devices that may be mounted on the peripheral interface 108a include a graphics processing unit (GPU), a network interface card (NIC), a storage controller, etc.

[0034] The peripheral interface 108a is communicatively coupled to the processor interconnect 106b using one or more second signal paths 110a. The second signal paths 110a are paths of conductive material that enable signal transmission between the processor interconnect 106b and the peripheral interface 108a. For example, the second signal paths 110a include buses, wiring, conductive traces, or other conductive paths for signals between the peripheral interface 108a and the processor interconnect 106b. When an application processor 104 is mounted on the processor interconnect 106b, the mounted processor 104 can communicate with peripheral devices mounted on the peripheral interface 108a via the second signal paths 110a. Device 112 is communicatively coupled to multiple second signal paths 110a by coupling the connection points of device 112 to the processor interconnect 106b in a state in which the processor interconnect 106b is communicatively coupled to the second signal paths 110a. This creates multiple signal paths between the peripheral interface 108a and the device 112.

[0035] Communicative coupling of the device 112 to a plurality of second signal paths 110a 204 includes mounting the device 112 on the processor interconnect 106b by forming a mechanical and electrical coupling between the device 112 and the circuit board 100 via the processor interconnect 106b. Thus, in some embodiments, mounting the device 112 on the processor interconnect 106b functions as communicative coupling of the device 112 to a plurality of first signal paths 110b 202 and communicative coupling of the device 112 to a plurality of second signal paths 110a 204.

[0036] The method in Figure 2 includes coupling the BSP 102 to a peripheral interface 108a in a communicative manner via one or more third signal paths 110c within the device 112. For example, if the device 112 is a printed circuit board, the third signal paths 110c include conductive traces (e.g., copper traces) within the PCB. One or more of the third signal paths 110c bridge or conductively couple the connection points of the device 112 that connect the device 112 to the processor interconnect 106b. If the device 112 is mounted on the processor interconnect 106b, the third signal paths 110c function to bridge the signal path 110a (between the processor interconnect 106b and the peripheral interface 108a) to the signal path 110b (between the processor interconnect 106b and the BSP 102). Therefore, the signal path between the BSP102 and the peripheral interface 108a is formed by bridging the first signal path 110a and the second signal path 110b in the circuit board 100 using the third signal path 110c in the device 112.

[0037] By coupling peripheral interface 108a to BSP102, peripheral devices mounted on peripheral interface 108a can communicate with BSP102 via device 112. The mounted peripheral devices can then use BSP102 instead of the unimplemented application processor 104, supporting the operation of the peripheral devices. Thus, performance loss caused by the unimplemented processor interconnect 106b is reduced or eliminated.

[0038] For further explanation, Figure 3 shows a flowchart illustrating an exemplary method for signal bridging using an unimplemented processor interconnect, which includes: 202 connecting the device 112 to a plurality of first signal paths 110b between the bootstrap processor (BSP) 102 of the circuit board 100 and the processor interconnect 106b; 204 connecting the device to a plurality of second signal paths 110a between the processor interconnect 106b of the circuit board 100 and the peripheral interface 108a; and 206 connecting the BSP 102 to the peripheral interface 108a via one or more third signal paths 110c within the device 112.

[0039] The method in Figure 3 differs from that in Figure 2 in that it includes communicatively coupling one or more other peripheral interfaces 108b to the BSP 102 via one or more fourth signal paths within the device 112. For example, the device 112 includes one or more additional peripheral interfaces 108b, such as additional PCIe slots, SATA connections, etc., to expand the number of peripheral interfaces 108a,b available on the circuit board 100. Such peripheral interfaces 108b are communicatively coupled to the processor interconnect 106b via the fourth signal path. Such a fourth signal path is similar to the third signal path 110c in that the fourth signal path includes conductive traces, wiring, buses, or other conductive paths within the device 112. However, unlike the third signal path 110c which is coupled to the first signal path 110a within the circuit board 100, the fourth signal path is coupled to the peripheral interface on the device 112. The fourth signal path operates from the BSP 102 to the peripheral interface 108b via the first signal path 110b and the processor interconnect 106b. Thus, the device 112 uses the unimplemented processor interconnect 106b to add an additional peripheral interface 108b to the circuit board 100 which is communicatively coupled to the BSP 102.

[0040] For further explanation, Figure 4 shows a flowchart illustrating an exemplary method for signal bridging using an unimplemented processor interconnect, which includes: 202 connecting the device 112 to a plurality of first signal paths 110b between the bootstrap processor (BSP) 102 of the circuit board 100 and the processor interconnect 106b; 204 connecting the device to a plurality of second signal paths 110a between the processor interconnect 106b of the circuit board 100 and the peripheral interface 108a; and 206 connecting the BSP 102 to the peripheral interface 108a via one or more third signal paths 110c within the device 112.

[0041] The method in Figure 4 differs from that in Figure 2 in that it includes communicatively coupling one or more other built-in peripheral devices 114 to the BSP 102 via one or more fourth signal paths within the device 112. The built-in peripheral devices 114 are peripheral devices whose functional components are included in or are components of the device 112 without the use of intermediary peripheral interfaces 108a, b. For example, the device 112 includes one or more built-in GPUs, NICs, storage devices, or other built-in devices that further extend the functionality available to the circuit board 100, as can be understood. Thus, the device 112 adds additional peripheral devices 114 to the circuit board 100 which is communicatively coupled to the BSP 102 using an unimplemented processor interconnect 106b.

[0042] For further explanation, Figure 5 shows a flowchart illustrating an exemplary method for signal bridging using an unimplemented processor interconnect, which includes: 202 coupling the device 112 communicatively to a plurality of first signal paths 110b between the bootstrap processor (BSP) 102 of the circuit board 100 and the processor interconnect 106b; 204 coupling the device communicatively to a plurality of second signal paths 110a between the processor interconnect 106b of the circuit board 100 and the peripheral interface 108a; and 206 coupling the BSP 102 communicatively to the peripheral interface 108a via one or more third signal paths 110c within the device 112.

[0043] The method in Figure 5 differs from that in Figure 2 in that it includes terminating one or more of the first signal paths 110b via one or more signal terminators 116 of the device 112. The terminators 116 terminate the signals from the BSP 102 that are carried to the processor interconnect 106b via the first signal paths 110b. For example, the terminators 116 prevent signal reflection, distortion, or other signal characteristics by matching the characteristic impedance of the first signal paths 110b. For example, suppose the BSP 102 provides output signals to the processor interconnect 106b via the first signal paths 110b. Furthermore, suppose these output signals do not need to be bridged to a peripheral interface 108a or provided to another component. These signals are instead carried to the terminators 116. In some embodiments, the terminators 116 include passive terminators such as resistors. In other embodiments, the terminator 116 includes an active terminator such as a voltage controller. Such a voltage controller affects the resistance applied to the signal from BSP102 by controlling the voltage applied to the resistor.

[0044] For further explanation, Figure 6 shows a flowchart illustrating an exemplary method for signal bridging using an unimplemented processor interconnect, which includes: 202 coupling the device 112 communicatively to a plurality of first signal paths 110b between the bootstrap processor (BSP) 102 of the circuit board 100 and the processor interconnect 106b; 204 coupling the device communicatively to a plurality of second signal paths 110a between the processor interconnect 106b of the circuit board 100 and the peripheral interface 108a; and 206 coupling the BSP 102 communicatively to the peripheral interface 108a via one or more third signal paths 110c within the device 112.

[0045] The method in Figure 6 differs from that in Figure 2 in that it includes communicatively coupling two or more of the first signal paths 110b via one or more loopback connections 118 of the device 112. The loopback connections 118 are signal paths within the device 112 that conductively couple two signal paths 110b. Thus, the output signal from the BSP 102 via the first signal path 110b is received by the BSP 102 as an input signal via the second signal path 110b.

[0046] In some embodiments, the proper functioning of the BSP102 coupled to the device 112 is ensured by using a terminator 116, a loopback connection 118, and a combination thereof within the device 112, as shown in Figure 5. In some embodiments, the specific configuration of the terminator 116, the loopback connection 118, and the BSP102 or processor interconnect 106b used in conjunction with the device 112 is determined by the BSP102 or processor interconnect 106b used. For example, if a certain output signal is not terminated, a certain model of the BSP102 will function incorrectly. As another example, if a certain output signal is not looped back as an input signal, a certain model of the BSP102 will function incorrectly. Therefore, those skilled in the art will understand that the specific configuration of the terminator 116, the loopback connection 118, and a combination thereof will vary depending on the design considerations of the corresponding BSP102 or processor interconnect 106b.

[0047] In some embodiments, the specific signaling protocol used by the BSP102 is determined by a particular configuration of the terminator 116, the loopback connection 118, or a combination thereof. Therefore, the specific signaling protocol used by the BSP102 is modified by reconfiguring the arrangement of the terminator 116, the loopback connection 118, or a combination thereof.

[0048] In light of the above explanation, readers will recognize that the advantages of signal bridging using unimplemented processor interconnects include the following: ● To improve the performance of the computing system by accessing the processing power of the bootstrap processor when the application processor is not implemented in the processor interface. ● To improve the performance of the computing system by enabling the bootstrap processor to be used by peripheral interfaces, by adding devices to an unimplemented processor interface, which is cheaper and simpler for manufacturers compared to application processors. ● To improve the performance of a computing system by expanding the number of peripheral devices or peripheral interfaces on a circuit board using unimplemented processor interfaces.

[0049] The flow diagrams and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flow diagram or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in a block may occur out of the order shown in the figure. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functions involved. It should also be noted that each block in a block diagram and / or flow diagram, and combinations of blocks in a block diagram and / or flow diagram, may be implemented by a dedicated hardware-based system that performs a specified function or action or combines dedicated hardware with computer instructions.

[0050] The advantages and features of this disclosure may be further described by the following statements. 1. A method for signal bridging using an unimplemented processor interconnect, comprising: communicatingly coupling a device to a plurality of first signal paths between a bootstrap processor (BSP) on a circuit board and a processor interconnect; communicatingly coupling the device to a plurality of second signal paths between a processor interconnect on a circuit board and a peripheral interface; and communicatingly coupling the BSP to a peripheral interface via one or more third signal paths within the device. 2. The statement according to claim 1, wherein the device includes a printed circuit board, and one or more third signal paths each include a conductive trace. 3. The method according to either statement 1 or 2, wherein the device is configured to connect the BSP to a peripheral interface in a communicative manner when mounted on a processor interconnect of a circuit board. 4. The method according to any one of statements 1 to 3, wherein the device includes one or more other peripheral interfaces, and the method further comprises coupling one or more other peripheral interfaces to a BSP in a communicative manner via one or more fourth signal paths within the device. 5. The method according to any one of statements 1 to 4, wherein the apparatus includes one or more internal peripheral devices, and the method further includes coupling one or more internal peripheral devices communicably to a BSP via one or more fourth signal paths within the apparatus. 6. The method according to any one of statements 1 to 5, further comprising terminating one or more of the first signal paths via one or more signal terminators of the device. 7. The method according to any one of statements 1 to 6, further comprising connecting two or more of the first signal paths in a communicative manner via one or more loopback connections of the device. 8. A device for signal bridging using an unimplemented processor interconnect, the device being configured to perform steps including: communicatingly coupling the device to a plurality of first signal paths between a bootstrap processor (BSP) on a circuit board and a processor interconnect; communicatingly coupling the device to a plurality of second signal paths between a processor interconnect on a circuit board and a peripheral interface; and communicatingly coupling the BSP to a peripheral interface via one or more third signal paths within the device. 9. The apparatus described in statement 8, wherein the apparatus includes a printed circuit board, and one or more third signal paths each include a conductive trace. 10. A device according to any one of statements 8 to 9, which is configured to connect a BSP to a peripheral interface in a communicative manner when mounted on a processor interconnect of a circuit board. 11. The apparatus according to any one of statements 8 to 10, further comprising one or more other peripheral interfaces and one or more fourth signal paths configured to communicatively couple one or more other peripheral interfaces to the BSP. 12. The apparatus according to any one of statements 8 to 11, further comprising one or more internal peripheral devices and one or more fourth signal paths configured to communicatively couple one or more internal peripheral devices to a BSP. 13. The apparatus described in any of statements 8 to 12, further comprising one or more signal terminators configured to terminate one or more of the first signal paths. 14. The apparatus described in any of statements 8 to 13, further comprising one or more loopback connections configured to combine two or more of the first signal paths. 15. A circuit board for signal bridging using an unimplemented processor interconnect, comprising a bootstrap processor, a peripheral interface, a processor interconnect, and a device mounted on the processor interconnect, wherein the device is configured to communicately couple to a plurality of first signal paths between the bootstrap processor (BSP) and the processor interconnect of the circuit board. The device is to be communicatively coupled to multiple second signal paths between the processor interconnects and peripheral interfaces of the circuit board, A circuit board comprising coupling a BSP to a peripheral interface in a communicative manner via one or more third signal paths within the device. 16. The device includes a printed circuit board, the circuit board described in statement 15, wherein one or more third signal paths each include a conductive trace. 17. A circuit board according to any one of statements 15, 16, further comprising one or more other peripheral interfaces and one or more fourth signal paths configured to communicatively couple one or more other peripheral interfaces to a BSP. 18. A circuit board according to any one of statements 15 to 17, further comprising one or more internal peripheral devices and one or more fourth signal paths configured to communicatively couple the one or more internal peripheral devices to a BSP. 19. A circuit board as described in any of statements 15 to 18, further comprising one or more signal terminators configured to terminate one or more of the first signal paths. 20. A circuit board as described in any of statements 15 to 19, further comprising one or more loopback connections configured to combine two or more of the first signal paths.

[0051] It will be understood from the foregoing that modifications and changes can be made to various embodiments of this disclosure. The statements herein are for illustrative purposes only and should not be construed as restrictive. The scope of this disclosure is limited only by the following claims.

Claims

1. A device for signal bridging using an unimplemented processor interconnect, The device includes a printed circuit board, The aforementioned device is The process involves connecting the device to a plurality of first signal paths between the bootstrap processor (BSP) and the processor interconnect of the circuit board in a communicative manner. The process of connecting the device to a plurality of second signal paths between the processor interconnect and peripheral interface of the circuit board in a communicative manner, A step of coupling the BSP to the peripheral interface in a communicative manner via one or more third signal paths within the device, wherein each of the one or more third signal paths includes a conductive trace, It is configured to perform a process that includes, Device.

2. The device is configured such that, when mounted on the processor interconnect of the circuit board, the BSP is connected to the peripheral interface in a communicative manner. The apparatus according to claim 1.

3. One or more other peripheral interfaces, The system further comprises one or more fourth signal paths configured to connect one or more of the aforementioned other peripheral interfaces to the BSP in a communicative manner. The apparatus according to claim 1.

4. One or more built-in peripheral devices, The system further comprises one or more fourth signal paths configured to communicatively couple one or more of the aforementioned internal peripheral devices to the BSP. The apparatus according to claim 1.

5. The system further comprises one or more signal terminators configured to terminate one or more of the first signal paths. The apparatus according to claim 1.

6. The system further comprises one or more loopback connections configured to combine two or more of the first signal paths, The apparatus according to claim 1.

7. A circuit board for signal bridging using an unimplemented processor interconnect, Bootstrap processor and Peripheral interfaces and Processor interconnects and A device mounted on the aforementioned processor interconnect, comprising a device including a printed circuit board, The aforementioned device is The device is to be communicatively coupled to a plurality of first signal paths between the bootstrap processor (BSP) and the processor interconnect of the circuit board, The device is to be communicatively coupled to a plurality of second signal paths between the processor interconnect and peripheral interface of the circuit board, The BSP is to be communicatively coupled to the peripheral interface via one or more third signal paths within the device, wherein each of the one or more third signal paths includes a conductive trace. It is configured to do, Circuit board.

8. The aforementioned device is One or more other peripheral interfaces, The system comprises one or more fourth signal paths configured to communicatively couple one or more of the aforementioned other peripheral interfaces to the BSP, The circuit board according to claim 7.

9. The aforementioned device is One or more built-in peripheral devices, The system comprises one or more fourth signal paths configured to communicatively connect one or more of the aforementioned internal peripheral devices to the BSP, The circuit board according to claim 7.

10. The device comprises one or more signal terminators configured to terminate one or more of the first signal paths. The circuit board according to claim 7.

11. The device comprises one or more loopback connections configured to combine two or more of the first signal paths. The circuit board according to claim 7.

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