Inverter control device, inverter circuit, motor module, and inverter control method

Abstract

Provided is an inverter control device which controls a three-phase inverter having a two-phase modulation scheme, wherein: the three-phase inverter comprises a first input terminal, a second input terminal, a capacitor, and three serial bodies; the inverter control device comprises a signal generation unit that generates three PWM signals to be input to the three serial bodies, respectively; the PWM signals include at least a negative-phase PWM segment to which a negative-phase PWM signal is applied; the phase of the negative-phase PWM signal is inverse of a positive-phase PWM signal; in the negative-phase PWM segment, the positive-phase PWM signal is applied to two phases among the three phases and the negative-phase PWM signal is applied to one phase among the three phases; and, in the negative-phase PWM segment, the signal generation unit selects, as a negative-phase PWM phase, the phase in which current zero-crossing will next occur when looking in the temporal axis direction.

Description

Technical Field

[0001] The present invention relates to an inverter control device, an inverter circuit, a motor module, and an inverter control method.

Background Art

[0002] An inverter control device for controlling a three-phase inverter is known (for example, Patent Document 1). In the inverter control device described in Patent Document 1, according to the output voltage phase and the output current phase of the inverter, which of the two triangular waves is used for comparison with each phase, and which phase is fixed to the maximum value or the minimum value are switched.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the inverter control device described in Patent Document 1, when the current phase is delayed with respect to the voltage phase, there are 12 operating states in one electrical angle cycle. When the delay of the current phase is large and the power factor is low, different operating states are further applied. Therefore, the control of the switching of the operating states becomes complicated and the control program becomes complex.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide an inverter control device, an inverter circuit, a motor module, and an inverter control method capable of simplifying the control program.

Means for Solving the Problems

[0006] An exemplary inverter control device of the present invention controls a two-phase modulation three-phase inverter. The three-phase inverter comprises a first input terminal, a second input terminal, a capacitor, and three series units. A first voltage is applied to the first input terminal. A second voltage is applied to the second input terminal. The second voltage is lower than the first voltage. The capacitor is connected between the first input terminal and the second input terminal. The three series units consist of two semiconductor switching elements connected in series. The inverter control device comprises a signal generation unit. The signal generation unit generates three PWM signals to be input to each of the three series units. The PWM signals include at least an inverse-phase PWM section to which an inverse-phase PWM signal is applied. The inverse-phase PWM signal is out of phase with respect to the positive-phase PWM signal. The inverse-phase PWM section is a section in which the positive-phase PWM signal is applied to two of the three phases and the inverse-phase PWM signal is applied to one of the three phases. The signal generation unit selects the phase that will next generate a zero current crossover in the time axis direction as the inverse-phase PWM phase within the inverse-phase PWM section.

[0007] An exemplary inverter circuit of the present invention comprises the inverter control device described above, a first input terminal, a second input terminal, a capacitor, and three series components. A first voltage is applied to the first input terminal. A second voltage is applied to the second input terminal. The second voltage is lower than the first voltage. The capacitor is connected between the first input terminal and the second input terminal. The three series components consist of two semiconductor switching elements connected in series.

[0008] An exemplary motor module of the present invention comprises the inverter control device described above, a three-phase inverter, and a three-phase motor. The three-phase inverter is controlled by the inverter control device. The three-phase inverter uses a two-phase modulation scheme. The three-phase motor receives the output of the inverter as input.

[0009] An exemplary inverter control method of the present invention is a method for controlling a two-phase modulation three-phase inverter. The three-phase inverter comprises a first input terminal, a second input terminal, a capacitor, and three series units. A first voltage is applied to the first input terminal. A second voltage is applied to the second input terminal. The second voltage is lower than the first voltage. The capacitor is connected between the first input terminal and the second input terminal. The three series units consist of two semiconductor switching elements connected in series. Three PWM signals are input to each of the three series units. The PWM signals include at least an inverse-phase PWM section in which an inverse-phase PWM signal is applied. The inverse-phase PWM signal is out of phase with respect to the positive-phase PWM signal. The inverse-phase PWM section is a section in which the positive-phase PWM signal is applied to two of the three phases and the inverse-phase PWM signal is applied to one of the three phases. The inverter control method includes a selection step of selecting the phase that will next generate a zero current crossover in the time axis direction within the inverse-phase PWM section as the inverse-phase PWM phase. [Effects of the Invention]

[0010] According to an exemplary version of the present invention, the control program can be simplified. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a block diagram of a motor module according to an embodiment of the present invention. [Figure 2] Figure 2 is a circuit diagram showing the inverter section. [Figure 3] Figure 3 shows the output voltage and output current. [Figure 4] Figure 4 shows the output voltage and output current. [Figure 5A] Figure 5A is a diagram illustrating the charging and discharging currents of a capacitor. [Figure 5B] Figure 5B is a diagram illustrating the charging and discharging currents of a capacitor. [Figure 5C] Figure 5C is a diagram illustrating the charging and discharging currents of a capacitor. [Figure 6A] Figure 6A is a diagram for explaining the charging and discharging current of a capacitor. [Figure 6B] Figure 6B is a diagram for explaining the charging and discharging current of a capacitor. [Figure 6C] Figure 6C is a diagram for explaining the charging and discharging current of a capacitor. [Figure 7A] Figure 7A is a diagram for explaining the charging and discharging current of a capacitor. [Figure 7B] Figure 7B is a diagram for explaining the charging and discharging current of a capacitor. [Figure 7C] Figure 7C is a diagram for explaining the charging and discharging current of a capacitor. [Figure 8] Figure 8 is a diagram showing the output voltage and the output current. [Figure 9] Figure 9 is a diagram showing the output voltage and the output current. [Figure 10] Figure 10 is a diagram showing the output voltage and the output current. [Figure 11] Figure 11 is a diagram showing the output voltage and the output current. [Figure 12] Figure 12 is a diagram showing the output voltage and the output current. [Figure 13A] Figure 13A is a diagram for explaining the charging and discharging current of a capacitor. [Figure 13B] Figure 13B is a diagram for explaining the charging and discharging current of a capacitor. [Figure 13C] Figure 13C is a diagram for explaining the charging and discharging current of a capacitor. [Figure 14A] Figure 14A is a diagram for explaining the charging and discharging current of a capacitor. [Figure 14B] Figure 14B is a diagram for explaining the charging and discharging current of a capacitor. [Figure 14C] Figure 14C is a diagram for explaining the charging and discharging current of a capacitor. [Figure 15] Figure 15 is a diagram showing the output voltage and the output current. [Figure 16]Figure 16 shows the output voltage and output current. [Figure 17] Figure 17 shows the sections to which inverted-phase PWM is applied in each divided section, and the phases to which the inverted-phase PWM signal is applied. [Figure 18] Figure 18 is a flowchart showing the inverter control method. [Modes for carrying out the invention]

[0012] Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts will be denoted by the same reference numerals and will not be repeated in the description.

[0013] A motor module 200 according to an embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a block diagram of the motor module 200 according to an embodiment of the present invention. Figure 2 is a circuit diagram showing the inverter unit 110.

[0014] As shown in Figure 1, the motor module 200 comprises a motor drive circuit 100 and a three-phase motor M. The three-phase motor M is driven by the motor drive circuit 100. The three-phase motor M is, for example, a brushless DC motor. The three-phase motor M has U-phase, V-phase, and W-phase. The motor drive circuit 100 corresponds to an example of an "inverter circuit".

[0015] The motor drive circuit 100 controls the drive of the three-phase motor M using a two-phase modulation method. The motor drive circuit 100 comprises an inverter unit 110 and an inverter control device 12. The inverter unit 110 is an example of a "three-phase inverter".

[0016] The inverter unit 110 is controlled by the inverter control device 12. The inverter unit 110 is a two-phase modulation system and is three-phase. The inverter unit 110 has three output terminals 102. The three output terminals 102 include output terminal 102u, output terminal 102v, and output terminal 102w. The three output terminals 102 output three-phase output voltages and three-phase output currents to the three-phase motor M. Specifically, output terminal 102u outputs the U-phase output voltage Vu and U-phase output current Iu to the three-phase motor M. Output terminal 102v outputs the V-phase output voltage Vv and V-phase output current Iv to the three-phase motor M. Output terminal 102w outputs the W-phase output voltage Vw and W-phase output current Iw to the three-phase motor M. The output of the inverter unit 110 is input to the three-phase motor M.

[0017] As shown in Figure 2, the inverter unit 110 includes a first input terminal P, a second input terminal N, a capacitor C, and three series components 112. The inverter unit 110 further includes a DC voltage source B. Note that the DC voltage source B may be located outside the inverter unit 110.

[0018] A first voltage V1 is applied to the first input terminal P. The first input terminal P is connected to a DC voltage source B.

[0019] A second voltage V2 is applied to the second input terminal N. The second input terminal N is connected to a DC voltage source B. The second voltage V2 is lower than the first voltage V1.

[0020] Capacitor C is connected between the first input terminal P and the second input terminal N.

[0021] Three series units 112 have two semiconductor switching elements connected in series. The semiconductor switching elements are, for example, IGBTs (Insulated Gate Bipolar Transistors). Note that the semiconductor switching elements may also be other transistors, such as field-effect transistors. The three series units 112 include series unit 112u, series unit 112v, and series unit 112w. The three series units 112 are connected in parallel to each other. One end of each of the three series units 112 is connected to the first input terminal P. The other end of each of the three series units 112 is connected to the second input terminal N. A rectifier element D is connected in parallel to each of these semiconductor switching elements, with the first input terminal P side (upper side of the paper) as the cathode and the second input terminal N side (lower side of the paper) as the anode. When field-effect transistors are used as semiconductor switching elements, parasitic diodes may be used as this rectifier element.

[0022] Each of the three series-connected elements 112 has a first semiconductor switching element and a second semiconductor switching element. Specifically, series-connected element 112u has a first semiconductor switching element Up and a second semiconductor switching element Un. Series-connected element 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn. Series-connected element 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.

[0023] The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are connected to the first input terminal P. In other words, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are high-voltage semiconductor switching elements.

[0024] The second semiconductor switching elements Un, Vn, and Wn are connected to the second input terminal N. In other words, the second semiconductor switching elements Un, Vn, and Wn are low-voltage semiconductor switching elements.

[0025] The first semiconductor switching element and the second semiconductor switching element are connected at connection point 114. More specifically, the first semiconductor switching element Up and the second semiconductor switching element Un are connected at connection point 114u. The first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at connection point 114v. The first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at connection point 114w.

[0026] Each of the three series units 112 has a connection point 114 that is connected to one of the three output terminals 102. Specifically, the connection point 114u in series unit 112u is connected to output terminal 102u. The connection point 114v in series unit 112v is connected to output terminal 102v. The connection point 114w in series unit 112w is connected to output terminal 102w.

[0027] PWM signals are input to the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp. The PWM signals are output from the signal generation unit 120. Hereinafter, in this specification, the PWM signal input to the first semiconductor switching element Up may be referred to as the "UpPWM signal". The PWM signal input to the first semiconductor switching element Vp may be referred to as the "VpPWM signal". The PWM signal input to the first semiconductor switching element Wp may be referred to as the "WpPWM signal". The first semiconductor switching elements Up, Vp, and Wp are switched on and off at a predetermined PWM period. For example, the first semiconductor switching elements Up, Vp, and Wp are turned on when the UpPWM signal, VpPWM signal, and WpPWM signal are at a HIGH level, respectively. On the other hand, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned off when the UpPWM signal, VpPWM signal, and WpPWM signal are at a LOW level, respectively.

[0028] PWM signals are input to the second semiconductor switching elements Un, Vn, and Wn. The PWM signals are output from the signal generation unit 120. Hereinafter, in this specification, the PWM signal input to the second semiconductor switching element Un may be referred to as the "UnPWM signal". The PWM signal input to the second semiconductor switching element Vn may be referred to as the "VnPWM signal". The PWM signal input to the second semiconductor switching element Wn may be referred to as the "WnPWM signal". The second semiconductor switching elements Un, Vn, and Wn are switched on and off at a predetermined PWM period. For example, the second semiconductor switching elements Un, Vn, and Wn are turned on when the UnPWM signal, VnPWM signal, and WnPWM signal are at a HIGH level, respectively. On the other hand, the second semiconductor switching elements Un, Vn, and Wn are turned off when the UnPWM signal, VnPWM signal, and WnPWM signal are at a LOW level, respectively.

[0029] As shown in Figure 1, the inverter control device 12 includes a signal generation unit 120. The signal generation unit 120 has a carrier generation unit 122, a voltage command value generation unit 124, and a comparison unit 126. The signal generation unit 120 is a hardware circuit composed of a processor such as a CPU (Central Processing Unit) and an ASIC (Application Specific Integrated Circuit). The processor of the signal generation unit 120 functions as the carrier generation unit 122, the voltage command value generation unit 124, and the comparison unit 126 by executing a computer program stored in a memory device.

[0030] The signal generation unit 120 controls the inverter unit 110. Specifically, the signal generation unit 120 controls the inverter unit 110 by generating and outputting PWM signals. More specifically, the signal generation unit 120 generates three PWM signals to be input to each of the three series units 112.

[0031] The carrier generation unit 122 generates a carrier signal. The carrier signal is, for example, a triangular wave. Alternatively, the carrier signal may be a sawtooth wave.

[0032] The voltage command value generation unit 124 generates a voltage command value. The voltage command value corresponds to the voltage value output from the motor drive circuit 100. That is, the voltage command value generation unit 124 generates voltage values ​​corresponding to the output voltages Vu, Vv, and Vw as voltage command values.

[0033] The comparison unit 126 generates a PWM signal by comparing the carrier signal with the voltage command value.

[0034] The operation of the signal generation unit 120 will be explained with reference to Figure 3. Figure 3 shows the output voltage and output current.

[0035] The upper part of Figure 3 shows the output voltages Vu, Vv, and Vw. In the upper part of Figure 3, the output voltage Vu is shown by a solid line, the output voltage Vv by a dashed line, and the output voltage Vw by a dotted line. The vertical axis of Figure 3 represents the voltage values ​​normalized by the input voltages V1-V2, and the output voltage of each phase takes a value in the range of 0 to 1. This value also represents the duty cycle, which is the ratio of the on time of the first semiconductor switching element of each phase to the PWM period. The horizontal axis of Figure 3 represents the electric rotation angle of the motor, in degrees.

[0036] The lower part of Figure 3 shows the output currents Iu, Iv, and Iw. In the lower part of Figure 3, the output current Iu is shown by a solid line, the output current Iv by a dashed line, and the output current Iw by a dotted line. The horizontal axis of Figure 3 represents the electric rotation angle of the motor, in degrees.

[0037] As shown in Figure 3, the output voltage waveform has a period during which one of the three phases is fixed off. Fixed off indicates that the first semiconductor switching element is continuously off and the second semiconductor switching element is continuously on over the duration of multiple PWM periods. Specifically, the output voltage Vu is fixed off from electrical angle 210 degrees to electrical angle 330 degrees. The output voltage Vv is fixed off from electrical angle 0 degrees to electrical angle 90 degrees and from electrical angle 210 degrees to electrical angle 330 degrees. The output voltage Vw is fixed off from electrical angle 210 degrees to electrical angle 330 degrees. In this specification, a modulation scheme having a period during which one of the three phases of the output voltage waveform is fixed off, as shown in Figure 3, may be described as a fixed-off mode (Min type) modulation scheme.

[0038] As shown in Figure 3, the signal generation unit 120 divides one full rotation of the electrical angle into multiple subdivisions. The signal generation unit 120 divides one full rotation of the electrical angle into multiple subdivisions at each current zero crossing. Specifically, the signal generation unit 120 divides one full rotation of the electrical angle into a first subdivision T1, a second subdivision T2, a third subdivision T3, a fourth subdivision T4, a fifth subdivision T5, and a sixth subdivision T6. In this specification, the first subdivision T1, the second subdivision T2, the third subdivision T3, the fourth subdivision T4, the fifth subdivision T5, and the sixth subdivision T6 may be collectively referred to as subdivision T. Note that the present invention is not limited to the case where the signal generation unit 120 divides into subdivision T precisely at the current zero crossing point. For example, the signal generation unit 120 may divide into subdivision T near the current zero crossing point. The detection of the current zero-crossing point may be done by direct observation using means such as a current sensor, or by prediction from calculations.

[0039] The second division section T2 follows the first division section T1. The third division section T3 follows the second division section T2. ​​The fourth division section T4 follows the third division section T3. The fifth division section T5 follows the fourth division section T4. The sixth division section T6 follows the fifth division section T5. Here, the first division section T1 is from an electrical angle of 20 degrees to an electrical angle of 80 degrees. The second division section T2 is from an electrical angle of 80 degrees to an electrical angle of 140 degrees. The third division section T3 is from an electrical angle of 140 degrees to an electrical angle of 200 degrees. The fourth division section T4 is from an electrical angle of 200 degrees to an electrical angle of 260 degrees. The fifth division section T5 is from an electrical angle of 260 degrees to an electrical angle of 320 degrees. The sixth division section T6 is from an electrical angle of 320 degrees to an electrical angle of 360 degrees.

[0040] The first divided section T1 is the section where only the output current Iv of the V phase is negative. The second divided section T2 is the section where only the output current Iu of the U phase is positive. The third divided section T3 is the section where only the output current Iw of the W phase is negative. The fourth divided section T4 is the section where only the output current Iv of the V phase is positive. The fifth divided section T5 is the section where only the output current Iu of the U phase is negative. The sixth divided section T6 is the section where only the output current Iw of the W phase is positive.

[0041] The PWM signal includes at least an inverted-phase PWM section in which an inverted-phase PWM signal is applied. The inverted-phase PWM signal is in phase with respect to the positive-phase PWM signal. Inverted phase means, for example, when the U-phase and V-phase are switching, that the phase is shifted such that in one PWM cycle, there are states where only the first semiconductor switching element Up is ON and states where only the first semiconductor switching element Vp is ON. More preferably, inverted phase means that in one PWM cycle, there are no states where both the first semiconductor switching element Up and the first semiconductor switching element Vp are ON, and no states where both the first semiconductor switching element Up and the first semiconductor switching element Vp are OFF. For example, inverted phase means that the phase is shifted by 180 degrees. Note that it may be shifted slightly from 180 degrees. The inverted-phase PWM section is a section in which a positive-phase PWM signal is applied to two of the three phases and an inverted-phase PWM signal is applied to one of the three phases.

[0042] The signal generation unit 120 determines for each of the multiple division sections T whether to apply a positive-sequence PWM signal to all three phases in a positive-sequence PWM section or an inverse-sequence PWM section. Here, in the first division section T1, the third division section T3, and the fifth division section T5, the signal generation unit 120 applies the inverse-sequence PWM section. In the second division section T2, the fourth division section T4, and the sixth division section T6, the signal generation unit 120 applies a positive-sequence PWM section to all phases.

[0043] The signal generation unit 120 selects the phase that will next generate a zero current crossover in the time axis direction as the inverse-phase PWM phase within the inverse-phase PWM section. Specifically, in the first division section T1, which is an inverse-phase PWM section, the W phase, which will next generate a zero current crossover in the time axis direction, is selected as the inverse-phase PWM phase. In the third division section T3, which is an inverse-phase PWM section, the U phase, which will next generate a zero current crossover in the time axis direction, is selected as the inverse-phase PWM phase. In the fifth division section T5, which is an inverse-phase PWM section, the V phase, which will next generate a zero current crossover in the time axis direction, is selected as the inverse-phase PWM phase.

[0044] Furthermore, the signal generation unit 120 switches the phase to which the inverse-phase PWM signal is applied in the inverse-phase PWM section to a positive-phase PWM signal at the current zero-crossing point. The phase that generates the current zero-crossing point is the phase in which the absolute value of the current is smallest when viewed in the time axis direction. Note that the present invention is not limited to the signal generation unit 120 completely switching the phase to which the inverse-phase PWM signal is applied in the inverse-phase PWM section to a positive-phase PWM signal at the current zero-crossing point. For example, the signal generation unit 120 may switch the phase to which the inverse-phase PWM signal is applied in the inverse-phase PWM section to a positive-phase PWM signal near the current zero-crossing point. The detection of the current zero-crossing point may be done by direct observation using means such as a current sensor, or it may be determined by prediction from calculations.

[0045] Referring to Figures 4 to 7C, the selection between the positive-sequence PWM section and the negative-sequence PWM section of the signal generation unit 120 will be explained. Figure 4 shows the output voltage and output current. Figures 5A to 7C are diagrams illustrating the charging and discharging current of the capacitor C.

[0046] As shown in Figure 4, the phase of the three-phase output currents (output current Iu, output current Iv, and output current Iw) is delayed by 20 degrees compared to the phase of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw).

[0047] First, we will explain the case where positive-sequence PWM signals are input to the first semiconductor switching element in section (A). Figures 5A to 5C show the section in section (A) where the electrical angle is between 140 degrees and 200 degrees.

[0048] As shown in Figure 5C, a positive-sequence PWM signal is input to the first semiconductor switching element Up. A positive-sequence PWM signal is input to the first semiconductor switching element Vp. A LOW-level signal is input to the first semiconductor switching element Wp.

[0049] In section (1) in Figure 5C, as shown in Figure 5A, the Up gate signal and the Vp gate signal are at a HIGH level. The Wp gate signal is at a LOW level. Therefore, the first semiconductor switching elements Up and Vp are ON, and the first semiconductor switching element Wp is OFF. On the other hand, the second semiconductor switching elements Un and Vn are OFF, and the second semiconductor switching element Wn is ON. Therefore, the discharge current from capacitor C increases.

[0050] In section (2) in Figure 5C, as shown in Figure 5B, the Up gate signal, Vp gate signal, and Wp gate signal are at a LOW level. Therefore, the first semiconductor switching elements Up, Vp, and Wp are off. On the other hand, the second semiconductor switching elements Un, Vn, and Wn are on. Therefore, the charging current to capacitor C increases.

[0051] Thus, when positive-sequence PWM signals are input to the first semiconductor switching element in section (A), the charge and discharge current from capacitor C increases.

[0052] Next, we will explain the case where inverse-phase PWM is applied to section (A). Figures 6A to 6C show the section of section (A) where the electrical angle is between 140 degrees and 200 degrees.

[0053] As shown in Figure 6C, an inverted-phase PWM signal is input to the first semiconductor switching element Up. A positive-phase PWM signal is input to the first semiconductor switching element Vp. A LOW-level signal is input to the first semiconductor switching element Wp.

[0054] In section (1) of Figure 6C, the Vp gate signal is at a HIGH level, as shown in Figure 6A. The Up gate signal and the Wp gate signal are at a LOW level. Therefore, the first semiconductor switching element Vp is ON, and the first semiconductor switching elements Up and Wp are OFF. On the other hand, the second semiconductor switching element Vn is OFF, and the second semiconductor switching elements Un and Wn are ON. Therefore, compared to the case in Figure 5A, the inverter current is distributed, and the charging and discharging current of capacitor C can be suppressed.

[0055] In section (2) in Figure 6C, the Up gate signal is at a HIGH level, as shown in Figure 6B. Also, the Vp gate signal and the Wp gate signal are at a LOW level. Therefore, the first semiconductor switching element Up is ON, and the first semiconductor switching elements Vp and Wp are OFF. On the other hand, the second semiconductor switching element Un is OFF, and the second semiconductor switching elements Vn and Wn are ON. Therefore, compared to the case in Figure 5B, the inverter current is distributed, and the charging and discharging current of capacitor C can be suppressed.

[0056] In this way, applying inverse-phase PWM to section (A) distributes the inverter current and suppresses the charging and discharging current of capacitor C.

[0057] Next, we will explain the case where inverse-phase PWM is applied to section (B). Figures 7A to 7C show the section of section (B) where the electrical angle is between 80 degrees and 140 degrees.

[0058] As shown in Figure 7C, a positive-phase PWM signal is input to the first semiconductor switching element Up. A negative-phase PWM signal is input to the first semiconductor switching element Vp. A low-level signal is input to the first semiconductor switching element Wp.

[0059] In section (1) in Figure 7C, the Up gate signal is at a HIGH level, as shown in Figure 7A. Also, the Vp gate signal and the Wp gate signal are at a LOW level. Therefore, the first semiconductor switching element Up is ON, and the first semiconductor switching elements Vp and Wp are OFF. On the other hand, the second semiconductor switching element Un is OFF, and the second semiconductor switching elements Vn and Wn are ON.

[0060] In section (2) in Figure 7C, the Vp gate signal is at a HIGH level, as shown in Figure 7B. Also, the Up gate signal and the Wp gate signal are at a LOW level. Therefore, the first semiconductor switching element Vp is ON, and the first semiconductor switching elements Up and Wp are OFF. On the other hand, the second semiconductor switching element Vn is OFF, and the second semiconductor switching elements Un and Wn are ON. In this case, a reverse current flows to capacitor C, and the charge / discharge current of capacitor C increases. Therefore, it is preferable to apply a PWM waveform with positive phases as shown in Figure 5C to section (B).

[0061] The selection of the positive-sequence PWM section and the negative-sequence PWM section of the signal generation unit 120 will be explained with reference to Figures 7A to 7C and Figure 8. Figure 8 shows the output voltage and output current.

[0062] As shown in Figure 8, the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 degrees compared to the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw).

[0063] When the phase delay of the three-phase output current exceeds 30 degrees, the interval (A) decreases by the amount exceeding the delay, and interval (C) is created. Interval (C) corresponds to the period from when the off-fixed phase switches until the current crossover occurs.

[0064] In section (C), in the section where the electrical angle is between 90 and 100 degrees, reverse current flow to capacitor C occurs, as explained with reference to Figures 7A and 7C, and the charging and discharging current of capacitor C increases. Therefore, it is preferable to apply a positive-sequence PWM waveform as shown in Figure 5C to section (C).

[0065] Refer to Figure 9 for a further explanation of the reverse-phase application section. Figure 9 shows the output voltage and output current. Figure 9 shows the case where the rotation direction of motor M is CW rotation (clockwise rotation). In other words, the direction of rotation is the direction from 0 degrees to 360 degrees in electrical angle.

[0066] As shown in Figure 9, the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 degrees compared to the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw).

[0067] In the first division section T1, the third division section T3, and the fifth division section T5, an inverse-phase PWM section is applied. As described above with reference to Figure 3, in the inverse-phase PWM section, the phase that will next generate a zero current crossover in the time axis direction is selected as the inverse-phase PWM phase. For example, in the first division section T1, a positive-phase PWM signal is applied to the V and U phases of the three phases, and an inverse-phase PWM signal is applied to the W phase of the three phases. Therefore, as shown in Figure 9, even if a section (C) occurs where the phase of the output current of the three phases is delayed by more than 30 degrees compared to the output voltage of the three phases, and it is preferable not to apply an inverse-phase PWM signal, the W phase, to which the inverse-phase PWM signal was applied before section (C), becomes continuously off in section (C), and a positive-phase PWM signal is automatically applied to the U and V phases that switch in section (C). Therefore, there is no need to distinguish between cases where the current phase delay exceeds 30 degrees and cases where it does not. Thus, the control program can be simplified.

[0068] In the third division section T3, a positive-sequence PWM signal is applied to the V and W phases of the three phases, and an inverted-sequence PWM signal is applied to the U phase of the three phases. Therefore, similar to the first division section T1, a positive-sequence PWM signal is automatically applied to the V and W phases that are switched in section (C).

[0069] In the fifth division section T5, a positive-sequence PWM signal is applied to the U and W phases of the three phases, and an inverted-sequence PWM signal is applied to the V phase of the three phases. Therefore, similar to the first division section T1, a positive-sequence PWM signal is automatically applied to the U and W phases that are switched in section (C).

[0070] Refer to Figure 10 for a further explanation of the reverse-phase application section. Figure 10 shows the output voltage and output current. Figure 10 shows the case when the rotation direction of motor M is CCW rotation (counterclockwise rotation). In other words, the direction of rotation is the direction from the electrical angle 360 ​​degrees toward 0 degrees.

[0071] As shown in Figure 10, the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 degrees compared to the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw).

[0072] In the first division section T1, the third division section T3, and the fifth division section T5, an inverse-phase PWM section is applied. As described above with reference to Figure 3, in the inverse-phase PWM section, the phase that will next generate a zero current crossover in the time axis direction is selected as the inverse-phase PWM phase. For example, in the first division section T1, a positive-phase PWM signal is applied to the V and W phases of the three phases, and an inverse-phase PWM signal is applied to the U phase of the three phases. Therefore, as shown in Figure 10, even if a section (C) occurs where the phase of the output current of the three phases is delayed by more than 30 degrees compared to the output voltage of the three phases, and it is preferable not to apply an inverse-phase PWM signal, the U phase, to which the inverse-phase PWM signal was applied before section (C), becomes continuously off in section (C), and a positive-phase PWM signal is automatically applied to the V and W phases that switch in section (C). Therefore, there is no need to distinguish between cases where the current phase delay exceeds 30 degrees and cases where it does not. Thus, the control program can be simplified.

[0073] In the third division section T3, a positive-sequence PWM signal is applied to the U and W phases of the three phases, and an inverted-sequence PWM signal is applied to the V phase of the three phases. Therefore, similar to the first division section T1, a positive-sequence PWM signal is automatically applied to the U and W phases that are switched in section (C).

[0074] In the fifth division section T5, a positive-sequence PWM signal is applied to the U and V phases of the three phases, and an inverted-sequence PWM signal is applied to the W phase of the three phases. Therefore, similar to the first division section T1, a positive-sequence PWM signal is automatically applied to the U and V phases that are switched in section (C).

[0075] As explained with reference to Figures 9 and 10, the inverter control device 12 can change the phase order of the three-phase output waveforms. Therefore, the degree of control can be increased. When driving a motor, the direction of rotation of the motor can be switched.

[0076] Furthermore, the signal generation unit 120 switches the phase to which the inverse-phase PWM signal is applied in the inverse-phase PWM section to a positive-phase PWM signal at the current zero-crossing point. Therefore, the control program can be simplified.

[0077] Furthermore, the signal generation unit 120 determines for each of the multiple divided sections T whether it is a positive-sequence PWM section or an inverse-sequence PWM section, where a positive-sequence PWM signal is applied to all three phases. Therefore, the control program can be simplified.

[0078] Furthermore, the signal generation unit 120 divides one full rotation of the electrical angle into a segmented section T each time the current crosses zero. Therefore, the control program can be simplified.

[0079] Furthermore, the signal generation unit 120 divides one full rotation of the electrical angle into a first division section T1, a second division section T2, a third division section T3, a fourth division section T4, a fifth division section T5, and a sixth division section T6. Therefore, the control program can be simplified.

[0080] Furthermore, in the first division section T1, the third division section T3, and the fifth division section T5, the signal generation unit 120 applies an inverse-phase PWM section. In the second division section T2, the fourth division section T4, and the sixth division section T6, the signal generation unit 120 applies a positive-phase PWM section to all phases. Therefore, control can be performed for the off-fixed mode (min type).

[0081] Next, with reference to Figure 11, another example of the operation of the signal generation unit 120 will be described. Figure 11 shows the output voltage and output current.

[0082] The upper part of Figure 11 shows the output voltages Vu, Vv, and Vw. In the upper part of Figure 11, the output voltage Vu is shown by a solid line, the output voltage Vv by a dashed line, and the output voltage Vw by a dotted line. The vertical axis of Figure 11 represents the voltage values ​​normalized by the input voltages V1-V2, and the output voltage of each phase takes a value in the range of 0 to 1. This value also represents the duty cycle, which is the ratio of the on time of the first semiconductor switching element of each phase to the PWM period. The horizontal axis of Figure 11 represents the electric rotation angle of the motor, in degrees.

[0083] The lower part of Figure 11 shows the output currents Iu, Iv, and Iw. In the lower part of Figure 11, the output current Iu is shown by a solid line, the output current Iv by a dashed line, and the output current Iw by a dashed line. The horizontal axis of Figure 11 represents the electric rotation angle of the motor, in degrees.

[0084] As shown in Figure 11, the output voltage waveform has a period during which one of the three phases is fixed on. Fixed on indicates that the first semiconductor switching element is continuously on and the second semiconductor switching element is continuously off over the duration of multiple PWM periods. Specifically, the output voltage Vu is fixed on from electrical angle 30 degrees to electrical angle 150 degrees. The output voltage Vv is fixed on from electrical angle 150 degrees to electrical angle 270 degrees. The output voltage Vw is fixed on from electrical angle 0 degrees to electrical angle 30 degrees and from electrical angle 270 degrees to electrical angle 360 ​​degrees. In this specification, a modulation scheme having a period during which one of the three phases of the output voltage waveform is fixed on, as shown in Figure 11, may be described as a fixed-on mode (Max type) modulation scheme.

[0085] In this embodiment, the signal generation unit 120 applies an inverse-phase PWM section in the second division section T2, the fourth division section T4, and the sixth division section T6. In the first division section T1, the third division section T3, and the fifth division section T5, a positive-phase PWM section is applied. Therefore, control can be performed for the ON fixed mode (Max type).

[0086] In this embodiment as well, the signal generation unit 120 selects the phase that will next generate a zero current crossover in the time axis direction as the inverse-phase PWM phase within the inverse-phase PWM section. Specifically, in the second division section T2, which is an inverse-phase PWM section, the V phase that will next generate a zero current crossover in the time axis direction is selected as the inverse-phase PWM phase. In the fourth division section T4, which is an inverse-phase PWM section, the W phase that will next generate a zero current crossover in the time axis direction is selected as the inverse-phase PWM phase. In the sixth division section T6, which is an inverse-phase PWM section, the U phase that will next generate a zero current crossover in the time axis direction is selected as the inverse-phase PWM phase.

[0087] Even in the ON-fixed mode (Max type), there is no need to differentiate between cases where the current phase delay exceeds 30 degrees and cases where it does not. Therefore, the control program can be simplified.

[0088] Next, with reference to Figure 12, another example of the operation of the signal generation unit 120 will be described. Figure 12 shows the output voltage and output current.

[0089] The upper part of Figure 12 shows the output voltages Vu, Vv, and Vw. In the upper part of Figure 12, the output voltage Vu is shown by a solid line, the output voltage Vv by a dashed line, and the output voltage Vw by a dotted line. The vertical axis of Figure 12 represents the voltage values ​​normalized by the input voltages V1-V2, and the output voltage of each phase takes a value in the range of 0 to 1. This value also represents the duty cycle, which is the ratio of the on time of the first semiconductor switching element of each phase to the PWM period. The horizontal axis of Figure 12 represents the electric rotation angle of the motor, in degrees.

[0090] The lower part of Figure 12 shows the output currents Iu, Iv, and Iw. In the lower part of Figure 12, the output current Iu is shown by a solid line, the output current Iv by a dashed line, and the output current Iw by a dashed line. The horizontal axis of Figure 12 represents the electric rotation angle of the motor, in degrees.

[0091] As shown in Figure 12, the output voltage waveform has periods in which one of the three phases is fixed on and periods in which one of the three phases is fixed off. Specifically, the output voltage Vu is fixed on from electrical angle 80 degrees to electrical angle 140 degrees. The output voltage Vu is fixed off from electrical angle 260 degrees to electrical angle 320 degrees. The output voltage Vv is fixed on from electrical angle 200 degrees to electrical angle 260 degrees. The output voltage Vv is fixed off from electrical angle 20 degrees to electrical angle 80 degrees. The output voltage Vw is fixed on from electrical angle 0 degrees to electrical angle 20 degrees and from electrical angle 320 degrees to electrical angle 360 ​​degrees. The output voltage Vw is fixed off from electrical angle 140 degrees to electrical angle 200 degrees. A modulation scheme in which the output voltage waveform has periods in which one of the three phases is fixed on and periods in which one of the three phases is fixed off, as shown in Figure 12, is sometimes described as an on-off fixed mode (Max-Min type) modulation scheme. The on-off fixed mode (Max-Min type) modulation scheme is a modulation scheme that switches between on-fixed mode (Max type) and off-fixed mode (Min type) every 60 degrees.

[0092] The charging and discharging currents of capacitor C will be explained with reference to Figures 12 to 14C. Figures 13A to 14C are diagrams illustrating the charging and discharging currents of capacitor C.

[0093] As shown in Figure 12, the phase of the three-phase output currents (output current Iu, output current Iv, and output current Iw) is delayed by 20 degrees compared to the phase of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw).

[0094] First, let's explain the case where inverse-phase PWM is applied to section (A). Figures 13A to 13C show the section within section (A) where the electrical angle is between 140 degrees and 200 degrees.

[0095] As shown in Figure 13C, a positive-phase PWM signal is input to the first semiconductor switching element Vp. An inverse-phase PWM signal is input to the first semiconductor switching element Up. A low-level signal is input to the first semiconductor switching element Wp.

[0096] In section (1) of Figure 13C, the Vp gate signal is at a HIGH level, as shown in Figure 13A. The Up gate signal and the Wp gate signal are at a LOW level. Therefore, the first semiconductor switching element Vp is ON, and the first semiconductor switching elements Up and Wp are OFF. On the other hand, the second semiconductor switching element Vn is OFF, and the second semiconductor switching elements Un and Wn are ON. Therefore, compared to the case in Figure 5A, the inverter current is distributed, and the charging and discharging current of capacitor C can be suppressed.

[0097] In the case of an on-off fixed mode (Max-Min type) modulation scheme, inverse phase PWM is applied not only to section (A) but also to section (B).

[0098] Next, we will explain the case where inverse-phase PWM is applied to section (B). Figures 14A to 14C show the sections of section (B) where the electrical angle is 0 to 20 degrees and 320 to 360 degrees.

[0099] As shown in Figure 14C, a positive-phase PWM signal is input to the first semiconductor switching element Vp. A negative-phase PWM signal is input to the first semiconductor switching element Up. A low-level signal is input to the first semiconductor switching element Wp.

[0100] In section (1) of Figure 14C, as shown in Figure 14A, the Vp gate signal and the Wp gate signal are at a HIGH level. The Up gate signal is at a LOW level. Therefore, the first semiconductor switching elements Vp and Wp are ON, and the first semiconductor switching element Up is OFF. On the other hand, the second semiconductor switching elements Vn and Wn are OFF, and the second semiconductor switching element Un is ON. In this case, no reverse current flows to capacitor C. Therefore, the charging and discharging current of capacitor C can be suppressed.

[0101] In section (2) of Figure 14C, as shown in Figure 14B, the Up gate signal and the Wp gate signal are at a HIGH level. Also, the Vp gate signal is at a LOW level. Therefore, the first semiconductor switching elements Up and Wp are ON, and the first semiconductor switching element Vp is OFF. On the other hand, the second semiconductor switching elements Un and Wn are OFF, and the second semiconductor switching element Vn is ON. In this case, a reverse current flows to capacitor C, and the charge / discharge current of capacitor C increases. In this case, no reverse current flows to capacitor C. Therefore, the charge / discharge current of capacitor C can be suppressed.

[0102] Refer to Figure 15 to explain the reverse-phase application section. Figure 15 shows the output voltage and output current. Figure 15 shows the case when the rotation direction of motor M is CW rotation (clockwise rotation). In other words, the direction of rotation is the direction from 0 degrees to 360 degrees in electrical angle.

[0103] As shown in Figure 15, the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 degrees compared to the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw).

[0104] In the first division section T1, the second division section T2, the third division section T3, the fourth division section T4, the fifth division section T5, and the sixth division section T6, the signal generation unit 120 applies an inverse phase PWM section. Therefore, control can be performed for an on-off fixed mode (min-max type).

[0105] In the inverse-phase PWM section, the phase that next generates a zero current crossover in the time axis direction is selected as the inverse-phase PWM phase. For example, in the first division section T1, a positive-phase PWM signal is applied to the V and U phases of the three phases, and an inverse-phase PWM signal is applied to the W phase of the three phases. In the second division section T2, a positive-phase PWM signal is applied to the U and W phases of the three phases, and an inverse-phase PWM signal is applied to the V phase of the three phases. In the third division section T3, a positive-phase PWM signal is applied to the V and W phases of the three phases, and an inverse-phase PWM signal is applied to the U phase of the three phases. In the fourth division section T4, a positive-phase PWM signal is applied to the V and U phases of the three phases, and an inverse-phase PWM signal is applied to the W phase of the three phases. In the fifth division section T5, a positive-phase PWM signal is applied to the U and W phases of the three phases, and an inverse-phase PWM signal is applied to the V phase of the three phases. In the sixth division section T6, a positive-sequence PWM signal is applied to the V and W phases of the three phases, and an inverted-sequence PWM signal is applied to the U phase of the three phases.

[0106] The inverter control device 12 includes an on-fixed mode (Max type) and an off-fixed mode (Min type). The signal generation unit 120 switches between the on-fixed mode (Max type) and the off-fixed mode (Min type) each time the current crosses zero. Therefore, the control program can be simplified. In this embodiment, the waveform of the on-fixed mode (Max type) is applied to the divided section T where only one phase has a positive current. Specifically, in this embodiment, the waveform of the on-fixed mode (Max type) is applied to the second divided section T2, the fourth divided section T4, and the sixth divided section T6. On the other hand, the waveform of the off-fixed mode (Min type) is applied to the divided section T where only one phase has a negative current. Specifically, in this embodiment, the waveform of the off-fixed mode (Min type) is applied to the first divided section T1, the third divided section T3, and the fifth divided section T5.

[0107] In this embodiment as well, even if the phase of the three-phase output current lags behind the three-phase output voltage by more than 30 degrees, causing interval (C), the reverse current to capacitor C can be suppressed. Therefore, there is no need to differentiate between cases where the current phase delay exceeds 30 degrees and cases where it does not. Consequently, the control program can be simplified.

[0108] Refer to Figure 16 for further explanation of the reverse-phase application section. Figure 16 shows the output voltage and output current. Figure 16 shows the case when the rotation direction of motor M is CCW rotation (counterclockwise rotation). In other words, the direction of rotation is the direction from the electrical angle 360 ​​degrees toward 0 degrees.

[0109] As shown in Figure 16, the phases of the three-phase output currents (output current Iu, output current Iv, and output current Iw) are delayed by 40 degrees compared to the phases of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw).

[0110] In the first division section T1, the second division section T2, the third division section T3, the fourth division section T4, the fifth division section T5, and the sixth division section T6, the signal generation unit 120 applies an inverted phase PWM section.

[0111] In the inverse-phase PWM section, the phase that next generates a zero current crossover in the time axis direction is selected as the inverse-phase PWM phase. For example, in the first division section T1, a positive-phase PWM signal is applied to the V and W phases of the three phases, and an inverse-phase PWM signal is applied to the U phase of the three phases. In the second division section T2, a positive-phase PWM signal is applied to the U and V phases of the three phases, and an inverse-phase PWM signal is applied to the W phase of the three phases. In the third division section T3, a positive-phase PWM signal is applied to the U and W phases of the three phases, and an inverse-phase PWM signal is applied to the V phase of the three phases. In the fourth division section T4, a positive-phase PWM signal is applied to the V and W phases of the three phases, and an inverse-phase PWM signal is applied to the U phase of the three phases. In the fifth division section T5, a positive-phase PWM signal is applied to the U and V phases of the three phases, and an inverse-phase PWM signal is applied to the W phase of the three phases. In the sixth division section T6, a positive-sequence PWM signal is applied to the U and W phases of the three phases, and an inverted-sequence PWM signal is applied to the V phase of the three phases.

[0112] The inverter control device 12 includes an ON fixed mode (Max type) and an OFF fixed mode (Min type). The signal generation unit 120 switches between the ON fixed mode (Max type) and the OFF fixed mode (Min type) each time the current crosses zero. In this embodiment, the ON fixed mode (Max type) waveform is applied to the divided section T where only one phase has a positive current. Specifically, in this embodiment, the ON fixed mode (Max type) waveform is applied to the second divided section T2, the fourth divided section T4, and the sixth divided section T6. On the other hand, the OFF fixed mode (Min type) waveform is applied to the divided section T where only one phase has a negative current. Specifically, in this embodiment, the OFF fixed mode (Min type) waveform is applied to the first divided section T1, the third divided section T3, and the fifth divided section T5.

[0113] In this embodiment as well, even if the phase of the three-phase output current lags behind the three-phase output voltage by more than 30 degrees, causing interval (C), the reverse current to capacitor C can be suppressed. Therefore, there is no need to differentiate between cases where the current phase delay exceeds 30 degrees and cases where it does not. Consequently, the control program can be simplified.

[0114] The inverse phase application section will be further explained with reference to Figure 17. Figure 17 shows the section to which inverse phase PWM is applied in each divided section, and the phase to which the inverse phase PWM signal is applied.

[0115] As shown in Figure 17, in CW rotation in off-fixed mode (Min type), an inverse PWM signal is applied to the W phase in the first division section T1. An inverse PWM signal is applied to the U phase in the third division section T3. An inverse PWM signal is applied to the V phase in the fifth division section T5.

[0116] In CCW rotation in off-fixed mode (Min type), an inverse-phase PWM signal is applied to the U phase in the first division section T1. An inverse-phase PWM signal is applied to the V phase in the third division section T3. An inverse-phase PWM signal is applied to the W phase in the fifth division section T5.

[0117] In the ON fixed mode (Max type) CW rotation, an inverse phase PWM signal is applied to the V phase in the second division section T2. ​​An inverse phase PWM signal is applied to the W phase in the fourth division section T4. An inverse phase PWM signal is applied to the U phase in the sixth division section T6.

[0118] In CCW rotation in ON fixed mode (Max type), an inverse phase PWM signal is applied to the W phase in the second division section T2. ​​An inverse phase PWM signal is applied to the U phase in the fourth division section T4. An inverse phase PWM signal is applied to the V phase in the sixth division section T6.

[0119] In CW rotation in on-off fixed mode (Min-Max type), an inverted phase PWM signal is applied to the W phase in the first division section T1. An inverted phase PWM signal is applied to the V phase in the second division section T2. ​​An inverted phase PWM signal is applied to the U phase in the third division section T3. An inverted phase PWM signal is applied to the W phase in the fourth division section T4. An inverted phase PWM signal is applied to the V phase in the fifth division section T5. An inverted phase PWM signal is applied to the U phase in the sixth division section T6.

[0120] In CCW rotation in on-off fixed mode (Min-Max type), an inverted phase PWM signal is applied to the U phase in the first division section T1. An inverted phase PWM signal is applied to the W phase in the second division section T2. ​​An inverted phase PWM signal is applied to the V phase in the third division section T3. An inverted phase PWM signal is applied to the U phase in the fourth division section T4. An inverted phase PWM signal is applied to the W phase in the fifth division section T5. An inverted phase PWM signal is applied to the V phase in the sixth division section T6.

[0121] As shown in Figure 17, the signal generation unit 120 applies the inverse-phase PWM signal to different phases depending on the rotation direction within the same divided section T to which the inverse-phase PWM signal is applied. Therefore, control can be performed according to the rotation direction.

[0122] The inverter control method will be explained with reference to Figure 18. Figure 18 is a flowchart of the inverter control method. Inverter control is performed by executing the processes shown in steps S102 to S118 in Figure 18. The inverter control method is a method for controlling a 3-phase inverter with a 2-phase modulation scheme.

[0123] Step S102: The signal generation unit 120 derives the instantaneous angle. Specifically, it derives the position (electrical angle) of the developing rotor. The process then proceeds to step S104.

[0124] Step S104: The signal generation unit 120 derives the instantaneous value of each phase output. Specifically, it calculates the sinusoidal output voltage of each phase based on the instantaneous angle. The process then proceeds to step S106.

[0125] Step S106: The signal generation unit 120 determines which division section T the instantaneous angle is included in. The process proceeds to step S108.

[0126] Step S106: The signal generation unit 120 calculates the modulation offset in a variable format (Min type or Max type) corresponding to the division section T. That is, it derives the Duty cycle.

[0127] Step S108: The signal generation unit 120 selects an inverse-phase PWM application pattern based on the division section T and the rotation direction. More specifically, the signal generation unit 120 selects whether or not to apply inverse-phase PWM and which phase to apply it to. More specifically, in the inverse-phase PWM section, the signal generation unit 120 selects the phase that will next generate a zero current crossover in the time axis direction as the inverse-phase PWM phase. Note that step S108 is an example of a "selection process". The process proceeds to step S112.

[0128] Step S112: The signal generation unit 120 determines whether or not there is a phase to which inverse phase is applied. If the signal generation unit 120 determines that there is no phase to which inverse phase is applied (Step S112: No), the process proceeds to Step S116. If the signal generation unit 120 determines that there is a phase to which inverse phase is applied (Step S112: Yes), the process proceeds to Step S114.

[0129] Step S114: The signal generation unit 120 changes the Duty cycle of the inverse-phase PWM phase to 1-Duty. The process proceeds to step S116.

[0130] Step S116: The signal generation unit 120 sets the duty cycle value in the register. The process proceeds to step S118.

[0131] Step S118: The signal generation unit 120 sets the positive-sequence PWM and negative-sequence PWM. The process ends.

[0132] As explained in Figure 18 above, the inverter control method includes a selection step in which the phase that will next generate a zero current crossover in the time axis direction is selected as the inverse-phase PWM phase within the inverse-phase PWM section. If the phase selected as the inverse-phase PWM phase is fixed on or off, as in section (C) of Figures 9, 10, 15, and 16, the Duty cycle value set in the register can be set to 1 or 0 while the phase remains set as the inverse-phase PWM phase. Therefore, there is no need to differentiate between cases where the current phase delay exceeds 30 degrees and cases where it does not. Consequently, the control program can be simplified.

[0133] Embodiments of the present invention have been described above with reference to the drawings (Figures 1 to 18). However, the present invention is not limited to the above embodiments and can be implemented in various forms without departing from its essence. The drawings schematically show each component for ease of understanding, and the thickness, length, number, etc. of each component shown may differ from the actual dimensions due to the convenience of drawing creation. Furthermore, the material, shape, dimensions, etc. of each component shown in the above embodiments are examples and are not particularly limited, and various modifications are possible without substantially departing from the effects of the present invention. [Industrial applicability]

[0134] The present invention can be suitably used in inverter control devices, inverter circuits, motor modules, and inverter control methods. [Explanation of symbols]

[0135] 12 Inverter control device 100 Motor drive circuit (inverter circuit) 110 Inverter section (3-phase inverter) 112, 112u, 112v, 112w series body 120 Signal generation unit 200 Motor Modules C Capacitor M Motor N Second input terminal P 1st input terminal T-section division T1 First divided section T2 Second Section T3 Third Section T4 4th Section T5 Fifth Section T6 6th Section V1 First voltage V2 Second voltage

Claims

1. An inverter control device for controlling a two-phase modulation three-phase inverter, The aforementioned three-phase inverter is A first input terminal to which a first voltage is applied, A second input terminal to which a second voltage lower than the first voltage is applied, A capacitor connected between the first input terminal and the second input terminal, Three series units, each consisting of two semiconductor switching elements connected in series, Equipped with, The inverter control device includes a signal generation unit that generates three PWM signals to be input to each of the three series units, The PWM signal includes at least an inverted-phase PWM section to which an inverted-phase PWM signal is applied. The aforementioned inverted-phase PWM signal is in opposite phase to the positive-phase PWM signal. The aforementioned inverted-phase PWM section is a section in which the positive-phase PWM signal is applied to two of the three phases and the inverted-phase PWM signal is applied to one of the three phases. The signal generation unit is an inverter control device that, in the inverse-phase PWM section, selects the phase that will next generate a zero current crossover in the time axis direction as the inverse-phase PWM phase.

2. The inverter control device according to claim 1, wherein the phase order of the three-phase output waveforms can be changed.

3. The inverter control device according to claim 1 or 2, wherein the signal generation unit switches the phase to which the inverse-phase PWM signal is applied in the inverse-phase PWM section to the positive-phase PWM signal at the current zero-crossing.

4. The signal generation unit divides one electrical angle into multiple subdivisions, The inverter control device according to any one of claims 1 to 3, wherein the signal generation unit determines for each of the plurality of divided sections whether it is a positive-sequence PWM section in which a positive-sequence PWM signal is applied to all three phases, or a negative-sequence PWM section.

5. The inverter control device according to claim 4, wherein the signal generation unit divides one rotation of the electrical angle into the division section each time the current crosses zero.

6. The signal generation unit, The aforementioned electrical angle is one full rotation, The first divided section and The second division section follows the first division section, The third section following the aforementioned second section, The fourth section following the third section, The fifth division section follows the fourth division section, The sixth division section that follows the fifth division section and The inverter control device according to claim 4 or claim 5, which divides into parts.

7. In the first, third, and fifth division sections, the signal generation unit applies the inverse phase PWM section. In the second, fourth, and sixth division sections, the signal generation unit applies the positive-sequence PWM section to all phases, as described in claim 6.

8. In the second, fourth, and sixth division sections, the signal generation unit applies the inverse phase PWM section. The inverter control device according to claim 6, wherein the positive-sequence PWM section is applied in the first divided section, the third divided section, and the fifth divided section.

9. The inverter control device according to claim 6, wherein in the first, second, third, fourth, fifth, and sixth division sections, the signal generation unit applies the inverse phase PWM section.

10. It has an on-fixed mode and an off-fixed mode. The inverter control device according to claim 9, wherein the signal generation unit switches between the on-fixed mode and the off-fixed mode each time the current crosses zero.

11. The inverter control device according to any one of claims 4 to 10, wherein the signal generation unit applies the inverse phase PWM signal to different phases depending on the rotation direction for the same divided section to which the inverse phase PWM signal is applied.

12. An inverter control device according to any one of claims 1 to 11, A first input terminal to which a first voltage is applied, A second input terminal to which a second voltage lower than the first voltage is applied, A capacitor connected between the first input terminal and the second input terminal, Three series units, each consisting of two semiconductor switching elements connected in series, An inverter circuit equipped with this.

13. An inverter control device according to any one of claims 1 to 11, The inverter control device is controlled by the aforementioned inverter control device, and uses a two-phase modulation method with a three-phase inverter. The three-phase motor to which the output of the inverter is input and A motor module equipped with the following features.

14. An inverter control method for controlling a three-phase inverter using a two-phase modulation scheme, The aforementioned three-phase inverter is A first input terminal to which a first voltage is applied, A second input terminal to which a second voltage lower than the first voltage is applied, A capacitor connected between the first input terminal and the second input terminal, Three series units, each consisting of two semiconductor switching elements connected in series, Equipped with, Three PWM signals are input to each of the three series units. The PWM signal includes at least an inverted-phase PWM section to which an inverted-phase PWM signal is applied. The aforementioned inverted-phase PWM signal is in opposite phase to the positive-phase PWM signal. The aforementioned inverted-phase PWM section is a section in which the positive-phase PWM signal is applied to two of the three phases and the inverted-phase PWM signal is applied to one of the three phases. The inverter control method An inverter control method comprising a selection step of selecting the phase that will next generate a zero current crossover in the time axis direction within the aforementioned inverse-phase PWM section as the inverse-phase PWM phase.

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