Wiring boards and elements

Abstract

To provide a wiring board in which cracking of a grass substrate at a mounting of a functional chip is suppressed, and a functional element using the wiring board.SOLUTION: A wiring board 10 includes: a glass substrate 1; a wiring layer 2 arranged on one surface side of the glass substrate 1; an isolation layer 3 that includes an open part H arranged on a surface side on the wiring layer 2 side of the glass substrate 1; and a connection convex part 4 that is arranged on the open part H of the isolation layer 3 and is electrically connected to the wiring layer 2. The wiring board is provided with a connection convex part group having the two or more connection convex parts 4 including the reference convex part in a region of a radial diameter of 100 μm from a center of a reference convex part when one connection convex part 4 is the reference convex part. A stress buffer layer 5 is arranged between at least one or more connection convex parts 4 of the connection convex part group and the glass substrate 1.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a wiring board and an element using the same.

Background Art

[0002] For example, functional chips such as semiconductor chips, and wiring boards for mounting the above functional chips are used in various electronic devices. The wiring board has, for example, a laminated structure in which a support substrate, a wiring layer, and an insulating layer having an opening are laminated in this order, and connection protrusions electrically connected to the wiring layer are provided in the opening of the insulating layer. The connection protrusion is, for example, a part for electrically connecting to a terminal of a functional chip, and is formed by, for example, solder bumps or the like.

[0003] For example, Patent Document 1 discloses a method for manufacturing a wiring board, which includes a step of measuring the height of the second conductor layer in at least one product area among a plurality of product areas, and when the measured height of the second conductor layer is less than a threshold value, using a first chemical solution for selectively etching the first conductor layer to etch a portion exposed by removing the resin layer in the first conductor layer and a portion located directly below the outer edge side of the second conductor layer, and when the height of the second conductor layer is greater than or equal to the threshold value, using a second chemical solution for etching the first conductor layer and the second conductor layer to etch a portion exposed by removing the resin layer in the first conductor layer and a part of the second conductor layer. The purpose is to reduce defects due to variations in the height of solder bumps.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, with the miniaturization and increased performance of electronic devices, there has been a demand for narrower pitch mounting of functional chips on the aforementioned wiring boards. Furthermore, in order to mount functional chips well on the wiring board, it is necessary to minimize the height variation of the connection protrusions placed on the wiring board. However, in narrow-pitch wiring boards, the distance between adjacent connection protrusions is short, making it difficult to maintain consistent height while suppressing surface contact between adjacent connection protrusions.

[0006] Furthermore, while resin substrates and glass epoxy substrates have conventionally been used as support substrates for wiring boards, these substrates have low heat resistance, which can cause distortion during heat treatment processes when mounting functional chips. Therefore, from the standpoint of heat resistance, the use of glass substrates as support substrates for wiring boards is being considered.

[0007] However, as mentioned above, in wiring boards with a narrow pitch, it is difficult to sufficiently suppress variations in the height of the connection protrusions. Furthermore, when a glass substrate is used as the support substrate, the pressing during the mounting of functional chips can cause localized stress concentration on the wiring board, which may lead to the glass substrate cracking.

[0008] This disclosure is an invention made in view of the above circumstances, and its main purpose is to provide a wiring board in which cracking of the glass substrate is suppressed when a functional chip is mounted, and a functional element using the above wiring board. [Means for solving the problem]

[0009] To achieve the above objective, the present disclosure provides a wiring board comprising a glass substrate, a wiring layer disposed on one side of the glass substrate, an insulating layer disposed on the side of the glass substrate facing the wiring layer and having an opening, and a connecting protrusion disposed at the opening of the insulating layer and electrically connected to the wiring layer, wherein, when one of the connecting protrusions is designated as a reference protrusion, a group of connecting protrusions comprising two or more connecting protrusions including the reference protrusion is provided in a region with a radius of 100 μm from the center of the reference protrusion, and a stress buffer layer is disposed between at least one of the connecting protrusions in the group of connecting protrusions and the glass substrate.

[0010] According to this disclosure, by arranging a stress buffer layer between at least one of the above-mentioned connecting protrusions and the glass substrate, a wiring substrate can be made in which cracking of the glass substrate is suppressed when a functional chip is mounted.

[0011] In the above disclosure, when the surface of the glass substrate on the wiring layer side is used as the reference plane, it is preferable that the height from the top of one of the connecting protrusions on which the stress buffer layer is placed to the reference plane is greater than the height from the top of a connecting protrusion on which the stress buffer layer is placed but is thinner than one of the connecting protrusions to the reference plane, or the height from the top of a connecting protrusion on which the stress buffer layer is not placed to the reference plane. This is because cracking of the glass substrate can be suitably suppressed when mounting the functional chip.

[0012] In the above disclosure, it is preferable that, among the group of connecting protrusions, the connecting protrusion with the highest height from its top to the reference plane, when the surface of the glass substrate on the wiring layer side is used as the reference plane, is positioned to correspond to the outermost terminal of the functional chip to be mounted. This is because it allows for a wiring board that enables better mounting of the functional chip.

[0013] In the above disclosure, among the group of connecting protrusions, when the surface of the glass substrate on the wiring layer side is used as the reference plane, it is preferable that the ratio of the thickness of the stress buffer layer to the height of the connecting protrusion with the highest height from the top of the connecting protrusion on which the stress buffer layer is placed to the reference plane is 10% or more. This is because it is possible to create a stress buffer layer that can easily suppress stress concentration when mounting a functional chip.

[0014] In the above disclosure, it is preferable that the connecting protrusion is a plated layer. This is because it is possible to form a good connecting protrusion on a narrow-pitch wiring substrate.

[0015] In the above disclosure, it is preferable that the stress buffer layer is a resin layer. This is because it can be a stress buffer layer that can easily suppress stress concentration when mounting functional chips.

[0016] This disclosure provides an element having the above-described wiring board and a functional chip electrically connected to the connecting protrusions of the group of connecting protrusions.

[0017] According to this disclosure, by having the above-described wiring board, a device can be made in which a functional chip is well mounted. [Effects of the Invention]

[0018] The wiring board of this disclosure has the effect of suppressing cracking of the glass substrate when mounting functional chips. [Brief explanation of the drawing]

[0019] [Figure 1] These are schematic plan views and schematic cross-sectional views illustrating a wiring board of this disclosure. [Figure 2] This is a schematic plan view illustrating the group of connecting protrusions in this disclosure. [Figure 3] This is a schematic cross-sectional view illustrating a wiring board in this disclosure. [Figure 4] This is a schematic plan view illustrating a functional chip in this disclosure. [Figure 5] It is an explanatory diagram of the wiring board of the present disclosure. [Figure 6] It is an explanatory diagram of the wiring board of the present disclosure. [Figure 7] They are schematic plan view and schematic cross-sectional view exemplifying the element of the present disclosure.

Embodiments for Carrying Out the Invention

[0020] The embodiments of the present disclosure will be described below with reference to the drawings and the like. However, the present disclosure can be implemented in many different modes and is not construed as being limited to the description of the embodiments exemplified below. Also, in order to make the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual form, but this is merely an example and does not limit the interpretation of the present disclosure. Also, in this specification and each drawing, elements that are the same as those described above with respect to the previously presented drawings may be denoted by the same reference numerals, and detailed description may be omitted as appropriate.

[0021] In this specification, when expressing the mode of arranging one member on another member, if simply denoted as "on" or "under", unless otherwise specified, it includes both the case of arranging another member directly above or directly below so as to contact the one member, and the case of arranging another member above or below the one member via yet another member.

[0022] Similarly, in this specification, when denoted as "on the surface side of a certain member", unless otherwise specified, it includes both the case of arranging another member directly so as to contact the surface of the one member, and the case of arranging another member on the surface of the one member via another member.

[0023] The present disclosure is a technology related to a wiring board and an element using the same. As mentioned above, wiring boards require a narrow pitch, such as mounting functional chips at a narrow pitch. Furthermore, in order to mount functional chips well on a wiring board, it is necessary to minimize the height variation of the connection protrusions placed on the wiring board. One way to adjust the height variation of the connection protrusions is to adjust the amount of solder placed in the openings of the insulating layer and adjust the size of the solder bumps. Another example that has been considered is to form the connection protrusions by plating. When forming the connection protrusions by plating, the thickness of the plating layer can be kept constant by performing the plating process until saturation is reached, and thus it is thought that the height variation of the connection protrusions can be suppressed. However, in wiring boards with a narrow pitch, the distance between adjacent connection protrusions is short, making it difficult to align their heights while suppressing surface contact between adjacent connection protrusions using the method described above.

[0024] Furthermore, from the standpoint of heat resistance, the use of a glass substrate as a support substrate for the wiring layer has been considered. However, in wiring boards with narrow pitches, it is difficult to sufficiently suppress variations in the height of the connection protrusions. Moreover, when a glass substrate is used as a support substrate, localized stress concentration occurs in the wiring board due to the pressing during the mounting of functional chips, which may cause the glass substrate to crack.

[0025] To address the above problem, for example, one approach is to reduce the height difference of the connecting protrusions by forming the insulating layer used in the wiring board with an inorganic material layer, but even in this case, it is difficult to sufficiently suppress cracking of the glass substrate. The wiring board and elements using the same described herein are inventions made to solve the above-mentioned problems.

[0026] A. Wiring board The wiring board of this disclosure comprises a glass substrate, a wiring layer disposed on one side of the glass substrate, an insulating layer disposed on the side of the glass substrate facing the wiring layer and having an opening, and a connecting protrusion disposed in the opening of the insulating layer and electrically connected to the wiring layer, wherein when one of the connecting protrusions is designated as a reference protrusion, a group of connecting protrusions is provided in a region with a radius of 100 μm from the center of the reference protrusion, having two or more of the connecting protrusions including the reference protrusion, and a stress buffer layer is disposed between at least one of the connecting protrusions in the group of connecting protrusions and the glass substrate.

[0027] The wiring board of this disclosure will be described with reference to the figures. Figure 1(a) is a schematic plan view showing an example of the wiring board of this disclosure, Figure 1(b) is an enlarged view of part A in Figure 1(a), and Figure 1(c) is a cross-sectional view of line BB in Figure 1(b). The wiring board 10 shown in Figures 1(a) to (c) includes a glass substrate 1, a wiring layer 2 disposed on one side of the glass substrate 1, an insulating layer 3 disposed on the side of the glass substrate 1 facing the wiring layer 2 and having an opening H, and a connecting projection 4 disposed at the opening of the insulating layer 3 and electrically connected to the wiring layer 2.

[0028] Furthermore, as shown in Figures 1(b) and (c), the wiring board 10 includes a group of connecting protrusions 4G, where, when one connecting protrusion 4 is designated as a reference protrusion 4S, two or more connecting protrusions 4, including the reference protrusion 4S, are located in a region with a predetermined radius R1 from the center of the reference protrusion 4S. The radius R1 is, for example, 100 μm. In Figures 1(b) and (c), an example is shown where, when a connecting protrusion 4e is designated as a reference protrusion 4S, the group of connecting protrusions 4G includes nine connecting protrusions 4a to 4i, including the connecting protrusion 4e, in a region with a radius R1 from the center of the connecting protrusion 4e. Also, as shown in Figure 1(c), the wiring board 10 has a stress buffer layer 5 placed between at least one connecting protrusion 4 from the group of connecting protrusions 4G and the glass substrate 1.

[0029] Figure 1(c) shows an example in which the connecting projection 4 consists of two plating layers, plating layer 41 and plating layer 42. It also shows an example in which the wiring board 10 has a first wiring layer 2a arranged on the glass substrate 1 side of the stress buffer layer 5 as the wiring layer 2, and a second wiring layer 2b arranged on the connecting projection side of the stress buffer layer 5. Furthermore, it shows an example in which a conductive layer 6 is provided between the first wiring layer 2a and the second wiring layer 2b.

[0030] According to this disclosure, by arranging a stress buffer layer between at least one of the above-mentioned connecting protrusions and the glass substrate, a wiring substrate can be made in which cracking of the glass substrate is suppressed when a functional chip is mounted.

[0031] The wiring board of this disclosure will be described below for each component.

[0032] 1. Group of connecting protrusions The wiring board of this disclosure includes a group of connection protrusions composed of a plurality of connection protrusions. The group of connection protrusions has two or more connection protrusions, including the reference protrusion, within a region of a predetermined radius from the center of the reference protrusion, when one connection protrusion is designated as a reference protrusion.

[0033] "Center of the reference protrusion (center of the connecting protrusion)" refers to the center or centroid of the figure in the plan view of the reference protrusion (connecting protrusion). For example, if the plan view of the reference protrusion is circular or elliptical, it refers to its center; if the plan view of the reference protrusion is polygonal, it refers to its centroid.

[0034] "When the above-mentioned connecting protrusion is designated as a reference protrusion, there are two or more connecting protrusions, including the reference protrusion, in a region with a predetermined radius from the center of the reference protrusion" means that the connecting protrusions adjacent to the region with a predetermined radius from the center of the reference protrusion are positioned so as to overlap with the region with the predetermined radius in a plan view.

[0035] The case where "when one connecting protrusion is designated as a reference protrusion, there are two or more connecting protrusions, including the reference protrusion, in a region with a predetermined radius from the center of the reference protrusion" specifically refers to the case shown in Figure 1(b), where, when connecting protrusion 4e is designated as a reference protrusion 4S, the connecting protrusions 4a, 4b, 4c, 4d, 4f, 4g, 4h, and 4i adjacent to the region with a predetermined radius R1 from the center of the reference protrusion 4S are positioned so as to overlap the region with the predetermined radius R1 in a plan view. In other words, in a group of connecting protrusions, adjacent connecting terminals are arranged within a predetermined distance from the center of the reference protrusion.

[0036] A reference protrusion is set to define the relative positional relationship between two or more connecting protrusions. In this disclosure, any connecting protrusion on the wiring board can be set as the reference protrusion. For example, Figure 1(b) describes the case where connecting protrusion 4e is set as the reference protrusion 4S, but for example, any of the other connecting protrusions 4a to 4d, 4f to 4h can also be set as the reference protrusion. Which of the multiple connecting protrusions on the wiring board is set as the reference protrusion can be set appropriately, for example, depending on the arrangement of the connecting protrusions.

[0037] In the group of connecting protrusions, there are two or more connecting protrusions, including the reference protrusion, within a region of a predetermined radius from the center of the reference protrusion. The region of a predetermined radius from the center of the reference protrusion is a region with a radius of 100 μm, but it may also be a region with a radius of 100 μm or less, a region with a radius of 80 μm or less, or a region with a radius of 60 μm or less. Furthermore, the region of a predetermined radius from the center of the reference protrusion may also be a region with a radius of 5 μm or more, a region with a radius of 8 μm or more, or a region with a radius of 10 μm or more. By defining the above range as an area with a predetermined radius from the center of the above-mentioned reference protrusion, a wiring board can be made in which functional chips can be arranged at a relatively narrow pitch. Furthermore, because variations in the height of the connecting protrusions are likely to occur, the effect of providing a stress buffer layer can be greatly enhanced.

[0038] In the group of connecting protrusions, the pitch width between adjacent connecting protrusions is not particularly limited as long as it is wide enough to have two or more connecting protrusions, including the reference protrusion, within the region of the predetermined radius described above, and is appropriately selected according to the pitch width of the terminals of the functional chip to be mounted. The pitch width between adjacent connecting protrusions may be larger than, the same as, or smaller than the radius described above. The pitch width may be, for example, 10 μm or more, 20 μm or more, or 30 μm or more. Alternatively, the pitch width may be, for example, 60 μm or less, 50 μm or less, or 40 μm or less. Note that the pitch width between adjacent connecting protrusions refers to the distance from the center of one connecting protrusion to the center of the other connecting protrusion.

[0039] The planar external shape of the group of connecting protrusions is appropriately selected according to the arrangement of terminals on the functional chip to be mounted. Examples of planar external shapes of the group of connecting protrusions include circular (Figure 2(a)), elliptical (not shown), triangular (Figure 2(b)), rectangular (Figure 2(c)), and n-sided (n is a real number of 5 or more, not shown). The planar external shape of the group of connecting protrusions refers to the shape in plan view of the region where the multiple connecting protrusions constituting the group of connecting protrusions are arranged.

[0040] In the group of connecting protrusions, each connecting protrusion is arranged in accordance with the arrangement of terminals on the functional chip to be mounted. In the group of connecting protrusions, each connecting protrusion may be arranged in a predetermined pattern, such as a line, or it may be arranged randomly.

[0041] The number of connection protrusions constituting the group of connection protrusions is at least two. The number of connection protrusions is adjusted as appropriate to match the number of terminals on the functional chip to be mounted.

[0042] The size of the connection protrusions is appropriately selected according to the size of the functional chip to be mounted. Examples of connection protrusion sizes include, but are not limited to, 40 μm or more and 20,000 μm or less. The size of the connection protrusions refers to the longest distance among the planar external shapes of the connection protrusions described above.

[0043] The distance (radius) from the center of the aforementioned reference protrusion and the pitch width can be measured, for example, by observing the wiring board using a scanning electron microscope (SEM).

[0044] In this disclosure, a stress buffer layer is provided between at least one of the connecting protrusions and the glass substrate. In other words, the connecting protrusions constituting the group of connecting protrusions may include not only those with a stress buffer layer on the glass substrate side, but also those without a stress buffer layer. Furthermore, if stress buffer layers are provided on the glass substrate side of multiple connecting protrusions, the thickness of the stress buffer layer provided on each connecting protrusion may be the same or different.

[0045] The wiring board of this disclosure typically has variations in the height of the connecting protrusions within the group of connecting protrusions. Specifically, within the group of connecting protrusions, there is variation in the height from the top of the connecting protrusion to the reference plane, with the surface of the glass substrate on the wiring layer side as the reference plane. In the following description, the "height from the top of the connecting protrusion to the reference plane, with the surface of the glass substrate on the wiring layer side as the reference plane" may be referred to as the "height of the connecting protrusion."

[0046] In this disclosure, when the surface of the glass substrate on the wiring layer side is used as the reference plane, it is preferable that the height from the top of one connecting protrusion on which a stress buffer layer is placed to the reference plane is greater than the height from the top of a connecting protrusion on which a stress buffer layer thinner than that of one connecting protrusion is placed to the reference plane, or the height from the top of a connecting protrusion on which no stress buffer layer is placed to the reference plane.

[0047] The relationship between the heights of the connecting protrusions described above will be explained with reference to a figure. Figure 3 is a schematic cross-sectional view showing another example of a wiring board of this disclosure. In the wiring board 10 shown in Figure 3, the group of connecting protrusions 4G includes a connecting protrusion 4j on which a stress buffer layer 5a is placed, a connecting protrusion 4k on which a stress buffer layer is not placed, and a connecting protrusion 4l placed on a stress buffer layer 5b that is thinner than the stress buffer layer 5a. In such a wiring board 10, it is preferable that the height T1 of the connecting protrusion 4j is higher than the height T2 of the connecting protrusion 4k or the height T3 of the connecting protrusion 4l. When pressing a functional chip onto a wiring board, stress concentration tends to occur in the area where the taller connecting protrusions are located. Therefore, by having the height of the connecting protrusion with the stress buffer layer higher than the height of the connecting protrusion without the stress buffer layer, the stress generated by pressing during mounting can be suitably mitigated, and cracking of the glass substrate can be suitably suppressed. Furthermore, the greater the thickness of the stress buffer layer, the greater its stress buffering effect tends to be. Therefore, by having a thicker stress buffer layer on the height of the connecting protrusion, the stress generated by pressing during mounting can be suitably relieved, and cracking of the glass substrate can be suitably suppressed. In this disclosure, in particular, as shown in Figure 3, it is preferable that the height T1 of the connecting protrusion 4j is higher than the height T2 of the connecting protrusion 4k and the height T3 of the connecting protrusion 4l.

[0048] Furthermore, in this disclosure, it is preferable that, among the group of connecting protrusions, the connecting protrusion with the highest height from its top to the reference plane, when the surface of the glass substrate on the wiring layer side is used as the reference plane, is positioned to correspond to the outermost terminal of the functional chip to be mounted.

[0049] The relationship between the heights of the above-mentioned connecting protrusions will be explained using diagrams. For example, consider the case where a functional chip 20 having a chip body 21 and terminals 22a to 22i is mounted on a group of connecting protrusions 4G having connecting protrusions 4a to 4i as shown in Figure 1(b), and the functional chip 20 having a chip body 21 and terminals 22a to 22i as shown in Figure 4. Assume that the connecting protrusions 4a to 4i are positioned to correspond to terminals 22a to 22i, respectively. For example, as shown in Figure 5(a), if the height of the connecting protrusion 4e corresponding to the central terminal 22e of the functional chip is the highest height T4 among the group of connecting protrusions 4G, then as shown in Figure 5(b), when mounting the functional chip 20, although the connecting protrusion 4e and terminal 22e can be made to make good contact, it may be difficult to make contact between other connecting protrusions (e.g., connecting protrusions 4d, 4f) and other terminals (e.g., terminals 22d, 22f). In this case, for example, it is conceivable to tilt the functional chip to bring other connection protrusions and other terminals into contact. However, it may be difficult to tilt the functional chip in a specific direction starting from the contact point between the connection protrusion 4e located in the center of the functional chip and terminal 22e. Furthermore, there are concerns about low stability, such as looseness in the functional chip during and after mounting.

[0050] In contrast, as shown in Figure 6(a), when the height of the connecting protrusion 4d corresponding to the outermost terminal 22d of the functional chip is the highest height T4 among the connecting protrusion group 4G, as shown in Figure 6(b), when mounting the functional chip 20, the connecting protrusion 4d and the terminal 22d can be made to make good contact. Furthermore, by tilting the functional chip so that, for example, the position of the end of the functional chip on the terminal 22f side is lower than the position of the end of the functional chip on the terminal 22d side, starting from the contact point between the connecting protrusion 4d and the terminal 22d, it becomes possible to make contact between other connecting protrusions (e.g., connecting protrusions 4d, 4f) and other terminals (e.g., terminals 22d, 22f). In addition, since the tilt of the functional chip can be adjusted in a certain direction, the stability of the functional chip during and after mounting can be improved.

[0051] In this disclosure, it is more preferable that the connecting protrusions located at positions corresponding to the outermost terminals of the functional chip to be implemented are connecting protrusions on which a stress buffer layer is provided. This is because stress concentration in the portion where the connecting protrusions are provided can be suppressed.

[0052] Furthermore, the height of the connecting protrusion, i.e., the height from the top of the connecting protrusion to the reference plane when the side of the glass substrate with the wiring layer is used as the reference plane, can be measured, for example, by observing a vertical cross-section using a scanning electron microscope (SEM).

[0053] One method for adjusting the height of the connecting protrusion is to adjust the thickness of a layer located between the glass substrate and the connecting protrusion, such as a stress buffer layer, wiring layer, or insulating layer.

[0054] The height of the connecting protrusion is appropriately selected according to the shape of the wiring board and is not particularly limited, but is preferably 5 μm or more, more preferably 8 μm or more, and preferably 10 μm or more. Furthermore, the height of the connecting protrusion is preferably 200 μm or less, preferably 180 μm or less, and particularly preferably 100 μm or less.

[0055] 2. Connecting protrusion The connecting protrusion is a component positioned at an opening in the insulating layer and electrically connected to the wiring layer. The connecting protrusion is used to electrically connect to the terminal portion of a functional chip.

[0056] The thickness of the connecting protrusion is usually greater than the thickness of the insulating layer on the wiring layer side of the connecting protrusion. The ratio of the thickness of the connecting protrusion to the thickness of the insulating layer is, for example, 1.01 or more, may be 1.5 or more, or may be 2 or more. Furthermore, the above ratio may be, for example, 10 or less, 8 or less, or 5 or less. This is because if the thickness of the connecting protrusion is too thin, it may be difficult to electrically connect it to the functional chip, and if the thickness of the connecting protrusion is too thick, it may be difficult to form the connecting protrusion.

[0057] The "thickness of the connecting projection" refers to the vertical distance from the wiring layer side of the connecting projection to its top, for example, the distance represented by t1 in Figure 1(c). The "thickness of the insulating layer from the wiring layer side of the connecting projection" refers to the vertical distance from the wiring layer side of the connecting projection to the opposite side of the insulating layer, for example, the distance represented by t2 in Figure 1(c). The "thickness of the connecting projection" and the "thickness of the insulating layer from the wiring layer side of the connecting projection" can be measured, for example, by observing the vertical cross-section using a scanning electron microscope (SEM).

[0058] The thickness of the connecting protrusions is appropriately selected according to the application and size of the wiring board and is not particularly limited, but for example, it is preferably 2 μm or more and 15 μm or less. Depending on the number of connecting protrusions arranged on the wiring board, if there are at least 10 connecting protrusions, it is preferable that the average thickness of the 10 connecting protrusions is within the above range.

[0059] The planar external shape of the connecting protrusion is appropriately selected according to the shape of the opening in the insulating layer. Examples of planar external shapes of the connecting protrusion include circular, elliptical, and rectangular shapes. The size of the connecting protrusion may be, for example, 10 μm to 150 μm, or 20 μm to 100 μm. The size of the connecting protrusion is defined as the longest distance among the planar external shapes of the connecting protrusions described above. The size of the connecting protrusion can be measured, for example, by observing the wiring board using a scanning electron microscope (SEM).

[0060] The material of the connecting protrusion is not particularly limited as long as it is conductive, and conductive materials commonly used in wiring can be used, and can be appropriately selected depending on the shape and formation method of the wiring layer.

[0061] Specific examples of materials for the connecting protrusions include metals such as copper, gold, silver, platinum, palladium, rhodium, tin, aluminum, nickel, and chromium, or alloys containing these metals. Solder can also be used as the material for the connecting protrusions. The connecting protrusions may be single-layered or multi-layered, consisting of multiple layers.

[0062] Furthermore, the connecting protrusion may be, for example, a plated layer formed by a plating method, or a vapor-deposited layer formed by a vapor deposition method. Alternatively, the connecting protrusion may be, for example, a solder bump formed using solder. In this disclosure, it is preferable that the connecting protrusion be a plated layer, because it allows for good formation of the connecting protrusion on a narrow-pitch wiring substrate. When the connecting protrusion is a plated layer, it is preferable to have a laminated structure in which a nickel-plated layer and a gold-plated layer are laminated in that order on the wiring layer, for example, because it can suppress the deterioration of the nickel-plated layer. Also, for example, when the wiring layer contains copper, the deterioration of the wiring layer can be suppressed by using a nickel-plated layer.

[0063] The method for forming the connecting protrusions is not particularly limited and includes, for example, PVD methods such as vapor deposition and sputtering, CVD methods, and plating methods.

[0064] 3. Stress buffer layer The stress buffer layer is a component placed between at least one of the connecting protrusions in the group of connecting protrusions and the glass substrate. The stress buffer layer has the function of buffering the stress generated in the wiring board due to the pressing during the mounting of the functional chip, i.e., it has a stress buffering function.

[0065] The material of the stress buffer layer is not particularly limited as long as it can provide stress buffering functionality. It may be an organic material or an inorganic material, but an organic material is preferred. This is because it allows the stress buffer layer to be a soft layer, and thus provides good stress buffering functionality.

[0066] The organic material used in the stress buffer layer is not particularly limited, but examples include polyimide resin, acrylic resin, epoxy resin, polyethylene terephthalate resin, and novolac resin. Including these materials can provide a better buffering effect.

[0067] The thickness of the stress buffer layer is not particularly limited as long as it can provide the desired stress buffering function. Preferably, the ratio of the thickness of the stress buffer layer to the height of the tallest connecting protrusion where the stress buffer layer is placed is a predetermined ratio. Specifically, the ratio of the thickness of the stress buffer layer to the height of the connecting protrusion is preferably 10% or more, more preferably 15% or more, and even more preferably 20% or more. This is because if the ratio is too small, it may be difficult to fully exhibit the stress buffering function. Furthermore, from the viewpoint of thinning and lightening the wiring board, the ratio may be, for example, 80% or less, 70% or less, or 60% or less.

[0068] The "thickness of the stress buffer layer" refers to the vertical distance from one surface of the stress buffer layer to the other surface. The "thickness of the stress buffer layer" can be measured, for example, by observing a vertical cross-section using a scanning electron microscope (SEM). Furthermore, the above ratio can be expressed, for example, as t3 / T1 in Figure 3.

[0069] The specific thickness of the stress buffer layer can be appropriately selected according to the size of the wiring board, etc., and is not particularly limited. The thickness of the stress buffer layer may be, for example, 1 μm or more, 3 μm or more, or 5 μm or more. Alternatively, the thickness of the stress buffer layer may be, for example, 20 μm or less, 15 μm or less, or 10 μm or less. Furthermore, the stress buffer layer described above may consist of multiple layers stacked together. Generally, the number of layers is around two to four. This is because, by keeping the thickness of the stress buffer layer within the above-mentioned range, stress concentration on the wiring substrate during the mounting of the functional chip can be effectively suppressed. Furthermore, if the stress buffer layer has a laminated structure consisting of multiple layers, it is preferable that the sum of the thicknesses of each layer falls within the above-mentioned numerical range.

[0070] The maximum thickness of the stress buffer layer refers to the thickness of the thickest part of the stress buffer layer, for example, the distance represented by t3 in Figure 1(c), where t3 and t4 are shown.

[0071] The stress buffer layer may also serve as an insulating layer. For example, if the wiring layers are arranged on both sides of the stress buffer layer, the stress buffer layer may also serve as an insulating layer to insulate the wiring layers from each other. As a specific example, as shown in Figures 1(c), 5(a), (b) and 6(a), (b), if the wiring layer 2 has a first wiring layer 2a arranged on the side of the stress buffer layer 5 facing the glass substrate 1 and a second wiring layer 2b arranged on the side of the stress buffer layer 5 facing the connecting protrusion, the stress buffer layer 5 may also serve as an insulating layer to insulate the first wiring layer 2a and the second wiring layer 2b.

[0072] Furthermore, when the stress buffer layer also serves as an insulating layer, the stress buffer layer 5 may have openings, as shown in Figure 1(c). In this case, it is preferable that the openings in the stress buffer layer 5 are positioned to overlap with the openings in the insulating layer 3 in a plan view. The shape, size, etc., of the openings provided in the stress buffer layer can be appropriately selected according to the layer configuration of the wiring board.

[0073] Furthermore, the stress buffer layer only needs to be at least one layer between the connecting protrusion and the glass substrate, and may have multiple layers.

[0074] 4.Wiring layer The wiring layer is a component that is placed on one side of the glass substrate. Furthermore, the wiring layer is a component that is electrically connected to the connecting protrusions.

[0075] The wiring layer may be located on one side of the glass substrate, directly on one side of the glass substrate, or via an insulating layer. In addition, in this disclosure, multiple wiring layers may be located via an insulating layer or a stress buffer layer.

[0076] The wiring layer typically has at least linear wiring sections. The line width of the linear wiring sections can be appropriately selected depending on the application of the wiring board and is not particularly limited. The wiring layer may also have pad sections for connecting to connecting protrusions. The pad sections are parts with a wider pattern than the linear wiring sections. The plan view shape of the pad sections can be, for example, circular, elliptical, rectangular, etc. The thickness of the wiring layer, the line width of the linear wiring sections, and the size of the pad sections can be the same as those used in general wiring boards, so a detailed explanation is omitted here.

[0077] The material of the wiring layer is not particularly limited as long as it is a conductive material, and can be the same as the conductive materials used for the wiring layer of a general wiring board. Examples of conductive materials that can be used for the wiring layer include titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), nickel (Ni), chromium (Cr), aluminum (Al), copper (Cu), these metals or compounds, or alloys thereof, as well as conductive oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0078] For forming the wiring layer, general wiring formation methods can be used and are appropriately selected depending on the shape of the wiring layer. Examples of wiring layer formation methods include PVD methods such as vapor deposition and sputtering, CVD methods, and plating methods. Furthermore, electroplating is preferred for the plating method.

[0079] 5. Insulating layer The insulating layer is a component that is positioned on the side of the glass substrate facing the wiring layer and has an opening. The insulating layer is typically positioned to cover the wiring layer.

[0080] The insulating layer typically has an opening that overlaps with a portion of the wiring layer in a plan view. Preferably, the opening in the insulating layer is positioned to overlap with the pad portion of the wiring layer in a plan view. The size of the opening in the insulating layer is appropriately selected according to the shape of the wiring board and is not particularly limited. Note that "size of the opening in the insulating layer" refers to the longest distance within the plan view shape of the opening in the insulating layer.

[0081] The material used for the insulating layer is not particularly limited as long as it has insulating properties, and can be the same as the material used for the insulating layer of a typical wiring board. Alternatively, the material used for the insulating layer can be the material described in section 3, "Stress Buffer Layer," above.

[0082] The thickness of the insulating layer can be appropriately selected depending on the configuration of the wiring layer. Furthermore, in this disclosure, the insulating layer only needs to be at least one layer on at least one side of the glass substrate, and may consist of multiple layers.

[0083] 6. Glass substrate The glass substrate is a component that supports the wiring layer, insulating layer, stress buffer layer, and connecting protrusions. Glass substrates are preferred because they have high flatness and high heat resistance. Examples of glass used for glass substrates include soda-lime glass, alkali-free glass, and quartz glass.

[0084] The thickness of the glass substrate is not particularly limited as long as it can support each of the layers described above, and can be appropriately selected depending on the application of the wiring board. The thickness of the glass substrate is preferably, for example, 10 μm or more and 1000 μm or less, more preferably 100 μm or more and 700 μm or less, and particularly preferably 300 μm or more and 500 μm or less.

[0085] 7. Conductive layer The wiring substrate of this disclosure may further have a conductive layer for connecting multiple wiring layers. The conductive layer is placed within an opening in the insulating layer or within an opening in the stress buffer layer and functions as a via layer. The material used for the conductive layer can be the same as the conductive material described in the section on wiring layers above. The conductive layer is not limited to this, but for example, a conductive paste can be used. The method for forming the conductive layer can be, for example, the same as the method for forming the wiring layer described above. It can also be formed simultaneously with the wiring layer by a plating method.

[0086] 8. Wiring board The wiring board of this disclosure is not particularly limited as long as it has each of the layers described above, and other configurations can be added as needed.

[0087] The wiring board of this disclosure is typically used together with a functional chip and constitutes an element described in section B. Elements below.

[0088] B. This The element of this disclosure comprises the wiring board described above and a functional chip electrically connected to the connecting protrusions of the group of connecting protrusions.

[0089] The elements of this disclosure will be described with reference to the figures. Figure 7(a) is a schematic plan view showing an example of the elements of this disclosure, and Figure 7(b) is an enlarged view showing a part of the cross-section of line BB in Figure 7(a). The element 100 shown in Figure 7 has a wiring board 10 and a functional chip 2 electrically connected to the connection protrusions 4 of the connection protrusion group 4G. The wiring board 10 has been explained in Figures 1(a) to (c), and the functional chip 20 has been explained in Figure 4, so a detailed explanation will be omitted.

[0090] According to this disclosure, by having the above-described wiring board, a device can be made in which a functional chip is well mounted.

[0091] The elements of this disclosure will be described below for each component.

[0092] 1. Wiring board The wiring boards in this disclosure are the same as those described in section "A. Wiring Boards" above, so a further explanation is omitted here.

[0093] 2. Functional chips In this disclosure, a functional chip is a component electrically connected to the connecting protrusions of a group of connecting protrusions. A functional chip has, for example, a chip body and terminals. Specific examples of functional chips include Dynamic Random Access Memory (DRAM), NAND flash memory, SAW devices, power amplifier ICs, display driver ICs, image sensors, acceleration sensors, and angle sensors.

[0094] 3. Elements The elements of this disclosure are not particularly limited as long as they have the wiring board and functional chip described above, and other necessary configurations can be appropriately selected and added.

[0095] The elements of this disclosure are, for example, 、 It can be used in smartphones, displays, cars, etc.

[0096] This disclosure is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of this disclosure and achieves similar effects is included within the technical scope of this disclosure. [Explanation of Symbols]

[0097] 1 ... Glass substrate 2 … Wiring layer 3… Glass substrate 4 ... Connecting protrusion 5. Stress buffer layer 10 ... Wiring board 20… Functional chips 100 ... element

Claims

1. A wiring board comprising a glass substrate, a wiring layer disposed on one side of the glass substrate, an insulating layer disposed on the side of the glass substrate facing the wiring layer and having an opening, and a connecting protrusion disposed at the opening of the insulating layer and electrically connected to the wiring layer, When one of the connecting protrusions is designated as a reference protrusion, a group of connecting protrusions is provided in a region with a radius of 100 μm from the center of the reference protrusion, having two or more connecting protrusions including the reference protrusion. A stress buffer layer is disposed between at least one of the connecting protrusions and the glass substrate. The stress buffer layer has wiring layers arranged on both the side of the stress buffer layer facing the glass substrate and the side facing the glass substrate. A wiring substrate in which, among the group of connecting protrusions, when the surface of the glass substrate on the wiring layer side is used as the reference plane, the height from the top of one of the connecting protrusions on which the stress buffer layer is disposed to the reference plane is greater than the height from the top of a connecting protrusion on which the stress buffer layer is disposed, which is thinner than one of the connecting protrusions, to the reference plane, or the height from the top of a connecting protrusion on which the stress buffer layer is not disposed to the reference plane.

2. A wiring board comprising a glass substrate, a wiring layer disposed on one side of the glass substrate, an insulating layer disposed on the side of the glass substrate facing the wiring layer and having an opening, and a connecting protrusion disposed at the opening of the insulating layer and electrically connected to the wiring layer, When one of the connecting protrusions is designated as a reference protrusion, a group of connecting protrusions is provided in a region with a radius of 100 μm from the center of the reference protrusion, having two or more connecting protrusions including the reference protrusion. A stress buffer layer is disposed between at least one of the connecting protrusions and the glass substrate. The stress buffer layer has wiring layers arranged on both the side of the stress buffer layer facing the glass substrate and the side facing the glass substrate. A wiring board in which, among the group of connecting protrusions, when the surface of the glass substrate on the wiring layer side is used as the reference plane, the connecting protrusion with the highest height from its top to the reference plane is positioned to correspond to the outermost terminal of the functional chip to be mounted.

3. The wiring substrate according to claim 1, wherein, among the group of connecting protrusions, when the surface of the glass substrate on the wiring layer side is used as the reference plane, the connecting protrusion with the highest height from its top to the reference plane is positioned at a location corresponding to the outermost terminal of the functional chip to be mounted.

4. The wiring substrate according to any one of claims 1 to 3, wherein, among the group of connecting protrusions, when the surface of the glass substrate on the wiring layer side is used as the reference plane, the ratio of the thickness of the stress buffer layer to the height of the connecting protrusion with the highest height from the top of the connecting protrusion on which the stress buffer layer is arranged to the reference plane is 10% or more.

5. The wiring board according to any one of claims 1 to 4, wherein the connecting protrusion is a plating layer.

6. The wiring board according to any one of claims 1 to 5, wherein the stress buffer layer is a resin layer.

7. A wiring board according to any one of claims 1 to 6, An element comprising a functional chip electrically connected to the connecting protrusions of the group of connecting protrusions.

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