Cooling system on wafer with means for reducing the effects of electrostatic discharge and / or electromagnetic interference

Abstract

The present disclosure relates to processing systems, and more particularly to integrated circuit (IC) packages designed to reduce the effects of electrostatic discharge and / or electromagnetic interference during integrated circuit manufacturing and / or use. The IC assembly may include a wafer positioned between a cooling system and a heat dissipation structure. The cooling system and the heat dissipation structure include a conductive material at ground potential such that the thermal system acts as an electrical ground. The wafer may be electrically connected to the cooling system and the heat dissipation structure to reduce static charge build-up during the assembly process. The cooling system and the heat dissipation structure may further provide radio frequency (RF) shielding to reduce electromagnetic interference during use of the IC assembly.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 158,201, filed Mar. 8, 2021, entitled "SYSTEM FOR REDUCED EFFECTS OF ELECTROSTATIC DISCHARGE AND / OR ELECTROMAGNETIC INTERFERENCE", the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] The present disclosure relates to a processing system, and more particularly, to an integrated circuit (IC) package capable of reducing the effects of electrostatic discharge and / or electromagnetic interference.

Background Art

[0003] The recent increase in market demand for artificial intelligence and high - power computing has pushed integrated circuit (IC) design towards the use of larger IC package sizes. During the assembly of large IC packages, the IC packages may experience electrostatic discharge (ESD) events. Also, large IC packages may be subject to electromagnetic interference (EMI) during use. EMI can generally degrade the performance of the IC.

Summary of the Invention

[0004] The technological innovations described in the claims each have several aspects, and no single one of them alone bears the desirable attributes. Without limiting the claims, some prominent features of this disclosure are briefly described here.

[0005] In some embodiments, integrated circuit (IC) packages are provided to reduce potential damage and unintended effects associated with electrostatic discharge (ESD) and / or electromagnetic interference (EMI). The IC assembly may include a system-on-wafer (SoW) positioned between a cooling system and a heat dissipation structure. The thermal system may include a cooling system and a heat dissipation structure. The SoW may include multiple IC dies connected to an integrated system via components such as a printed circuit board for data transfer. The thermal system may include a conductive structure configured to ground potential so that the thermal system can function as an electrical ground. The SoW may be electrically connected to a conductive structure, thereby reducing and / or eliminating electrostatic charge buildup during the assembly process. A conductive functional portion extending between the SoW and the conductive structure of the thermal system may provide radio frequency (RF) shielding during use of the IC assembly.

[0006] One aspect of this disclosure is a system-on-wafer (SoW) assembly comprising a SoW, a thermal system, and a plurality of conductive functional parts. The SoW comprises a plurality of integrated circuit (IC) dies and one or more routing layers providing electrical connections for the IC dies. The thermal system includes conductive structures at ground potential. The thermal system is configured to cool the SoW. The plurality of conductive functional parts are located in electrical paths between contacts on the surface of the SoW and the conductive structures of the thermal system.

[0007] Multiple conductive functional parts can ground the SoW to the conductive structure of the thermal system to provide electrostatic discharge protection. Multiple conductive functional parts can ground the SoW to the conductive structure of the thermal system to provide electromagnetic interference shielding. Multiple conductive functional parts may be located around the SoW. Multiple conductive functional parts may be conductive foam. Alternatively, multiple conductive functional parts may include wire bonds or spring-loaded clips.

[0008] The SoW can be an integrated fan-out wafer. The SoW can have a diameter of at least 12 inches. The SoW assembly may include a voltage regulation module located between the IC die and the conductive structure of the thermal system.

[0009] The thermal system may include a heat dissipation structure on the opposite side of the SoW from the conductive structure. An electrical connection may exist between the heat dissipation structure and the conductive structure.

[0010] A SoW assembly can include multiple components in the electrical path between contacts on the surface of the SoW and multiple conductive functional parts. Each of these components may have a conductive material exposed within the electrical path with the conductive functional part.

[0011] Another aspect of the present disclosure is an SoW assembly comprising a SoW, a thermal system, a plurality of components, and a plurality of conductive functional parts. The SoW comprises a plurality of IC dies and one or more routing layers for electrical connections for the IC dies. The thermal system comprises a conductive structure at ground potential. The thermal system is configured to cool the SoW. The plurality of components are located between the SoW and the conductive structure of the thermal system. Each component has a conductive material exposed on the surface opposite the SoW. The plurality of components are electrically connected to the SoW by contacts on the surface of the SoW, and the plurality of conductive functional parts are located in electrical paths between the exposed conductive material of the plurality of components and the conductive structure of the thermal system.

[0012] Multiple components may include a printed circuit board. The SoW assembly may include electrostatic discharge protection circuits on the printed circuit board. Multiple components may be positioned around multiple IC dies.

[0013] Multiple conductive functional parts contribute to electrostatic discharge protection and / or electromagnetic interference shielding. Multiple conductive functional parts may include conductive foam.

[0014] Another aspect of the present disclosure is a method for manufacturing a SoW assembly. The method includes providing a SoW with contacts on the surface of the SoW, wherein the SoW comprises a plurality of IC dies and one or more routing layers for making electrical connections for the IC dies, and the contacts are electrically connected to the IC dies via one or more routing layers; and electrically connecting a conductive structure of a thermal system to the contacts on the surface of the SoW via at least a plurality of conductive functional parts, wherein the conductive structure of the thermal system is at ground potential.

[0015] For the purpose of summarizing this disclosure, specific aspects, advantages, and novel features of the technological innovation are described herein. It should be understood that not all of such advantages can necessarily be achieved according to any particular embodiment. Thus, the technological innovation may be embodied or performed to achieve or optimize one or more advantages or groups of advantages as taught herein, without necessarily achieving other advantages that can be taught or suggested herein. [Brief explanation of the drawing]

[0016] [Figure 1] An example of a processing system is shown.

[0017] [Figure 2] This is a plan view of a system-on-wafer used in a processing system.

[0018] [Figure 3] A cross-sectional view of an example of a processing system is shown.

[0019] [Figure 4] This shows a cross-sectional view of a connector with a conductive functional part used in a processing system.

[0020] [Figure 5A] Examples of conductive functional parts that may be used in processing systems are shown. [Figure 5B] Examples of conductive functional parts that may be used in processing systems are shown. [Figure 5C] An example of a conductive functional unit that can be used in a processing system is shown.

[0021] [Figure 6] It is a schematic diagram of an example of an electrostatic discharge protection circuit.

[0022] Throughout the drawings, reference numerals are reused to indicate the correspondence between the elements being referenced. The drawings are provided to illustrate examples of the embodiments described in this specification and are not intended to limit the scope of the present disclosure.

Mode for Carrying Out the Invention

[0023] The following description of specific embodiments presents various descriptions of specific embodiments. However, the technological innovations described in this specification can be embodied in many different ways, for example, as defined and encompassed by the claims. In this description, reference is made to the drawings in which like reference numerals can indicate the same or functionally similar elements. It can be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it can be understood that a particular embodiment can include more elements than those shown in the drawings and / or a subset of the elements shown in the drawings. Additionally, some embodiments can incorporate any suitable combination of features from two or more of the drawings.

[0024] As mentioned earlier, the recent increase in market demand for high-power computing is driving integrated circuit (IC) design toward the use of larger IC package sizes. During the assembly of large IC packages, static charge can accumulate on the bodies of assembly machines and / or manufacturing plant technicians. Under such charged conditions, proximity interaction or direct contact with the IC package can cause static charge transfer to the IC package via an event known as electrostatic discharge (ESD). The IC chip contained within the IC package can be damaged by the ESD event. Without ESD protection, the yield of the IC assembly may be reduced due to ESD damage. Furthermore, during the use of the assembled IC package, electromagnetic interference (EMI) can interfere with the proper functioning of the IC. Without EMI protection, the performance of the IC assembly may be reduced due to EMI. Therefore, IC package forms incorporating ESD protection and / or EMI protection are required.

[0025] Generally, integrated circuit (IC) packages have a fairly small form factor. In such IC packages, physical space for ESD protection devices and / or EMI protection structures may be limited. Manufacturing machines that come into contact with IC packages can be configured to meet the stringent ESD specifications of such IC packages. Since IC packages are assembled by manufacturing machines, factory workers do not need to touch the IC package components in some cases. Some ESD / EMI protection functions are incorporated within individual chips during the wafer manufacturing process, but ESD / EMI protection functions are not usually built at the system level in a system-on-wafer configuration. Only after the IC package is mounted on a printed circuit board (PCB) motherboard does the IC package generally have system-level protection by ESD and / or EMI protection mechanisms, as well as components on the PCB motherboard.

[0026] However, for IC packages with a large form factor, the assembly and system installation process may involve manual handling. Manual handling carries the risk of ESD damage to the IC package because static charge can accumulate on the human body, and close-range interaction and / or direct contact with the IC package can cause discharge to the IC package. Due to the sensitive nature and morphology of IC components, even relatively small electrostatic discharges can damage the entire component. Furthermore, IC packages with a large form factor may not be mounted on a PCB motherboard, in which case the ESD and / or EMI protection features from the PCB motherboard cannot be utilized.

[0027] Preferably, in some embodiments, a processing system with integrated ESD protection can reduce the risk of ESD damage during manual processing. The processing system may be a system-on-wafer (SoW) assembly in which a SoW is positioned between two parts of a thermal system. In such an assembly, the thermal interface material positioned between the SoW and the thermal system may include a high thermal conductivity material. If the thermal interface material has relatively low conductivity, static charge buildup may occur during manufacturing. The processing systems of embodiments disclosed herein ground the SoW to protect the IC devices on the SoW from ESD damage. The thermal system of the processing system may include a conductive material at ground potential so that the thermal system acts as an electrical ground. The SoW may be electrically connected to the thermal system. Thus, any accumulated charge on the SoW can be discharged from the system. Thus, the processing system can reduce the risk of ESD damage during manual processing.

[0028] The processing system can also allow for greater flexibility in the selection of manufacturing machinery. In contrast, IC package assemblies with smaller form factors can include stringent ESD standards applicable to manufacturing machinery where the IC package generally does not have system-level ESD protection. Furthermore, individual IC dies may have internal ESD protection that may not provide sufficient ESD protection to the system-level package assembly for the SoW. The processing system in the embodiments disclosed herein can have integrated ESD protection, allowing for the use of a wider range of machinery during system assembly. The presence of ESD protection in the processing system can also enable more diverse uses of the processing system. Since the processing system may not need to utilize a connection to a motherboard for ESD protection, the processing system may be placed in configurations that were previously impractical.

[0029] Preferably, the processing systems of the embodiments disclosed herein can reduce the risk of unreliable function and / or hardware damage caused by EMI during the operation of the processing system. EMI effects can be reduced by radio frequency (RF) shielding. Two parts of the thermal system of the processing system may be fixed to each other via a conductive frame. The conductive thermal system and the conductive frame can form a shielding cage to reduce EMI effects. Thus, the processing system can reduce the risk of damage caused by one or more ESD events and undesirable EMI effects.

[0030] The IC package configuration can be used to improve any suitable large IC packaging system that can benefit from ESD protection and / or EMI shielding, such as a system having multiple silicon chips assembled directly on a build-up substrate. While embodiments disclosed herein may be described with reference to ESD protection, any suitable principles and benefits disclosed herein may be applied to provide electrical overstress protection. Electrical overstress protection includes ESD protection, overvoltage protection, and the like. Exemplary processing system configuration

[0031] The drawings are referenced here, and the same reference numbers throughout refer to the same parts. Unless otherwise indicated, the drawings are schematic and not necessarily drawn to scale.

[0032] Figure 1 shows a processing system 5 according to an aspect of this disclosure. Features of this disclosure can be implemented in processing system 5 and / or any other suitable processing system (e.g., processing system 10). Processing system 5 can have a high computation density and can dissipate the heat generated by processing system 5. Processing system 5 can perform trillions of operations per second in a particular application. Processing system 5 can be used in and / or specifically configured for high-performance computing and / or computationally intensive applications such as neural network training and / or processing, machine learning, and artificial intelligence. Processing system 5 can implement redundancy. In some applications, processing system 5 can be used for neural network training to generate data used by autopilot systems for vehicles (e.g., automobiles).

[0033] As shown in the figure, the processing system 5 includes a heat dissipation structure 12, a system-on-wafer (SoW) 14, and a cooling system 18. The heat dissipation structure 12 and the cooling system 18 are positioned on both sides of the SoW 14 as shown in the figure. The thermal system of the processing system includes the heat dissipation structure 12 and the cooling system 18. To illustrate the features of the SoW 14, the processing system 5 is shown with the surface of the SoW 14 separated from the cooling system 18. After assembly, the SoW 14 may be attached to the cooling system 18 directly or by one or more intervening structures. The processing system 5 is an SoW assembly.

[0034] The heat dissipation structure 12 can dissipate heat from the SoW 14. The heat dissipation structure 12 may include a heat spreader. Such a heat spreader may include a metal plate. Alternatively or in addition, the heat dissipation structure may include a heat sink. The heat dissipation structure 12 may include metals such as copper and / or aluminum. Alternatively or in addition, the heat dissipation structure 12 may include any other suitable material having desirable heat dissipation properties. In certain applications, the heat dissipation structure 12 may include a copper heat spreader and an aluminum heat sink. A thermal interface material may be included between the heat dissipation structure 12 and the SoW 14 to reduce and / or minimize heat transfer resistance.

[0035] SoW14 may include an array of integrated circuit (IC) dies. The IC dies may be embedded in the molding material. SoW14 may have a high computation density. The IC dies may be semiconductor dies such as silicon dies. The array of IC dies may include any appropriate number of IC dies. For example, the array of ICs may include 16 IC dies, 25 IC dies, 36 IC dies, or 49 IC dies. SoW14 may be, for example, an integrated fan-out (InFO) wafer. An InFO wafer may include multiple routing layers across the array of IC dies. For example, an InFO wafer may include 4, 5, 6, 8, or 10 routing layers in a particular application. The routing layers of the InFO wafer can provide signal connections between IC dies and / or to external components. SoW14 may have a relatively large diameter, such as in the range of 10 to 15 inches. As an example, SoW14 may have a diameter of 12 inches. SoW14 may have a diameter of at least 12 inches.

[0036] The cooling system 18 can provide active cooling to the processing system 5. The cooling system 18 may include a metal having a channel for a heat transfer fluid to flow through. For example, the cooling system 18 may include a machined metal such as copper. The cooling system 18 may include a brazed fin array for high cooling efficiency. The cooling system 18 may include a conductive structure at ground potential. The conductive structure may be a ground plane, a conductive layer, or any other suitable conductive structure at ground potential. In the assembled processing system 5, the cooling system 18 may be bolted or otherwise fastened to the thermal structure 12. This can provide structural support to the SoW 14 and / or reduce the possibility of failure of the SoW 14. The bolts or other fasteners may be metal and can electrically connect the conductive structure of the cooling system 18 and the heat dissipation structure 12. Wafer configuration example

[0037] Figure 2 is a plan view of SoW14. SoW14 includes a wafer 22. The wafer 22 may be a silicon wafer. The illustrated SoW14 includes an array of IC dies 28. In some implementations, the IC dies 28 may be embedded in the SoW14 and therefore not visible when viewing SoW14 from above. For example, a molding material may cover the IC dies 28. SoW14 may also include one or more routing layers 31 (see Figure 3). The IC dies 28 may be semiconductor dies such as silicon dies, but are not limited to these. The array of IC dies 28 may include any appropriate number of IC dies.

[0038] The IC die 28 may be connected to a component 26 for data transfer. For example, component 26 may be a PCB. Component 26 may be any other suitable component, including circuit elements and / or routing, instead of or in addition to the above. Component 26 may be arranged to form a boundary around the array of IC dies 28. As shown in the figure, component 26 is located around the outer perimeter of the array of IC dies 28. Component 26 may be electrically connected to the IC die 28 from above the surface of the wafer 22 (e.g., via soldering). The solder mask portion may be peeled off so that the metal connection portion underneath is exposed. The exposed metal connection region 42 of component 26 (see Figure 4) may be electrically connected to the cooling system 18 so that component 26 is electrically connected to the cooling system 18.

[0039] The surface of the wafer 22 may further include a plurality of electrical contacts 24. In some mounting configurations, the electrical contacts 24 may be located beneath a bump metallization (UBM) pad. The electrical contacts 24 shown are UBM pads. The electrical contacts 24 may be made of a conductive material such as copper, but are not limited to this. In certain applications, the electrical contacts 24 may be copper pillars, such as in applications where copper pillar UBM pads are used. A higher density of electrical contacts 24 may be desirable to provide EMI protection to the SoW 14. The electrical contacts 24 may be spaced 100 microns, 300 microns, 800 microns, or 900 microns apart, depending on manufacturing limitations and / or available space on the wafer 22. In some mounting configurations, the electrical contacts 24 may consist only of open-air UBM pads occupying any area of ​​the wafer 22 not utilized by the IC die 28 or component 26. Open-air UBM pads may not be connected to external components and may therefore be in direct contact with the outside air. In some other mounting configurations, the electrical contacts 24 may also occupy an area beneath the components 26, and these components may be soldered to the electrical contacts 24 rather than being directly attached to the wafer surface. In such mounting configurations, only a portion of the electrical contacts 24 may be open-air UBM pads. In some mounting configurations, the electrical contacts 24 may form a boundary around the components 26. The electrical contacts 24 may be in the shape of a column or a hemisphere. As described herein, the electrical contacts 24 can be electrically connected to the cooling system 18 (see Figures 5A-5C). ESD / EMI protection configuration example

[0040] Figure 3 shows a cross-sectional view of an assembled processing system 10 according to an aspect of the present disclosure. This assembled processing system 10 is a SoW assembly. The processing system 10 may include a heat dissipation structure 12, a SoW 14, a voltage regulation module (VRM) 16, and a cooling system 18. The heat dissipation structure 12 and / or SoW 14 may include any suitable features described with reference to Figure 1. In certain applications, the VRMs 16 may be arranged so that each VRM is stacked with the IC die 28 of the SoW 14. In the processing system 10, high-density packing may be present in the VRMs 16. Therefore, the VRMs 16 may consume considerable power. The VRMs 16 may be configured to receive a direct current (DC) supply voltage and supply a lower output voltage to the corresponding IC die of the SoW 14. Each VRM 16 can supply a regulated voltage to its respective IC die 28. The cooling system 18 can provide active cooling to the VRMs 16. The cooling system 18 may include any suitable features described with reference to Figure 1.

[0041] As shown in Figure 3, the SoW 14 and VRM 16 are positioned between the cooling system 18 and the heat dissipation structure 12. The SoW 14 can be bonded to the heat dissipation structure 12 using a conductive thermal interface material. The cooling system 18 may also be coated with a thermal interface material to fix conductive functional parts to the cooling system 18, as described herein. In some embodiments, the thermal interface material used on the heat dissipation structure 12 may differ from the thermal interface material used on the cooling system 18. The cooling system 18 and the heat dissipation structure 12 may be made of materials having both high thermal conductivity and high electrical conductivity.

[0042] The thermal system of the processing system 10 includes a cooling system 18 and a heat dissipation structure 12. Since the thermal system can include a relatively large body of conductive material, it can be at ground potential and function as an electrical ground. Therefore, the conductive layer formed by the thermal interface material can also be at ground potential. The cooling system 18 and the heat dissipation structure 12 can be connected via a conductive frame 38. The conductive frame 38 may be any fastening mechanism made of conductive material, such as one or more of screws, bolts, nails, or metal clamps, but is not limited to these. The structure created by the cooling system 18, the conductive frame 38, and the heat dissipation structure 12 can function as part of a Faraday cage to reduce EMI associated with the processing system 10. The Faraday cage can protect the internal circuit elements of the processing system 10 from EMI generated by external circuit elements. The Faraday cage can reduce EMI emitted to external circuit elements by the processing system 10. The SoW 14 can be electrically connected to the thermal system so that the IC die 28 is grounded, thereby reducing the risk of damage from ESD events.

[0043] As described herein, the IC die 28 and one or more routing layers 31 may be embedded in the SoW 14. In some implementations, the IC die 28 may be electrically connected to the heat dissipation structure 12 via direct contact with the heat dissipation structure 12. In some other embodiments, the IC die 28 may be electrically connected to the heat dissipation structure 12 via the routing layers 31. The routing layers 31 can also electrically connect the IC die 28 to components of the processing system 10. The IC die 28 may be electrically connected to the VRM 16 and components 26 by the routing layers 31 and electrical contacts 24.

[0044] In some implementations, the electrical contacts 24 may consist only of open-air UBM pads and may occupy areas of the wafer 22 not utilized by the IC die 28 or connector 26. In such embodiments, external components can be fabricated directly on the SoW 14 without soldering. In some other implementations, as shown in Figure 3, the electrical contacts 24 may also occupy areas utilized by the IC die 28 or component 26, and external components may be attached to the electrical contacts 24 via solder 32. In such embodiments, only the outermost UBM pads are open-air UBM pads.

[0045] The IC die 28 may be electrically connected to the cooling system 18 via one or more other components. The solder mask portion of component 26 may be stripped so that the underlying metal is exposed. The exposed metal connection area 42 (see Figure 4) may be covered by a first conductive functional part 36 so that the exposed metal connection area 42 is electrically connected to the cooling system 18. The first conductive functional part 36 may be, for example, a conductive ESD foam. The open-air type UBM pad may be electrically connected to the cooling system 18 via a second conductive functional part 34. Both component 26 and the second conductive functional part 34 may be electrically connected to the IC die 28 via a routing layer 31. Thus, the IC die 28 may be electrically connected to the cooling system 18 and the heat dissipation structure 12 (both functioning as electrical grounds) via other components. Thus, static electricity can be discharged to the heat system, reducing the risk of hardware damage due to ESD events. Furthermore, similar to the structure generated by the thermal system and the conductive frame 38, the first conductive functional section 36 and the second conductive functional section 34 can generate a structure having a thermal system that functions as a Faraday cage, thereby providing EMI shielding. In certain applications, the first conductive functional section 36 and the second conductive functional section 34 are formed from the same material. Alternatively, the first conductive functional section 36 and the second conductive functional section 34 may be made from different materials.

[0046] The VRM16 may be connected to the surface of the SoW14 so that the VRM16 is electrically connected to the routing layer 31 and the IC die 28. The VRM16 may be aligned with the IC die 28 so that each IC die 28 is located directly beneath its respective VRM16. In some embodiments, the VRM16 is not connected to the cooling system 18. In such mounting configurations, static charge may accumulate on the SoW14. Preferably, the static charge can be discharged from the system through the routing layer 31, the connector 26, and the open-air UBM pad.

[0047] In certain embodiments, the conductive structure of the thermal system may be at ground potential and electrically connected by a conductive functional part to the metallic connections of components placed on the SoW. An example is shown in Figure 4.

[0048] Figure 4 shows a cross-sectional view of a single component 26 attached to the first conductive functional unit 36. The first conductive functional unit 36 ​​can be an ESD foam, a conductive foam, a conductive adhesive, or any other suitable conductive material. As an example, the first conductive functional unit 36 ​​may include an ESD foam containing a conductive material on a foam gasket. As described herein, the component 26 may also be a PCB. The component 26 may have a solder mask on its surface to protect the underlying circuitry and / or metal structure. The solder mask may be removed in a limited area to expose the underlying metal connection area. The exposed metal connection area 42 can electrically connect the component 26 to other components of the processing system 10. For example, the metal connection area 42 may be electrically connected to the conductive structure of the cooling system 18 by a conductive mechanism such as the first conductive functional unit 36. There may be one or more exposed metal connection areas 42. For example, there may be one, two, three, or four exposed metal connection areas 42 for a given connector 26. In some implementations, the conductive functional part attached to component 26 may be made of any suitable conductive material. Component 26 can also be grounded to the SoW via contacts such as copper pillars on the surface of the SoW that are electrically connected to component 26.

[0049] In certain embodiments, the conductive structure of the thermal system may be at ground potential and electrically connected to a contact on the surface of the SoW via a plurality of conductive functional parts. The conductive functional parts may be arranged around the SoW. In certain applications, the conductive functional parts may extend from a contact on the surface of the SoW. Exemplary conductive functional parts and electrical connections between a contact, such as a UBM pad, and the conductive structure of the thermal system, such as the conductive structure of the cooling system 18, are described with reference to Figures 5A to 5C. The processing system and / or SoW assembly may include a first set of conductive functional parts by any suitable principle and advantages described with reference to Figure 4, and a second set of conductive functional parts by any suitable principle and advantages described with reference to any of Figures 5A to 5C.

[0050] Figures 5A to 5C show exemplary conductive functional units 34 that can be used to connect an open-air UBM pad to a cooling system 18. Figures 5A to 5C show the electrical connections between the SoW 14, electrical contacts 24, conductive functional units 34, and the cooling system 18. Figure 5A shows a wire 34A as the conductive functional unit. One end of the wire 34A may be attached to the electrical contacts 24 using solder 32, and the other end of the wire 34A may be attached to the cooling system 18. The wire 34A may be made of any suitable conductive material. In some mounting configurations, the wire 34A may be attached to the electrical contacts 24 without using solder 32. The wire 34A may be referred to as a wire bond. Any suitable number or all of the electrical contacts 24 shown in Figure 2 can be electrically connected to the cooling system 18 by the wire 34A.

[0051] Figure 5B shows the ESD foam 34B as a conductive functional part. The layer of ESD foam 34B may be placed between the electrical contacts 24 and the cooling system 18. The ESD foam 34B may be a conductive foam. For example, the ESD foam 34B may include a conductive material on top of the foam gasket. The ESD foam 34B can have various sizes. For example, in some embodiments, the electrical contacts 24 may be connected to the cooling system 18 via one or more slabs of the ESD foam 34B to increase and / or maximize the surface area of ​​the cooling system 18 that contacts the ESD foam 34B. In some other embodiments, the ESD foam 34B includes smaller pieces such that each piece of ESD foam covers only the surface area of ​​one electrical contact 24 and each electrical contact 24 is connected to one ESD foam 34B. In some mounting configurations, the ESD foam 34B may be attached to the electrical contacts 24 by solder 32. In some other embodiments, the ESD foam 34B may be in direct contact with the electrical contacts 24. Any suitable number or all of the electrical contacts 24 shown in Figure 2 may be electrically connected to the cooling system 18 by the ESD foam 34B. In certain applications, a conductive adhesive or other suitable conductive material may be used instead of the ESD foam 34B.

[0052] Figure 5C shows a spring-loaded conductive functional section 34C that can be a spring-loaded clip. The spring-loaded conductive functional section 34C can be made of any suitable conductive material. The spring-loaded conductive functional section 34C may include a spring. In other configurations, the spring-loaded conductive functional section 34C may be a semi-rigid component that returns to its original shape after deformation. Figure 5C shows a side view and an isometric view of an exemplary semi-rigid spring-loaded conductive functional section configuration. In some configurations, the spring-loaded conductive functional section 34C may be soldered to the electrical contacts 24. In some other configurations, the spring-loaded conductive functional section 34C may be positioned in direct contact with the electrical contacts 24. Any suitable number or all of the electrical contacts 24 shown in Figure 2 may be electrically connected to the cooling system 18 by the spring-loaded conductive functional section 34C. Each of the conductive functional sections described herein can be used individually or in combination with one or more other types of conductive functional sections.

[0053] In some applications, ESD protection circuits may be included in the processing systems disclosed herein. For example, an ESD protection circuit may be implemented with a component 26 that is grounded by an electrical connection to the conductive structure of the cooling system 18 in Figure 3 and / or Figure 4. An exemplary ESD protection circuit 60 is shown in Figure 6. The ESD protection circuit 60 may be on the component 26 (for example, on the PCB if the component 26 is a PCB). In certain applications, the ESD protection circuit 60 may be on the SoW 14. The ESD protection circuit 60 can provide ESD protection to any of the processing systems and / or SoW assemblies disclosed herein.

[0054] In some implementations, a processing system having an integrated ESD and / or EMI protection function can be manufactured by electrically connecting a SoW to a thermal system. The SoW may include multiple IC dies electrically connected to one or more routing layers within the SoW. The thermal system may include two parts, each of which may include a conductive structure at ground potential. The SoW may be positioned between the two parts of the thermal system. The SoW may be positioned in contact with the first part of the thermal system such that the SoW is electrically connected to the first part of the thermal system.

[0055] Components for data transfer may be arranged on the surface of the SoW between the SoW and a second part of the thermal system, such that the components are electrically connected to the IC die via a routing layer. Each component may have exposed conductive material on the opposite surface of the SoW. Conductive functional parts are arranged in contact with the exposed conductive material and the second part of the thermal system, allowing each component to be electrically connected to the second part of the thermal system.

[0056] The electrical contact area may also be located on the surface of the SoW such that the contact area is electrically connected to the IC die via a routing layer. The conductive functional part may be located between the second part of the thermal system and the contact area such that the second part of the thermal system is electrically connected to the contact area. Thus, the second part of the thermal system may be electrically connected to the IC die via its components and the contact area. The first part of the thermal system and the second part of the thermal system may be fixed to each other by a conductive frame.

[0057] The foregoing disclosure is not intended to limit the disclosure to the exact form or specific field of use disclosed herein. Therefore, various other embodiments and / or modifications to the disclosure, whether expressly described or implied herein, are conceivable in light of the disclosure. While embodiments of the disclosure have been described in this manner, as those skilled in the art will see, modifications can be made in form and detail without departing from the scope of the disclosure. Therefore, the disclosure is limited solely by the claims.

[0058] The above specification describes the disclosure with reference to specific embodiments. However, as will be apparent to those skilled in the art, the various embodiments disclosed herein can be modified or implemented in various other ways without departing from the spirit and scope of the disclosure. Therefore, this description should be considered illustrative and is intended to teach those skilled in the art how to create and use various embodiments of the disclosed IC assemblies. It should be understood that the forms of disclosure shown and described herein should be interpreted as representative embodiments. Equivalent elements, materials, processes, or steps may be substituted for those typically illustrated and described herein. Furthermore, certain features of the disclosure may be used independently of the use of other features, as will be apparent to those skilled in the art after benefiting from this description of the disclosure. Expressions such as “including,” “comprising,” “incorporating,” “consisting of,” “have,” and “is” used to describe the disclosure and to describe the claims are intended to be interpreted in a non-exclusive manner, that is, to allow for the existence of items, components, or elements not expressly described. Furthermore, any reference to the singular form should be interpreted as also relating to the plural form.

[0059] Furthermore, the various embodiments disclosed herein should be interpreted in an illustrative and descriptive sense and not in any way as limiting the disclosure. All references to joining (e.g., mounting, fixing, joining, connection, etc.) are used solely to aid the reader's understanding of the disclosure and do not imply any limitation with respect to the location, orientation, or use of the systems and / or methods disclosed herein. Accordingly, where there is a reference to joining, it should be interpreted broadly. Moreover, such references to joining do not necessarily mean that the two elements are directly connected to each other.

[0060] Furthermore, numerical terms such as “first,” “second,” “third,” “primary,” “secondary,” “main,” or any other common and / or numerical terms, without limitation, should be interpreted solely as identifiers to aid the reader’s understanding of the various elements, embodiments, variations, and / or modifications of this disclosure, and in particular, they should not impose any restrictions on the order or preference of any elements, embodiments, variations, and / or modifications, or any elements, embodiments, variations, and / or modifications beyond those of other elements, embodiments, variations, and / or modifications.

[0061] Furthermore, it can be seen that one or more elements depicted in the drawings / figures may be implemented in a more separated or integrated manner to be useful for a particular purpose, or even removed or rendered in a non-functional manner in certain cases. Moreover, any signal hatches in the drawings / figures should be considered as illustrative examples only, and not as limiting, unless otherwise specified.

Claims

1. A system-on-wafer (SoW) assembly, A SoW comprising multiple integrated circuit (IC) dies and one or more routing layers for electrical connections for the IC dies, A thermal system having a conductive structure at ground potential, configured to cool the SoW, A SoW assembly comprising a plurality of conductive functional parts in an electrical path between a contact on the surface of the SoW and the conductive structure of the thermal system.

2. The SoW assembly according to claim 1, wherein the plurality of conductive functional parts ground the SoW to the conductive structure of the thermal system to provide electrostatic discharge protection.

3. The SoW assembly according to claim 1, wherein the plurality of conductive functional parts ground the SoW to the conductive structure of the thermal system to perform electromagnetic interference shielding.

4. The SoW assembly according to claim 1, wherein the plurality of conductive functional parts are located around the SoW.

5. The SoW assembly according to claim 1, wherein the plurality of conductive functional parts are provided with conductive foam.

6. The SoW assembly according to claim 1, wherein the plurality of conductive functional parts are provided with wire bonds.

7. The SoW assembly according to claim 1, wherein the plurality of conductive functional parts are equipped with spring load clips.

8. The SoW assembly according to claim 1, wherein the SoW is an integrated fan-out wafer.

9. The SoW assembly according to claim 1, further comprising a voltage regulation module located between the IC die and the conductive structure of the thermal system.

10. The SoW assembly according to claim 1, wherein the thermal system further comprises a heat dissipation structure on the opposite side of the SoW from the conductive structure, and there is an electrical connection between the heat dissipation structure and the conductive structure.

11. The SoW assembly according to claim 1, further comprising a plurality of components in an electrical path between the contacts on the surface of the SoW and the plurality of conductive functional parts, each of the plurality of components having a conductive material exposed in the electrical path with the conductive functional parts.

12. The SoW assembly according to claim 1, wherein the SoW has a diameter of at least 12 inches.

13. A system-on-wafer (SoW) assembly, A SoW comprising multiple integrated circuit (IC) dies and one or more routing layers for electrical connections for the IC dies, A thermal system having a conductive structure at ground potential, configured to cool the SoW, A plurality of components located between the SoW and the conductive structure of the thermal system, each of which has a conductive material exposed on the surface opposite to the SoW, and the plurality of components are electrically connected to the SoW by contacts on the surface of the SoW, A SoW assembly comprising a plurality of conductive functional parts in an electrical path between the exposed conductive material of the plurality of components and the conductive structure of the thermal system.

14. The SoW assembly according to claim 13, wherein the plurality of components include a printed circuit board.

15. The SoW assembly according to claim 14, further comprising an electrostatic discharge protection circuit on the printed circuit board.

16. The SoW assembly according to claim 13, wherein the plurality of conductive functional parts contribute to electrostatic discharge protection.

17. The SoW assembly according to claim 13, wherein the plurality of conductive functional parts perform electromagnetic interference shielding.

18. The SoW assembly according to claim 13, wherein the plurality of components are positioned around the plurality of IC dies.

19. The SoW assembly according to claim 13, wherein the plurality of conductive functional parts are provided with conductive foam.

20. A method for manufacturing a system-on-wafer (SoW) assembly, A step of providing a SoW with contacts on the surface of the SoW, wherein the SoW comprises a plurality of integrated circuit (IC) dies and one or more routing layers for making electrical connections for the IC dies, and the contacts are electrically connected to the IC dies via the one or more routing layers. A method comprising the steps of electrically connecting the conductive structure of a thermal system to the contacts on the surface of the SoW via at least a plurality of conductive functional parts, wherein the conductive structure of the thermal system is at ground potential.

21. The method according to claim 20, wherein the electrical connection is made between the conductive structure and the contact by the components on the contact.

22. The method according to claim 20, wherein the thermal system comprises a second portion on the opposite side of the SoW with respect to the conductive structure, and the method further comprises the step of fixing the first portion of the thermal system and the second portion of the thermal system to each other via a conductive frame.

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