Semiconductor device and communication method between semiconductor devices

Abstract

To provide a semiconductor device and a communication method between semiconductor devices that utilize a plurality of pins for transmitting data by parallel transmission to improve transmission performance while reducing frequency of transmission.SOLUTION: A semiconductor device includes a plurality of pins, semiconductor components, and a scalable digital interface circuit. The pins are divided into a plurality of data sending groups and a plurality of data receiving groups. The semiconductor components provide output data and receive input data. The scalable digital interface circuit is coupled to the data sending groups, the data receiving groups, and the semiconductor components, wherein the scalable digital interface circuit reorganizes the output data into parallel transmission data to send the parallel transmission data to an external semiconductor device by parallel transmission, and receives parallel reception data from the external semiconductor device by parallel transmission to reorganize the parallel reception data into the input data.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a semiconductor device using parallel transmission, and a communication method between semiconductor devices.

Background Art

[0002] The process of semiconductor manufacturing technology has been continuously progressing over a long period of time to increase the number of transistors on a chip in order to improve computing performance. As a result, the gate length has gradually become shorter and is gradually approaching the known physical limits at present. However, with the rapid development of artificial intelligence (AI), AI-generated content (AIGC), and other related applications, the performance requirements for the equipment for core chips have been increasing more and more. When the improvement of manufacturing technology encounters bottlenecks, increasing the number of transistors on a chip by advanced packaging technology of chip stacking has become a necessary choice. However, in view of the fact that the demand for computing resources continues to rise with the computing demand, improving the chip performance in the current packaging technology is still an important issue.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide a semiconductor device and a communication method between semiconductor devices that use a plurality of pins to transmit data by parallel transmission in order to improve transmission performance and reduce transmission frequency.

Means for Solving the Problems

[0004] One embodiment of the present invention provides a semiconductor device comprising a plurality of pins, at least one semiconductor component, and a scalable digital interface circuit. The pins are divided into a plurality of data transmission groups and a plurality of data reception groups. At least one semiconductor component provides at least one output data and receives at least one input data. The scalable digital interface circuit is coupled to at least one data transmission group, at least one data reception group, and at least one semiconductor component. The scalable digital interface circuit transmits at least one parallel transmission data to an external semiconductor device by parallel transmission by reconfiguring at least one output data into at least one parallel transmission data, and also reconfigures at least one parallel reception data into at least one input data.

[0005] Another embodiment of the present invention provides a method for communication between semiconductor devices, comprising the following steps: At least one output data provided by at least one semiconductor component is reconstructed into at least one parallel transmit data by a scalable digital interface circuit. The at least one parallel transmit data is transmitted to an external semiconductor device via parallel transmission by at least one of a plurality of data transmit groups of a plurality of pins. At least one parallel receive data is received from the external semiconductor device by at least one of a plurality of data receive groups of pins. The scalable digital interface circuit reconstructs the at least one parallel receive data into at least one input data and provides it to at least one semiconductor component. [Effects of the Invention]

[0006] Based on the above, in the semiconductor device and communication method between semiconductor devices according to the embodiment of the present invention, data is transmitted between semiconductor devices via parallel transmission. The use of parallel transmission increases the speed of transmission of vast amounts of data and is also possible even at low signal frequencies. In this way, transmission performance can be improved and the transmission frequency can be reduced. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic diagram of a system for packaging multiple semiconductor devices according to one embodiment of the present invention. [Figure 2] This is a diagram showing the pin configuration for connecting semiconductor devices according to one embodiment of the present invention. [Figure 3] This is a system diagram of a scalable digital interface circuit according to one embodiment of the present invention. [Figure 4] This is a diagram showing the pin configuration for connecting semiconductor devices according to another embodiment of the present invention. [Figure 5] This is a system diagram of a scalable digital interface circuit according to another embodiment of the present invention. [Figure 6] This is a stacked diagram of a semiconductor device according to one embodiment of the present invention. [Figure 7] This is a stacked view of a semiconductor device according to another embodiment of the present invention. [Figure 8] This is a circuit diagram of a general-purpose input / output interface according to one embodiment of the present invention. [Figure 9] This is a flowchart illustrating a communication method for multiple semiconductor devices according to one embodiment of the present invention. [Modes for carrying out the invention]

[0008] Figure 1 is a schematic diagram of a system for packaging multiple semiconductor devices according to one embodiment of the present invention. Referring to Figure 1, in this embodiment, the integrated circuit 10 includes at least semiconductor devices 100 and 200, where semiconductor devices 100 and 200 are, for example, chips. The semiconductor devices 100 and 200 can be packaged as a single integrated circuit using three-dimensional (3D) chip packaging or chiplet packaging. That is, the semiconductor devices 100 and 200 can be stacked adjacently or in close proximity in an integrated circuit in different ways, but the present invention is not limited thereto.

[0009] In this embodiment, the semiconductor device 100 includes, for example, a plurality of pins (e.g., a plurality of transmit pins GPTX1 and a plurality of receive pins GPRX1), at least one semiconductor component (e.g., memory units 110_1 to 110_n and / or arithmetic units 120_1 to 120_m, where n and m may be any positive integers and depend on the circuit design), a signal bus 130, and a scalable digital interface circuit 140. The transmit pins GPTX1 are divided into a plurality of data transmission groups (GTX1 to GTX5 shown in Figure 8), and the receive pins GPRX1 are divided into a plurality of data reception groups (GRX1 to GRX5 shown in Figure 8). The scalable digital interface circuit 140 is based on a data transmission group for data output (GTX1 to GTX5 shown in Figure 8) and a data reception group for data input (GRX1 to GRX5 shown in Figure 8).

[0010] The signal bus 130 is coupled to the memory units 110_1 to 110_n, the arithmetic units 120_1 to 120_m, and the scalable digital interface circuit. Specifically, the scalable digital interface circuit 140 is coupled to the memory units 110_1 to 110_n and the arithmetic units 120_1 to 120_m via the signal bus 130. The scalable digital interface circuit 140 is coupled to at least one of the data transmission group (GTX1 to GTX5 shown in Figure 8) of the transmit pin GPTX1, and to at least one of the data reception group (GRX1 to GRX5 shown in Figure 8) of the receive pin GPRX1.

[0011] When at least one of the memory units 110_1 to 110_n and the arithmetic units 120_1 to 120_m provides output data Dout, the scalable digital interface circuit 140 receives at least one output data Dout via the signal bus 130. The at least one output data Dout is then reconfigured into at least one parallel transmission data Dpsent, and the at least one parallel transmission data Dpsent is transmitted by parallel transmission via a combined data transmission group (GTX1 to GTX5 shown in Figure 8) to another external semiconductor device (e.g., semiconductor device 200).

[0012] When the scalable digital interface circuit 140 receives at least one parallel received data Dprce from another external semiconductor device (e.g., semiconductor device 200) via parallel transmission through a combined data receiving group (GRX1 to GRX5 shown in Figure 8), the scalable digital interface circuit 140 may reconstruct the at least one parallel received data Dprce into at least one input data Din before transmitting it to the signal bus 130, where the input data Din may correspond to the data format of the receiving object (i.e., one of the storage units 110_1 to 110_n and the arithmetic units 120_1 to 120_m). Then, one or more of the storage units 110_1 to 110_n and the arithmetic units 120_1 to 120_m receive the corresponding one of the at least one input data Din via the signal bus 130.

[0013] Based on the above, in 3D chip packaging or chiplet packaging, chips can be stacked adjacent to or close to each other, and multiple channels (e.g., through-silicon vibrators (TSVs) or redistribution layers (RDLs)) can be established between semiconductor devices 100 and 200. The data transmission rate (e.g., bandwidth) can be increased through multiple channels, and it is not necessarily required that the signal frequency be high. In this way, it is possible to improve transmission performance while reducing power consumption and cost. Furthermore, signals are transmitted between semiconductor devices 100 and 200 by digital connection via scalable digital interface circuits 140 and 240, which allows for flexible switching of the semiconductor component manufacturing process.

[0014] In this embodiment, the semiconductor device 200 includes, for example, a plurality of pins (e.g., a plurality of transmit pins GPTX2 and a plurality of receive pins GPRX2), at least one semiconductor component (e.g., memory units 210_1 to 210_p and / or arithmetic units 220_1 to 220_q, where p and q may be any positive integers or 0, depending on the circuit design), a signal bus 230, and a scalable digital interface circuit 240. The coupling structure and operating mode of the semiconductor device 200 can be found in the description of the semiconductor device 100 and will not be repeated here.

[0015] In this embodiment, the memory units 110_1 to 110_n and / or the arithmetic units 120_1 to 120_m may be integrated into at least one crystal grain. For example, depending on the circuit design, the memory units 110_1 to 110_n may be integrated into one or more crystal grains, and the arithmetic units 120_1 to 120_m may be integrated into one or more crystal grains, and the embodiments of the present invention are not limited thereto. Similarly, the memory units 210_1 to 210_p and / or the arithmetic units 220_1 to 220_q may also be integrated into at least one crystal grain.

[0016] In this embodiment, according to the circuit designs of the memory units 110_1 to 110_n and / or the arithmetic units 120_1 to 120_m, each of the output data Dout and the input data Din may include, for example, at least one of an Advanced High-Performance Bus (AHB) signal, an Advanced eXtensible Interface (AXI) signal, a serial bus signal, and a parallel bus signal.

[0017] In this embodiment, the arithmetic units 120_1 to 120_m and 220_1 to 220_q include, for example, at least one of a central processing unit (CPU), an application processor (AP), and a graphics processing unit (GPU).

[0018] In this embodiment, the memory units 110_1 to 110_n and 210_1 to 210_p may include a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a thyristor random access memory (TRAM) device, a NAND flash memory device, a NOR flash memory device, a resistive random access memory (RRAM) device, a ferroelectric random access memory (FRAM) device, a phase change memory (PRAM) device, a magnetic random access memory (MRAM) device, a solid state drive (SSD), a memory card, a (UFS), a Universal Flash Storage (UFS), or a similar device.

[0019] FIG. 2 is a connection diagram of pins for connecting between semiconductor devices according to one embodiment of the present invention. Referring to FIGS. 1 and 2, in this embodiment, for semiconductor devices 300 and 400, those shown in the embodiments of semiconductor devices 100 and 200 may be referred to. In this embodiment, the number of transmission pins GPTX3 of semiconductor device 300 may be different from the number of reception pins GPRX4 of semiconductor device 400, and the number of reception pins GPRX3 of semiconductor device 300 may be different from the number of transmission pins GPTX4 of semiconductor device 400. However, the transmission pins GPTX3 of semiconductor device 300 and the reception pins GPRX4 of semiconductor device 400 can be grouped into a plurality of data transmission groups and a plurality of data reception groups based on the same number of pin bases (for example, 40 pins), and the data transmission groups of semiconductor device 300 and the data reception groups of semiconductor device 400 can be coupled group-to-group. Thereby, semiconductor device 300 and semiconductor device 400 can transmit data from semiconductor device 300 to semiconductor device 400 via the coupled data transmission groups and data reception groups.

[0020] In this embodiment, the number of connections between the transmission pins GPTX3 of semiconductor device 300 and the reception pins GPRX4 of semiconductor device 400 is based on the number of pin bases (for example, 40 pins) of a single data transmission group / single data reception group, and is not more than the smaller of the number of transmission pins GPTX3 of semiconductor device 300 and the number of reception pins GPRX4 of semiconductor device 400. For example, the number of connections between the transmission pins GPTX3 (for example, 640 pins) of semiconductor device 300 and the reception pins GPRX4 (for example, 560 pins) of semiconductor device 400 may be 14 sets of data transmission group - data transmission group (that is, 14 × 40 = 560 pins).

[0021] Based on the above, semiconductor devices 300 and 400 can be connected without defining the same number of pins via a digital connection, that is, it is possible to connect semiconductor devices with different numbers of pins, thereby improving the flexibility of semiconductor device connection.

[0022] In this embodiment, when the transmission speed of the transmit pin GPTX3 of the semiconductor device 300 is higher than the transmission speed of the receive pin GPRX4 of the semiconductor device 400, the utilization rate of the connection portion between the transmit pin GPTX3 of the semiconductor device 300 and the receive pin GPRX4 of the semiconductor device 400 may be increased to avoid signal transmission delay. Relatively, when the transmission speed of the transmit pin GPTX3 of the semiconductor device 300 is lower than the transmission speed of the receive pin GPRX4 of the semiconductor device 400, the utilization rate of the connection portion between the transmit pin GPTX3 of the semiconductor device 300 and the receive pin GPRX4 of the semiconductor device 400 may be decreased to reduce wasted system performance without affecting signal transmission.

[0023] In this embodiment, if the transmission speed of output data Dout and input data Din increases, the usage rate of the transmit pin GPTX3 of semiconductor device 300 and the receive pin GPRX4 of semiconductor device 400 may be increased in order to reduce the idle time of the scalable digital interface circuit (e.g., scalable digital interface circuits 140, 240) or the time during which signals to be transmitted are stored in the scalable digital interface circuit (e.g., scalable digital interface circuits 140, 240). Relatively, if the transmission speed of output data Dout and input data Din decreases, the usage rate of the transmit pin GPTX3 of semiconductor device 300 and the receive pin GPRX4 of semiconductor device 400 may be decreased.

[0024] Figure 3 is a system diagram of a scalable digital interface circuit according to one embodiment of the present invention. Referring to Figures 1 to 3, in this embodiment, the semiconductor device 300 includes, for example, a scalable digital interface circuit 340, and the scalable digital interface circuits 140 and 240 may refer to this scalable digital interface circuit 340. The scalable digital interface circuit 340 also includes a bus package circuit 341, an address / data reconstruction register 342, a transmit rearassembler 343, a receive rearassembler 344, a transmit buffer 345, an input / output controller 346, a receive buffer 347, and a general-purpose input / output interface circuit 348.

[0025] The bus package circuit 341 is coupled to the signal bus 130. The address / data reconstruction register 342 is coupled to the bus package circuit 341. The transmit assembler 343 is coupled to the address / data reconstruction register 342. The receive assembler 344 is coupled to the address / data reconstruction register 342. The transmit buffer 345 is coupled to the transmit assembler 343. The receive buffer 347 is coupled to the receive assembler 344. The general-purpose input / output interface circuit 348 is coupled to the transmit buffer 345 and the receive buffer 347. The input / output controller 346 is coupled to the transmit buffer 345 and the receive buffer 347.

[0026] The input / output controller 346 is used to control the transmit buffer 345 and the receive buffer 347. When the bus package circuit 341 receives output data (e.g., output data Dout) from a storage unit (e.g., storage units 110_1~110_n and 210_1~210_p) via a signal bus (e.g., signal buses 130, 230), the bus package circuit 341 temporarily stores the output data (e.g., output data Dout) in the address / data reconfiguration register 342. The transmit assembler 343 then reconfigures the output data (e.g., output data Dout) into parallel transmit data (e.g., parallel transmit data Dpsent) for temporary storage in the transmit buffer 345, and the transmit assembler 343 is responsible for structuring the execution sequence of read and write instructions into small packets of continuous data in order to provide the parallel transmit data (e.g., parallel transmit data Dpsent). Furthermore, the general-purpose input / output interface circuit 348 transmits parallel transmission data (e.g., parallel transmission data Dpsent) temporarily stored in the transmit buffer 345 to another external semiconductor device (e.g., semiconductor device 400) via at least one data transmission group of the transmit pin GPTX3.

[0027] On the other hand, when the general-purpose input / output interface circuit 348 receives parallel received data (e.g., parallel received data Dprce) from another external semiconductor device (e.g., semiconductor device 300) via at least one group of receive pins GPRX3, the general-purpose input / output interface circuit 348 temporarily stores the parallel received data (e.g., parallel received data Dprce) in the receive buffer 347. The receive assembler 344 then reconstructs the parallel received data (e.g., parallel received data Dprce) temporarily stored in the receive buffer 347 into input data (e.g., input data Din) and temporarily stores it in the address / data reconstruction register 342. The receive assembler 344 is responsible for restoring the small packets of data (i.e., parallel received data Dprce) into a randomly writable execution sequence in order to provide the input data (e.g., input data Din). Furthermore, the bus package circuit 341 provides the input data (e.g., input data Din) temporarily stored in the address / data reconstruction register 342 to the storage units (e.g., storage units 110_1~110_n, 210_1~210_p) and / or the arithmetic units (e.g., arithmetic units 120_1~120_m, 220_1~220_q) via the signal bus (e.g., signal buses 130, 230).

[0028] Figure 4 is a diagram showing the pin configurations connecting semiconductor devices according to another embodiment of the present invention. Referring to Figures 1, 2, and 4, in this embodiment, the embodiments of semiconductor devices 100 and 200 may be used for semiconductor devices 500, 600, and 700. In this embodiment, the transmit pins GPTX51 and GPTX52 of semiconductor device 500 can be divided into multiple data transmission groups, and the receive pins GPRX51 and GPRX52 of semiconductor device 500 can be divided into multiple data reception groups. Similarly, the transmit pin GPTX6 of semiconductor device 600 and the transmit pin GPTX7 of semiconductor device 700 can be divided into multiple data transmission groups, and the receive pin GPRX6 of semiconductor device 600 and the GPRX7 of semiconductor device 700 can be divided into multiple data reception groups.

[0029] In this embodiment, the data transmission group of the transmit pin GPTX51 of semiconductor device 500 and the data reception group of the receive pin GPRX6 of semiconductor device 600 can be combined in a group-to-group manner. The data transmission group of the transmit pin GPTX52 of semiconductor device 500 and the data reception group of the receive pin GPRX7 of semiconductor device 700 can be combined in a group-to-group manner. The data reception group of the receive pin GPRX51 of semiconductor device 500 and the data transmission group of the transmit pin GPTX6 of semiconductor device 600 can be combined in a group-to-group manner. Furthermore, the data reception group of the receive pin GPRX52 of semiconductor device 500 and the data transmission group of the transmit pin GPTX7 of semiconductor device 700 can be combined in a group-to-group manner.

[0030] The ratio of the receiving pins GPRX51 and GPRX52 of semiconductor device 500 may relate to the ratio of the transmission speed of the transmitting pin GPTX6 of semiconductor device 600 to the transmission speed of the transmitting pin GPTX7 of semiconductor device 700, or it may relate to the ratio of the transmission speed of the output data (e.g., output data Dout) and / or input data (e.g., input data Din) inside semiconductor device 600 to the transmission speed of the output data (e.g., output data Dout) and / or input data (e.g., input data Din) inside semiconductor device 700, that is, the higher the transmission speed, the higher the ratio.

[0031] On the other hand, the ratio of the transmit pins GPTX51 and GPTX52 of semiconductor device 500 may be related to the ratio of the transmission speed of the receive pin GPRX6 of semiconductor device 600 to the transmission speed of the receive pin GPRX7 of semiconductor device 700, i.e., the lower the transmission speed, the higher the ratio. Alternatively, the ratio may be related to the ratio of the transmission speed of the output data (e.g., output data Dout) and / or input data (e.g., input data Din) inside semiconductor device 600 to the transmission speed of the output data (e.g., output data Dout) and / or input data (e.g., input data Din) inside semiconductor device 700, i.e., the higher the transmission speed, the higher the ratio.

[0032] Figure 5 is a system diagram of a scalable digital interface circuit according to another embodiment of the present invention. Referring to Figures 1 to 5, in this embodiment, the semiconductor device 500 includes, for example, a scalable digital interface circuit 540, and the scalable digital interface circuits 140 and 240 may refer to this scalable digital interface circuit 540. The scalable digital interface circuit 540 also includes a bus package circuit 541, an address / data reconstruction register 542, transmit rearassemblers 543_1 to 543_x, receive rearassemblers 544_1 to 544_x, transmit buffers 545_1 to 545_x, input / output controllers 546_1 to 546_x, receive buffers 547_1 to 547_x, and general-purpose input / output interface circuits 548_1 to 548_x, where x may be any positive integer. The operation of the scalable digital interface circuit 540 can be described by referring to the scalable digital interface circuit 340, and will not be repeated here. In addition, since parallel transmission requires a large number of connections, semiconductor devices (e.g., semiconductor devices 500, 600) do not span long distances, and x is usually < 4. However, when long-distance transmission is required, other connection protocols such as PCIe (Peripheral Component Interconnect Express) and UCIE (Universal Chip Interconnect Express) may be used, and the embodiments of the present invention are not limited thereto.

[0033] Figure 6 is a stacked diagram of a semiconductor device according to one embodiment of the present invention. Referring to Figures 1 to 6, in this embodiment, semiconductor devices 100a and 200a are directly stacked, that is, semiconductor devices 100a and 200a are packaged using a 3D chip packaging method.

[0034] Figure 7 is a stacked diagram of a semiconductor device according to another embodiment of the present invention. Referring to Figures 1 to 7, in this embodiment, semiconductor devices 100b and 200b are stacked adjacent to each other on the same surface of an interposer or substrate 800, that is, semiconductor devices 100b and 200b are packaged using a chiplet packaging method. Semiconductor devices 100b and 200b are coupled to each other via paths formed by redistribution layers (RDLs) and / or through-silicon electrodes (TVAs) on the interposer or substrate 800.

[0035] Figure 8 is a circuit diagram of a general-purpose input / output interface according to one embodiment of the present invention. Referring to Figures 1, 3, and 8, in this embodiment, the general-purpose input / output interface circuit 348 may be referred to as the general-purpose input / output interface circuit 348a, which includes a plurality of general-purpose input / output transmit circuits GPX1 to GPX5, a plurality of general-purpose input / output receive circuits GPE1 to GPE5, a plurality of transmit multiplexers TMX1 to TMX3, and a plurality of receive multiplexers RMX1 to RMX4.

[0036] In this embodiment, it is assumed that the parallel transmission data (e.g., parallel transmission data Dpsent) stored in the transmission buffer 345a has four transmission data sections DPX1 to DPX4, and the received parallel reception data (e.g., parallel reception data Dprce) has four reception data sections DPE1 to DPE4, and is stored in the reception buffer 347a. In this case, the general-purpose input / output interface circuit 348a can selectively use the general-purpose input / output transmission circuits GPX1 to GPX5 to transmit parallel transmission data (e.g., parallel transmission data Dpsent), and the general-purpose input / output interface circuit 348a can selectively use the general-purpose input / output reception circuits GPE1 to GPE5 to receive parallel reception data (e.g., parallel reception data Dprce).

[0037] In this embodiment, each transmit multiplexer TMX1 to TMX3 has a first input terminal that receives one of the transmit data sections DPX1 to DPX4 (corresponding to the first transmit data section) from the transmit buffer 345a, a second input terminal that receives another of the transmit data sections DPX1 to DPX4 adjacent to the first transmit data section (corresponding to the second transmit data section) from the transmit buffer 345a, and an output terminal that is coupled to one of the general-purpose input / output transmit circuits GPX1 to GPX5.

[0038] Furthermore, the transmit multiplexer TMX1 receives the transmit data units DPX1 and DPX2 and connects them to the general-purpose input / output transmit circuit GPX2. The transmit multiplexer TMX2 receives the transmit data units DPX2 and DPX3 and connects them to the general-purpose input / output transmit circuit GPX3. The transmit multiplexer TMX3 receives the transmit data units DPX3 and DPX4 and connects them to the general-purpose input / output transmit circuit GPX4. The general-purpose input / output transmit circuit GPX1 directly receives the transmit data unit DPX1, and the general-purpose input / output transmit circuit GPX5 directly receives the transmit data unit DPX5. Based on the above, the general-purpose input / output transmit circuits GPX1_GPX5 are used individually to receive one of the transmit data units DPX1~DPX4, and the data is allocated via the transmit multiplexers TMX1~TMX3.

[0039] Each receiving multiplexer RMX1 to RMX4 has a first input terminal connected to one of the general-purpose input / output receiving circuits GPE1 to GPE5 (corresponding to the first general-purpose input / output receiving circuit), a second input terminal connected to another of the general-purpose input / output receiving circuits GPE1 to GPE5 adjacent to the first general-purpose input / output receiving circuit (corresponding to the second general-purpose input / output receiving circuit), and an output terminal that provides one of the received data sections DPE1 to DPE4.

[0040] Furthermore, the receiving multiplexer RMX1 is coupled to the general-purpose input / output receiving circuits GPE1 and GPE2 to provide the received data section DPE1. The receiving multiplexer RMX2 is coupled to the general-purpose input / output receiving circuits GPE2 and GPE3 to provide the received data section DPE2. The receiving multiplexer RMX3 is coupled to the general-purpose input / output receiving circuits GPE3 and GPE4 to provide the received data section DPE3. The receiving multiplexer RMX4 is coupled to the general-purpose input / output receiving circuits GPE4 and GPE5 to provide the received data section DPE4. Based on the above, the general-purpose input / output receiving circuits GPE1 to GPE5 are individually used to receive one of the received data sections DPE1 to DPE4, and the data is allocated via the receiving multiplexers RMX1 to RMX4.

[0041] Based on the above, if a failure or error occurs in one of the general-purpose input / output transmission circuits GPX1 to GPX5, the data can be transmitted by the other general-purpose input / output transmission circuits. Similarly, if a failure or error occurs in one of the general-purpose input / output reception circuits GPE1 to GPE5, the data can be received by the other general-purpose input / output reception circuits.

[0042] In this embodiment, the general-purpose input / output interface circuit 348a further includes a plurality of transmit synchronization circuits T1 to T5 and a plurality of receive synchronization circuits R1 to R5. One of the general-purpose input / output transmit circuits GPX1 to GPX5 and one of the transmit synchronization circuits T1 to T5 are grouped as pins connected to the same data transmission group (e.g., data transmission groups GTX1 to GTX5). For example, the general-purpose input / output transmit circuit GPX1 and the transmit synchronization circuit T1 are grouped as pins connected to data transmission group GTX1, and the general-purpose input / output transmit circuit GPX2 and the transmit synchronization circuit T2 are grouped as pins connected to data transmission group GTX2. The remaining parts can also be inferred in this way and are shown in the drawings, so they will not be repeated here.

[0043] One of the general-purpose input / output receiver circuits GPE1 to GPE5 and one of the receiver synchronization circuits R1 to R5 are grouped together as pins connected to the same data reception group (e.g., data reception groups GRX1 to GRX5). For example, the general-purpose input / output receiver circuit GPE1 and the receiver synchronization circuit R1 are grouped together as pins connected to data reception group GRX1, and the general-purpose input / output receiver circuit GPE2 and the receiver synchronization circuit R2 are grouped together as pins connected to data reception group GRX2. The remaining parts can also be estimated in this way and shown in the diagram, so they will not be repeated here.

[0044] Transmit synchronization circuits T1 to T5 are used to transmit a transmit synchronization signal (usually a clock signal or data ready signal) and to receive a receive synchronization signal (usually a clock signal or data ready signal from the receiving end). Receive synchronization signals R1 to R5 are used to receive a transmit synchronization signal (usually a clock signal or data ready signal from the transmitting end) and to transmit a receive synchronization signal (usually a clock signal or data ready signal).

[0045] In embodiments of the present invention, the semiconductor device (e.g., semiconductor device 100) further includes a channel controller 810. The channel controller 810 is coupled to the transmit multiplexers TMX1-TMX3 and the receive multiplexers RMX1-RMX4 to control the output terminals of each transmit multiplexer TMX1-TMX3 coupled to one of the first and second input terminals, and to control the output terminals of each receive multiplexer RMX1-RMX4 coupled to one of the first and second input terminals, based on a channel test. Furthermore, the channel controller 810 may first test the channels (i.e., between connected pins / data transmit group and data receive group) before initiating communication, that is, to test whether the channels are valid by transmitting and receiving data. If all channels are valid, data may be transmitted and received through the pre-configured channels. If there are invalid channels and they are within fault tolerance limits, data may be transmitted and received through the valid channels. Furthermore, after communication, the channel controller 810 may perform a data / channel handshake using transmit synchronization circuits (e.g., transmit synchronization circuits T1-T5) and receive synchronization circuits (e.g., receive synchronization circuits R1-R5).

[0046] In embodiments of the present invention, the channel controller 810 may be configured within the input / output controller 346, and the channel controllers 810 between various semiconductor devices (e.g., semiconductor devices 100-700) may be connected to each other in a communicative manner to perform channel testing.

[0047] Figure 9 is a flowchart of a communication method for multiple semiconductor devices according to one embodiment of the present invention. Referring to Figure 9, in this embodiment, the communication method for semiconductor devices includes the following steps: In step S110, at least one output data provided by at least one semiconductor component is reconstructed into at least one parallel transmit data by a scalable digital interface circuit. In step S120, the at least one parallel transmit data is transmitted to an external semiconductor device via parallel transmission by at least one of a plurality of data transmit groups of a plurality of pins. In step S130, at least one parallel receive data is received from the external semiconductor device by at least one of a plurality of data receive groups of pins. In step S140, the at least one parallel receive data is reconstructed into at least one input data by the scalable digital interface circuit and provided to at least one semiconductor component. The order of steps S110, S120, S130, and S140 is illustrative, and embodiments of the present invention are not limited thereto. Details of steps S110, S120, S130, and S140 can be found in the embodiments shown in Figures 1 to 8 and will not be repeated here.

[0048] In summary, the semiconductor device and communication method for the semiconductor device according to embodiments of the present invention transmit data via a large number of channels used for parallel transmission. In this case, the signal frequency can be further reduced to save interface power consumption and reduce the complexity and manufacturing cost of the interface circuit. In addition, large-scale parallel transmission can improve actual transmission performance while achieving low power consumption and a high-performance data transmission interface. Furthermore, since signals are transmitted between semiconductor devices via digital connections, the manufacturing process of the semiconductor devices can be freely changed without affecting the connection method. Moreover, it is not necessary to have the same number of pins for transmitting signals between semiconductor devices, improving the flexibility of mix-and-match transmission between semiconductor devices.

[0049] Although the present invention has been disclosed above as embodiments, it is not intended to limit the invention. Those skilled in the art can make any modifications without departing from the spirit and scope of the invention. Accordingly, the scope of protection of the present invention shall be determined by the claims. [Industrial applicability]

[0050] The semiconductor device and communication method between semiconductor devices using parallel transmission according to the present invention can be applied to a system for packaging multiple semiconductor devices. [Explanation of symbols]

[0051] 10: Integrated Circuits 100, 200, 100a, 200a, 100b, 200b, 300, 400, 500, 600, 700: Semiconductor devices 110_1~110_n, 210_1~210_p: Memory Units 120_1~120_m, 220_1~220_q: Calculation Units 130, 230: Signal bus 140, 240, 340, 540: Scalable Digital Interface Circuits 341, 541: Bus package circuit 342, 542: Address / Data Reconfiguration Registers 343, 543_1~543_x: Transmit Reassembler 344, 544_1~544_x: Receiver Reassembler 345, 345a, 545_1~545_x: Transmit buffer 346, 546_1~546_x: Input / Output Controllers 347, 347a, 547_1~547_x: Receive buffer 348, 348a, 548_1~548_x: General-purpose input / output interface circuits 800: Circuit board Din: Input data Dout: Output data DPE1~DPE4: Received data section Dprce: Parallel received data Dpsent: Parallel transmission data DPX1~DPX4: Transmission data section GPE1~GPE5: General-purpose input / output receiving circuit GPRX1, GPRX2, GPRX3, GPRX4, GPRX51, GPRX52, GPRX6, GPRX7: Receive pins GPTX1, GPTX2, GPTX3, GPTX4, GPTX51, GPTX52, GPTX6, GPTX7: Transmit pins GPX1~GPX5: General-purpose input / output transmission circuit R1~R5: Receiver synchronization circuit RMX1~RMX4: Receiver Multiplexer T1~T5: Transmitter synchronization circuit RDL: Redistribution layer TMX1~TMX3: Transmitter Multiplexer TVA: Through-electrode of silicon S110, S120, S130, S140: Step

Claims

1. Multiple pins that can be divided into multiple data transmission groups and multiple data reception groups, A semiconductor component that provides at least one output data and receives at least one input data, A scalable digital interface circuit coupled to at least one of the data transmission groups, at least one of the data reception groups, and at least one semiconductor component, A signal bus coupled to at least one semiconductor component and the scalable digital interface circuit, Includes, The at least one semiconductor component includes at least one storage unit or at least one arithmetic unit, The scalable digital interface circuit transmits at least one parallel transmission data to an external semiconductor device via parallel transmission, reconstructs the at least one output data into the at least one parallel transmission data, receives at least one parallel reception data from the external semiconductor device via parallel transmission, and reconstructs the at least one parallel reception data into the at least one input data. Semiconductor equipment.

2. The at least one output data and the at least one input data each include at least one of the following: an advanced high-performance bus signal, an advanced expandable interface signal, a serial bus signal, and a parallel bus signal. The semiconductor device according to claim 1.

3. The number of connections between the pins of the data transmission group and the multiple data reception pins of the external semiconductor device is less than or equal to the smaller of the number of pins in a single data transmission group and the number of data reception pins, with the number of pins in the data transmission group being the unit of the number of pins. The semiconductor device according to claim 1.

4. When the transmission speed of the pins of the data transmission group is higher than the transmission speed of the data transmission group, the utilization rate of the connection portion between the pins of the data transmission group and the data receiving pins of the external semiconductor device increases. The semiconductor device according to claim 3.

5. When the transmission speed of the at least one output data and the at least one input data increases, the utilization rate of the connection portion between the pins of the data transmission group and the data reception pins of the external semiconductor device increases. The semiconductor device according to claim 3.

6. The aforementioned scalable digital interface circuit is A bus package circuit coupled to the aforementioned signal bus, The address / data reconfiguration register coupled to the bus package circuit, A transmit assembler coupled to the address / data reconstruction register, A receive rearranger coupled to the address / data reconstruction register, A transmit buffer coupled to the transmit rearranger, A receive buffer coupled to the aforementioned receive rearranger, A general-purpose input / output interface circuit coupled to the transmit buffer and the receive buffer, An input / output controller is coupled to the transmit buffer and the receive buffer and configured to control the transmit buffer and the receive buffer. Includes, When the bus package circuit receives the at least one output data from the at least one semiconductor component via the signal bus, the at least one output data is temporarily stored in the address / data reconfiguration register, the transmit reassembler then reconfigures the at least one output data into the at least one parallel transmit data for temporary storage in the transmit buffer, and the general-purpose input / output interface circuit transmits the at least one parallel transmit data temporarily stored in the transmit buffer to the external semiconductor device via at least one of the data transmission group. When the general-purpose input / output interface circuit receives at least one parallel received data from the external semiconductor device via at least one of the data receiving group, the at least one parallel received data is temporarily stored in the receive buffer, the receive reassembler then reconstructs the at least one parallel received data into at least one input data for temporary storage in the address / data reconstruction register, and the bus package circuit provides the at least one input data temporarily stored in the address / data reconstruction register to the at least one semiconductor component via the signal bus. The semiconductor device according to claim 5.

7. The general-purpose input / output interface circuit is, A plurality of general-purpose input / output transmission circuits, each individually configured to receive at least one of the transmission data portions of the at least one parallel transmission data, Multiple transmit synchronization circuits configured to send transmit synchronization signals and receive receive synchronization signals, Multiple general-purpose input / output receiving circuits, each individually configured to receive at least one of the received data portions of the at least one parallel received data via the aforementioned pins, Multiple receiving synchronization circuits are configured to receive the aforementioned transmission synchronization signal and send the aforementioned receiving synchronization signal, A plurality of transmit multiplexers each having a first input terminal that receives a first transmit data portion of at least one transmit data portion from the transmit buffer, a second input terminal that receives a second transmit data portion adjacent to the first transmit data portion of at least one transmit data portion from the transmit buffer, and an output terminal coupled to one of the general-purpose input / output transmit circuits, A plurality of receiving multiplexers each having a first input terminal coupled to a first general-purpose input / output receiving circuit of the general-purpose input / output receiving circuit, a second input terminal coupled to a second general-purpose input / output receiving circuit adjacent to the first general-purpose input / output receiving circuit of the general-purpose input / output receiving circuit, and an output terminal that provides one of the at least one received data section. Includes, One of the transmission synchronization circuit and the general-purpose input / output transmission circuit is coupled to multiple pins of the same data transmission group in the data transmission group. One of the receiving synchronization circuit and the general-purpose input / output receiving circuit is coupled to multiple pins of the same data receiving group of the data receiving group. The semiconductor device according to claim 6.

8. A channel controller is coupled to the transmit multiplexer and the receive multiplexer in order to control the coupling of each output terminal of the transmit multiplexer to one of the first input terminal and the second input terminal, and to control the coupling of each output terminal of the receive multiplexer to one of the first input terminal and the second input terminal, based on a channel test. This also includes, The semiconductor device according to claim 7.

9. The semiconductor device and the external semiconductor device include a chip, and the at least one semiconductor component includes at least one crystal grain. The semiconductor device according to claim 1.

10. A method of communication between semiconductor devices, Reconstructing at least one output data provided by at least one semiconductor component into at least one parallel transmit data by a scalable digital interface circuit, The above-mentioned at least one parallel transmission data is transmitted to an external semiconductor device via parallel transmission by at least one of multiple data transmission groups of multiple pins, At least one parallel received data is received from the external semiconductor device by at least one of the multiple data receiving groups of the aforementioned pins, The at least one parallel received data is reconstructed into at least one input data, and the at least one input data is provided to the at least one semiconductor component by the scalable digital interface circuit. Includes, The at least one semiconductor component includes at least one storage unit or at least one arithmetic unit, The at least one semiconductor component is coupled to the scalable digital interface circuit via a signal bus. Communication method.

11. The at least one output data and the at least one input data each include at least one of the following: an advanced high-performance bus signal, an advanced expandable interface signal, a serial bus signal, and a parallel bus signal. The communication method according to claim 10.

12. The number of connections between the pins of the data transmission group and the multiple data reception pins of the external semiconductor device is less than or equal to the smaller of the number of pins in a single data transmission group and the number of data reception pins, with the number of pins in the data transmission group being the unit of the number of pins. The communication method according to claim 10.

13. When the transmission speed of the pins of the data transmission group is higher than the transmission speed of the data transmission group, the utilization rate of the connection portion between the pins of the data transmission group and the data receiving pins of the external semiconductor device is increased. This also includes, The communication method according to claim 12.

14. When the transmission speed of the at least one output data and the at least one input data increases, the utilization rate of the connection portion between the pins of the data transmission group and the data reception pins of the external semiconductor device is increased. This also includes, The communication method according to claim 12.

15. The semiconductor device and the external semiconductor device include a chip, and the at least one semiconductor component includes at least one crystal grain. The communication method according to claim 10.

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