Current limiting circuit, display device, and current limiting method

Abstract

To provide a current limiting circuit, etc., with which it is possible to suppress the power consumption of a display panel, even when the luminance indicated by a video signal rapidly increases.SOLUTION: A current limiting circuit 40 accepts as input a video signal for a display panel having a plurality of pixels and limits the current consumption of the plurality of pixels. The current limiting circuit comprises: a first gain computing circuit 51 for computing a first gain to be multiplied to the video signal, on the basis of first power consumption that represents the power consumption in the plurality of pixels corresponding to the video signal; a second gain computing circuit 52 for computing a second gain to be multiplied to the video signal, on the basis of the first power consumption and a change rate of the first power consumption; a gain selection circuit 55 for selecting one of the first gain and the second gain as the gain to be multiplied to the video signal; and a gain multiplication circuit 44 for multiplying the video signal and the gain together.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a current limiting circuit, a display device, and a current limiting method.

Background Art

[0002] Conventionally, display devices in which each pixel, such as an organic EL (Electro-Luminescence) display device, includes a self-emitting element have been developed. In such display devices, an increase in the size of the display panel has been demanded. As the size of the display panel increases, the power consumption of the display device increases. Therefore, a technique for suppressing the power consumption of the display device is known (see Patent Document 1). In the display device disclosed in Patent Document 1, the power consumption of the display panel is calculated for each horizontal period (horizontal synchronization period) based on a video signal, and the current supplied to each pixel of the display panel is limited based on the calculation result, thereby controlling the power consumption of the display panel. As a result, in the display device disclosed in Patent Document 1, an attempt is made to suppress the power consumption of the display panel to a value below the control target power value.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the display device disclosed in Patent Document 1, for example, when the luminance indicated by the video signal rapidly increases, such as when switching from all-black display to all-white display, the power consumption of the display panel can greatly exceed the control target power value.

[0005] This disclosure has been made in view of the above-mentioned problems, and aims to provide a current limiting circuit and the like that can suppress the power consumption of a display panel even when the brightness indicated by the video signal increases rapidly. [Means for solving the problem]

[0006] To achieve the above objective, a current limiting circuit according to one aspect of the present disclosure is a current limiting circuit that receives a video signal for a display panel having a plurality of pixels and limits the current consumption of the plurality of pixels, comprising: a first gain calculation circuit that calculates a first gain for multiplying the video signal based on a first power consumption which is the power consumption of the plurality of pixels corresponding to the video signal; a second gain calculation circuit that calculates a second gain for multiplying the video signal based on the first power consumption and the rate of change of the first power consumption; a gain selection circuit that selects one of the first gain and the second gain as the gain to be multiplied by the video signal; and a gain multiplication circuit that multiplies the video signal and the gain.

[0007] Furthermore, in order to achieve the above objective, a display device according to one aspect of the present disclosure comprises the current limiting circuit and the display panel.

[0008] Furthermore, in order to achieve the above objective, a current limiting method according to one aspect of the present disclosure is a current limiting method for limiting the current consumption of a plurality of pixels having a display panel, and includes: a first gain calculation step of calculating a first gain for multiplying the video signal based on a first power consumption which is the power consumption of the plurality of pixels corresponding to a video signal for the display panel; a second gain calculation step of calculating a second gain for multiplying the video signal based on the first power consumption and the rate of change of the first power consumption; a gain selection step of selecting one of the first gain and the second gain as the gain to be multiplied by the video signal; and a gain multiplication step of multiplying the video signal and the gain. [Effects of the Invention]

[0009] According to this disclosure, it is possible to provide a current limiting circuit and the like that can suppress the power consumption of the display panel even when the brightness of the video signal increases rapidly. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a block diagram showing the configuration of a display device according to an embodiment. [Figure 2] Figure 2 is a block diagram showing the functional configuration of a current limiting circuit according to an embodiment. [Figure 3] Figure 3 is a block diagram showing the functional configuration of the weighted average circuit in the current limiting circuit according to the embodiment. [Figure 4] Figure 4 is a block diagram showing the functional configuration of the gain multiplication circuit in the current limiting circuit according to the embodiment. [Figure 5] Figure 5 is a block diagram showing the functional configuration of the display panel of the display device according to the embodiment. [Figure 6] Figure 6 is a circuit diagram showing an example of the configuration of subpixels constituting a pixel according to the embodiment. [Figure 7] Figure 7 shows an example of a write signal input to a subpixel according to the embodiment. [Figure 8] Figure 8 is a schematic diagram showing the transition of the display state of the display unit according to the embodiment. [Figure 9] Figure 9 is a flowchart showing the flow of the current limiting method according to the embodiment. [Figure 10] Figure 10 is a schematic diagram showing the configuration of the first screen data storage unit according to the embodiment. [Figure 11] Figure 11 is a flowchart showing the first gain calculation method in the first gain calculation circuit according to the embodiment. [Figure 12] Figure 12 is a schematic diagram showing the configuration of the second screen data storage unit according to the embodiment. [Figure 13] Figure 13 is a flowchart showing the second gain calculation method in the second gain calculation circuit according to the embodiment. [Figure 14]FIG. 14 is a graph showing the time waveforms of the power consumption of a plurality of pixels when changing from all-black display to all-white display in each display device according to Comparative Example 1, Comparative Example 2, and the embodiment. [Figure 15] FIG. 15 is a block diagram showing the relationship between the current limiting circuit according to the modification and the display device. [Figure 16] FIG. 16 is an external view of a PC incorporating the current limiting circuit according to the modification. [Figure 17] FIG. 17 is an external view of a hard disk recorder incorporating the current limiting circuit according to the modification. [Figure 18] FIG. 18 is an external view of a thin flat TV incorporating the display device according to the embodiment.

Embodiments of the Invention

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that each of the embodiments described below shows a specific example in the present disclosure. Therefore, the numerical values, shapes, materials, components, arrangement positions and connection forms of the components, processes, and the order of the processes shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0012] Each figure is a schematic diagram and is not necessarily drawn precisely. Also, in each figure, the same reference numerals are given to substantially the same configurations, and overlapping explanations are omitted or simplified.

[0013] (Embodiment) The current limiting circuit, display device, and current limiting method according to the embodiment will be described.

[0014] [1. Overall Configuration of the Display Device] The overall configuration of the display device according to the embodiment will be described with reference to FIGS. 1 to 5.

[0015] Figure 1 is a block diagram showing the configuration of the display device 10 according to this embodiment. Figure 2 is a block diagram showing the functional configuration of the current limiting circuit 40 according to this embodiment. Figures 3 and 4 are block diagrams showing the functional configurations of the weighted average circuit 45 and the gain multiplication circuit 44, respectively, of the current limiting circuit 40 according to this embodiment. Figure 5 is a block diagram showing the functional configuration of the display panel 60 provided in the display device 10 according to this embodiment.

[0016] As shown in Figure 1, the display device 10 includes a current limiting circuit 40 and a display panel 60.

[0017] The display panel 60 is a panel that displays an image corresponding to a video signal, each having multiple pixels, each containing an elemental light. As shown in Figure 5, the display panel 60 has a display unit 70, a writing processing unit 62, a source driver 68, and a writing shift register 64. The display unit 70 has multiple pixels arranged in a matrix and displays an image corresponding to a video signal. The writing processing unit 62 outputs a control signal and a data signal for writing display data to the display unit 70. The writing processing unit 62 is a circuit included in a so-called TCON (Timing-Controller) chip. The source driver 68 outputs a data signal to the display unit 70. The writing shift register 64 outputs a writing signal to the display unit 70, which is a control signal for writing the data signal to the display unit 70.

[0018] The current limiting circuit 40 is a circuit that receives a video signal for a display panel 60 having multiple pixels and suppresses the power consumption of the display panel 60 by limiting the current consumption of the multiple pixels. In this embodiment, the current limiting circuit 40 limits the current supplied to the multiple pixels so as to prevent the power value supplied to the multiple pixels, which corresponds to the power consumption of the display panel 60, from exceeding the control target power value. The control target power value is the control target upper limit value for the power consumption of the multiple pixels. The current limiting circuit 40 reduces the pixel value of the video signal by multiplying the pixel value included in the video signal by a gain of 1 or less, and limits the current consumption of the multiple pixels by outputting a video signal including the reduced pixel value to the display panel 60. As shown in Figure 2, the current limiting circuit 40 includes a weighted average circuit 45, a horizontal period data calculation circuit 46, a first screen data storage unit 41, a second screen data storage unit 42, a coefficient generation circuit 47, a multiplication circuit 48, a first gain calculation circuit 51, a second gain calculation circuit 52, a gain selection circuit 55, and a gain multiplication circuit 44.

[0019] The current limiting circuit 40 can be implemented, for example, as an integrated circuit. The current limiting circuit 40 may be integrated as part of the TCON chip together with the writing processing unit 62 included in the display panel 60, or it may be a standalone integrated circuit. Furthermore, the integration form of the current limiting circuit 40 is not limited to these. The current limiting circuit 40 may also be implemented using electrical circuits other than integrated circuits.

[0020] The weighted average circuit 45 is a circuit that calculates the weighted average of the pixel values ​​included in the video signal. In this embodiment, the video signal includes RGB signals. As shown in Figure 3, the weighted average circuit 45 multiplies each of the RGB display data by a weighting coefficient (R signal weighting coefficient, G signal weighting coefficient, and B signal weighting coefficient) corresponding to the power consumption characteristics of each RGB pixel of the display unit 70, and calculates their sum.

[0021] The horizontal period data calculation circuit 46 calculates horizontal period power conversion data corresponding to the displayed data for each horizontal period. In this embodiment, the horizontal period data calculation circuit 46 calculates the horizontal period power conversion data (level integrated value) using the weighted average value or average value of the weighted average output by the weighted average circuit 45 during the horizontal period.

[0022] The first screen data storage unit 41 is a storage unit that stores power conversion data for at least one frame. In this embodiment, the first screen data storage unit 41 receives power conversion data output by the horizontal period data calculation circuit 46, and stores power conversion data for one frame.

[0023] The first gain calculation circuit 51 is a circuit that calculates a first gain to multiply the video signal based on the first power consumption, which is the power consumed by multiple pixels corresponding to the video signal. The first power consumption is the power consumed by multiple pixels when the video signal is input to the display panel 60. The first gain calculation circuit 51 outputs the calculated first gain to the gain selection circuit 55.

[0024] The first gain calculation circuit 51 calculates a first gain for multiplication to the video signal based on the power conversion data stored in the first screen data storage unit 41 and the control target power value. In this embodiment, the first gain calculation circuit 51 calculates a first screen power value, which is a predicted value of the power consumption at multiple pixels corresponding to one frame of video signal, based on the power conversion data stored in the first screen data storage unit 41. The first screen power value is an example of first power consumption. The first gain calculation circuit 51 calculates the sum of the horizontal period power conversion data for the number of horizontal lines stored in the first screen data storage unit 41 as the first screen power value.

[0025] The first gain calculated by the first gain calculation circuit 51 is less than 1 if the first screen power value exceeds the control target power value. More specifically, the first gain calculated by the first gain calculation circuit 51 is less than or equal to the value obtained by dividing the control target power value by the screen power value if the first screen power value exceeds the control target power value. In this embodiment, the first gain is the value obtained by dividing the control target power value by the first screen power value if the first screen power value exceeds the control target power value. The first gain calculation circuit 51 sets the first gain to 1 if the first screen power value does not exceed the control target power value. In this embodiment, the first gain calculation circuit 51 calculates the first gain by dividing the control target power value by the screen power value if the first screen power value exceeds the control target power value.

[0026] The first gain calculation circuit 51 calculates and outputs the first gain at intervals shorter than the vertical period of the video signal. In this embodiment, the first gain calculation circuit 51 calculates and outputs the first gain at intervals of the horizontal period.

[0027] The method for setting the first gain is not limited to this. For example, the first gain calculation circuit 51 may have a lookup table that shows the relationship between a value corresponding to the first screen power value and the first gain, and the first gain corresponding to the first screen power value may be set based on this lookup table.

[0028] The coefficient generation circuit 47 is a circuit that generates a sensitivity coefficient. The sensitivity coefficient is a coefficient that increases as the rate of change of the first power consumption increases. In this embodiment, the sensitivity coefficient Cs is expressed by the following equation (1) using the sensitivity level lv, the frame average image level apl, the rate of change dl, and the coefficient of change diff.

[0029] Cs = 1 + lv × dl × diff × apl (1)

[0030] Here, the sensitivity level lv is a coefficient that adjusts the sensitivity of the sensitivity coefficient Cs to the current limiting in the current limiting circuit 40, and is set to a value greater than 0 and less than or equal to 16.

[0031] The frame-average image level (apl) is a value corresponding to the average number of grayscale levels in an image displayed in one frame. In this embodiment, the ratio of the first screen power value to the upper limit of the first screen power value is used as the frame-average image level. The upper limit of the first screen power value is the first screen power value when each of multiple pixels is set to its maximum brightness (i.e., when all white is displayed). The frame-average image level (apl) is an example of a value corresponding to the first power consumption.

[0032] The rate of change dl is the rate of change of the frame-average image level apl with respect to time. The rate of change dl is the ratio of the amount of change in the frame-average image level apl for periods shorter than the vertical period to the upper limit of the frame-average image level apl. The upper limit of the frame-average image level is the frame-average image level when each of multiple pixels is set to its maximum brightness (i.e., when all pixels are displayed in white). The rate of change dl is a value between -1 and 1. In this embodiment, the rate of change dl is calculated for each horizontal period.

[0033] The coefficient of change diff is a coefficient that adjusts the influence of the rate of change dl on the sensitivity coefficient Cs, and is set to a value between 0 and 1, for example. In this embodiment, when the rate of change dl is 0 or less, that is, when the frame average image level apl has not increased, the coefficient of change diff is set to 0. In this case, the sensitivity coefficient Cs becomes 1.

[0034] The sensitivity coefficient Cs is a coefficient that increases as the rate of change dl (i.e., the rate of change of the first power consumption) of the frame-average image level apl increases, as shown in equation (1) above. Note that the formula for expressing the sensitivity coefficient Cs is not limited to equation (1). For example, the rate of change diff and the sensitivity level lv may be combined into a single coefficient. Alternatively, a coefficient to adjust the influence of the frame-average image level apl on the sensitivity coefficient Cs may be multiplied by the frame-average image level apl in equation (1).

[0035] The multiplication circuit 48 is a circuit that multiplies the power conversion data by a sensitivity coefficient. The multiplication circuit 48 multiplies the horizontal period power conversion data output from the horizontal period data calculation circuit 46 by the sensitivity coefficient output from the coefficient generation circuit 47, and outputs the product obtained by the multiplication to the second screen data storage unit 42.

[0036] The second screen data storage unit 42 is a storage unit that stores values ​​obtained by multiplying power conversion data by a sensitivity coefficient. In this embodiment, the second screen data storage unit 42 stores converted data obtained by multiplying each of the horizontal period power conversion data for one frame by a sensitivity coefficient that is generated immediately after each horizontal period power conversion data is stored in the first screen data storage unit 41.

[0037] The second gain calculation circuit 52 is a circuit that calculates a second gain to multiply the video signal based on the first power consumption, which is the power consumption of multiple pixels corresponding to the video signal, and the rate of change of the first power consumption. In this embodiment, the second gain calculation circuit 52 calculates the second gain based on the second power consumption. Here, the second power consumption is the power consumption of multiple pixels corresponding to the value obtained by multiplying the video signal by the sensitivity coefficient generated by the coefficient generation circuit 47. In other words, the second power consumption is the power consumed by multiple pixels when the signal obtained by multiplying the video signal by the sensitivity coefficient is input to the display panel 60. The second gain calculation circuit 52 outputs the calculated second gain to the gain selection circuit 55. As described above, the sensitivity coefficient used in the calculation of the second power consumption is a coefficient that depends on the frame average image level apl corresponding to the first power consumption and its rate of change dl. Therefore, the second power consumption is a value determined based on the first power consumption and the rate of change of the first power consumption. Thus, in this embodiment, the second gain calculation circuit 52 calculates the second gain based on the second power consumption, thereby calculating the second gain based on the first power consumption and the rate of change of the first power consumption.

[0038] The second gain calculation circuit 52 calculates a second gain for multiplication to the video signal based on the conversion data stored in the second screen data storage unit 42 and the control target power value. In this embodiment, the second gain calculation circuit 52 calculates a second screen power value, which is a predicted value of the power consumption at multiple pixels corresponding to the value obtained by multiplying the video signal for one frame by a sensitivity coefficient, based on the conversion data stored in the second screen data storage unit 42. The second screen power value is an example of second power consumption and is determined based on the first power consumption and the rate of change of the first power consumption. The second gain calculation circuit 52 calculates the second screen power value as the sum of the conversion data of the number of horizontal lines stored in the second screen data storage unit 42.

[0039] The second gain calculated by the second gain calculation circuit 52 is less than 1 if the second screen power value exceeds the control target power value. More specifically, the second gain calculated by the second gain calculation circuit 52 is less than or equal to the value obtained by dividing the control target power value by the screen power value if the second screen power value exceeds the control target power value. In this embodiment, the second gain is the value obtained by dividing the control target power value by the second screen power value if the second screen power value exceeds the control target power value. The second gain calculation circuit 52 sets the second gain to 1 if the second screen power value does not exceed the control target power value. In this embodiment, the second gain calculation circuit 52 calculates the second gain by dividing the control target power value by the screen power value if the second screen power value exceeds the control target power value.

[0040] The second gain calculation circuit 52 calculates and outputs the second gain at intervals shorter than the vertical period of the video signal. In this embodiment, the second gain calculation circuit 52 calculates and outputs the second gain at intervals of the horizontal period.

[0041] The method for setting the second gain is not limited to this. For example, the second gain calculation circuit 52 may have a lookup table that shows the relationship between a value corresponding to the second screen power value and the second gain, and the second gain corresponding to the second screen power value may be set based on this lookup table.

[0042] The gain selection circuit 55 is a circuit that selects one of the first gain and the second gain as the gain to be multiplied by the video signal. The gain selection circuit 55 receives the first gain and the second gain from the first gain calculation circuit 51 and the second gain calculation circuit 52, respectively. In this embodiment, the gain selection circuit 55 selects the first gain as the gain when the first power consumption is decreasing (i.e., when the first power consumption decreases as time passes), and selects the second gain as the gain when the first power consumption is increasing (i.e., when the first power consumption increases as time passes). Furthermore, if the first power consumption is not changing (i.e., when the first power consumption is constant with respect to time), the gain selection circuit 55 selects the gain that was selected immediately before, from the first gain and the second gain. Also, if the change in the first power consumption with respect to time cannot be determined, such as immediately after the start of input of the video signal to the current limiting circuit 40, the gain selection circuit 55 selects the first gain.

[0043] In this embodiment, the conversion data stored in the second screen data storage unit 42 is used to determine the change in the first power consumption over time. The gain selection circuit 55 calculates the sum of the conversion data of the number of horizontal lines stored in the second screen data storage unit 42 as the second screen power value, and selects either the first gain or the second gain based on the increase or decrease in the second screen power value. The increase or decrease in the second screen power value corresponds to the increase or decrease in the first power consumption, respectively.

[0044] In addition, in the gain selection circuit 55, information other than the conversion data stored in the second screen data storage unit 42 may be used to determine the change in the first power consumption with respect to time. For example, power conversion data stored in the first screen data storage unit 41 may be used.

[0045] The gain multiplication circuit 44 is a circuit that multiplies the video signal by a gain. The gain multiplication circuit 44 multiplies the video signal by the gain selected by the gain selection circuit 55. In this embodiment, as shown in Figure 5, each RGB signal included in the video signal is multiplied by a gain. As a result, when the screen power value exceeds the control target power value, the video signal is multiplied by a gain of less than 1, thereby reducing the brightness of the video signal. Therefore, the current supplied to multiple pixels of the display panel 60 is limited.

[0046] The multiple pixels of the display panel 60 will be explained with reference to Figure 6. Figure 6 is a circuit diagram showing an example of the configuration of subpixels that constitute a pixel according to this embodiment. Figure 6 shows a subpixel that uses an organic EL element as a self-luminescent element. The pixel according to this embodiment includes three subpixels corresponding to the three colors RGB. The subpixel shown in Figure 6 is a subpixel for emitting red (R) light. The subpixels for emitting green and blue light have a circuit configuration similar to the circuit shown in Figure 6.

[0047] As shown in Figure 6, the subpixel includes a TFT (Thin Film Transistor) 81, a capacitor 84, a TFT 82, and a self-luminescent element 85r.

[0048] The data signal, which is the output signal of the source driver 68, is input to one end of TFT81. Capacitor 84 is connected to TFT81. The control terminal of TFT82 is connected to the connection point between TFT81 and capacitor 84. The self-luminous element 85r is connected to TFT82.

[0049] The TFT81 switches on and off based on the write signal, which is a control signal output by the write shift register 64. When the TFT81 is turned on by the write signal within one horizontal period, the data signal, which is a source driver output signal corresponding to the signal level to be written to the pixel, is held in the capacitor 84.

[0050] After the write signal is turned off, a current corresponding to the voltage held in capacitor 84 flows to TFT 82, and the self-luminous element 85r lights up.

[0051] [2. Operation of the current limiting circuit and current limiting method] The operation of the current limiting circuit 40 and the current limiting method will be described below.

[0052] First, before explaining the operation of the current limiting circuit 40, the signals input to the sub-pixels shown in Figure 6 will be explained using Figure 7. Figure 7 is a diagram showing an example of a write signal input to a sub-pixel according to this embodiment. The display device 10 writes the data signal output by the source driver 68 for each horizontal period to the display unit 70 using the write signal, and emits light in units of horizontal lines (hereinafter also simply referred to as "lines"). The display device 10 repeats this operation for each vertical period.

[0053] Next, the transition of the display state of the display unit 70 will be explained using Figure 8. Figure 8 is a schematic diagram showing the transition of the display state of the display unit 70 according to this embodiment. In Figure 8, the display screen transitions from the display at time T1 to time T2, and from time T2 to time T3. At time T1, which corresponds to the end of the m-th frame shown in Figure 8, the screen of the m-th frame is displayed. Here, the write shift register 64, which outputs a write signal, which is a control signal for writing data signals to each pixel, outputs the write signal to scan from the top to the bottom of the screen, starting from the beginning of the display area of ​​the display unit 70. Therefore, at time T2, which corresponds to the middle of the n-th frame (i.e., the m+1-th frame), which is the frame after the m-th frame, the upper half of the screen becomes the screen of the n-th frame, and the lower half remains the screen of the m-th frame. At time T3, which corresponds to the end of the n-th frame, the display area is scanned to the bottom, and the entire screen becomes the screen of the n-th frame.

[0054] Next, the operation of the current limiting circuit 40 and the current limiting method according to this embodiment will be explained with reference to Figure 9. Figure 9 is a flowchart showing the flow of the current limiting method according to this embodiment.

[0055] As shown in Figure 9, first, the first gain calculation circuit 51 of the current limiting circuit 40 calculates a first gain to multiply the video signal based on the first power consumption, which is the power consumption of multiple pixels corresponding to the video signal for the display panel 60 (first gain calculation step S1). The first gain calculation step S1 will be described below.

[0056] The first gain calculation circuit 51 uses power conversion data in the calculation of the first gain. The configuration of the first screen data storage unit 41, which stores this power conversion data, will be explained with reference to Figure 10. Figure 10 is a schematic diagram showing the configuration of the first screen data storage unit 41 according to this embodiment. As shown in Figure 10, the first screen data storage unit 41 stores the power conversion data output from the horizontal period data calculation circuit 46. The power conversion data output from the horizontal period data calculation circuit 46 is stored in the first screen data storage unit 41 as the power value of the i-th line. When the rewriting of the next frame begins, the first screen data storage unit 41 rewrites the stored power values ​​in order from the first line.

[0057] Next, the calculation process in the first gain calculation circuit 51 will be explained using Figure 11. Figure 11 is a flowchart of the first gain calculation method in the first gain calculation circuit 51 according to this embodiment.

[0058] As shown in Figure 11, first, the first gain calculation circuit 51 calculates the first screen power value based on the horizontal period power conversion data stored in the first screen data storage unit 41 (S11). Specifically, it calculates the sum of the horizontal period power conversion data for the number of horizontal lines stored in the first screen data storage unit 41 as the first screen power value. As described above, the first screen power value is an example of the first power consumption.

[0059] Next, the first gain calculation circuit 51 determines whether the calculated first screen power value exceeds a predetermined control target power value (S12). If the first screen power value does not exceed the control target power value (No in S12), the first gain is set to 1 (S13). If the first screen power value exceeds the control target power value (Yes in S12), the ratio of the control target power value to the first screen power value is calculated as a first gain of less than 1 (S14).

[0060] As described above, the first gain is calculated.

[0061] Returning to Figure 9, the second gain calculation circuit 52 of the current limiting circuit 40 calculates a second gain to multiply the video signal based on the first power consumption and the rate of change of the first power consumption (second gain calculation step S2). The second gain calculation step S2 will be described below.

[0062] The second gain calculation circuit 52 uses the converted data in the calculation of the second gain. The configuration of the second screen data storage unit 42 that stores this converted data will be explained with reference to Figure 12. Figure 12 is a schematic diagram showing the configuration of the second screen data storage unit 42 according to this embodiment. As shown in Figure 12, the second screen data storage unit 42 stores converted data obtained by multiplying the power conversion data output from the horizontal period data calculation circuit 46 by a sensitivity coefficient. This converted data is stored in the second screen data storage unit 42 as the power value of the i-th line. When the rewriting of the next frame begins, the second screen data storage unit 42 rewrites the stored power values ​​in order from the first line.

[0063] Next, the calculation process in the second gain calculation circuit 52 will be explained using Figure 13. Figure 13 is a flowchart of the second gain calculation method in the second gain calculation circuit 52 according to this embodiment.

[0064] As shown in Figure 13, first, the second gain calculation circuit 52 calculates the second screen power value based on the conversion data stored in the second screen data storage unit 42 (S21). Specifically, it calculates the second screen power value as the sum of the conversion data for the number of horizontal lines stored in the second screen data storage unit 42. As described above, the second screen power value is an example of the second power consumption and is determined based on the first power consumption and the rate of change of the first power consumption.

[0065] Next, the second gain calculation circuit 52 determines whether the calculated second screen power value exceeds a predetermined control target power value (S22). If the second screen power value does not exceed the control target power value (No in S22), the second gain is set to 1 (S23). If the second screen power value exceeds the control target power value (Yes in S22), the ratio of the control target power value to the second screen power value is calculated as a second gain of less than 1 (S24).

[0066] As described above, the second gain is calculated.

[0067] Returning to Figure 9, the gain selection circuit 55 of the current limiting circuit 40 selects one of the first gain and the second gain as the gain to be multiplied by the video signal (gain selection step S3). The gain selection circuit 55 selects the first gain as the gain when the first power consumption is decreasing, and selects the second gain as the gain when the first power consumption is increasing.

[0068] Next, the gain multiplication circuit 44 of the current limiting circuit 40 multiplies the video signal by the gain (gain multiplication step S4). The gain multiplication circuit 44 multiplies the input video signal by the gain input from the gain selection circuit 55. In this embodiment, the gain multiplication circuit 44 multiplies the gain by each of the R signal, G signal, and B signal included in the video signal. By multiplying the video signal by the gain, the gain multiplication circuit 44 limits the current supplied to the multiple pixels of the display panel 60 when the screen power value exceeds the control target power value. As described above, the current limiting method according to this embodiment can limit the current consumption of the multiple pixels of the display panel 60.

[0069] [3. Effects] The effects of the display device 10 according to this embodiment will be explained in comparison with the display device according to the comparative example. Here, as the display device according to comparative example 1, a display device is used that differs from the display device 10 according to this embodiment in that it does not have a current limiting circuit, but is otherwise the same. As the display device according to comparative example 2, a display device is used that differs from the display device 10 according to this embodiment in that it has a conventional current limiting circuit, but is otherwise the same. The current limiting circuit provided in the display device according to comparative example 2 differs from the current limiting circuit 40 according to this embodiment in that it always uses the first gain according to this embodiment as the gain multiplied by the video signal.

[0070] The power consumption of multiple pixels in the display unit 70 will be explained using Figure 14. Figure 14 is a graph showing the time waveform of power consumption at multiple pixels when changing from a fully black display to a fully white display in each display device according to Comparative Example 1, Comparative Example 2, and this embodiment. In the example shown in Figure 14, the display unit 70 is changed from a fully black display to a fully white display (i.e., all pixels are white at maximum brightness) and then maintained in a fully white display. Figure 14 also shows images (a) to (d) displayed on the display unit 70 according to Comparative Example 2 and images (e) to (h) displayed on the display unit 70 according to this embodiment at each point in time.

[0071] As shown in images (a) and (e) of Figure 14, at time t=1.0 [frame time] in the graph of Figure 14, the display unit 70 of each display device is in a completely black display state. In this case, the current supplied to the multiple pixels of the display unit 70 is almost zero. Subsequently, when a video signal indicating a completely white display is input to each display device, the display unit 70 switches from black to white sequentially, starting from the line at the top of the display unit 70, for each horizontal period of the display unit 70. In this case, in the display device according to Comparative Example 1, all lines are switched to white according to the video signal input to the display device. In other words, the display device according to Comparative Example 1 corresponds to a display device in which the gain multiplied by the video signal is always 1.

[0072] In the display device according to Comparative Example 1, the display unit 70 is switched from black to white at maximum brightness, starting from the upper line, starting at time t=1.0. Accordingly, as shown in the graph in Figure 14, the power consumption gradually increases from 0%, reaching 100% at time t=2.0.

[0073] In the display device according to Comparative Example 2, when the display unit 70 switches from black to white sequentially from the upper edge line after time t=1.0, the lines near the upper edge are switched to white at maximum brightness according to the video signal. In this case, as shown in the graph of Figure 14, the power consumption exceeds the control target power value during the switch to white (see around time t=1.4 in the graph of Figure 14). In the example shown in Figure 14, the control target power value is 40% of the power consumption when white is displayed at maximum brightness across the entire screen. When the power consumption of multiple pixels exceeds the control target power value in this way, the current limiting circuit according to Comparative Example 2 multiplies the video signal by a gain of less than 1 (the first gain according to this embodiment). This limits the current supplied to multiple pixels.

[0074] For example, at time t=1.5 in Figure 14, the lines located in the upper half of the display unit 70 are switched from black to white. In the display device according to Comparative Example 2, in this state, as shown in image (b) of Figure 14, the brightness of the video signal is reduced by the current limiting circuit, so the brightness of the white display decreases as you move from the upper line towards the lower line. Specifically, the upper line of the display unit 70 is displayed in white as per the video signal, but the line located at the very bottom of the white lines in image (b) of Figure 14 (that is, the line located in the vertical center of the display unit 70) is displayed in white (i.e., gray) with a brightness lower than the brightness indicated by the video signal. Subsequently, the pixels located in the lower half of the display unit 70 are also displayed in white with a brightness lower than the brightness indicated by the video signal. In the example shown in Figure 14, the gain becomes less than 1 after about time t=1.4, and at time t=2.0, the gain is 0.4 (=40 / 100). As a result, at time t=2.0, as shown in image (c) of Figure 14, the display unit 70 according to Comparative Example 2 displays in all white, with brightness decreasing as it approaches the lower end of the display unit 70. At time t=2.0, the line near the upper end of the display unit 70 displays in white with brightness according to the video signal, so the power consumption of multiple pixels significantly exceeds the control target power value.

[0075] From time t=2.0 for one frame duration, the current supplied to multiple pixels is limited by the current limiting circuit. In the example shown in Figure 14, the gain is maintained at 0.4. As a result, at time t=3.0, after one vertical period has elapsed from time t=2.0, all lines are displayed as full white with a brightness lower than the brightness indicated by the video signal. This limits the power consumption of multiple pixels to below the control target power value from time t=3.0 onward.

[0076] As described above, in the display device according to Comparative Example 2, the power consumption of multiple pixels may temporarily exceed the control target power value by a large margin.

[0077] On the other hand, as shown in image (e) of Figure 14, the display unit 70 of the display device 10 according to this embodiment is in a completely black display state at time t=1.0 in the graph of Figure 14. The display unit 70 displays a completely black display when the video signal for one frame input to the display panel 60 shows a completely black display. When the video signal for one frame following the video signal showing a completely black display shows a completely white display, the first power consumption increases after time t=1.0. For this reason, the gain selection circuit 55 selects the second gain as the gain. As described above, the second screen power value used when calculating the second gain is calculated using the value obtained by multiplying the horizontal period power conversion data by the sensitivity coefficient. When the first power consumption increases, the sensitivity coefficient becomes greater than 1 (see equation (1) above), so the second screen power value becomes greater than the first screen power value calculated using the horizontal period power conversion data itself. Therefore, when the first power consumption increases, the second gain is smaller than the first gain. Also, the second gain becomes less than 1 before the first screen power value exceeds the control target power value. As shown in image (f) of Figure 14, the brightness of the video signal is reduced by the current limiting circuit 40, so, similar to image (b), the brightness of the white display decreases as you move from the upper line towards the lower line. Specifically, the upper line of the display unit 70 is displayed in white as per the video signal, but the line located at the very bottom of the lines displayed in white in image (b) of Figure 14 (i.e., the line located in the vertical center of the display unit 70) is displayed in white with a brightness lower than that indicated by the video signal and lower than that of the display unit 70 in Comparative Example 2 shown in image (b). Subsequently, the pixels located on the lower half of the display unit 70 are also displayed in white with a brightness lower than that indicated by the video signal and lower than that of the display unit 70 in Comparative Example 2. As a result, at time t=2.0, as shown in image (g) of Figure 14, the display unit 70 in this embodiment displays in all white, with the brightness decreasing as you move towards the lower end of the display unit 70.

[0078] At time t=2.0, the line near the top edge of the display unit 70 is displayed in white with the brightness as per the video signal, so the power consumption of multiple pixels slightly exceeds the control target power value. However, the second gain is smaller than the gain in Comparative Example 2. For example, at time t=2.0, the second gain is smaller than the gain (0.4) in the Comparative Example. Therefore, the power consumption of multiple pixels in this embodiment is suppressed compared to the power consumption of multiple pixels in Comparative Example 2.

[0079] From time t=2.0 onward, the switch from black display to white display is completed, and the first power consumption becomes constant. Therefore, from time t=2.0 onward, the sensitivity coefficient becomes 1, and the second gain becomes equal to the first gain. For this reason, from time t=2.0 onward, similar to the display device in Comparative Example 2, the power consumption of multiple pixels in the display device 10 of this embodiment decreases. However, in this embodiment, the brightness of the line near the lower end of the display unit 70 is lower than that of the line near the lower end of the display unit 70 in Comparative Example 2, so the power consumption of multiple pixels in this embodiment initially falls below the control target power value. Then, as the line near the lower end of the display unit 70 is switched to a white display with relatively high brightness, similar to Comparative Example 2, the power consumption of multiple pixels in this embodiment increases, reaching the control target power value at time t=3.0. From time t=3.0 onward, the power consumption of multiple pixels is limited to below the control target power value.

[0080] As described above, according to the current limiting circuit 40 and current limiting method of this embodiment, by using the first power consumption and the second gain calculated based on the rate of change of the first power consumption, it is possible to suppress the power consumption of the display panel 60 even when the brightness indicated by the video signal increases rapidly.

[0081] Furthermore, in the display device 10 according to this embodiment, the power consumption (and current consumption) of multiple pixels can be adjusted by adjusting the sensitivity coefficient. For example, as shown by the dashed line in the graph of Figure 14, the influence of the sensitivity coefficient can be reduced by reducing the sensitivity level lv shown in equation (1) above. In other words, the current limiting characteristics of the current limiting circuit 40 according to this embodiment can be brought closer to the current limiting characteristics of the current limiting circuit according to Comparative Example 2. Also, as shown by the double dashed line in the graph of Figure 14, the influence of the sensitivity coefficient can be increased by increasing the sensitivity level lv in equation (1) above. In other words, the current can be limited even further.

[0082] (Other embodiments) The present disclosure has been described above based on embodiments, but the present disclosure is not limited to the embodiments described above. Other embodiments realized by combining any of the components in the embodiments, modified examples obtained by applying various modifications to the embodiments that a person skilled in the art could conceive of without departing from the spirit of the present disclosure, and various devices incorporating the current limiting circuit according to these embodiments are also included in the present disclosure.

[0083] For example, in the above embodiment, the current limiting circuit 40 is provided in the display device 10, but the current limiting circuit 40 does not necessarily have to be provided in the display device 10. Such a modified example will be explained using Figure 15. Figure 15 is a block diagram showing the relationship between the current limiting circuit 40 and the display device 710 according to this modified example. As shown in Figure 15, the current limiting circuit 40 is provided in the GPU (Graphics Processing Unit) 712. The GPU 712 is an arithmetic unit for image processing, and receives a video signal as input and outputs a video signal that has been multiplied by a gain by the current limiting circuit 40. The GPU 712 is located outside the display device 710. The GPU 712 may be provided in, for example, a PC (Personal Computer) 804 as shown in Figure 16. The PC 804 is operated by a keyboard 806 and a mouse 807, etc. The display device 710 may be provided in a monitor 805 shown in Figure 16. The monitor 805 is equipped with the display device 710 and displays the video signal from the PC 804. Furthermore, the GPU 712 may be provided in a hard disk recorder 808 as shown in Figure 17.

[0084] As described above, even when the current limiting circuit 40 according to the above embodiment is not provided in the display device 10, the same effects as the current limiting circuit 40 according to the above embodiment are achieved.

[0085] Furthermore, the display device 10 according to the above embodiment may be built into a thin flat TV 802 as shown in Figure 18. In this case as well, the same effects as in the above embodiment will be achieved.

[0086] Furthermore, although the above embodiment shows a configuration in which the pixels of the display panel include three subpixels corresponding to the three RGB colors, the pixel configuration is not limited to this. For example, a pixel may include four subpixels corresponding to the four RGBW colors. Also, if the display panel is a monochrome display panel, the pixel may include a single circuit as shown in Figure 6.

[0087] Furthermore, in the above embodiment, the video signal was an RGB signal, but the video signal may include signals other than RGB signals. In other words, the video signal only needs to include RGB signals.

[0088] Furthermore, the video signal is not limited to a signal containing RGB signals. For example, the video signal may be a color difference signal that includes a luminance signal.

[0089] Furthermore, although the above embodiment shows an example in which an organic EL element is used as the self-light-emitting element, the self-light-emitting element is not limited to this. For example, an inorganic EL element or the like may be used as the self-light-emitting element.

[0090] Furthermore, some of the components constituting the current limiting circuit 40 according to the above embodiment may be a computer system consisting of a microprocessor, ROM, RAM, hard disk unit, display unit, keyboard, mouse, etc. A computer program is stored in the RAM or the hard disk unit. The microprocessor achieves its function by operating in accordance with the computer program. Here, the computer program is composed of a combination of multiple instruction codes that indicate commands to the computer in order to achieve a predetermined function.

[0091] Furthermore, some of the components constituting the current limiting circuit 40 according to the above embodiment may be composed of a single system LSI (Large Scale Integration). The system LSI is a highly functional LSI manufactured by integrating multiple components onto a single chip, and specifically, it is a computer system composed of a microprocessor, ROM, RAM, etc. The RAM stores a computer program. The system LSI achieves its function by operating the microprocessor in accordance with the computer program.

[0092] Furthermore, some of the components constituting the current limiting circuit 40 according to the above embodiment may consist of an IC card or a standalone module that can be attached to and detached from each device. The IC card or module is a computer system consisting of a microprocessor, ROM, RAM, etc. The IC card or module may also include the above-mentioned multi-functional LSI. The IC card or module achieves its function by operating the microprocessor according to the computer program. The IC card or module may also be tamper-resistant.

[0093] Furthermore, some of the components constituting the current limiting circuit 40 according to the above embodiment may be recorded on a recording medium that can be read by a computer, such as a flexible disk, hard disk, CD-ROM, MO, DVD, DVD-ROM, DVD-RAM, BD (Blu-ray® Disc), semiconductor memory, etc. Alternatively, the digital signal may be recorded on one of these recording media.

[0094] Furthermore, some of the components constituting the current limiting circuit 40 according to the above embodiment may transmit the computer program or the digital signal via a telecommunications line, a wireless or wired communication line, a network such as the Internet, data broadcasting, etc.

[0095] Furthermore, this disclosure may also be the method described above. Alternatively, it may be a computer program that implements these methods using a computer, or a digital signal consisting of the above computer program. Furthermore, this disclosure may be implemented as a non-temporary computer-readable recording medium, such as a CD-ROM, on which the computer program is recorded.

[0096] Furthermore, this disclosure relates to a computer system comprising a microprocessor and memory, wherein the memory stores the computer program, and the microprocessor operates in accordance with the computer program.

[0097] Furthermore, the program or digital signal may be implemented by another independent computer system by recording it on the recording medium and transferring it, or by transferring the program or digital signal via the network or the like.

[0098] The above embodiments and their variations may be combined. [Industrial applicability]

[0099] This disclosure is useful, for example, for organic EL flat panel displays, and is particularly well-suited for use in large-screen displays where power consumption is high. [Explanation of symbols]

[0100] 10, 710 display device 40 Current limiting circuit 41 First screen data storage unit 42 Second screen data storage unit 44 Gain Multiplication Circuit 45 Weighted average circuit 46 Horizontal Period Data Calculation Circuit 47 Coefficient generation circuit 48 Multiplier circuits 51 First Gain Calculation Circuit 52 Second Gain Calculation Circuit 55 Gain Selector Circuit 60 Display Panels 62 Writing Processing Unit 64 Shift register for writing 68 Source Drivers 70 Display section 81, 82 TFT 84 Capacitors 85r Self-luminescent element 712 GPU 802 Slim Flat TV 804 PC 805 Monitor 806 Keyboard 807 Mouse 808 Hard Disk Recorder

Claims

1. A video signal is input to a display panel having multiple pixels, which in turn displays an image on the display panel, and a current limiting circuit is provided to limit the current consumption of the multiple pixels, A first gain calculation circuit calculates a first gain for multiplying the video signal based on a first power consumption, which is the power consumption of the plurality of pixels corresponding to the video signal. A second gain calculation circuit calculates a second gain for multiplying the video signal based on the first power consumption and the rate of change of the first power consumption, A gain selection circuit that selects one of the first gain and the second gain as the gain to be multiplied by the video signal, The system includes a gain multiplication circuit that multiplies the video signal by the gain, If the first power consumption is increasing, the second gain is smaller than the first gain. The gain selection circuit selects the first gain as the gain when the first power consumption is decreasing, based on the rate of change of the first power consumption, and selects the second gain as the gain when the first power consumption is increasing. Current limiting circuit.

2. When the first power consumption is constant, the second gain is equal to the first gain. The current limiting circuit according to claim 1.

3. If the first power consumption has not changed, the gain selection circuit selects the gain that was previously selected from the first gain and the second gain. The current limiting circuit according to claim 1 or 2.

4. If the gain selection circuit cannot determine the change in the first power consumption with respect to time, it selects the first gain as the gain. A current limiting circuit according to any one of claims 1 to 3.

5. The first gain calculation circuit calculates a first screen power value, which is a predicted value of the power consumption at the plurality of pixels corresponding to one frame of the video signal, The first gain is less than 1 if the first screen power value exceeds the control target power value, which is the control target upper limit value for power consumption at the plurality of pixels. A current limiting circuit according to any one of claims 1 to 4.

6. The first gain is less than or equal to the value obtained by dividing the control target power value by the first screen power value, if the first screen power value exceeds the control target power value. The current limiting circuit according to claim 5.

7. The second gain calculation circuit calculates the second gain based on the second power consumption, which is the power consumption at the plurality of pixels corresponding to the value obtained by multiplying the first coefficient by the video signal. The first coefficient is a coefficient that increases as the rate of change of the first power consumption increases. A current limiting circuit according to any one of claims 1 to 6.

8. The second gain calculation circuit calculates a second screen power value, which is a predicted value of the power consumption at the plurality of pixels corresponding to the value obtained by multiplying the video signal for one frame by the first coefficient, The second gain is less than 1 if the second screen power value exceeds the control target power value, which is the upper limit of the control target for the power consumption of the plurality of pixels. The current limiting circuit according to claim 7.

9. The second gain is less than or equal to the value obtained by dividing the control target power value by the second screen power value, if the second screen power value exceeds the control target power value. The current limiting circuit according to claim 8.

10. The first gain calculation circuit and the second gain calculation circuit each calculate and output the first gain and the second gain at intervals shorter than the vertical period of the video signal. A current limiting circuit according to any one of claims 1 to 9.

11. The aforementioned video signal includes an RGB signal. A current limiting circuit according to any one of claims 1 to 10.

12. A current limiting circuit according to any one of claims 1 to 11, The system includes the aforementioned display panel. Display device.

13. A current limiting method for limiting the current consumption of multiple pixels in a display panel, A first gain calculation step involves calculating a first gain for multiplying the video signal based on a first power consumption, which is the power consumption of the plurality of pixels corresponding to the video signal that is input to the display panel and causes the display panel to display an image; A second gain calculation step, which calculates a second gain for multiplying the video signal based on the first power consumption and the rate of change of the first power consumption, A gain selection step in which one of the first gain and the second gain is selected as the gain to be multiplied by the video signal, The process includes a gain multiplication step of multiplying the video signal by the gain, If the first power consumption is increasing, the second gain is smaller than the first gain. In the gain selection step, based on the rate of change of the first power consumption, if the first power consumption is decreasing, the first gain is selected as the gain; if the first power consumption is increasing, the second gain is selected as the gain. Current limiting method.

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