Distributed control computing system and method for high-altitude, long-endurance aircraft.

Abstract

To provide a flight control computer for an Unmanned Aerial Vehicle (UAV) that detects and reacts against a fault.SOLUTION: A computing device includes: a first flight control computer (FCC) (112); a second FCC (113); at least one selector (182) in communication with the first FCC; and at least one watchdog window (180) in communication with the at least one selector (182), the at least one watchdog window monitoring a performance of the first FCC (112) based on an electrical pulse emitted by the FCC (112). The watchdog window detects a fault pulse of the electrical pulse emitted by the first FCC (112), and the selector (182) toggles to the second FCC based on the detected fault pulse emitted by the first FCC.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention generally relates to a flight control computer, and more particularly to a flight control computer for an unmanned aerial vehicle (UAV).

[0002] Cross - reference to related applications This application claims the priority and benefit of U.S. Provisional Patent Application No. 62 / 838,783, filed on April 25, 2019, U.S. Provisional Patent Application No. 62 / 838,833, filed on April 25, 2019, and U.S. Provisional Patent Application No. 62 / 855,593, filed on May 31, 2019, the entire contents of which are hereby incorporated by reference for all purposes.

Background Art

[0003] An unmanned aerial vehicle (UAV) is an aircraft capable of controlled and sustained flight. The UAV has no on - board pilot, and the flight control computer (FCC) mounted on the UAV serves as the central information unit of the aircraft. The FCC includes one or more processors, and the FCC controls the functions of the UAV.

Summary of the Invention

[0004] Embodiments of the system can include a first flight control computer (FCC) among two or more FCCs, a second FCC among two or more FCCs, at least one selector communicating with the first FCC, and at least one watchdog window communicating with the at least one selector and configured to monitor the performance of the first FCC based on electrical pulses emitted by the FCC. The at least one watchdog window can be configured to detect a fault pulse among the electrical pulses emitted by the first FCC, and the selector can be configured to toggle to the second FCC based on the detected fault pulse emitted by the first FCC.

[0005] In additional system embodiments, the detected fault pulse may be a pulse outside the preferred range. In additional system embodiments, the detected fault pulse may be a pulse that skips a beat. In additional system embodiments, the detected fault pulse may have a frequency and amplitude outside the preferred range of the baseline pulse.

[0006] In an additional system embodiment, the selector may be further configured to reset power to the first FCC. In an additional system embodiment, the selector may be configured to toggle to the first FCC after resetting power to the first FCC. In an additional system embodiment, at least one watchdog window may be further configured to monitor the performance of the first FCC after the selector has toggled to the first FCC.

[0007] Embodiments of the method may include the steps of: monitoring the performance of a first flight control computer (FCC) among two or more flight control computers (FCCs) using a watchdog window, wherein the performance is based on electrical pulses emitted by the first FCC; detecting fault pulses among the electrical pulses emitted by the first FCC via the watchdog window; and using a selector communicating with the watchdog window to toggle to a second FCC based on the detected fault pulse emitted by the first FCC.

[0008] In an embodiment of the additional method, the detected fault pulse may be a pulse outside the preferred range. In an embodiment of the additional method, the detected fault pulse may be a pulse that skips a beat. In an embodiment of the additional method, the detected fault pulse may be a pulse having a frequency and amplitude outside the preferred range of the baseline pulse.

[0009] An additional embodiment of the method may further include the step of resetting power to the first FCC via a selector. An additional embodiment of the method may further include the step of toggling the selector to the first FCC after resetting power to the first FCC. An additional embodiment of the method may include the step of monitoring the performance of the first FCC via a watchdog window after the selector has toggled the first flight control computer (FCC) to the first FCC.

[0010] An embodiment of a flight control computer may include a field-programmable gate array (FPGA), a flight control computer (FCC) processor that communicates with the FPGA via an FCC bus, a plurality of serial ports that communicate with the FPGA and the FCC processor, and a controller chip that communicates with the plurality of serial ports and is configured to convert the parallel output of the FCC bus into a serial format for transmission through one of the plurality of serial ports. [Brief explanation of the drawing]

[0011] The components in the drawings do not necessarily need to be to a specific scale; instead, the focus is on illustrating the principles of the present invention. Similar reference numerals indicate corresponding parts throughout the various drawings. Embodiments are shown as examples and are not limited to those shown in the accompanying drawings. [Figure 1] Figure 1 shows a system for an unmanned aerial vehicle with distributed control computing according to one embodiment. [Figure 2] Figure 2 shows a top-level functional block diagram of a computing device for distributed control computing according to one embodiment. [Figure 3] Figure 3 shows a computing device for distributed control computing that includes multiple serial ports, according to one embodiment. [Figure 4]Figure 4 shows a system for monitoring the performance of two computing devices according to one embodiment. [Figure 5] Figure 5 shows an electrical pulse related to a computing device for distributed control computing according to one embodiment. [Figure 6] Figure 6 shows a flowchart of a method for distributed control computing to monitor the performance of a flight control computer, according to one embodiment. [Figure 7] Figure 7 shows a higher-level block diagram and process of a computing system for executing one embodiment of the system and process. [Figure 8] Figure 8 shows a block diagram and process of an exemplary system that can perform one embodiment. [Figure 9] Figure 9 shows a cloud computing environment for performing one embodiment of the system and process disclosed herein. [Modes for carrying out the invention]

[0012] The following description is intended to illustrate the general principles of the embodiments disclosed herein and is not intended to limit the concepts disclosed herein. Furthermore, certain features described herein can be used in combination with other features described herein in each of the various possible combinations and permutations. Unless otherwise specifically defined herein, all terms should be given the broadest possible interpretation, including the meaning implied by the description, as well as the meaning understood by those skilled in the art and / or defined in dictionaries, papers, etc.

[0013] Embodiments of the systems and methods disclosed herein may include distributed control computing for flight control computers (FCCs) of unmanned aerial vehicles (UAVs). In one example, the UAV is a high-altitude, long-endurance solar-powered aircraft. For an FCC, it is difficult to physically accommodate all the desired communication lines, so-called "inputs / outputs" or "I / O," between the information processing system and external systems. An FCC can be controlled and programmed using a field-programmable gate array (FPGA). An FPGA is a field-programmable integrated circuit in the sense that it can be programmed after manufacturing to perform one or more logical operations. The FPGA is connected to a central processing unit (CPU) by bus and can handle all the necessary I / O. In such a point-to-point design, only one connection is established per node of the aircraft's avionics, and each node is assigned a specific task. Such a configuration can lead to high serial traffic that burdens the CPU.

[0014] Furthermore, it is crucial to have a system to monitor the performance of the FCCs so that the UAV can maintain flight if the FCCs fail. A UAV can have at least two FCCs, with at least one of them acting as a backup in case the other FCCs fail. Additionally, a matrix of checkers or selectors may monitor the performance of each FCC. If one FCC fails, the UAV can maintain flight by switching to the backup FCC. This approach is complex, as it increases the likelihood of one of the selectors failing. Moreover, matrix configurations are difficult to debug, require a great deal of wiring, and can be very expensive to implement. Furthermore, matrix configurations can require considerable power, making the architecture difficult to build.

[0015] In one embodiment, the FCC has a processor with an FPGA fabric adjacent to the processor. The FPGA has radiation resistance that helps protect the computer from high-frequency solar radiation that could damage the electronics housed therein. Multiple serial ports are connected to the processor / FPGA system. Using FPGAs to design the circuitry increases the flexibility of serial port and pin connections. In one embodiment, the FCC has an increased capacity of serial ports. Generally, constraints on the total number of serial ports are the number of physical I / O pins and the size of the FPGA. In one embodiment, 20 serial ports are located in the FCC, providing substantial I / O. This configuration provides a so-called "party line" from which all nodes of the aircraft's avionics listen and communicate.

[0016] Each of the 20 serial ports can be connected to a different element of the flight control system. For example, there may be ports for buses, data links, transponders, etc. This system requires minimal maintenance and can accurately distribute control without placing an excessive load on the processor. Furthermore, this system can operate at low power. For example, a typical Ethernet connection configuration uses about 1 watt of power, while the FCC has power usage in the approximate range measured in milliwatts (mW).

[0017] The systems for distributed control computing of FCCs described above further include monitoring the performance of the FCCs. More specifically, this specification describes a system for automatically switching from one FCC to another identical FCC in the event of a failure. In one embodiment, the selector connected to the FCC has a simple configuration and does not include, for example, logic gates, transistors, etc. Individual aspects of the selector may fail. However, because the selector is simple, there are few failure modes in the system, and thus the reliability may be much higher.

[0018] In one embodiment, each FCC has pulses or "watchdogs" generated by the FCC programming and FCC circuitry. A watchdog window associated with the selector can detect electrical pulses. If the watchdog window detects that performance specifications are not being met, for example, the absence of pulses, the selector can toggle to a second FCC, while the first FCC can be powered back on, for example, shut off and then on again. Furthermore, the power to the first FCC may be reset, and the identified problem may be resolved. The FCC may recover and become operational again in a sufficiently short time to ensure the safety of the aircraft. Thus, because the selector toggles to a functioning backup FCC, the UAV can maintain continuous flight.

[0019] Referring to Figure 1, a system 100 for distributed control computing for the flight control computer (FCC) 112 of an unmanned aerial vehicle (UAV) 101 is shown. A UAV is an aircraft without an onboard pilot and can fly autonomously or remotely. In one embodiment, UAV 101 is a high-altitude, long-endurance aircraft. In one embodiment, UAV 101 may have one or more motors, e.g., 1 to 40 motors, and a wingspan of 100 to 400 feet. In one embodiment, UAV 101 may have a wingspan of approximately 260 feet and can be propelled by multiple motors, 10 electric motors, driven by a solar cell array covering the wing surface, thereby resulting in zero emissions. UAV 101 is designed to fly at an altitude of approximately 65,000 feet above sea level, above the clouds, and to perform continuous long-endurance missions for up to several months without landing.

[0020] The high-altitude long-endurance UAV 101 optimally functions at high altitudes, at least partially due to the lightweight payload of the UAV, and can fly continuously for a significant period without relying on landing. In one embodiment, the high-altitude long-endurance UAV 101 weighs approximately 3,000 pounds and includes two or more outer wing panel sections and one or more central wing panel sections, and the mutual attachment and detachment of the wing panel sections and / or the attachment and detachment to the central panel are possible, so that the efficient assembly and disassembly of the UAV 101 can be provided.

[0021] In one embodiment, there is no on-board pilot in the UAV 101. For this reason, the flight control computer (FCC) 112 installed in the UAV 101 is the central information department of the aircraft. The FCC 112 can partially or completely control many functions of the UAV 101, such as determining the flight pattern and changing the direction of the UAV 101. In one embodiment, the FCC 112 can determine the flight pattern based on weather conditions, the purposes of the payload operator, the flight patterns of other UAVs in the air squadron, and various external sensors. In one embodiment, the operator determines the flight pattern of the UAV 101.

[0022] Figure 2 shows an example of the top-level functional block diagram of the FCC 112 of the high-altitude long-endurance aircraft. The FCC 112 includes at least a processor 153 such as a central processing unit (CPU), an addressable memory 154, and an external device interface 156, for example, an optional USB port and related processing, and / or an Ethernet port and related processing, and an optional user interface, for example, an array of status lights, sensors, and one or more toggle switches, and / or a touch screen. Optionally, the addressable memory may be, for example, flash memory, EPROM, and / or a disk drive or other hard drive. These elements can communicate with each other via a data bus 160.

[0023] In some embodiments, the processor 153 may be configured to perform steps in the process of establishing a communication channel via an operating system 162 that provides support for application 164, etc.

[0024] The FCC112 can further connect to or communicate with a Global Positioning System (GPS) 126 configured to receive positional data from a group of satellites. Furthermore, the FCC112 may include a transmitter 157 for working with a ground GPS receiver to transmit repeated GPS signals to the ground and / or for transmitting GPS signals converted to an auxiliary frequency band to a ground RF receiver.

[0025] As shown in Figure 3, the FCC processor 153 can be connected to a field-programmable gate array (FPGA) fabric 152. The FPGA 152 can be a field-programmable integrated circuit in the sense that it can be programmed after manufacturing to perform one or more logical operations. More specifically, the FPGA 152 can include a collection of logic cells surrounded by an interconnect fabric, or a "lookup table" (LUT). The LUT and interconnect fabric are programmable and provide a system for implementing algorithms. In one embodiment, the FPGA 152 can be reprogrammed to implement different logical functions, thereby providing flexible and reconfigurable computing.

[0026] FPGA152 can help extend the I / O capabilities of processor 153. FPGA152 can have large resources of logic gates and RAM blocks to implement complex algorithms. The architecture of FPGA152 can consist of LUTs, routing channels, and I / O pads, the I / O pads enabling memory mapping between processor 153 and other peripherals in FCC112.

[0027] FPGA152 may have radiation resistance that helps protect the computer from high-frequency solar radiation that could damage the electronics housed therein. In one embodiment, FPGA152 may be a SmartFusion® 2 FPGA from Microsemi Corporation in Aliso Viejo, California.

[0028] Multiple serial ports 170 are connected to the FCC 112 and can communicate with the processor 153 and FPGA 152 via inputs 176, such as a bus. In one embodiment, each serial port 170 may be a serial communication interface in which information enters and leaves the FCC 112 one bit at a time. In one embodiment, the serial port 170 interfaces with a controller chip, for example, a general-purpose asynchronous transceiver circuit. The controller chip may be configured to receive the parallel output of the FCC bus 160 and convert the output to a serial format for transmission via the serial port 170, as shown in Figure 2. The serial port 170 may require minimal support software from the FPGA 152. The serial port 170 can be divided into male and female, and the connector of the serial port 170 can only mate with the opposite male / female connector. Generally, male serial port connectors have protruding pins, and female connectors have sockets. In one embodiment, the serial port 170 may have a male connector that can mate with a female output 174. Output 174 may be a cable connecting to external elements 172, such as a modem, transponder, and other external elements related to the avionics of a UAV.

[0029] The configuration can be created using FPGA152, thereby increasing the flexibility of serial ports and pins. In one embodiment, FCC112 can increase the capacity of serial ports. Generally, the constraints on the total number of serial ports are the number of physical I / O pins of serial port 170 and the size of FPGA152. In one embodiment, multiple serial ports, for example 20 serial ports, are arranged on FCC112.

[0030] An embodiment having 20 serial ports can provide substantial I / O to the FCC112. Each of the 20 serial ports 170 may be connected to a different external element 172 of the FCC112. For example, there may be ports for a bus, modem, data link, transponder, etc. The 20 serial ports 170 require minimal maintenance and allow control to be accurately distributed without placing an excessive burden on the processor 153. In one embodiment, the serial ports 170 can reduce the amount of processing required by the processor 153. Furthermore, the configuration of 20 serial ports allows the FCC112 to operate at low power. For example, while a typical Ethernet connection configuration uses about 1 watt of power, the FCC has power consumption in the approximate range measured in milliwatts (mW).

[0031] The system for distributed control computing can further provide monitoring of the performance of the FCC112. More specifically, as shown in Figure 4, the system includes an automatic switch that toggles from the first FCC112 to the second FCC113 if it is not functioning correctly. The FCC112 and 113 are shown without the serial port 170 as shown in Figure 3 for clarity. In one embodiment, the first FCC112 may be identical to the second FCC113. In one embodiment, the selector 182 may be a microcontroller connected to the FCC112 and 113 via an output 185. Furthermore, the selector 182 may have a configuration without logic gates or transistors. In another embodiment, multiple selectors may be connected to the FCC112 and 113.

[0032] In one embodiment, an integrated watchdog window 180 can be located on the selector 182 chip. In another embodiment, the watchdog window 180 can be located on an external expansion card within the FCC chassis. The watchdog window 180 can communicate with at least one selector 182 to monitor the electrical pulses, or "watchdogs," emitted by each of the FCCs 112, 113. Watchdog windows may be found in embedded systems that are not easily accessible to the operator, such as the FCCs 112, 113 mounted on a UAV. In such systems, the FCCs 112, 113 do not need to rely on the operator to restart the FCC if it malfunctions.

[0033] In one embodiment, one or more sensors 190 can be connected to both FCCs 112, 113. In one embodiment, the system may include three sensors 190. In one embodiment, each sensor may be identical. Each sensor 190 can detect information related to the health and performance of the FCC via an output 184. The three sensors 190 can provide a triple-redundant critical flight sensor system. In one embodiment, the FCCs 112, 113 can select an intermediate value from the redundant set of the three sensors 190 to evaluate the performance of the FCCs 112, 113.

[0034] In one embodiment, a watchdog window 180 monitors the electrical pulses, or "heartbeats," generated by the FCC 112 as the heartbeat passes through the FCC 112's circuitry. For example, as shown in Figure 5, a normal signal 192 is monitored by the watchdog window 180, in which case the frequency window of signal 192 is within a preferred range for a properly functioning first FCC 112, as shown in Figure 4. At another point, the watchdog window 180 may detect pulses that are too slow or skip beats, such as pulse 194. At yet another point, the watchdog window 180 may detect pulses that are too fast, such as pulse 196. In one embodiment, performance specifications may require that the frequency and amplitude of the FCC heartbeat be within a specific percentage range of the baseline pulse. In one embodiment, if signal 192 is outside the frequency window, for example, if the heartbeat is too fast or too slow, the FCC 112 will be reset. A faulty pulse may be a pulse outside the preferred range, a pulse that skips a beat, a pulse slower than the preferred range, a pulse faster than the preferred range, or a pulse with a frequency and amplitude outside the preferred range of the baseline pulse.

[0035] In one embodiment, if the watchdog window 180 does not detect a heartbeat, or if the detected heartbeat indicates an anomaly in the first or active FCC 112, such as a time delay between consecutive pulses, the watchdog window 180 can instruct the selector 182 to toggle to a second or backup FCC 113. In one embodiment, power to the first FCC 112 is reset, and the identified problem may be resolved by resetting the memory and processor. Thus, the first FCC 112 can be backed up and operational again immediately after power-on, allowing the UAV to maintain continuous flight. Furthermore, because the selector 182 toggles to a normal second or backup FCC 113, continuous flight is not interrupted while operating on the second or backup FCC 113. In some embodiments, the second or backup FCC 113 may be a duplicate of the first FCC 112.

[0036] In one embodiment, if the watchdog window 180 detects a normal pulse for the operational FCC 112 but does not detect a pulse for the backup FCC 113, the selector 182 does not toggle to the backup FCC 113. In one embodiment, each FCC 112, 113 can last for approximately 8 hours or more, which may be sufficient time to land the UAV after one of the FCCs 112, 113 fails. If the power is completely cut off and neither FCC can be powered on and function, the UAV can perform landing procedures. In one embodiment, the landing procedure may be performed by activating the end-of-flight system.

[0037] Figure 6 illustrates a flowchart of a distribution control computing method 200 for monitoring FCC performance. In one embodiment, a watchdog window, such as watchdog window 180, can communicate with at least one selector, such as selector 182, to monitor electrical pulses, or “watchdogs,” emitted by FCCs such as FCCs 112, 113, etc. The watchdog window monitors electrical pulses (or “heartbeats”) generated by the first FCC as the heartbeat passes through the circuitry of the first FCC (step 202). In one embodiment, performance specifications may require that the frequency and amplitude of the heartbeats of the first FCC be within a specific percentage range of the baseline pulse. The watchdog window can detect the absence of a pulse or that the pulse is outside the frequency window of a preferred frequency range for an FCC that is functioning properly (step 204). The watchdog window can detect fault pulses. Fault pulses may be pulses outside the preferred range, pulses that skip beats, pulses slower than the preferred range, pulses faster than the preferred range, or pulses with frequencies and amplitudes outside the preferred range of the baseline pulse. The watchdog window can tell the selector to toggle to a backup second FCC (step 206). The second FCC can then control the UAV and maintain its flight (step 208). Power to the first FCC can be reset, and any identified problems may be resolved by resetting the memory and processor (step 210). Thus, the first FCC can be backed up and operational again immediately after being powered back on, and the UAV can maintain continuous flight. When the first FCC is operational, the selector can be told by the watchdog window to toggle back to the first FCC (step 212). Once the first FCC is operational, the UAV can continue flying with the first FCC (step 214).The watchdog window can continue to monitor the electrical pulses generated by the first FCC (step 216).

[0038] Figure 7 is a high-level block diagram 500 showing a computing system comprising a computer system useful for carrying out one embodiment of a system and process disclosed herein. Embodiments of the system may be carried out in different computing environments. The computer system includes one or more processors 502 and may further include an electronic display device 504 (for displaying graphics, text and other data, e.g.), main memory 506 (e.g., random access memory (RAM)), storage device 508, removable storage device 510 (e.g., removable storage drive, removable memory module, magnetic tape drive, optical disc drive, computer-readable medium storing computer software and / or data therein), user interface device 511 (e.g., keyboard, touchscreen, keypad, pointing device), and communication interface 512 (e.g., modem, network interface (such as an Ethernet card), communication port, or PCMCIA slot and card). The communication interface 512 enables software and data to be transferred between the computer system and external devices. The system further includes a communication infrastructure 514 (e.g., a communication bus, crossover bar, or network) to which the aforementioned devices / modules are connected as shown.

[0039] Information transferred via the communication interface 514 may be in the form of signals such as electronic, electromagnetic, optical, or other signals that can be transmitted and received by the communication interface 514 via a communication link 516 which can be implemented using wires or cables, optical fibers, telephone lines, mobile phone / cellular link, radio frequency (RF) link, and / or other communication channels. Computer program instructions representing block diagrams and / or flowcharts herein may be loaded into a computer, a programmable data processing device, or a processing device, where a series of operations may be performed to generate a computer implementation process.

[0040] Embodiments have been described with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to the embodiments. Each block or combination thereof in such examples / diagrams can be implemented by computer program instructions. When computer program instructions are provided to a processor, the machine generates means for instructions executed through the processor to perform the functions / operations identified in the flowcharts and / or block diagrams. Each block in the flowchart / block diagram may represent a hardware and / or software module or logic that implements the embodiment. In alternative implementations, the functions shown in the blocks may occur simultaneously, outside of the order shown in the diagrams.

[0041] The computer program (i.e., computer control logic) is stored in main memory and / or auxiliary memory. The computer program may also be received via the communication interface 512. When executed, such a computer program enables the computer system to perform features of embodiments discussed herein. In particular, when executed, the computer program enables the processor and / or multicore processor to perform features of the computer system. Such a computer program represents the controller of the computer system.

[0042] Figure 8 shows a block diagram of an exemplary system 600 in which one embodiment may be implemented. System 600 includes one or more client devices 601, such as consumer electronic devices, connected to one or more server computing systems 630. Server 630 includes a bus 602 or other communication mechanism for communicating information, and a processor (CPU) 604 coupled to the bus 602 for processing information. Server 630 also includes main memory 606, such as random access memory (RAM) or other dynamic storage device, coupled to the bus 602, for storing information and instructions executed by the processor 604. Main memory 606 may also be used to store temporary variables or other intermediate information in progress, or instructions executed by the processor 604. Server computer system 630 further includes read-only memory (ROM) 608 or other static storage device coupled to the bus 602 for storing static information and instructions for the processor 604. A storage device 610, such as a magnetic disk or optical disk, is provided and coupled to the bus 602 for storing information and instructions. Bus 602 may include, for example, 32 address lines for addressing video memory or main memory 606. Bus 602 may also include a 32-bit data bus for transferring data between and within components such as CPU 604, main memory 606, video memory, and storage 610. Alternatively, multiplexed data / address lines may be used instead of separate data lines and address lines.

[0043] Server 630 may be coupled via bus 602 to a display 612 for displaying information to a computer user. An input device 614, including alphanumeric and other keys, is coupled to bus 602 to communicate information and command selections to processor 604. Another type of user input device may include a cursor control 616, such as a mouse, trackball, or cursor directional keys, for communicating directional information and command selections to processor 604 and for controlling cursor movement on display 612.

[0044] According to one embodiment, the function is performed by a processor 604 that executes one or more sequences of one or more instructions contained in main memory 606. Such instructions may be read into main memory 606 from another computer-readable medium, such as a storage device 610. By executing the sequence of instructions contained in main memory 606, the processor 604 performs the process steps described herein. One or more processors in a multiprocessing configuration may be employed to execute the sequence of instructions contained in main memory 606. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions to carry out the embodiment. Therefore, the embodiment is not limited to any particular combination of hardware circuitry and software.

[0045] The terms “computer program medium,” “computer-usable medium,” “computer-readable medium,” and “computer program product” are generally used to refer to media such as main memory, auxiliary memory, removable storage drives, hard disks installed on hard disk drives, and signals. These computer program products are means for providing software to a computer system. Computer-readable medium allows a computer system to read data, instructions, messages or message packets, and other computer-readable information from it. Computer-readable medium may include non-volatile memory such as floppy disks, ROMs, flash memory, disk drive memory, CD-ROMs, and other permanent storage. For example, it is useful when transferring information such as data and computer instructions between computer systems. Furthermore, computer-readable medium may include computer-readable information in transient state medium such as network links and / or network interfaces, including wired or wireless networks, which allow computers to read such computer-readable information. Computer programs (also called computer control logic) are stored in main memory and / or auxiliary memory. Computer programs may also be received via communication interfaces. Such computer programs, when executed, enable a computer system to perform features of embodiments discussed herein. In particular, when executed, the computer programs enable a multicore processor to perform features of the computer system. Thus, such computer programs represent the controller of the computer system.

[0046] Generally, as used herein, the term “computer-readable medium” refers to any medium that participates in providing instructions to the processor 604 for execution. Such mediums can take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks such as storage device 610. Volatile media include dynamic memory such as main memory 606. Transmission media include coaxial cables, copper wires, and optical fibers, including wires that constitute bus 602. Transmission media can also take the form of acoustic waves or light waves, such as those generated during radio waves or infrared data communications.

[0047] Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tapes or any other magnetic media, CD-ROMs, any other optical media, punch cards, paper tapes, any other physical media having a pattern of holes, RAM, PROMs, EPROMs, FLASH-EPROMs, other memory chips or cartridges, carriers as described below, or any other media that can be read by a computer.

[0048] Various forms of computer-readable media can be involved in holding one or more sequences of one or more instructions for the processor 604 to execute. For example, an instruction may first be executed on a magnetic disk of a remote computer. The remote computer may load the instruction into dynamic memory and transmit the instruction over a telephone line using a modem. A modem local to the server 630 may receive data over the telephone line and convert the data into an infrared signal using an infrared transmitter. An infrared detector coupled to the bus 602 may receive the data held as an infrared signal and place that data on the bus 602. The bus 602 transmits the data to the main memory 606, from which the processor 604 reads and executes the instruction. The instruction received from the main memory 606 may optionally be stored in a storage device 610 either before or after execution by the processor 604.

[0049] Server 630 also includes a communication interface 618 coupled to bus 602. The communication interface 618 provides bidirectional data communication coupled to network link 620, which is connected to a global packet data communication network now commonly referred to as the Internet 628. The Internet 628 uses electrical, electromagnetic, or optical signals to carry digital data streams. Signals across various networks, signals on network link 620, and signals through the communication interface 618 to and from Server 630, which carry digital data, are exemplary forms or carriers for transmitting information.

[0050] In another embodiment of server 630, interface 618 is connected to network 622 via communication link 620. For example, communication interface 618 may be an Integrated Services Digital Network (ISDN) card or modem for providing data communication connectivity to a corresponding type of telephone line that can constitute part of network link 620. As another example, communication interface 618 may be a Local Area Network (LAN) card for providing data communication connectivity to a compatible LAN. Wireless links may also be implemented. In any such implementation, communication interface 618 transmits and receives electromagnetic or optical signals that hold digital data streams representing various types of information.

[0051] Network link 620 typically provides data communication to other data devices through one or more networks. For example, network link 620 may provide connection to data devices operated by a host computer 624 or an Internet service provider (ISP) through a local network 622. The ISP then provides data communication services through the Internet 628. Both the local network 622 and the Internet 628 use electrical, electromagnetic, or optical signals to carry digital data streams. Signals through various networks, signals on network link 620, and signals through the communication interface 618 that transmits digital data to and from server 630 are exemplary forms or carriers for transmitting information.

[0052] Server 630 can send and receive messages and data, including email, and program code via the network, network link 620, and communication interface 618. Furthermore, communication interface 618 may be equipped with a USB / tuner, and network link 620 may be an antenna or cable for connecting Server 630 to a cable provider, satellite provider, or other terrestrial transmission system for receiving messages, data, and program code from another source.

[0053] Exemplary versions of the embodiments described herein may be implemented as logical operations in a distributed processing system, such as a system 600 including a server 630. The logical operations of the embodiments may be implemented as a series of steps executed within the server 630 and as interconnected machine modules within the system 600. Implementation is a matter of choice and may depend on the capabilities of the system 600 implementing the embodiments. Thus, the logical operations constituting the exemplary versions of the embodiments may be referred to, for example, as operations, steps, or modules.

[0054] Similar to the server 630 described above, the client device 601 may include a processor, memory, storage devices, a display, input devices, and a communication interface (e.g., an email interface) for connecting the client device to the Internet 628, ISP, or LAN 622 for communication with the server 630.

[0055] System 600 may further include computers (e.g., personal computers, computing nodes) 605 that operate in the same manner as client devices 601, and a user can use one or more computers 605 to manage data in server 630.

[0056] Referring here to Figure 9, an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 comprises one or more cloud computing nodes 10 that can communicate with local computing devices used by cloud consumers, such as personal digital assistants (PDAs), smartphones, smartwatches, set-top boxes, video game systems, tablets, mobile computing devices or cell phones 54A, desktop computers 54B, laptop computers 54C, and / or automotive computer systems 54N. The nodes 10 can communicate with each other. They can be grouped physically or virtually into one or more networks, such as the private, community, public, or hybrid clouds described above, or a combination thereof (not shown). This allows the cloud computing environment 50 to provide infrastructure, platforms and / or software as a service, eliminating the need for cloud consumers to maintain resources on their local computing devices. It is understood that the types of computing devices 54A-N shown in Figure 9 are intended for illustrative purposes only, and that the computing nodes 10 and the cloud computing environment 50 can communicate with any type of computerized device via any type of network and / or network addressable connection (e.g., using a web browser).

[0057] Various combinations and / or partial combinations of the specific features and aspects of the embodiments described above may be made and are still considered to be within the scope of the present invention. Therefore, it should be understood that the various features and aspects of the disclosed embodiments may be combined with or substituted for each other to form various modes of the disclosed invention. Furthermore, it is intended that the scope of the present invention disclosed herein as an example should not be limited by the specific disclosed embodiments described above.

Claims

1. Of two or more flight control computers (FCCs) (112, 113), the first FCC (112) and The second FCC (113) among the two or more FCCs mentioned above, At least one selector (182) that communicates with the first FCC, The watchdog window (180) communicates with the at least one selector (182) and includes at least one watchdog window that monitors the performance of the first FCC (112) based on electrical pulses (192, 194, 196) emitted by the FCC (112), The at least one watchdog window is configured to detect fault pulses among the electrical pulses emitted by the first FCC, The selector is configured to toggle to the second FCC based on a detected fault pulse emitted by the first FCC. The detected fault pulse is a pulse outside the preferred range. The system is further characterized in that the selector is configured to reset the power to the first FCC and, after resetting the power to the first FCC, to toggle to the first FCC.

2. In the system described in claim 1, The system is characterized in that the detected fault pulse is a pulse that skips a beat.

3. In the system according to claim 1 or 2, The system is characterized in that the detected fault pulse is a pulse having a frequency and amplitude outside the preferred range of the baseline pulse.

4. In the system described in claim 1, The system is characterized in that the at least one watchdog window is further configured to monitor the performance of the first FCC after the selector has toggled it to the first FCC.

5. In the system according to any one of claims 1 to 4, The first FCC (112) is Field-programmable gate array (FPGA) (152) and Multiple serial ports (170) for communicating with the FGPA and FCC processors, A system comprising a controller chip that communicates with the plurality of serial ports, configured to convert the parallel output of the FCC bus into a serial format for transmission via one of the plurality of serial ports.

6. A step of monitoring the performance of a first flight control computer (FCC) (112) among two or more flight control computers (FCCs) using a watchdog window (180), wherein the performance is based on electrical pulses (192, 194, 196) emitted by the first FCC, The steps include detecting fault pulses among the electrical pulses emitted by the first FCC through the watchdog window, The system includes a step of using a selector that communicates with the watchdog window to toggle to a second FCC (113) based on a fault pulse detected by the first FCC, The detected fault pulse is a pulse outside the preferred range. moreover, The steps include resetting the power to the first FCC via the selector, A method characterized by comprising the step of resetting the power to the first FCC, and then toggling the selector to switch to the first FCC.

7. In the method according to claim 6, The method is characterized in that the detected fault pulse is a pulse that skips a beat.

8. In the method according to claim 6 or 7, The method is characterized in that the detected fault pulse is a pulse having a frequency and amplitude outside the preferred range of the baseline pulse.

9. In the method according to claim 6, The method further comprises the step of monitoring the performance of the first flight control computer (FCC) after toggling the first FCC via the selector through the watchdog window.

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