Circuit layout generation system

Abstract

To provide a system for generating circuit layouts with a new configuration.SOLUTION: A system for generating circuit layouts includes a storage part, a restriction data calculation part, and a layout data calculation part. The storage part has a function of storing circuit connection data and first restriction data. The circuit connection data relate to connection of transistors and capacitors in pixel circuits. The first restriction data include data for setting wiring intervals of transistors and capacitors and data for setting placement coordinates of transistors and capacitors. The restriction data calculation part has a function of generating second restriction data on the basis of the circuit connection data and the first restriction data and storing the second restriction data in the storage part. The second restriction data are data for setting transistors and capacitors specified in placement coordinates so as to be placed to be close thereto, The layout data calculation part generates layout data on the basis of the circuit connection data, the first restriction data and the second restriction data.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a system for generating layout data related to a circuit layout (circuit arrangement).

[0002] Note that one aspect of the present invention is not limited to the above technical field. As the technical field of one aspect of the present invention disclosed in this specification and the like, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, or manufacturing methods thereof can be cited as an example.

Background Art

[0003] In the logical circuit design of LSI (Large Scale Integrated circuit), techniques for automatically generating circuit arrangements (also referred to as circuit layouts) such as design automation tools have become widespread. On the other hand, techniques for automatically generating the layout of analog circuits typified by pixel circuits in display devices and the like have not been widely adopted.

[0004] An important factor in determining the circuit layout of a pixel circuit is to consider the layout constraints of the circuit layout. Examples of layout constraints include constraint conditions for relaxing variations in characteristics caused by the manufacturing process of transistors, and constraint conditions for avoiding signal delays and capacitive coupling between nodes due to wiring parasitic effects.

[0005] Patent Document 1 discloses a configuration for performing automatic design of the circuit layout of an analog circuit based on the constraints of the circuit layout.

Prior Art Documents

Patent Documents

[0006] [[ID=​​​​​​​

[0007] The transistors and capacitors within a pixel circuit can have countless combinations in their circuit configuration. By adding constraints to the circuit configuration, the data for the transistor and capacitor configurations within the pixel circuit can be generated with limited computational processing.

[0008] On the other hand, the arrangement of transistors and capacitors within the pixel circuit also affects the parasitic capacitance of the wiring and signal noise within the pixel circuit. Parasitic capacitance and signal noise have a significant impact on display quality. Furthermore, the pixel circuit must obtain an optimal solution that satisfies design requirements such as power or signal delay within a limited area. For this reason, it is difficult to automatically generate layout data for pixel circuits and other components using computer processing. As a result, the current practice is to generate layout data for pixel circuits and other components manually, drawing on past design experience.

[0009] One aspect of the present invention aims to provide a circuit layout generation system that can reduce the impact on display quality. Alternatively, one aspect of the present invention aims to provide a circuit layout generation system that can shorten the design period. Alternatively, one aspect of the present invention aims to provide a circuit layout generation system that can reduce costs such as labor costs. Alternatively, one aspect of the present invention aims to provide a novel circuit layout generation system.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a circuit layout generation system comprising a storage unit, a constraint data calculation unit, and a layout data calculation unit, wherein the storage unit has the function of storing circuit connection data and first constraint data, the constraint data calculation unit has the function of generating second constraint data based on the circuit connection data and first constraint data and storing the second constraint data in the storage unit, and the layout data calculation unit generates layout data based on the circuit connection data, first constraint data and second constraint data.

[0012] One aspect of the present invention is a circuit layout generation system comprising a storage unit, a constraint data calculation unit, and a layout data calculation unit, wherein the storage unit has the function of storing circuit connection data and first constraint data, the circuit connection data being data relating to the connections of transistors and capacitors in a pixel circuit, the first constraint data being data that sets the wiring intervals of transistors and capacitors, the constraint data calculation unit having the function of generating second constraint data based on the circuit connection data and first constraint data and storing the second constraint data in the storage unit, the second constraint data being data that sets transistors and capacitors connected to the same wiring to be placed in close proximity, and the layout data calculation unit generating layout data based on the circuit connection data, first constraint data and second constraint data.

[0013] One aspect of the present invention is a circuit layout generation system comprising a storage unit, a constraint data calculation unit, and a layout data calculation unit, wherein the storage unit has the function of storing circuit connection data and first constraint data, the circuit connection data being data relating to the connections of transistors and capacitors in a pixel circuit, the first constraint data being data for setting the wiring interval of transistors and capacitors and data for setting the placement coordinates of transistors and capacitors, the constraint data calculation unit having the function of generating second constraint data based on the circuit connection data and first constraint data and storing the second constraint data in the storage unit, the second constraint data being data for setting the transistors and capacitors specified in the placement coordinates to be placed in close proximity, and the layout data calculation unit generating layout data based on the circuit connection data, first constraint data and second constraint data.

[0014] In one embodiment of the present invention, a layout generation system is preferred in which the pixel circuit is a pixel circuit connected to a light-emitting device.

[0015] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings. [Effects of the Invention]

[0016] One aspect of the present invention can provide a circuit layout generation system that can reduce the impact on display quality. Alternatively, one aspect of the present invention can provide a circuit layout generation system that can shorten the design period. Alternatively, one aspect of the present invention can provide a circuit layout generation system that can reduce costs such as labor costs. Alternatively, one aspect of the present invention can provide a novel circuit layout generation system.

[0017] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0018] [Figure 1] FIG. 1 is a diagram for explaining a configuration example of a circuit layout generation system. [Figure 2] FIG. 2 is a diagram for explaining a configuration example of a circuit layout generation system. [Figure 3] FIGS. 3(A) and 3(B) are diagrams for explaining a configuration example of a circuit layout generation system. [Figure 4] FIGS. 4(A) and 4(B) are diagrams for explaining a configuration example of a circuit layout generation system. [Figure 5] FIG. 5 is a diagram for explaining a configuration example of a circuit layout generation system. [Figure 6] FIGS. 6(A) and 6(B) are diagrams for explaining a configuration example of a circuit layout generation system. [Figure 7] FIGS. 7(A) and 7(B) are diagrams for explaining a configuration example of a circuit layout generation system. [Figure 8] FIGS. 8(A) and 8(B) are diagrams for explaining a configuration example of a circuit layout generation system. [Figure 9] FIGS. 9(A) and 9(B) are diagrams for explaining a configuration example of a circuit layout generation system.

Best Mode for Carrying Out the Invention

[0019] Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different forms, and the forms and details can be variously changed without departing from the spirit and scope thereof. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0020] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0021] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the active layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0022] The following describes an embodiment relating to one aspect of the present invention.

[0023] A circuit layout generation system according to one aspect of the present invention can be applied in particular to the generation of layout data for transistors and capacitors in pixel circuits of a display device. The circuit layout generation system can also be described as a system for generating layout data for pixel circuits.

[0024] Figure 1 shows an example of a hardware configuration capable of running a circuit layout generation system according to one aspect of the present invention.

[0025] The circuit layout generation system 100 includes an input unit 10, an output unit 20, a storage unit 30, and an arithmetic unit 40.

[0026] The input unit 10 may include, for example, human interface devices such as keyboards, mice, or touch panels; cameras such as digital cameras and digital video cameras; scanners; and read-only external storage devices such as CD-ROMs and DVD-ROMs. Alternatively, the system may be configured to receive input via a communication line such as the Internet.

[0027] The output unit 20 may include, for example, an EL display device or a liquid crystal display device. Alternatively, the output may be configured to be transmitted via a communication line such as the Internet.

[0028] The memory unit 30 can be ROM (Read Only Memory), RAM (Random Access Memory), SSD (Solid State Drive), or hard disk drive, among other examples.

[0029] The memory unit 30 has the function of storing multiple types of data, such as circuit connection data or constraint data. Figure 1 shows the memory area 31B for storing circuit connection data and the memory areas 31A and 31C for storing constraint data, for the purpose of the explanation to be described later.

[0030] One example of a configuration in which the arithmetic unit 40 is equipped with multiple arithmetic circuits such as CPUs or GPUs is an example. The arithmetic unit 40 has the function of executing programs stored in the storage unit 30. Such programs include functions for generating constraint data or functions for generating layout data. The function of the arithmetic unit 40 that executes the function for generating constraint data is sometimes called the constraint data arithmetic unit. The function of the arithmetic unit 40 that executes the function for generating layout data is sometimes called the layout data arithmetic unit.

[0031] Figure 1 shows a constraint data calculation unit 41A, which executes a program in the calculation unit 40 to generate new constraint data based on circuit connection data and constraint data, for the purpose of the explanation described later. Also in Figure 1, for the purpose of the explanation described later, a layout data calculation unit 41B is shown, which executes a program in the calculation unit 40 to generate pixel circuit layout data based on circuit connection data and multiple constraint data.

[0032] The circuit layout generation system 100 shown in Figure 1 is configured to generate new constraint data in the calculation unit 40. This configuration reduces the amount of data related to constraint conditions stored in the storage unit 30. The new constraint data generated by the calculation unit 40 is data that excludes combinations that may result in inappropriate layout data. The new constraint data generated by the calculation unit 40 is generated based on circuit connection data and constraint data provided in advance by the designer, is temporarily stored in the storage unit 30, and can then be provided to the calculation unit 40. Since the newly generated constraint data can exclude combinations that may result in inappropriate layout data, the number of calculation trials required to generate optimized layout data can be reduced.

[0033] Furthermore, in the circuit layout generation system 100 shown in Figure 1, the calculation unit 40 can generate pixel circuit layout data based on circuit connection data and multiple constraint data. Therefore, the design period can be shortened compared to when pixel circuit layout data is created manually. In addition, human costs can be reduced. Moreover, the number of trials for generating layout data can be increased, which can optimize circuit performance.

[0034] This section describes a flowchart for generating circuit layout data, such as transistors and capacitors, within a pixel circuit. First, Figure 2 illustrates a flowchart for explaining the overall process performed by the circuit layout generation system 100.

[0035] Before generating the circuit layout, the designer (user) performs circuit design and verification (step S10). Circuit design and verification involves simulations to ensure the circuit operates correctly. Step S10 involves circuit design and verification up to the point of placing elements such as transistors and capacitors required for the pixel circuit, as well as the wiring that provides signals to drive these elements. The success or failure of this circuit design and verification is determined in the judgment (PASS?) in step S11.

[0036] Next, the circuit layout generation system 100 performs the layout design (step S12). In step S12, by generating layout data for the pixel circuit including transistors and capacitors, it is possible to reduce the impact on display quality, shorten the design period, or reduce costs such as labor costs.

[0037] The layout data obtained in step S12 is subjected to circuit connection verification by the designer (step S13). Circuit connection verification verifies whether the circuit designed in step S10 and the layout data generated in step S12 represent the same circuit. The pass / fail result of this circuit connection verification is determined in step S14 (PASS?).

[0038] The layout data whose circuit connections have been verified in step S14 is then subjected to design rule verification by the designer (step S15). Design rule verification confirms whether the layout data generated in step S12 meets the requirements for a layout pattern (such as trace width or spacing between traces) that can be manufactured in the semiconductor manufacturing process, as defined in the PDK (Process Design Kit). The pass / fail result of this design rule verification is determined in step S16 (PASS?).

[0039] In step S16, the layout data for which the design rules have been verified is subjected to parasitic capacitance component extraction (step S17). Parasitic capacitance component extraction calculates circuit parameters that depend on the circuit layout (such as the resistance value of the wiring or the capacitance value due to the overlap between layout patterns) from the layout data generated in step S12.

[0040] In step S17, the layout data from which parasitic capacitance components have been extracted is subjected to circuit performance verification by the designer (step S18). Circuit performance verification involves simulating the circuit, including the circuit parameters dependent on the circuit layout extracted in step S16, to confirm whether the circuit performance meets the design requirements set by the designer. The pass / fail result of this circuit performance verification is determined in step S19 (PASS?).

[0041] By following the steps described above, the desired circuit layout data can be obtained.

[0042] Next, we will describe in detail the case in which a circuit layout generation system according to one embodiment of the present invention is applied to the layout design shown in step S12 of Figure 2. Figure 3(A) shows a flowchart illustrating the multiple steps (subroutines) involved in generating layout data such as transistors and capacitors within a pixel circuit.

[0043] First, the first constraint data (hereinafter referred to as the first constraint condition) stored in the storage area 31A of the storage unit 30 is read and assigned (inputted) to the constraint data calculation unit 41A of the calculation unit 40 (step S20). Next, the circuit connection data stored in the storage area 31B of the storage unit 30 is read and assigned (inputted) to the constraint data calculation unit 41A of the calculation unit 40 (step S21). The order of steps S20 and S21 may be reversed, or they may be performed simultaneously.

[0044] The first constraint refers to the constraints that are predetermined by the designer. Examples include the condition that the orientation of the source and drain of the semiconductor layer in a transistor, and the orientation of the gate (back gate), must be aligned and arranged at equal intervals (1D layout); the coordinate conditions for constraining the placement of each element (wiring grid); the condition for series arrangement (source and drain in series) when arranging multiple transistors; the condition for parallel arrangement (source and drain in parallel) when arranging multiple transistors; or conditions related to the shape of capacitive elements. In other words, the wiring grid is a condition that divides the area where the pixel circuit is provided into multiple areas (e.g., a mesh) and restricts the coordinates for placing elements. By applying the 1D layout and wiring grid, the electrical characteristics of each element can be stabilized in the generated pixel circuit layout data.

[0045] Circuit connection data corresponds to information such as a netlist. The netlist is data created by the designer during the circuit design in step S10 above. The netlist includes information such as the channel length and channel width size of transistors (transistor size), and connection information between terminals such as the gate (back gate), source, drain, etc. of transistors, and electrodes, etc. of capacitors. Initial information may also include information such as whether some transistors and capacitors are placed close together or spaced apart. It may also include information specifying the coordinates of some transistors and capacitors.

[0046] Next, the constraint data calculation unit 41A of the arithmetic unit 40 generates second constraint data (hereinafter referred to as the second constraint condition) based on the first constraint condition and circuit connection data provided to it (step S22). Figure 4(A) is a schematic diagram showing the flow of each data in steps S20 to S22. In Figure 4(A), the data D1 of the first constraint condition and the data D2 of the circuit connection data are provided to the constraint data calculation unit 41A of the arithmetic unit 40, generating the data D3 of the second constraint condition, which is then stored in the storage area 31C of the storage unit 30.

[0047] The second constraint refers to the constraint generated by the constraint data calculation unit 41A of the calculation unit 40. For example, it refers to constraints that specify coordinates for placing transistors or capacitors connected to the same wiring or terminals in close proximity, by referring to circuit connection data, etc.

[0048] The constraint data calculation unit 41A of the calculation unit 40 generates a second constraint condition that takes into account the circuit connection data information. This allows the designer's circuit layout image to be incorporated during circuit data design, while also excluding combinations that could result in inappropriate layout data. As a result, the number of trials required for optimization can be reduced.

[0049] A pattern is generated based on the data D1 of the first constraint, the data D2 of the circuit connection data, and the data D3 of the second constraint generated in step S22 (step S23). If the generated pattern is correct, it is output as layout data to the output unit 20 or the like (step S24).

[0050] Figure 3(B) shows the flowchart of the pattern generation subroutine shown in step S23. Element placement is performed using automatic placement (step S30), and a determination is made as to whether the placement is correct or not (step S31). Next, wiring connections are made using automatic routing (step S32), and a determination is made as to whether the connections are correct or not (step S33). If both the element placement and wiring connections are correct, the layout data is completed, and pattern generation is finished (step S34).

[0051] Element placement can be determined using methods based on dynamic models, such as cluster growth. Alternatively, the placement of transistors and capacitors can be attempted using methods such as Min-Cut, pair-swapping, relaxation, or Steinberg. Furthermore, wiring connections can be attempted by applying methods such as maze methods, line-search methods, channel wiring methods, or genetic algorithms to determine the wiring connections between each element.

[0052] Figure 4(B) schematically shows the flow of each data during pattern generation as shown in step S23. In Figure 4(B), the data D1 of the first constraint, the data D2 of the circuit connection data, and the data D3 of the second constraint are provided to the layout data calculation unit 41B of the calculation unit 40, and the layout data L D The diagram illustrates how the output is generated and output to the output unit 20 (indicated by the thick arrow).

[0053] Figures 5 to 9(B) illustrate an example of designing a pixel circuit for a display device by applying a circuit layout generation system according to one embodiment of the present invention.

[0054] Figure 5 shows the circuit diagram of the pixel circuit for driving the light-emitting element. Figure 5 shows transistors M1 to M9, wiring G1 to G3, wiring SL, wiring AN, wiring ML, terminal PX, nodes N1 to N5, and node GR. The light-emitting element is omitted for simplicity in the explanation.

[0055] Wirings G1 to G3 function as gate signal lines (scan lines) that provide signals to control the on / off state of transistors M1 to M3, which function as switches. Wiring SL functions as a data signal line (source line or data line) that provides data signals to the pixel circuit. Wiring AN functions as a current supply line to supply current to the light-emitting element connected to the pixel circuit. Terminal PX is the terminal to which a light-emitting element such as an organic EL is connected. Transistors M4 to M9 function as drive transistors to supply current to the light-emitting element based on the data signal. Wiring ML functions as an output line for externally measuring the current value of the drive transistor. Wiring ML also functions as a power supply line for setting the potential of node GR or terminal PX to a constant potential.

[0056] The circuit connection data corresponds to the data representing the connections in the pixel circuit shown in Figure 5. This data can be described as data using SPICE (Simulation Program with Integrated Circuit Emphasis).

[0057] For example, in the pixel circuit shown in Figure 5, the data representing the connections includes information such as the gate of transistor M1 being connected to wiring G1, one of its source or drain being connected to node GR, and the other source or drain being connected to wiring SL. This information is described as SPICE data. Similarly, the connections between each transistor and wiring or nodes are described as SPICE data.

[0058] Furthermore, by inserting blank rows into the SPICE data, it is possible to create data that places connections or transistors at a distance from each other. Alternatively, data specifying the initial coordinates of any element can be provided.

[0059] The first constraint can be the distance between wires, the 1D layout, or the wiring grid. It is preferable not to impose constraints on global wiring such as gate signal lines, data signal lines, current supply lines, or power lines, which have little impact on circuit performance. In other words, it is acceptable for elements to be connected to any node on the global wiring.

[0060] Furthermore, a second constraint that restricts the placement of transistors can be added based on the first constraint and circuit connection data described above. In the example of the pixel circuit in Figure 5, the second constraint is a condition for restricting the placement pattern of transistors M4 to M9 connected to nodes N1 to N5 and node GR.

[0061] The layout data derived from the first constraint, circuit connection data, and second constraint is weighted to determine placement when no positional information is provided. The second constraint, etc., restricts the range of element placement for optimization purposes relative to the initial element positions, allowing for the exploration of element and wiring placements. This enables automatic layout under local conditions, thereby reducing combination patterns and enabling automatic layout within the element placement intended by the designer.

[0062] One example of element and wiring arrangement is shown in the flowchart in Figure 6(A). For example, it can be represented by steps S41 to S46, in which case layout data is obtained for arranging four wiring layers on a semiconductor layer. In other words, this is an example of determining the element arrangement and wiring arrangement of transistors M1 to M9 in a top-gate structure transistor.

[0063] Specifically, first, the area where the pixel circuit will be placed is divided into a mesh (step S41). Next, the semiconductor layers are arranged (step S42). Then, the first wiring layer on the same layer as the gate electrode is arranged (step S43). Next, the second wiring layer on the same layer as the source electrode or drain electrode is arranged (step S44). Next, the third wiring layer is arranged (step S45). Finally, the fourth wiring layer on the same layer as the pixel electrode is arranged (step S46). Each of these steps is performed automatically by the circuit layout generation system 100.

[0064] Each layer shown in steps S42 to S46 corresponds to the conductive layer and semiconductor layer in the transistor shown in the schematic cross-sectional diagram of Figure 6(B). For example, the semiconductor layer placed in step S42 corresponds to semiconductor layer P42 in the schematic cross-sectional diagram of Figure 6(B). The wiring layer placed in step S43 corresponds to conductive layer P43 in the schematic cross-sectional diagram of Figure 6(B). The wiring layer placed in step S44 corresponds to conductive layer P44 in the schematic cross-sectional diagram of Figure 6(B). The wiring layer placed in step S45 corresponds to conductive layer P45 in the schematic cross-sectional diagram of Figure 6(B). The wiring layer placed in step S46 corresponds to conductive layer P46 in the schematic cross-sectional diagram of Figure 6(B).

[0065] The schematic diagrams of the arrangement of conductive and semiconductor layers in each layer shown in Figures 7(A) to 9(B) correspond to steps S41 to S46. The reference numerals in Figures 7(B) to 9(B) correspond to the reference numerals attached to the wiring or nodes, etc., of the pixel circuit shown in Figure 5.

[0066] Figure 7(A) illustrates a region where the area in which each element of the pixel circuit shown in Figure 5 is placed is divided into a mesh. By placing elements in the mesh-divided region, the coordinates of the area in which elements are placed can be restricted for optimization relative to the initial position of the elements, allowing for the exploration of element placement and wiring paths.

[0067] Figure 7(B) shows the region in which the semiconductor layer P42 shown in Figure 6(B) is arranged within the mesh-like divided region shown in Figure 7(A). As described above, in one aspect of the present invention, new constraints are generated from pre-given constraints and circuit connection data, and layout data is generated including these constraints. This configuration allows for the suppression of pre-given constraints and efficient restriction of the conditions for generating layout data. The number of divisions in the mesh-like divided region is preferably determined according to the spacing (design rules) of transistors and wiring. By using a configuration that divides the region into a mesh-like shape and determines the arrangement, unnecessary combinations are reduced in the automatically generated layout data, and many pixel circuit layout candidates can be created.

[0068] Figure 8(A) shows the areas in the mesh-like region shown in Figure 7(A) where the conductive layer P43 shown in Figure 6(B) is placed. In Figure 8(A), the mesh-like regions marked with an "x" represent areas where the conductive layer P43 is not placed. When stacking another circuit on the layer below the pixel circuit, it is necessary to consider parasitic components between the lower layer and the stack.

[0069] Figure 8(B) shows the region in which the conductive layer P44 shown in Figure 6(B) is arranged within the mesh-like divided region shown in Figure 7(A).

[0070] Figure 9(A) shows the region where the conductive layer P45 shown in Figure 6(B) is arranged within the mesh-like region shown in Figure 7(A). It is preferable to make the capacitance in the overlapping wiring layers as large as possible to stabilize the data potential for displaying the image and reduce parasitic capacitance with nodes that experience potential fluctuations. Furthermore, the wiring (G1, G2, G3) has a large signal amplitude and a significant impact on its surroundings. Therefore, it is preferable to set a first constraint condition to ensure that parasitic capacitance is not added to nodes sensitive to potential changes. Also, the wiring (G1, G2, G3) needs to have reduced parasitic capacitance to suppress gate signal degradation. Finally, it is preferable to set a first constraint condition for node GR to reduce parasitic capacitance and other factors in order to maintain its potential.

[0071] Figure 9(B) shows the region in which the conductive layer P46 shown in Figure 6(B) is arranged within the mesh-like divided region shown in Figure 7(A). Since wiring SL is for supplying data signals to each pixel circuit, it is preferable to set it as a first constraint condition so that parasitic capacitance and the like are reduced. The same applies to wiring ML. On the other hand, since wiring AN is for supplying a fixed potential, slight potential fluctuations do not affect the display quality within the range in which the drive transistor operates in the saturation region.

[0072] The schematic diagrams of the arrangement of conductive and semiconductor layers in each layer shown in Figures 7(A) to 9(B) above involve many parameters that must be considered when performed manually. Therefore, optimizing the layout data automatically using a circuit layout generation system allows for exploration under more conditions and optimization in a shorter time than manual optimization.

[0073] As described above, in one aspect of the present invention, the circuit layout generation system is configured to generate new constraint data in the calculation unit, thus not increasing the amount of data related to constraint conditions stored in the memory unit. The constraint data necessary for generating layout data can be appropriately modified based on the circuit connection data and constraint data and provided to the calculation unit. The newly generated constraint data incorporates the designer's circuit placement image at the time of circuit connection data generation and can exclude combinations that may result in inappropriate placements. Therefore, the number of trials required for optimization can be reduced.

[0074] Furthermore, in a circuit layout generation system according to one aspect of the present invention, the calculation unit can generate pixel circuit layout data based on circuit connection data and multiple constraint data. Therefore, the design period can be shortened compared to when pixel circuit layout data is created manually. In addition, human costs can be reduced. Furthermore, the number of trials for generating layout data can be increased, thereby optimizing circuit performance.

[0075] <Notes regarding the description in this specification, etc.> The above embodiments and a description of each component in those embodiments are provided below.

[0076] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples can be appropriately combined.

[0077] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0078] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0079] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0080] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

[0081] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0082] In this specification and other documents, when describing the connections of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the context.

[0083] Furthermore, in this specification, the terms "electrode" or "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0084] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0085] In this specification, terms such as "film" and "layer" may be interchanged depending on the context or situation. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0086] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0087] In this specification, channel length refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of a transistor, or in the region where the channel is formed.

[0088] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0089] In this specification, "A and B are connected" includes not only those that are directly connected, but also those that are electrically connected. Here, "electrically connected" means that when there is an object between A and B that has some kind of electrical effect, it enables the exchange of electrical signals between A and B. [Explanation of symbols]

[0090] AN wiring GR node LD layout data ML wiring P42 Semiconductor Layer P43 Conductive layer P44 conductive layer P45 Conductive layer P46 Conductive layer PX terminal SL wiring 10 Input section 20 Output section 30 Storage section 31A storage area 31B storage area 31C storage area 40 Arithmetic section 41A Constraint Data Calculation Unit 41B Layout Data Calculation Unit 100 generation systems

Claims

1. Memory unit and, Constraint data calculation unit, It has a layout data calculation unit, The storage unit has the function of storing circuit connection data and first constraint data. The constraint data calculation unit has the function of generating second constraint data based on the circuit connection data and the first constraint data, and storing the second constraint data in the storage unit. The layout data calculation unit generates layout data based on the circuit connection data, the first constraint data, and the second constraint data, and is a circuit layout generation system.

2. Memory unit and, Constraint data calculation unit, It has a layout data calculation unit, The storage unit has the function of storing circuit connection data and first constraint data. The circuit connection data is data relating to the connections of transistors and capacitors in the pixel circuit. The first constraint data includes data that sets the interval between the transistor and the capacitor, The constraint data calculation unit has the function of generating second constraint data based on the circuit connection data and the first constraint data, and storing the second constraint data in the storage unit. The second constraint data is data that sets the transistor and the capacitor connected to the same wiring to be placed in close proximity. The layout data calculation unit generates layout data based on the circuit connection data, the first constraint data, and the second constraint data, and is a circuit layout generation system.

3. Memory unit and, Constraint data calculation unit, It has a layout data calculation unit, The storage unit has the function of storing circuit connection data and first constraint data. The circuit connection data is data relating to the connections of transistors and capacitors in the pixel circuit. The first constraint data includes data for setting the spacing between the transistor and the capacitor, and data for setting the arrangement coordinates of the transistor and the capacitor. The constraint data calculation unit has the function of generating second constraint data based on the circuit connection data and the first constraint data, and storing the second constraint data in the storage unit. The second constraint data is data that sets the transistor and capacitor specified in the arrangement coordinates to be placed in close proximity to each other. The layout data calculation unit generates layout data based on the circuit connection data, the first constraint data, and the second constraint data, and is a circuit layout generation system.

4. In claim 2 or claim 3, The aforementioned pixel circuit is a pixel circuit connected to a light-emitting element, and is a circuit layout generation system.

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