Wiring board, semiconductor device, and method for manufacturing a wiring board

Abstract

To provide a wiring board, a semiconductor device and a wiring board manufacturing method capable of aligning the heights of semiconductor chips even when different semiconductor chips are mounted while maintaining a uniform pitch interval of solder balls.SOLUTION: A wiring board 100 has a multilayer structure with a plurality of build-up layers 1. Among the build-up layers 1, a lastly formed build-up layer 3 on a surface side has a first solder pad 61 and a second solder pad 62. The surface side build-up layer 3 has a solder resist layer 4 on the surface side. The height from respective surfaces of the first solder pad 61 and the second solder pad 62 to a surface of the solder resist layer 4 differ.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board.

Background Art

[0002] Conventionally, as a semiconductor device in which a semiconductor element (semiconductor chip) is mounted, a semiconductor device using a wire bonding connection method using a fine metal wire such as a gold wire is known. In recent years, in order to meet the requirements for miniaturization, thinning, high speed, high integration, etc. of semiconductor devices, a flip chip bonding method wiring board (FC-BGA wiring board) formed so as to be able to be joined to the electrodes of a semiconductor chip through conductive protrusions called solder balls has been widely known (for example, see Patent Document 1).

[0003] Further, in fields such as servers and high-end computers (HPC), the configuration of the processor has a configuration called a plurality of multi-CPUs and multi-cores, so the processing speed has increased, and the amount of information handled by the processor has increased significantly. Along with this, the transmission capacity between the processor and the outside has also increased dramatically, and furthermore, high speed of the transmission speed is also required. Along with such an increase in transmission capacity and the requirement for high-speed transmission, the development of optical interconnection technology using optical signals for information processing in routers and servers has been promoted. And it is desired that devices, semiconductor packages, etc. using optical interconnection technology can correspond to the mounting methods of conventional electrical interconnections. In recent years, as a mounting method for optical interconnections, various types of optoelectronic hybrid substrates in which an optical semiconductor element (semiconductor chip) for transmitting and receiving optical signals is mounted on an FC-BGA wiring board have been proposed (for example, see Patent Document 2).

[0004] By the way, when mounting a plurality of semiconductor chips having different thicknesses (heights) on a wiring board, it is desirable that the heights of the upper surfaces of the respective semiconductor chips are aligned in terms of the design convenience of the wiring board or the semiconductor chips, the ease of attaching a heat spreader mounted on the upper part of the semiconductor chip, etc. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2001-85558 [Patent Document 2] Japanese Patent Publication No. 2011-107206 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, the optical semiconductor elements (semiconductor chips) mounted on the photoelectric mixed-signal substrate described in Patent Document 2 are often thicker (higher) than semiconductor chips that handle only electrical signals. As a result, in a printed circuit board on which semiconductor chips of different thicknesses (heights) are directly mounted, there will be differences in the height of the top surface of each semiconductor chip.

[0007] To align the height of the top surfaces of multiple mounted semiconductor chips, a semiconductor device has been devised, as described in Patent Document 1, that can individually adjust the height from the substrate electrodes to the semiconductor chip electrodes by changing the size of the solder balls. However, the semiconductor device in Patent Document 1 requires changing the pitch between solder balls to match the difference in solder ball size. If larger or smaller solder balls than usual are mounted without changing the pitch between solder balls, problems can occur during reflow, such as the solder balls joining together and creating unwanted connections, or the solder balls not being able to reach the electrodes of the semiconductor chip and thus failing to make a connection.

[0008] Furthermore, solder balls can be mounted on semiconductor chips, semiconductor packages, or printed circuit boards. When solder balls are mounted on a printed circuit board, solder balls of different diameters cannot be mounted simultaneously. Therefore, the process is increased because the mounting of solder balls must be repeated multiple times for each diameter. In addition, mounting solder balls of different diameters separately requires additional effort in considering the order in which they should be mounted.

[0009] This invention has been made in consideration of these circumstances, and aims to provide a wiring board, a semiconductor device, and a method for manufacturing a wiring board that can make the pitch spacing of solder balls uniform while also ensuring that the height of the top surface of the mounted product is the same even when semiconductor packages or semiconductor chips of different heights are mounted. [Means for solving the problem]

[0010] To solve the above problems, this invention proposes the following means. A wiring board according to a first aspect of the present invention is a multilayer wiring board having a plurality of build-up layers, wherein the last-formed surface-side build-up layer has a first solder pad and a second solder pad, and the surface-side build-up layer has a solder resist layer, and the heights from the surfaces of the first solder pad and the second solder pad to the surface of the solder resist layer are different.

[0011] According to a second aspect of the present invention, the wiring board according to the first aspect is characterized in that the solder resist layer has openings through which the surface of the first solder pad and the surface of the second solder pad are exposed to the surface side, and the surface of the solder resist layer excluding the openings has a substantially uniform height.

[0012] According to a third aspect of the present invention, the wiring board according to the first or second aspect further has a third solder pad in the surface-side build-up layer, wherein the first solder pad, the second solder pad, and the third solder pad are formed at equal intervals.

[0013] According to a fourth aspect of the present invention, a wiring board according to any one of the first to third aspects is characterized in that the first solder pad and the second solder pad are provided with solder balls of substantially the same diameter and substantially the same shape on the surface side.

[0014] According to a fifth aspect of the present invention, the wiring board according to the fourth aspect is characterized in that the difference in height between the first solder pad and the second solder pad is determined by the height of the semiconductor chip bonded to the surface side of the solder ball.

[0015] According to a sixth aspect of the present invention, the wiring board according to the fourth aspect is characterized in that the height difference between the first solder pad and the second solder pad is determined by the height of the mounting pad portion of the semiconductor chip that is bonded to the surface side of the solder ball.

[0016] A semiconductor device according to the seventh aspect of the present invention comprises a wiring board according to the fifth aspect and the semiconductor chip.

[0017] A semiconductor device according to the eighth aspect of the present invention comprises a wiring board according to the sixth aspect, the semiconductor chip, and the mounting pad portion.

[0018] A method for manufacturing a wiring board according to the ninth aspect of the present invention is a method for manufacturing a wiring board characterized in that, among a plurality of build-up layers, the last formed surface-side build-up layer has a first solder pad and a second solder pad, and the surface-side build-up layer has a solder resist layer, and the heights from the respective surfaces of the first solder pad and the second solder pad to the surface of the solder resist layer are different, the method comprising the steps of: forming a wiring layer and the first solder pad and the second solder pad on at least the surface-side build-up layer; forming a plating resist layer such that a part of the surface of the first solder pad and a part of the surface of the second solder pad are exposed to the surface side; depositing copper on the surface side of the first solder pad and the second solder pad by copper plating; peeling off the plating resist layer; forming the solder resist layer on the surface side of the surface-side build-up layer; and providing an opening in the solder resist layer such that a part of the surface of the first solder pad and a part of the surface of the second solder pad are exposed to the surface side. [Effects of the Invention]

[0019] According to the wiring board, semiconductor device, and method for manufacturing the wiring board of the present invention, the pitch spacing of solder balls can be made uniform, and even when semiconductor packages or semiconductor chips of different heights are mounted, the height of the top surface of the mounted product can be made uniform. Furthermore, the solder resist layer covers solder pads of different heights with a uniform height. As a result, when injecting underfill between the wiring board and the semiconductor chip after mounting the semiconductor chip, the flow of the underfill is not obstructed by steps and spreads smoothly, resulting in a significant improvement in the productivity of the underfilling process. [Brief explanation of the drawing]

[0020] [Figure 1] This figure shows a cross-section of a wiring board for FC-BGA according to the first embodiment of the present invention. [Figure 2]It is a diagram for explaining an example of a manufacturing process of a wiring board for an FC-BGA. [Figure 3] It is a diagram for explaining an example of a manufacturing process of a wiring board for an FC-BGA. [Figure 4] It is a cross-sectional view showing an example of a semiconductor device in which a semiconductor chip is mounted on a wiring board for an FC-BGA according to the second embodiment of the present invention. [Figure 5] It is a cross-sectional view showing an example of a semiconductor device in which a semiconductor chip is mounted on a wiring board for an FC-BGA according to the third embodiment of the present invention. [Figure 6] It is a diagram showing a modified example of a semiconductor device in which a semiconductor chip and a heat spreader are mounted on a wiring board for an FC-BGA according to the third embodiment of the present invention.

Mode for Carrying Out the Invention

[0021] (First Embodiment) The first embodiment of the present invention will be described with reference to FIGS. 1 to 3. In the embodiments and modified examples described below, components that correspond to each other are denoted by the same reference numerals, and descriptions of overlapping portions may be omitted. In the following description, expressions indicating relative or absolute arrangements such as "parallel", "orthogonal", "center", "coaxial", etc. represent not only such strict arrangements but also states in which they are relatively displaced with tolerances and angles or distances that can obtain the same function.

[0022] Here, as shown in FIG. 1, UP indicates the upper side and RH indicates the right side. In the following description of the wiring board 100 for FC-BGA, the vertical direction is the up-down direction (arrow UP is the upper side). In the up-down direction, the surface provided on the upper side is the upper surface (front surface), and the surface provided on the lower side opposite to the upper side is the lower surface (back surface). Further, the horizontal direction orthogonal to the up-down direction is the left-right direction (arrow RH is the right side). In the left-right direction, the direction opposite to the right side is the left side. As shown in FIG. 1, the wiring board 100 (wiring board) for FC-BGA according to the first embodiment of the present invention includes a wiring board 10 and solder balls 20.

[0023] The wiring board 10 is a multilayer substrate having multiple build-up layers. The wiring board 10 comprises a build-up layer (wiring layer) 1 and a solder resist layer 4.

[0024] The build-up layer (wiring layer) 1 is a layer in which multiple wiring layers are stacked. The build-up layer 1 comprises a first layer 2 and a second layer 3. Note that the build-up layer 1 is not limited to the multilayer structure of two layers stacked as illustrated in Figure 1, but may be a multilayer structure of three or more layers stacked.

[0025] As shown in Figure 1, the first layer 2 is one of the build-up layers 1 and is formed below. The first layer 2 is formed by layering interlayer insulating materials, such as epoxy resin, and laminating them using a hot press or the like. For example, a thermal insulating resin is used as the interlayer insulating material. In some cases, a material containing glass cloth is used as the interlayer insulating material. The first layer 2 may be formed of paper or other resins. The first layer 2 includes a plurality of third conductor parts 7 in some parts.

[0026] The third conductor portion 7 is formed from a conductive material whose main component is a metal such as copper. A portion of the first layer 2 shown in Figure 1 is provided with three third conductor portions 7 of substantially the same shape and size. The third conductor portions 7 are arranged in a single row along the left-right direction in a portion of the first layer 2.

[0027] The third conductor section 7 shown in Figure 1 is a pad-on-via structure in which interlayer conductive sections 71 called vias are provided on the pad section 72. However, the third conductor section 7 is not limited to a pad-on-via structure. The third conductor section 7 may also have the pad section 72 positioned so as not to overlap with the interlayer conductive section 71 in the vertical direction, using wiring or the like to connect the pad section 72 and the interlayer conductive section 71.

[0028] The interlayer conductive portion 71 is formed together with the pad portion 72 by electrolytic copper plating or the like in a hole that penetrates the first layer 2. The upper surface of the interlayer conductive portion 71 is at approximately the same height as the upper surface 2f of the first layer 2.

[0029] The pad portion 72 is provided above the interlayer conductive portion 71. The pad portion 72 is formed together with the interlayer conductive portion 71 by electrolytic copper plating or the like. The pad portion 72 protrudes upward from the first layer 2, and the upper surface of the pad portion 72 is the upper surface 7f of the third conductor portion 7.

[0030] The third conductor portion 7 is formed by integrating the interlayer conductive portion 71 and the pad portion 72 through a semi-additive plating process described later. Furthermore, the upper surfaces 7f of the three third conductor portions 7 are approximately the same height in the vertical direction.

[0031] The second layer 3 is laminated onto the upper surface (surface) 2f of the first layer 2. The second layer 3 is the last layer formed on the upper surface 1f of the build-up layer 1. The second layer 3 is formed, for example, by layering film-like interlayer insulating materials and laminating them using a hot-pressure press or the like, similar to the first layer 2. As the film-like interlayer insulating material, a thermosetting resin that hardens with the heat generated during lamination can be used. Furthermore, when opening via holes in the laminated interlayer insulating material using a photolithography method, a photosensitive insulating resin can also be used as the interlayer insulating material for the second layer 3. In this embodiment, the second layer 3 uses a photosensitive insulating resin layer 3a (see Figure 2(a), etc.), which will be described later.

[0032] A portion of the second layer 3 shown in Figure 1 is provided with multiple solder pads 6. As shown in Figure 1, three solder pads 6 are provided in a single row along the left-right direction in a portion of the second layer 3. The multiple solder pads 6 are arranged in a grid pattern, for example, on the upper surface 2f side of the first layer 2. The solder pads 6 shown in Figure 1 are stacked above the third conductor portion 7 to form stacked vias. However, the solder pads 6 do not need to be formed by stacking them like stacked vias; for example, they may be formed in a stepped shape like staggered vias, or in other shapes.

[0033] In this embodiment, the solder pad 6 is a pad-on-via structure, similar to the third conductor portion 7, consisting of a pad and vias provided on the pad. However, the solder pad 6 is not limited to a pad-on-via structure, and a pad may be provided using wiring or the like at a position that does not overlap the via in the vertical direction. Furthermore, the solder pad 6 may also be constructed using lands, wiring, or the like.

[0034] The solder pad 6 is formed by a plating process described later. The solder pad 6 serves as an electrode for joining with the semiconductor element. The solder pad 6 comprises a first solder pad 61, a second solder pad 62, and a third solder pad 63. In this embodiment, the second solder pad 62 and the third solder pad 63 are substantially the same shape and size as shown in Figure 1, so the description of the third solder pad 63 is omitted. Here, the pitch distance from the center of the first solder pad 61 to the center of the second solder pad 62 in the left-right direction is defined as pitch P1. The pitch distance from the center of the second solder pad 62 to the center of the third solder pad 63 is defined as pitch P2. In this embodiment, the lengths of pitch P1 and pitch P2 are substantially the same. Therefore, the first solder pad 61, the second solder pad 62, and the third solder pad 63 are formed at equal intervals on the second layer 3. Note that the lengths of pitch P1 and pitch P2 do not have to be the same.

[0035] The first solder pad 61 is located above the rightmost of the three third conductor portions 7. Note that the solder pad 6 is not limited to a stacked via, so the first solder pad 61 does not necessarily have to be located above the third conductor portion 7. The first solder pad 61 is located to the right of the second solder pad 62 and the third solder pad 63. As shown in Figure 1, the first solder pad 61 comprises a first conductor portion 81 and a second conductor portion 82.

[0036] The first conductor portion 81 is a plated portion provided above the pad portion 72 of the third conductor portion 7. The first conductor portion 81 is formed by a semi-additive plating process described later. The first conductor portion 81 is composed of, for example, an upper pad and a lower via formed in a through hole penetrating the second layer 3. The first conductor portion 81 is formed, for example, by plating each opening (first resist opening 4p, see Figure 3(a)) opened by exposure development described later. Furthermore, the first conductor portion 81 formed in each opening is formed so that the upper surfaces of the first conductor portion 81 are at the same height in the vertical direction, as shown in Figure 3(b). The upper pad of the first conductor portion 81 is formed to be larger than the inner diameter of the opening and protrudes upward from the second layer 3. The first conductor portion 81 may also include lands, wiring, etc.

[0037] The second conductor portion 82 is a plating layer provided above the first conductor portion 81. The second conductor portion 82 is formed by a semi-additive plating process described later. The outer diameter of the second conductor portion 82 is smaller than the outer diameter of the pad above the first conductor portion 81. After the first conductor portion 81 is formed by the plating process described later, the second conductor portion 82 is further formed above the first conductor portion 81 by a plating process. The first conductor portion 81 and the second conductor portion 82 are integrated to form the first solder pad 61.

[0038] The second solder pad 62 includes the first conductor portion 81 described above. The second solder pad 62 does not include the second conductor portion 82. The second solder pad 62 is formed between the first solder pad 61 and the third solder pad 63.

[0039] As shown in Figure 3(c), the second solder pad 62 and the third solder pad 63, which are equipped with the first conductor portion 81, are formed such that the heights of the upper surfaces 62f and 63f of the second solder pad 62 and the third solder pad 63 are approximately the same in the vertical direction. Furthermore, the height of the upper surface 61f of the first solder pad 61, which is equipped with the first conductor portion 81 and the second conductor portion 82, is higher than the upper surfaces 62f and 63f of the second solder pad 62 and the third solder pad 63, respectively, by the amount of the second conductor portion 82.

[0040] The solder resist layer 4 is a layer laminated on the upper surface (top surface) 1f of the build-up layer 1. The upper surface 4f of the solder resist layer 4 is the upper surface of the wiring board 10. The solder resist layer 4 may use, for example, a photosensitive insulating resin mainly composed of phenolic resin or polyimide resin, or it may contain fillers such as silica or alumina. The solder resist layer 4 is provided with openings 5.

[0041] The opening 5 is a hole formed in the solder resist layer 4. The opening 5 comprises a first opening 51, a second opening 52, and a third opening 53. As shown in Figure 1, the second opening 52 and the third opening 53 are substantially the same shape and size, so the description of the third opening 53 is omitted.

[0042] The first opening 51 is formed on the upper surface 4f of the solder resist layer 4 and accommodates a portion of the solder balls 20, which will be described later. The first opening 51 is formed above the first solder pad 61 and to the right of the second opening 52 and the third opening 53. The bottom surface of the first opening 51 is approximately the same as the upper surface 61f of the first solder pad 61 of the solder pads 6 of the second layer 3. The inner diameter of the first opening 51 is smaller than the upper surface 61f of the first solder pad 61.

[0043] The second opening 52 is formed on the upper surface 4f of the solder resist layer 4 and accommodates a portion of the solder balls 20, which will be described later. The second opening 52 is formed above the second solder pad 62. The bottom surface of the second opening 52 is approximately the same as the upper surface 62f of the second solder pad 62 of the solder pad 6 of the second layer 3. The inner diameter of the second opening 52 is smaller than the upper surface 62f of the second solder pad 62. The third opening 53 is formed above the third solder pad 63.

[0044] The first opening 51, the second opening 52, and the third opening 53, formed above the three solder pads 6, are arranged in this order from right to left in the left-right direction. That is, the first opening 51, the second opening 52, and the third opening 53 are each located above the solder pads 6 and are formed at equal intervals in the solder resist layer 4.

[0045] In the vertical direction, the height of the upper surface 4f of the solder resist layer 4 is uniformly formed. As described above, the height of the upper surface 61f of the first solder pad 61 is higher than the upper surfaces 62f and 63f of the second solder pad 62 and the third solder pad 63, respectively, by the amount of the second conductor portion 82. Here, as shown in Figure 1, let H1 be the height from the upper surface 61f of the first solder pad 61 to the upper surface 4f of the solder resist layer 4. Let H2 be the height from the upper surface 62f of the second solder pad 62 and the upper surface 63f of the third solder pad 63 to the upper surface 4f of the solder resist layer 4. Height H1 is smaller than height H2 by the amount of the second conductor portion 82. Therefore, heights H1 and H2 are different.

[0046] The solder ball 20 is formed from a material primarily composed of tin (Sn), such as a tin-silver solder (SnAg solder). The solder ball 20 comprises a first solder ball 21 and a second solder ball 22. The solder ball 20 may be made from the same material as the solder pad 6.

[0047] The first solder ball 21 is formed in a dome shape with an upward convexity on the upper surface 61f of the first solder pad 61. A portion of the lower part of the first solder ball 21 is housed in the first opening 51.

[0048] The second solder ball 22 is formed in a dome shape with its upper surface convex on the upper surface 62f of the second solder pad 62 and the upper surface 63f of the third solder pad 63. A portion of the lower part of the second solder ball 22 is housed in the second opening 52 and the third opening 53. In this embodiment, the first solder ball 21 and the second solder ball 22 are formed to be substantially the same shape and size.

[0049] Next, an example of the manufacturing process for the FC-BGA wiring board 100 described above will be explained using Figures 2 and 3.

[0050] In this embodiment, the wiring board 10 of the FC-BGA wiring board 100 is manufactured using a semi-additive process. The wiring board 10 is formed by creating a resist pattern that is the reverse of the wiring pattern formed on the upper surface of a seed layer, such as the seed layer 3b (see Figure 2(c)), which will be described later. Subsequently, the wiring board 10 is subjected to electrolytic copper plating to form a third conductor portion 7 on the first layer 2, and a first conductor portion 81 and a second conductor portion 82 on the second layer 3. Next, the resist pattern is removed from the wiring board 10, and finally, the seed layer is removed by flash etching.

[0051] First, as shown in Figure 2(a), a negative-type photosensitive insulating resin is applied to or laminated onto the upper surface 2f of the first layer 2 to form an insulating resin layer 3a. Here, a third conductor portion 7 is formed on the first layer 2 by a conventionally known method.

[0052] Next, as shown in Figure 2(b), the area where the insulating resin layer 3a remains intact is designated as the exposure area 3p, and the area above the position where the third conductor portion 7 is formed is designated as the unexposed area 3q. Exposure is then performed, followed by development. The exposure intensity of the exposure area 3p during this exposure process is 20,000 W / cm². 2 Less than 10,000 W / cm² is preferable, and even more preferably 10,000 W / cm² 2 The following is preferable:

[0053] As shown in Figure 2(c), development creates through-holes that penetrate the insulating resin layer 3a beneath the unexposed area 3q. If necessary, plasma treatment is performed on the through-holes to remove resin residue.

[0054] Subsequently, as shown in Figure 2(c), a seed layer 3b is formed on the upper surface of the insulating resin layer 3a using sputtering or vacuum deposition, consisting of a thin metal film or a chemical copper plating film. The seed layer 3b is a thin film layer that imparts conductivity. The seed layer 3b is removed by flash etching in the semi-additive process. The second layer 3 is formed through the above manufacturing process.

[0055] Next, as shown in Figure 2(d), the first resist layer (plating resist layer) 4a is formed on the upper surface 3f of the second layer 3 by coating or lamination.

[0056] Subsequently, as shown in Figures 2(e) and 3(a), the first resist openings 4p are formed above each through-hole in the second layer 3 by exposure and development.

[0057] Subsequently, as shown in Figures 3(b) and (c), electrolytic copper plating is performed until each opening (first resist opening 4p) is filled, thereby first forming the first conductor portion 81 in each opening. The height of the first conductor portion 81 in each opening is formed so that the upper surfaces of the first conductor portion 81 are at the same height in the vertical direction. As the material for the first conductor portion 81, for example, metals such as Cu and Ni, or alloys containing at least one metal selected from these metals can be used. Through the above process, the two first conductor portions 81 formed on the left side become the second solder pad 62 and the third solder pad 63, respectively.

[0058] Subsequently, as shown in Figure 3(c), the first resist layer (plating resist layer) 4a is removed using a stripping solution specifically designed for the plating resist being used, or a stripping solution with equivalent functionality.

[0059] Next, as shown in Figure 3(d), a second resist layer (plating resist layer) 4b is formed on the upper surface of the second layer 3 and the first conductor portion 81 by coating or lamination. Subsequently, a second resist opening 4q is formed on the rightmost first conductor portion 81 by exposure and development.

[0060] Subsequently, as shown in Figure 3(e), the second resist opening 4q is filled with electrolytic copper plating (deposition) to form the second conductor portion 82. As for the material of the second conductor portion 82, similar to the first conductor portion 81, for example, metals such as Cu and Ni, or alloys containing at least one metal selected from these metals can be used.

[0061] Through the above process, the first conductor portion 81 and the second conductor portion 82 are integrated to form the first solder pad 61. In this embodiment, the first conductor portion 81 and the second conductor portion 82 are formed from the same type of metal.

[0062] Subsequently, as shown in Figure 3(f), the second resist layer (plating resist layer) 4b is removed using a stripping solution specifically designed for the plating resist being used, or a stripping solution with equivalent functionality.

[0063] Furthermore, any excess electrolytic copper plating deposited as needed can be removed by physical or chemical polishing.

[0064] Here, the first resist layer 4a and the second resist layer 4b are for forming openings for electroplating before electroplating is performed on the seed layer 3b. In the case of a non-photosensitive plating resist layer, openings can be formed by screen printing or by irradiating with a laser beam to remove the desired portion and form the opening. In the case of a photosensitive plating resist layer, the opening is formed through an exposure and development process. The material of the plating resist layer does not need to be particularly limited as long as it is a material that can withstand the electroplating bath. For example, if the electroplating bath is a copper sulfate plating bath, it is acidic, so any acid-resistant material will suffice, and ordinary dry film resists or various liquid resists can be used.

[0065] Furthermore, the first conductor portion 81 and the second conductor portion 82 may be plated with a plating layer that is harder than copper plating and less prone to polishing, in addition to copper plating. For example, nickel plating can be suitably used.

[0066] Next, as shown in Figure 3(g), the solder resist layer 4 is formed on the upper surfaces of the second layer 3, the first solder pad 61, the second solder pad 62, and the third solder pad 63 by coating or lamination. Subsequently, exposure and development form openings 4r with radii approximately the same size as the first solder ball 21 and the second solder ball 22 on the upper surface 61f of the first solder pad 61, the upper surface 62f of the second solder pad 62, and the upper surface 63f of the third solder pad 63. Here, the formed openings 4r are the first opening 51, the second opening 52, and the third opening 53 described above. In this state, parts of the upper surface 61f of the first solder pad 61, the upper surface 62f of the second solder pad 62, and the upper surface 63f of the third solder pad 63 are exposed upwards. Surface treatment may be applied to the bottom of the openings 4r of the solder resist layer 4 as needed. Also, the height of the upper surface 4f of the solder resist layer 4, excluding the openings 4r, is formed uniformly.

[0067] Subsequently, as shown in Figure 3(h), solder paste is screen printed or flux is screen printed onto the first solder pad 61, second solder pad 62, and third solder pad 63 of the build-up layer 1 of the wiring board 10. Then, ball-shaped electrode terminals (solder balls) are ball-cast and reflowed to form solder balls 20, completing the FC-BGA wiring board 100. The FC-BGA wiring board 100 is formed by the above manufacturing process. Note that by repeating the steps in Figures 2(a) to 3(h), any number of layers can be formed on the upper surface of the wiring board 10.

[0068] In this embodiment, the above manufacturing method makes it possible to manufacture an FC-BGA wiring board 100 that includes solder pads 6 of different heights in some areas. Therefore, in the above manufacturing method, by adjusting heights H1 and H2, the upper surface height of the first solder ball 21 and the upper surface height of the second solder ball 22, which is approximately the same size and shape as the first solder ball 21, can be arbitrarily adjusted.

[0069] Furthermore, in this embodiment, heights H1 and H2 can be adjusted arbitrarily. That is, in the manufacturing method of the FC-BGA wiring board 100, the upper surface 4f of the solder resist layer 4 can be set to a uniform height while adjusting the height of each solder pad 6. Therefore, for example, when mounting liquid resin for encapsulating integrated circuits, such as underfill, onto the FC-BGA wiring board 100 with the upper surface 4f as the upper surface, good mountability can be maintained without hindering the flow of the liquid resin.

[0070] Furthermore, in this embodiment, the lengths of pitch P1 and pitch P2 are formed to be approximately the same. Therefore, for example, when mounting a semiconductor chip on the solder ball 20, it is possible to use it without having to match the length between each electrode (mounting pad portion) on the semiconductor chip side to the solder ball 20 on the FC-BGA wiring board 100. Moreover, since the lengths of pitch P1 and pitch P2 are approximately the same, the manufacturing of semiconductor chips becomes easier, and the time and effort required for the manufacturing process can be reduced.

[0071] (Second embodiment) Next, a second embodiment of the present invention will be described with reference to Figure 4. In the following description, components common to those already described will be denoted by the same reference numerals, and redundant descriptions will be omitted. Note that the following embodiments differ from the first embodiment in that the wiring board is different. Therefore, the following description will focus on the differences from the first embodiment. The semiconductor device 400 according to the second embodiment of the present invention includes a semiconductor chip 200 in addition to the FC-BGA wiring board 100A. As shown in Figure 4, the semiconductor chip 200 includes an optical communication semiconductor chip 210 and an electrical communication semiconductor chip 220. The electrical communication semiconductor chip 220 is shorter in height than the optical communication semiconductor chip 210 in the vertical direction. The FC-BGA wiring board 100A includes a wiring board 10A and solder balls 20. Note that the semiconductor chip 200 may include mounting pads, which are not shown. The mounting pads are located below the semiconductor chip 200 and are joined to the solder balls 20 to electrically connect the semiconductor chip 200 and the wiring board 10A.

[0072] The wiring board 10A has solder pads 6A on a part of the second layer 3 shown in Figure 4. Compared to the first embodiment, the wiring board 10A has a different number of solder pads 6A, as shown in Figure 4. The solder pads 6A are arranged in a single row along the left-right direction, with two second solder pads 62, three first solder pads 61, and two second solder pads 62 from the right. The solder pads 6A are arranged so that they are approximately equally spaced.

[0073] The difference in height between heights H1 and H2 in the vertical direction is arbitrarily adjusted so that when the semiconductor chip 200 is joined (mounted) to the solder ball 20 from above, the lower surface 3g of the second layer 3, which has the solder pad 6A, and the upper surface 200f of the semiconductor chip 200 are all at approximately the same height. In other words, the difference in height between heights H1 and H2 is determined by the height of the semiconductor chip 200. In this embodiment, as in the first embodiment, height H1 is set to be smaller than height H2. If the semiconductor chip 200 has a mounting pad portion, the difference in height between heights H1 and H2 may be determined by the height of the mounting pad portion.

[0074] The solder ball 20, similar to the first embodiment, comprises a first solder ball 21 and a second solder ball 22. The first solder ball 21 is formed on the upper surface 61f of the first solder pad 61. The second solder ball 22 is formed on the upper surface 62f of the second solder pad 62. The first solder ball 21 and the second solder ball 22 are formed to be substantially the same size and shape.

[0075] Next, the semiconductor chip 200 is mounted onto the FC-BGA wiring board 100A.

[0076] As shown in Figure 4, first, each electrode (mounting pad portion) of the two optical communication semiconductor chips 210 is mounted so as to contact the second solder ball 22 formed on the upper surface 62f of the second solder pad 62 of the wiring board.

[0077] Next, the electrodes (mounting pad portion) of the telecommunications semiconductor chip 220, which is shorter in height than the optical communication semiconductor chip 210 in the vertical direction, are mounted so that they contact the first solder ball 21 formed on the upper surface 62f of the first solder pad 61 of the wiring board 10A. At this time, since the height H1 is set to be smaller than the height H2, even though the telecommunications semiconductor chip 220 is shorter than the optical communication semiconductor chip 210, the upper surfaces 200f of all semiconductor chips 200 are at approximately the same height.

[0078] With the above configuration, multiple semiconductor chips 200 are mounted on the FC-BGA wiring board 100A to form a semiconductor device 400.

[0079] In this embodiment, heights H1 and H2 can be adjusted to match the heights of multiple semiconductor chips 200. Therefore, after mounting multiple semiconductor chips 200, the top surfaces 200f of all semiconductor chips 200 can be set to approximately the same height. Furthermore, when mounting, for example, a heat spreader or the like, to the top surface 200f of the semiconductor chip 200, it can be accurately attached to the semiconductor chip 200.

[0080] Furthermore, in this embodiment, the height of the upper surfaces of the first solder ball 21 and the second solder ball 22 can be adjusted without changing their respective sizes. Therefore, the first solder ball 21 and the second solder ball 22 can be easily formed on the wiring board 10A.

[0081] Furthermore, in this embodiment, if the first solder ball 21 and the second solder ball 22 are too large, a problem occurs where adjacent solder balls 20 join together, resulting in unwanted conductivity. Also, if the first solder ball 21 and the second solder ball 22 are too small, a problem occurs where they do not contact the respective mounting pads on the opposing semiconductor chip 200 during mounting, for example. In this embodiment, the occurrence of the above-mentioned problems can be reduced.

[0082] (Third embodiment) Next, a third embodiment of the present invention will be described with reference to Figure 5. In all of the following embodiments, the wiring board and semiconductor chip differ particularly from those of the second embodiment. The semiconductor device 400B according to the third embodiment of the present invention comprises an FC-BGA wiring board 100B and a semiconductor chip 200B. The semiconductor chip 200B comprises a first semiconductor chip 210B and a second semiconductor chip 220B, which have different lengths in the left-right direction. The first semiconductor chip 210B is shorter in length than the second semiconductor chip 220B in the left-right direction. The FC-BGA wiring board 100B comprises a wiring board 10B and solder balls 20. The semiconductor chip 200B may also have mounting pad portions (not shown), similar to the second embodiment.

[0083] The wiring board 10B is provided with solder pads 6B on a portion of the second layer 3 as shown in Figure 5. Compared to the first embodiment, the wiring board 10B has a different number of solder pads 6B, as shown in Figure 5. The solder pads 6B are arranged in a single row along the left-right direction, with one first solder pad 61, four second solder pads 62, and one first solder pad 61 from the right. The first solder pads 61 are provided at both ends of the wiring board 10B. The solder pads 6B are provided at approximately equal intervals. In this embodiment, as in the first and second embodiments, the height H1 is set to an arbitrary height such that it is smaller than the height H2.

[0084] The solder ball 20, as in the first and second embodiments, comprises a first solder ball 21 and a second solder ball 22. The first solder ball 21 is formed on the upper surface 61f of the first solder pad 61. The second solder ball 22 is formed on the upper surface 62f of the second solder pad 62. The first solder ball 21 and the second solder ball 22 are formed to be substantially the same size and shape.

[0085] Next, the semiconductor chip 200B is mounted onto the FC-BGA wiring board 100B.

[0086] As shown in Figure 5, first, the electrodes (mounting pad portion) of the first semiconductor chip 210B are mounted so that they contact the second solder ball 22 formed on the upper surface 62f of the second solder pad 62 of the wiring board 10B. At this time, in the vertical direction, the height of the upper surface 210Bf of the first semiconductor chip 210B and the height of the upper surface 21f of the first solder ball 21 are approximately the same.

[0087] Next, the second semiconductor chip 220B is mounted from above so as to overlap the first semiconductor chip 210B in the vertical direction. The electrodes (mounting pad portion) of the second semiconductor chip 220B are mounted so as to contact the first solder balls 21 formed on the upper surface 61f of the first solder pads 61 provided at both ends of the wiring board 10B.

[0088] With the above configuration, multiple semiconductor chips 200B are mounted on an FC-BGA wiring board 100B to form a semiconductor device 400B.

[0089] Even in this case, the FC-BGA wiring board 100B of this embodiment allows the height of the upper surfaces of the first solder balls 21 and the second solder balls 22 to be adjusted by adjusting heights H1 and H2, without having to change the size of the first solder balls 21 and the second solder balls 22, which are substantially the same size and shape. Therefore, the second semiconductor chip 220B can be mounted so that its lower surface 220Bg is in precise contact with the upper surface 210Bf of the first semiconductor chip 210B, while the upper surface 220Bf is substantially horizontal.

[0090] It should be noted that the present invention is not limited by the above-described embodiment. Furthermore, the components in the embodiment include those that can be easily conceived by those skilled in the art, those that are substantially the same, and those that fall within the so-called equivalent range. Moreover, the components disclosed in the embodiment can be combined as appropriate.

[0091] Although embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments, and design modifications and the like are also included within the scope of the gist of the present invention. Furthermore, the components shown in the above-described embodiments and the following modifications can be combined as appropriate.

[0092] (modified version) The wiring board of the FC-BGA wiring board of the present invention is not limited to the embodiments described above, and may be composed of a number of build-up layers. Furthermore, the third conductor portion and solder pads of the wiring board of the FC-BGA wiring board of the present invention are not limited to a pad-on-via structure. The third conductor portion and solder pads may be positioned so as not to overlap the vias in the vertical direction. Also, the pads are not an essential component and may be lands. The wiring board of the present invention may be composed of lands and wiring, or a combination of each.

[0093] Furthermore, the solder pads of the present invention do not need to be formed by stacking them like stacked vias; for example, they may be formed in a stepped shape like staggered vias, or in other shapes.

[0094] Furthermore, the FC-BGA wiring board of the present invention may also include an interposer board for chip connection, etc.

[0095] Furthermore, the number of solder pads, solder balls, etc., on the FC-BGA wiring board of the present invention is not limited. The number of solder pads, solder balls, etc., can be arbitrarily set according to the size or shape of the wiring board and the mounting pad area of ​​the semiconductor chip.

[0096] Furthermore, the FC-BGA wiring board of the present invention does not necessarily have to include solder balls 20. Solder balls 20 are not an essential component. Moreover, in the embodiments described above, the size and shape of the first solder ball 21 and the second solder ball 22 were substantially the same, but in the FC-BGA wiring board of the present invention, the size and shape of the first solder ball 21 and the second solder ball 22 may be different.

[0097] Furthermore, in the embodiments described above, the first solder pad 61, the second solder pad 62, and the third solder pad 63 are arranged in a single row along the left-right direction. However, the FC-BGA wiring board of the present invention is not limited to this, and may be arranged in a single row along a direction intersecting the left-right direction. The number of rows is also not particularly limited.

[0098] Furthermore, in the embodiments described above, the first conductor portion 81 and the second conductor portion 82 of the first solder pad 61, the second solder pad 62, and the third solder pad 63 are made of the same type of metal, but are not limited to this, and may be made of different metals.

[0099] Furthermore, the semiconductor chip 200 mounted on the FC-BGA wiring board 100A according to the second embodiment of the present invention comprises an optical communication semiconductor chip 210 and an electrical communication semiconductor chip 220, but is not particularly limited. The semiconductor chip 200 may be a conventionally known semiconductor made of, for example, silicon, gallium arsenide, selenium, or carbon. Similarly, the semiconductor chip 200B mounted on the FC-BGA wiring board 100B according to the third embodiment of the present invention is not particularly limited, and may be a conventionally known semiconductor made of, for example, silicon, gallium arsenide, selenium, or carbon. Moreover, the present invention can also be applied to mounting methods such as stacking semiconductor chip groups (3D mounting) and mounting semiconductor chip groups on an interposer (2.5D mounting).

[0100] Furthermore, although the above-described embodiment shows an example of semiconductor chip mounting, it is also possible to mount a semiconductor package in which semiconductors are mounted on a relay substrate instead of semiconductor chips.

[0101] Furthermore, in the second embodiment described above, the solder pad 6A comprises two second solder pads 62, three first solder pads 61, and two second solder pads 62 arranged in a single row along the left-right direction from the right. However, the present invention is not limited to this, and the solder pads may be arranged in a single row along a direction intersecting the left-right direction on the upper or lower surface of the FC-BGA wiring board. The order of arrangement and the number of solder pads are also not limited, and they may be arranged from the left instead of the right. Furthermore, the number of rows is not particularly limited. In addition, the solder pad 6B in the third embodiment may be formed in a single row along the left-right direction, similar to the solder pad 6A, or it may be formed in a single row along a direction intersecting the left-right direction.

[0102] Furthermore, in the FC-BGA wiring board 100B according to the third embodiment of the present invention, as shown in Figure 6, a heat spreader 300 may be mounted in place of the second semiconductor chip 220B of the semiconductor chip 200B. In this case as well, the FC-BGA wiring board 100B can be arbitrarily adjusted by adjusting heights H1 and H2 to control the upper surface height of the solder balls 20, which are formed on the upper surfaces of the first solder pad 61, the second solder pad 62, and the third solder pad 63 and are of substantially the same size and shape. Therefore, the heat spreader 300 can be mounted so that its lower surface 300g is in precise contact with the upper surface 210Bf of the first semiconductor chip 210B, while the upper surface 300f is mounted to be substantially horizontal.

[0103] In any of the above embodiments, according to the wiring board, semiconductor device, and method for manufacturing the wiring board according to the present invention, the pitch spacing of the solder balls can be maintained uniformly, and even when different semiconductor packages are mounted, the height of their top surfaces can be made uniform. [Industrial applicability]

[0104] According to the wiring board, semiconductor device, and method for manufacturing the wiring board of the present invention, the pitch spacing of solder balls can be maintained uniformly, and even when different semiconductor packages are mounted, the height of their top surfaces can be made uniform. This makes it easier to mount components that require high adhesion, such as heat sinks, in the assembly of electronic devices, and therefore it is industrially applicable. [Explanation of Symbols]

[0105] Wiring board for 100, 100A, and 100B FC-BGA (wiring board) 10, 10A, 10B Wiring Boards 1. Build-up layer (wiring layer) 2 First layer 3 Second layer 4 Solder Resist Layers 4a First resist layer (plating resist layer) 4b Second resist layer (plating resist layer) 5 Openings 6, 6A, 6B solder pads 61 First solder pad 62 Second solder pad 63 Third solder pad 7 Third conductor section 81 First conductor section 82 Second Conductor Section 20 solder balls 21 First Solder Ball 22 Second solder ball 200, 200B semiconductor chips 300 Heat Spreader 400, 400B Semiconductor Device H1, H2 Height P1, P2 pitch

Claims

1. A multilayer wiring substrate having multiple build-up layers, Of the aforementioned build-up layers, the last-formed surface-side build-up layer has a first solder pad, a second solder pad, and a third solder pad. The aforementioned surface-side build-up layer has a solder resist layer on the surface side, The aforementioned solder resist layer is The first solder pad surface, the second solder pad surface, and the third solder pad surface are provided with openings that expose the surface side, The surface of the solder resist layer, excluding the aforementioned opening, has a substantially uniform height. The first solder pad, the second solder pad, and the third solder pad are formed at equal intervals. Of the first solder pad, the second solder pad, and the third solder pad, some of the solder pads have a different height from the surface to the surface of the solder resist layer compared to the other solder pads. Each of the aforementioned solder pads and the aforementioned other solder pads is provided with a first conductor portion, The aforementioned solder pad is further characterized by having a second conductor portion on the first conductor portion, which is smaller in diameter than the first conductor portion and made of the same material as the first conductor portion. Wiring board.

2. The portion of the solder pads and the other solder pads are, The aforementioned surface is characterized by having solder balls of substantially the same diameter and substantially the same shape. The wiring board according to claim 1.

3. The part of the solder pad and the other solder pad are, The difference in height is determined by the height of the semiconductor chip bonded to the surface side of the solder ball. The wiring board according to claim 2.

4. The part of the solder pad and the other solder pad are, The difference in height is determined by the height of the mounting pad portion of the semiconductor chip that is bonded to the surface side of the solder ball. The wiring board according to claim 2.

5. The wiring board according to Claim 3, The aforementioned semiconductor chip, A semiconductor device equipped with a semiconductor device.

6. A wiring board according to claim 4, The aforementioned semiconductor chip, The aforementioned mounting pad section, A semiconductor device equipped with a semiconductor device.

7. Of the multiple build-up layers, the last-formed surface build-up layer has a first solder pad, a second solder pad, and a third solder pad. The aforementioned surface-side build-up layer has a solder resist layer on the surface side, The aforementioned solder resist layer is The first solder pad surface, the second solder pad surface, and the third solder pad surface are provided with openings that expose the surface side, The surface of the solder resist layer, excluding the aforementioned opening, has a substantially uniform height. The first solder pad, the second solder pad, and the third solder pad are formed at equal intervals. A method for manufacturing a wiring board, characterized in that some of the first solder pad, the second solder pad, and the third solder pad have a different height from the surface to the surface of the solder resist layer compared to the other solder pads, at least The process of forming a wiring layer and the first solder pad, the second solder pad, and the third solder pad on the surface-side build-up layer, A step of forming a plating resist layer such that a portion of the surface of the first solder pad, a portion of the surface of the second solder pad, and a portion of the surface of the third solder pad are exposed to the surface side, A step of forming a first conductor portion by depositing copper on the surface side of the first solder pad, the second solder pad, and the third solder pad by copper plating, A step of further forming the plating resist layer such that only a portion of the surface of the first conductor portion of the aforementioned solder pad is exposed to the surface side, A step of forming a second conductor portion by further depositing copper on the surface side of the first conductor portion of a portion of the solder pad by copper plating, The process of removing the aforementioned plating resist layer, The process of forming the solder resist layer on the surface side of the build-up layer on the surface side, The process involves providing the solder resist layer with the openings such that a portion of the surface of the first solder pad, a portion of the surface of the second solder pad, and a portion of the surface of the third solder pad are exposed to the surface side. A method for manufacturing a wiring board, characterized by including the following:

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