Integrated circuits, power supply circuits

Abstract

To provide an integrated circuit capable of suppressing an increase in number of terminals.SOLUTION: An integrated circuit comprises: a first terminal connected with a first resistor, a second resistor for temperature detection, and a switch; a current output circuit that outputs a current to the first terminal; a switch control circuit that brings the switch into a first state so as to apply a voltage according to the first resistor to the first terminal, and then brings the switch into a second state so as to apply a voltage according to the second resistor to the first terminal; a storage circuit; a processing circuit that stores an operation condition of the integrated circuit in the storage circuit on the basis of a first voltage of the first terminal at the time when the switch is in the first state; and a temperature detection circuit that detects a temperature on the basis of a second voltage of the first terminal at the time when the switch is in the second state.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to an integrated circuit and a power supply circuit.

Background Art

[0002] Patent Document 1 discloses a power supply circuit that generates an output voltage at a target level from an input voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, a power supply circuit is generally provided with an integrated circuit that controls the switching of a power transistor. In such an integrated circuit, if a dedicated terminal for determining the operating conditions of the integrated circuit is provided, the number of terminals of the integrated circuit increases.

[0005] The present invention has been made in view of the above conventional problems, and an object thereof is to provide an integrated circuit capable of suppressing an increase in the number of terminals.

Means for Solving the Problems

[0006] The first aspect of the present invention, which is the main aspect for solving the aforementioned problems, is an integrated circuit comprising: a first terminal to which a first resistor, a second resistor for temperature detection, and a switch are connected; a current output circuit that outputs current to the first terminal; a switch control circuit that sets the switch to a first state so that a voltage corresponding to the first resistor is applied to the first terminal, and then sets the switch to a second state so that a voltage corresponding to the second resistor is applied to the first terminal; a memory circuit; a processing circuit that stores the operating conditions of the integrated circuit in the memory circuit based on a first voltage at the first terminal when the switch is in the first state; and a temperature detection circuit that detects the temperature based on a second voltage at the first terminal when the switch is in the second state.

[0007] A second aspect of the present invention, which is the main aspect for solving the aforementioned problems, is a power supply circuit that generates an output voltage of a target level from an input voltage, comprising an inductor and a transistor for controlling the inductor current flowing through the inductor, the power supply circuit comprising a first resistor, a second resistor for temperature detection, a switch, and an integrated circuit for controlling the switching of the transistor, wherein the integrated circuit includes a first terminal to which the first resistor, the second resistor, and the switch are connected, a current output circuit for outputting a current to the first terminal, a switch control circuit for setting the switch to a first state so that a voltage corresponding to the first resistor is applied to the first terminal, and then setting the switch to a second state so that a voltage corresponding to the second resistor is applied to the first terminal, a memory circuit, a processing circuit for storing the operating conditions of the integrated circuit in the memory circuit based on a first voltage at the first terminal when the switch is in the first state, and a temperature detection circuit for detecting the temperature based on a second voltage at the first terminal when the switch is in the second state.

[0008] A third aspect of the present invention, which is the main aspect for solving the aforementioned problems, is an integrated circuit comprising: a first terminal to which a first resistor is connected; a current output circuit that outputs a current to the first resistor to the first terminal; a temperature detection circuit that detects temperature based on a first voltage at the first terminal generated by the current from the current output circuit; and a signal output circuit that outputs a setting signal via the first terminal to an external circuit provided outside the integrated circuit for setting the operation of the external circuit.

[0009] A fourth aspect of the present invention, which is the main aspect for solving the aforementioned problems, is a power supply circuit that generates an output voltage of a target level from an input voltage, comprising an inductor and a transistor for controlling the inductor current flowing through the inductor, wherein the power supply circuit comprises a first resistor and an integrated circuit for controlling the switching of the transistor, the integrated circuit including a first terminal to which the first resistor is connected, a current output circuit that outputs a current to the first resistor to the first terminal, a temperature detection circuit that detects the temperature based on a first voltage at the first terminal generated by the current from the current output circuit, and a signal output circuit that outputs a setting signal to an external circuit provided outside the integrated circuit via the first terminal for setting the operation of the external circuit. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide an integrated circuit that can suppress an increase in the number of terminals. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example of a power supply unit 10. [Figure 2] This figure shows an example of a variable resistor circuit 23. [Figure 3] This figure shows an example of a DC-DC converter 22. [Figure 4] This figure shows an example of the control IC 50. [Figure 5] This figure shows an example of drive signals Vdr1 and Vdr2 in normal mode. [Figure 6]It is a diagram showing an example of drive signals Vdr1 and Vdr2 in burst mode. [Figure 7] It is a diagram for explaining the switch control circuit 114 and the load detection circuit 115. [Figure 8] It is a diagram for explaining the voltage Vca. [Figure 9] It is a diagram for explaining the circuit 116. [Figure 10] It is a diagram for explaining the signal Sstb. [Figure 11] It is a diagram showing an example of the power factor improvement circuit 21. [Figure 12] It is a diagram showing an example of the power factor improvement IC605. [Figure 13] It is a diagram for explaining the operation of the DC-DC converter 22. [Figure 14] It is a flowchart showing an example of the process executed by the processing circuit 120.

Embodiments of the Invention

[0012] From the description in this specification and the attached drawings, at least the following matters become clear.

[0013] Here, the same or equivalent components, members, etc. shown in each drawing are denoted by the same reference numerals, and repeated explanations are omitted as appropriate. Also, in this embodiment, "connection" means a state of being electrically connected unless otherwise specified. For this reason, "connection" includes cases where two components are connected not only by wiring but also, for example, via a resistor.

[0014] =====This Embodiment===== <<<Overview of the Power Supply Device 10>>> FIG. 1 is a diagram showing an example of the power supply device 10. The power supply device 10 is a device that drives the load 11 based on, for example, a commercial AC voltage Vac. The power supply device 10 includes a full-wave rectifier circuit 20, an AC-DC converter 21, a DC-DC converter 22, and a variable resistor circuit 23.

[0015] The full-wave rectifier circuit 20 full-wave rectifies the AC voltage Vac applied to nodes N1 and N2 and outputs it as the voltage Vrec1.

[0016] The AC-DC converter 21 outputs an output voltage Vout1 (for example, 400V) based on the AC voltage Vac applied to nodes N1 and N2. Although details will be described later, the AC-DC converter 21 operates in a mode according to the signal Sstb transmitted from the DC-DC converter 22.

[0017] The DC-DC converter 22 generates an output voltage Vout2 (for example, 12V) based on the output voltage Vout1 generated between nodes N3 and N4.

[0018] The variable resistance circuit 23 is a circuit whose resistance value changes in the case of state setting and temperature detection described later. FIG. 2 is a diagram showing an example of the variable resistance circuit 23. The variable resistance circuit 23 includes resistors 100, 103, 104, a thermistor 101, an NMOS transistor 102, and a capacitor 105.

[0019] The resistor 100 is a resistor for setting the operating conditions of the DC-DC converter 22. Details of the setting of the operating conditions will be described later.

[0020] Also, in the present embodiment, the resistor 100 is connected to the line La connecting the DC-DC converter 22 and the AC-DC converter 21.

[0021] The thermistor 101 is, for example, a temperature detection resistor whose resistance value decreases as the temperature rises. In the present embodiment, the thermistor 101 is connected in series with the resistor 100.

[0022] The NMOS transistor 102 is connected in series with the resistor 100 and in parallel with the thermistor 101. Therefore, when the NMOS transistor 102 is turned on, the resistance value between the line La and the ground becomes the resistance value of the resistor 100. On the other hand, when the NMOS transistor 102 is turned off, the resistance value between the line La and the ground becomes the resistance value of the combined resistance of the resistor 100 and the thermistor 101. Here, the on-resistance of the NMOS transistor 102 is assumed to be sufficiently smaller than the resistance value of the resistor 100 and is ignored.

[0023] The resistors 103 and 104 are voltage dividing circuits for changing the state of the NMOS transistor 102, and divide the voltage Vca (described later) output from the DC-DC converter 22. Although details will be described later, the DC-DC converter 22 turns on the NMOS transistor 102 at startup and outputs a predetermined current to the line La. Therefore, in this case, the voltage of the line La becomes a level corresponding to the resistance value of the state setting resistor 100.

[0024] Also, when startup of the DC-DC converter 22 is completed, it turns off the NMOS transistor 102 and outputs a predetermined current to the line La. Therefore, in this case, the voltage of the line La becomes a level corresponding to the resistance value of the thermistor 101. Thus, in the present embodiment, by changing the state of the NMOS transistor 102, the voltage of the line La can be set to a level corresponding to the state setting resistor 100 or the thermistor 101 for temperature detection.

[0025] [[ID=-- -- -- -- --]] The capacitor 105 is an element for stabilizing the DC level of the voltage Vstb of the line La.

[0026] <<<Overview of the DC-DC Converter 22>>> FIG. 3 is a diagram showing an example of the DC-DC converter 22 of the present embodiment. The DC-DC converter 22 is an LLC current resonance type power supply circuit that generates an output voltage Vout2 (for example, 12V) at a target level from a predetermined input voltage Vout1 (for example, 400V).

[0027] The DC-DC converter 22 is comprised of capacitors 30, 31, 42, NMOS transistors 32, 33, a transformer 34, a control block 35, diodes 40, 41, a constant voltage circuit 43, and a light-emitting diode 44.

[0028] Capacitor 30 stabilizes the voltage between the power line to which the input voltage Vout1 is applied and the ground line on the earth side, thereby removing noise and other unwanted signals. The input voltage Vout1 is a DC voltage of a predetermined level.

[0029] NMOS transistor 32 is the high-side power transistor, and NMOS transistor 33 is the low-side power transistor. In this embodiment, NMOS transistors 32 and 33 are used as switching elements, but PMOS transistors or bipolar transistors may also be used, for example.

[0030] The transformer 34 is equipped with a primary coil L1, secondary coils L2 and L3, and an auxiliary coil L4, and the primary coil L1 (inductor), secondary coils L2 and L3, and auxiliary coil L3 are insulated from each other. In the transformer 34, a voltage is generated in the secondary coils L2 and L3 on the secondary side in response to a change in the voltage across the primary coil L1 on the primary side, and a voltage is generated in the auxiliary coil L4 on the primary side in response to a change in the voltage of the secondary coils L2 and L3.

[0031] Furthermore, the primary coil L1 has the source of NMOS transistor 32 and the drain of NMOS transistor 33 connected to one end, and the source of NMOS transistor 33 connected to the other end via capacitor 31.

[0032] Therefore, when the switching of NMOS transistors 32 and 33 begins, the voltages across the secondary coils L2 and L3 and the auxiliary coil L4 will change. Note that the primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with the same polarity, and the secondary coils L2 and L3 and the auxiliary coil L4 are also electromagnetically coupled with the same polarity.

[0033] Control block 35 is a circuit block for controlling the switching of NMOS transistors 32 and 33, and its details will be described later.

[0034] Diodes 40 and 41 rectify the voltages across secondary coils L2 and L3, and capacitor 42 smooths the rectified voltage. As a result, capacitor 42 generates a smoothed output voltage Vout2. The output voltage Vout2 is a DC voltage of the desired level (for example, 12V).

[0035] The constant voltage circuit 43 is a circuit that generates a constant DC voltage, and is constructed, for example, using a shunt regulator.

[0036] The light-emitting diode 44 is an element that emits light of an intensity corresponding to the difference between the output voltage Vout2 and the output of the constant voltage circuit 43, and together with the phototransistor 62, which will be described later, it constitutes a photocoupler. In this embodiment, as the level of the output voltage Vout2 increases, the intensity of the light from the light-emitting diode 44 increases.

[0037] ===Control Block 35=== The control block 35 includes a control IC 50, a diode 60, capacitors 61, 63, 64, 67, 68, a phototransistor 62, and resistors 65, 66.

[0038] The control IC 50 is an integrated circuit that controls the switching of NMOS transistors 32 and 33, and has terminals VCC, GND, STB, BO, FB, IS, CA, HO, LO, and VH.

[0039] Terminal VCC is the terminal to which the voltage Vcc required to operate the control IC 50 is applied. The cathode of diode 60 and capacitor 61, with one end grounded, are connected to terminal VCC. As will be explained in detail later, capacitor 61 is charged when the control IC 50 starts switching the NMOS transistors 32 and 33. The charging voltage of capacitor 61 then becomes the voltage Vcc required to operate the control IC 50.

[0040] The GND terminal is a terminal that is connected to (i.e., grounded to) the casing of a device, such as the power supply unit 10.

[0041] Terminal STB is a terminal that generates a voltage Vstb for setting the operating conditions of the control IC 50 when the control IC 50 is activated. In this embodiment, a thermistor 101 for temperature detection is connected to terminal STB, so a voltage Vstb corresponding to the temperature is generated at terminal STB. Furthermore, a signal Sstb for setting the operation of the AC-DC converter 21 is output from terminal STB.

[0042] Terminal BO is the terminal to which the voltage Vout1 output from the AC-DC converter 21 is applied.

[0043] Terminal FB is the terminal to which a feedback voltage Vfb corresponding to the output voltage Vout2 is generated, and a phototransistor 62 and a capacitor 63 are connected. The phototransistor 62 flows a bias current I1, whose magnitude corresponds to the light intensity from the light-emitting diode 44 in Figure 3, from terminal FB to ground, and the capacitor 63 is provided to remove noise between terminal FB and ground. Therefore, the phototransistor 62 operates as a transistor that generates sink current.

[0044] Terminal IS is a terminal to which a voltage corresponding to the resonant current of the DC-DC converter 22 is applied. Here, a voltage corresponding to the resonant current of the primary coil L1 is generated at the node to which capacitor 64 and resistor 65 are connected. The resistor 66 and capacitor 67 constitute a low-pass filter. Therefore, a voltage Vs from which noise components have been removed is applied to terminal IS, corresponding to the resonant current of the primary coil L1.

[0045] The resonant current increases in accordance with the input power of the DC-DC converter 22. Furthermore, the input power of the DC-DC converter 22 increases in accordance with the power consumed by the load 11. Therefore, the voltage Vs applied to terminal IS will represent a voltage corresponding to the power consumed by the load 11.

[0046] Terminal CA applies a voltage Vca to capacitor 68 that changes according to the voltage Vs at terminal IS.

[0047] Terminal VH is the terminal to which the rectified voltage Vrec1 is applied. The control IC 50 starts up based on the rectified voltage Vrec1 at terminal VH, charges the capacitor 61 at terminal VCC, and generates the voltage Vcc.

[0048] Terminal HO is the terminal to which the drive signal Vdr1, which drives the NMOS transistor 32, is output, and the gate of the NMOS transistor 32 is connected to it.

[0049] Terminal LO is the terminal to which the drive signal Vdr2, which drives the NMOS transistor 33, is output, and the gate of the NMOS transistor 33 is connected to it.

[0050] Note that "the state of load 14 is heavy load" refers to a case where, for example, the load current Iout flowing through load 14 is greater than a predetermined value (for example, 1A). Conversely, "the state of load 14 is light load" refers to a case where, for example, the load current Iout flowing through load 14 is less than a predetermined value (for example, 1A).

[0051] Here, "startup" refers to the operation from the time an AC voltage Vac is applied to the power supply 10 until the drive circuit 113 in the control IC 50 outputs drive signals Vdr1 and Vdr2 (described later).

[0052] In this embodiment, the "startup" of the control IC 50 includes at least the operation of a "state setting period" in which the various circuits of the control IC 50 are initialized after the AC voltage Vac is applied to the power supply 10.

[0053] <<<Details of Control IC 50>>> Figure 4 shows an example of the configuration of the control IC 50. The control IC 50 is composed of resistors 90-92, a startup circuit 110, an internal power supply (REG) 111, a control circuit 112, a drive circuit 113, a switch control circuit 114, a load detection circuit 115, and a circuit 116.

[0054] Resistors 90 and 91 constitute a voltage divider circuit that generates a voltage Vh by dividing the rectified voltage Vrec1. Resistor 92 is an element that generates a feedback voltage Vfb at terminal FB corresponding to a bias current I1 whose magnitude corresponds to the light intensity of the light-emitting diode 44 in Figure 2. The power supply voltage (described later) is applied to one end, and the other end is connected to terminal FB.

[0055] In this embodiment, when the output voltage Vout2 rises above the target level, the bias current I1 increases, causing the feedback voltage Vfb to decrease. Conversely, when the output voltage Vout2 falls below the target level, the bias current I1 decreases, causing the feedback voltage Vfb to rise.

[0056] Furthermore, in this embodiment, in addition to resistors 90 to 92, there are several resistors (not shown) that divide the output voltage Vout1 and output it to the control circuit 112, but these are omitted here for convenience.

[0057] ===Startup Circuit 110=== The startup circuit 110 generates a power supply voltage Vcc for the operation of the control IC 50 based on the rectified voltage Vrec1 when the control IC 50 is started (or when the power supply voltage Vcc is lower than a predetermined level). Specifically, the startup circuit 110 charges the capacitor 61 connected to terminal VCC based on the rectified voltage Vrec1 to generate the voltage Vcc.

[0058] Furthermore, once the voltage Vcc becomes sufficiently high and the control IC 50 has finished starting up, it stops charging the capacitor 61. After the control IC 50 has finished starting up, the capacitor 61 at terminal VCC is charged by the current from the auxiliary coil L4. ===Internal power supply 111=== The internal power supply 111 generates a power supply voltage Vreg (e.g., 5V) based on the power supply voltage Vcc to operate various circuits inside the control IC 50 (e.g., control circuit 112).

[0059] ===Control circuit 112=== The control circuit 112 is a circuit that provides overall control for the control IC 50. For example, the control circuit 112 stores the operating conditions of the control IC 50 based on the voltage Vstb, and controls the operation of various circuits of the control IC 50 based on the voltages Vh, Vca, Vstb, and Votp. Specifically, the control circuit 112 outputs signals Scnt, Sclmp, Sset, Sotp, Sdis, Scom, Smode, and Sope to control various circuits based on multiple input voltages.

[0060] The control circuit 112 is a digital controller that includes an AD converter (not shown) that converts the voltages Vh, Vca, Vout1, and Vstb into digital values, a processing circuit 120, and a memory circuit 121. As mentioned above, the divided voltage Vout1 is input to the control circuit 112, but for convenience, this explanation will assume that only the voltage Vout1 is input.

[0061] The processing circuit 120 stores information indicating the operating conditions of the control IC 50 in the memory circuit 121 based on the voltage input to the control circuit 112, and also outputs the various signals (signal Scnt, etc.) mentioned above. The details of the operation of the processing circuit 120 will be described later. The memory circuit 121 is composed of, for example, registers and memory.

[0062] The memory circuit 121 stores various information, such as a program to operate the processing circuit 120 and information indicating the operating conditions of the control IC 50. Here, "operating conditions" refer to, for example, condition C1 for determining whether the control IC 50 will operate in normal mode (described later) or burst mode (described later), and condition C2 for the control IC 50 to detect that the load 11 is in an overload state. Furthermore, the "overload state" of the load 11 is a state in which the load current Iout of the load 11 becomes greater than a predetermined current (for example, 2A).

[0063] ===Drive Circuit 113=== The drive circuit 113 controls the switching of NMOS transistors 32 and 33 based on the signals Smode,Sope and the feedback voltage Vfb. In this embodiment, the drive circuit 113 drives the NMOS transistors 32 and 33 based on the signal Sope for operating the drive circuit 113. On the other hand, the drive circuit 113 stops driving the NMOS transistors 32 and 33 based on the signal Sope for stopping the operation of the drive circuit 113.

[0064] Furthermore, the drive circuit 113 operates in normal mode based on a low-level (hereinafter referred to as L-level) signal Smode, and operates in burst mode based on a high-level (hereinafter referred to as H-level) signal Smode.

[0065] Here, "normal mode" refers to the operating mode in which the drive circuit 113 continuously switches the NMOS transistors 32 and 33, as shown in Figure 5. In this mode, the drive circuit 113 outputs pulse-like drive signals Vdr1 and Vdr2 to the NMOS transistors 32 and 33, respectively, which have a frequency determined by the level of the feedback voltage Vfb and a constant duty cycle (for example, 50%).

[0066] Furthermore, "burst mode" is an operating mode in which the drive circuit 113 alternately repeats a switching period in which it continuously switches NMOS transistors 32 and 33, and a stop period in which it intermittently stops switching, as shown in Figure 6. The frequencies of the drive signals Vdr1 and Vdr2 in this mode are also determined by the level of the feedback voltage Vfb.

[0067] Furthermore, the drive circuit 113, in both normal mode and burst mode, provides a dead time to ensure that the NMOS transistors 32 and 33 do not turn on simultaneously, while complementaryly changing the drive signals Vdr1 and Vdr2.

[0068] Furthermore, as described above, when the drive circuit 113 receives the signal Sope which operates the drive circuit 113, it drives the NMOS transistors 32 and 33 based on the signal Smode and the feedback voltage Vfb.

[0069] On the other hand, when the drive circuit 113 receives the signal Sope which stops the operation of the drive circuit 113, it stops driving the NMOS transistors 32 and 33.

[0070] In this embodiment, terminal STB corresponds to the "first terminal," and terminal CA corresponds to the "second terminal." Also, for example, resistor 100 in Figure 2 corresponds to the "first resistor," and thermistor 101 corresponds to the "second resistor."

[0071] Furthermore, the NMOS transistor 102 corresponds to a "switch," and the gate electrode of the NMOS transistor 102 corresponds to a "control electrode." Also, the ON state of the NMOS transistor 102 corresponds to the "first state," and the OFF state of the NMOS transistor 102 corresponds to the "second state." Furthermore, when the NMOS transistor 102 is ON, the voltage Vstb at terminal STB corresponds to the "first voltage," and when the NMOS transistor 102 is OFF, the voltage Vstb at terminal STB corresponds to the "second voltage."

[0072] ===Switch control circuit 114 and load detection circuit 115=== Figure 7 shows an example of a switch control circuit 114 and a load detection circuit 115. For convenience, in Figure 7, the terminal CA and circuit of the control IC 50 are depicted in a different position than in Figure 4.

[0073] When the signal Sclmp reaches a high level, the switch control circuit 114 outputs a voltage Va to turn on the NMOS transistor 102 of the variable resistor circuit 23. On the other hand, when the signal Sclmp reaches a low level, the switch control circuit 114 stops generating the voltage Va and sets the impedance between the switch control circuit 114 and terminal CA to high impedance.

[0074] The switch control circuit 114 can be implemented, for example, using an operational amplifier 200 that operates based on a high-level signal Sclmp and stops operating based on a low-level signal Sclmp. In this embodiment, a reference voltage Vref1 is applied to the non-inverting terminal of the operational amplifier 200, and the output is connected to the inverting terminal.

[0075] Therefore, when the operational amplifier 200 receives a high-level signal Sclmp, it outputs a voltage Va that is equal to the level of the reference voltage Vref1. As will be explained in more detail later, the reference voltage Vref1 is a voltage that can turn on the NMOS transistor 102.

[0076] The load detection circuit 115 is a circuit that detects the state of the load 11 (in this case, the power consumption of the load 11). Specifically, the load detection circuit 72 outputs a voltage Va corresponding to the load current Iout flowing through the load 11, based on the voltage Vs applied to terminal IS.

[0077] The load detection circuit 115 includes a variable gain amplifier 210 and a buffer 211. The variable gain amplifier 210 amplifies the voltage Vs with a gain corresponding to the signal Scnt. The buffer 211 applies the voltage output from the variable gain amplifier 210 as voltage Vb to terminal CA.

[0078] As mentioned above, both voltages Va and Vb correspond to the voltage Vca applied to terminal CA, but here, different signs are assigned to them so that the output of the switch control circuit 114 and the output of the load detection circuit 115 can be distinguished.

[0079] Figure 8 is a diagram illustrating the waveform of the voltage Vca applied to terminal CA. Here, the voltage Va output by the switch control circuit 114 is shown as a dashed line, and the voltage Vb output by the load detection circuit 115 is shown as a solid line.

[0080] Furthermore, as will be described in detail later, in this embodiment, when the switch control circuit 114 is operating, the load detection circuit 115 does not operate, and when the switch control circuit 114 stops operating, the load detection circuit 115 operates, with signals Sclmp and Scnt output from the control circuit 112. Therefore, either voltage Va or Vb will be applied to terminal CA as voltage Vca.

[0081] In this embodiment, the switch control circuit 114 outputs a voltage Va at a predetermined level as voltage Vca. Therefore, the voltage Vb output by the load detection circuit 115 in response to the load current Iout will be described here.

[0082] Here, the control circuit 112 changes the gain of the variable gain amplifier 210 of the load detection circuit 115 based on the level of the input voltage Vca. Specifically, as shown in Figure 8, in the range A1 where the load current Iout of the load 11 is small (the range where the voltage Vs level is 0 to V1 and the voltage Va level is 0 to V11), the control circuit 112 sets the gain of the variable gain amplifier 210 to gain G1.

[0083] Furthermore, in the range A2 where the load current Iout gradually increases (the range where the voltage Vs level is V1 to V2 and the voltage Va level is V10 to V11), the control circuit 112 sets the gain of the variable gain amplifier 210 to gain G2. In addition, in the range A3 where the load current Iout is large (the range where the voltage Vs level is V2 to V3 and the voltage Va level is V10 to V12), the control circuit 112 sets the gain of the variable gain amplifier 210 to gain G3.

[0084] In this embodiment, gain G1 is greater than gain G2, and gain G2 is greater than gain G3. Also, the load current Iout in each of the ranges A1 to A3 is, for example, 0 to 1 mA, 1 mA to 100 mA, and 100 mA to 2 A.

[0085] Thus, by the control circuit 112 changing the gain of the variable gain amplifier 210, the voltage Vb changes in accordance with the voltage Vs (i.e., the load current Iout), as shown in Figure 8.

[0086] Furthermore, in this embodiment, the load detection circuit 115 sets the voltage Vb (i.e., voltage Vca) to V12 when the load 11 is in an overload state and the voltage Vs level becomes V3. Here, "the load 11 is in an overload state" means that the load current Iout is greater than a predetermined current indicating an overload (for example, 2A).

[0087] As will be explained in more detail later, when the voltage Vca level reaches V12, the control circuit 112 stops the operation of the drive circuit 113 in Figure 4 so that the generation of the output voltage Vout2 of the DC-DC converter 22 is stopped. Therefore, the level of the voltage Vb (voltage Vca) output from the load detection circuit 115 will never exceed V12.

[0088] Furthermore, in this embodiment, as shown in Figure 8, the voltage level V12 is lower than the voltage Va output by the switch control circuit 114 (dotted line). The NMOS transistor 102 in Figure 7 is configured such that it does not turn on even when the voltage Vb level is V12, for example, by setting the resistance values ​​of resistors 103 and 104. Therefore, when the DC-DC converter 22 is generating the output voltage Vout2, the NMOS transistor 102 does not turn on. As a result, when the DC-DC converter 22 is operating, a voltage Vstb corresponding to the resistance value of the thermistor 101 is always applied to terminal STB.

[0089] The voltage Va output by the load detection circuit 115 corresponds to the "third voltage," and the voltage Vb output by the switch control circuit 114 corresponds to the "fourth voltage." Furthermore, the level of the voltage Vb output by the switch control circuit 114 is outside the range from the voltage Va level when the load 11 is unloaded (0V) to the voltage Va level when the load 11 is overloaded (V12).

[0090] ===Details of Circuit 116=== Figure 9 shows an example of the circuit 116 in Figure 4. The circuit 116 includes a current output circuit 300, a signal output circuit 301, a discharge circuit 302, and an overheat protection circuit (OTP) 303.

[0091] <<Current output circuit 300>> The current output circuit 300 outputs a current Iset for setting the operating conditions of the control IC 50, and a current Iotp used by the overheat protection circuit 308 when detecting temperature. The current output circuit 300 is composed of current sources 400, 401 and NMOS transistors 402, 403.

[0092] Current source 400 generates current Iset, and current source 401 generates current Iotp. NMOS transistor 402 is a switch connected in series with current source 400, which turns on when the signal Sset is at a high level and turns off when it is at a low level.

[0093] The NMOS transistor 403 is a switch connected in series with the current source 401, turning on when the signal Sotp is at a high level and turning off when it is at a low level.

[0094] Therefore, the current output circuit 300 outputs current Iset when the signal Sset is at a high level, and outputs current Iotp when the signal Sotp is at a high level. In this embodiment, current Iset is greater than current Iotp. Also, current Iset corresponds to the "first current," and current Iopt corresponds to the "second current."

[0095] <<Signal output circuit 301>> The signal output circuit 301 outputs a setting signal Sstb to set the operation of the AC-DC converter 21 based on the signal Scom from the control circuit 112. The signal output circuit 301 also outputs the currents Iset and Iotp from the current output circuit 300 to terminal STB. The signal output circuit 301 is composed of an NPN transistor 410, resistors 411 and 412, and an operational amplifier 413.

[0096] The NPN transistor 410 is a so-called diode-connected transistor, with its collector and base connected to the output node of the current output circuit 300, and its emitter connected to terminal STB via resistor 411. Therefore, current from the current output circuit 300 is output to terminal STB via the NPN transistor 410 and resistor 411.

[0097] Incidentally, since the NPN transistor 410 is diode-connected, it acts as a "reverse current prevention element" that prevents current from flowing from terminal STB to the operational amplifier 413. In this embodiment, an NPN transistor 410 was used as the "reverse current prevention element," but for example, a diode with its anode connected to the current output circuit 300 and the operational amplifier 413, and its cathode connected to terminal STB, could also be used.

[0098] The resistor 412 and the operational amplifier 413, together with the reverse current prevention element (NPN transistor 410) mentioned above, output a setting signal Sstb to the AC-DC converter 21.

[0099] The operational amplifier 413 operates, for example, based on a high-level signal Scom and stops operating based on a low-level signal Scom. In this embodiment, a reference voltage Vref2 is applied to the non-inverting terminal of the operational amplifier 413, and the output and the inverting terminal are connected via an NPN transistor 410 and resistors 411 and 412.

[0100] Therefore, when the operational amplifier 413 receives a high-level signal Sclmp, it changes the voltage Vstb at terminal STB to a level corresponding to the reference voltage Vref2. Specifically, during the period when the high-level signal Sclmp is input, the operational amplifier 413 changes the level of voltage Vstb to a level lower than the reference voltage Vref2 by the forward voltage of the diode of the NPN transistor 410. In this embodiment, the voltage Vstb that changes based on the high-level signal Sclmp may be referred to as "signal Sstb".

[0101] Furthermore, when the signal Scom becomes low, the operational amplifier 413 stops generating the signal Sstb and sets the impedance between the output of the operational amplifier 413 and the NPN transistor 410 to high impedance.

[0102] Incidentally, the signal output circuit 301 of this embodiment outputs a signal Sstb that includes information indicating the effective value of the AC voltage Vac and information indicating the operating mode of the AC-DC converter 21. Here, the effective value of the AC voltage Vac is 100V or 200V. Therefore, when the effective value of the AC voltage Vac is 100V, the signal output circuit 301 of this embodiment outputs a signal Sstb that is high level twice (see Figure 10). Also, when the effective value of the AC voltage Vac is 200V, the signal output circuit 301 outputs a signal Sstb that is high level once. Figure 10 is a diagram for illustrating the signal Sstb.

[0103] Furthermore, the AC-DC converter 21 has two operating modes: normal mode and burst mode. Therefore, when the AC-DC converter 21 is operating in normal mode, the signal output circuit 301 outputs a signal Sstb that is at a high level for a period Tx1. When the AC-DC converter 21 is operating in burst mode, the signal output circuit 301 outputs a signal Sstb that is at a high level for a period Tx2. Note that periods Tx1 and Tx2 are different periods.

[0104] Therefore, for example, when the effective value of the AC voltage Vac is 100V and the AC-DC converter 21 is operated in normal mode, the signal output circuit 301 outputs a signal Sstb that is high level for a period of Tx1 twice. Hereafter, when the effective value of the AC voltage Vac is 100V and the operating mode is normal mode, it may be written as (effective value, operating mode) = (100V, normal mode). Furthermore, as will be described in detail later, in this embodiment the processing circuit 120 generates the signal Sstb by setting the signal Scom to high level for a period of Tx twice.

[0105] <<Discharge circuit 302>> The discharge circuit 302 is a circuit that discharges the capacitor 105 of the variable resistor circuit 23 based on the signal Sdis from the control circuit 112. The discharge circuit 302 is composed of a resistor 420 and an NMOS transistor 421.

[0106] Resistor 420 and NMOS transistor 421 are connected in series between terminal STB and ground. NMOS transistor 421 turns on when the signal Sdis becomes high, and discharges capacitor 105. Resistor 420 is a component that limits the discharge current from capacitor 105. On the other hand, NMOS transistor 421 turns off when the signal Sdis becomes low, and stops the discharge of capacitor 105.

[0107] <<Overheat protection circuit 303>> The overheat protection circuit 303 is a circuit that detects temperature based on the voltage Vstb of the terminal STB and protects the DC-DC converter 22. The overheat protection circuit 303 includes a resistor 430, a comparator 431, and an AND circuit 432.

[0108] The resistor 430 connects the terminal STB and the non-inverting input terminal of the comparator 431. Also, a reference voltage Vref3 corresponding to a predetermined temperature Ta (for example, 125°C) is applied to the inverting input terminal of the comparator 431.

[0109] When the voltage Vstb of the terminal STB is higher than the reference voltage Vref3, the comparator 431 outputs a voltage Vo of L level indicating that the temperature of the thermistor 101 is lower than the predetermined temperature Ta. On the other hand, when the voltage Vstb of the terminal STB is lower than the reference voltage Vref3, the comparator 431 outputs a voltage Vo of H level indicating that the temperature of the thermistor 101 is higher than the predetermined temperature Ta.

[0110] When a signal Sotp of H level is input from the control circuit 112 to operate the overheat protection circuit 303, the AND circuit 432 outputs the comparison result of the comparator 431 as a voltage Votp. When the signal Sotp is of L level, the overheat protection circuit 303 always outputs a voltage Votp of L level. The overheat protection circuit 303 corresponds to a "temperature detection circuit" that detects temperature.

[0111] <<<Overview of the AC-DC converter 21>>> FIG. 11 is a diagram showing an example of the AC-DC converter 21. The AC-DC converter 21 is a boost chopper type power supply circuit that generates an output voltage Vout1 of a target level from the AC voltage Vac of a commercial power supply. Also, the AC-DC converter 21 of the present embodiment operates as a power factor correction circuit.

[0112] The AC-DC converter 21 includes a full-wave rectifier circuit 600, capacitors 601, 604, a transformer 602, a diode 603, a power factor correction IC 605, an NMOS transistor 606, and resistors 610, 611.

[0113] The full-wave rectifier circuit 600 applies a rectified voltage Vrec2, obtained by full-wave rectifying a predetermined AC voltage Vac, to the capacitor 601 and the main coil L5 of the transformer 602. Here, the AC voltage Vac is, for example, a voltage with a frequency of 50 to 60 Hz and a value of 100 to 240 V.

[0114] Capacitor 601 is an element that smooths the rectified voltage Vrec2, and transformer 602 has a main coil L5 and an auxiliary coil L6 that is magnetically coupled to the main coil L5. In this embodiment, the auxiliary coil L6 is wound such that the voltage generated in the auxiliary coil L6 has the opposite polarity to the voltage generated in the main coil L5. The voltage Vzcd generated in the auxiliary coil L6 is applied to terminal ZCD of power factor correction IC 605 (described later).

[0115] The rectified voltage Vrec2 is applied directly to the main coil L5, but it may also be applied to the main coil L5 via an element such as a resistor (not shown).

[0116] Furthermore, the main coil L5, together with the diode 603, capacitor 604, and NMOS transistor 606, constitutes a boost chopper circuit. Therefore, the charging voltage of capacitor 604 becomes the DC output voltage Vout1. The output voltage Vout1 is, for example, 400V.

[0117] The power factor correction IC 605 is an integrated circuit that controls the switching of the NMOS transistor 606 so that the output voltage Vout1 level reaches the target level (e.g., 400V) while improving the power factor of the AC-DC converter 12. The power factor correction IC 605 has terminals ZCD, OUT, R, and S. In addition to the four terminals mentioned above, the power factor correction IC 605 also has terminals for power supply, grounding, phase compensation, etc., but these are omitted here for convenience. Further details of the power factor correction IC 605 will be described later.

[0118] The NMOS transistor 606 is a power transistor for controlling the power of the AC-DC converter 21. In this embodiment, the NMOS transistor 606 is a MOS (Metal Oxide Semiconductor) transistor, but it is not limited to this. The NMOS transistor 176 may be any transistor capable of controlling power, such as a bipolar transistor. The gate electrode of the NMOS transistor 606 is connected to be driven by a signal from terminal OUT.

[0119] Resistors 610 and 611 form a voltage divider circuit that divides the output voltage Vout1, generating the feedback voltage Vr used when switching the NMOS transistor 606. The feedback voltage Vr generated at the node to which resistors 610 and 611 are connected is applied to terminal R.

[0120] <<An example of power factor correction IC605>> Figure 12 shows an example of a power factor correction IC 605. The power factor correction IC 605 drives an NMOS transistor 606 based on a voltage Vzcd corresponding to the inductor current IL, a voltage Vr corresponding to the output voltage Vout1, and a signal Sstb. The power factor correction IC 605 is composed of a signal detection circuit 700, a memory circuit 701, and a drive circuit 702.

[0121] The signal detection circuit 700 detects the signal Sstb output from the DC-DC converter 22 and stores the information D1 indicated by the signal Sstb in the memory circuit 701. As mentioned above, the information D1 includes the effective value of the AC voltage Vac and the operating mode of the AC-DC converter 21. The memory circuit 701 is composed of, for example, registers and memory. The signal Sstb corresponds to a "setting signal for setting the operation" of the AC-DC converter 21.

[0122] The drive circuit 702 adjusts the target level of the output voltage Vout1 based on the information indicating the effective value among the information D1 in the memory circuit 701. Specifically, when the effective value is 200V, the switching of the NMOS transistor 606 is controlled so that the target level of the output voltage Vout1 is lower than when the effective value is 100V. Here, the target level of the output voltage Vout1 when the effective value is 100V is, for example, 400V, and the target level of the output voltage Vout1 when the effective value is 200V is, for example, 390V.

[0123] Also, the drive circuit 702 controls the switching of the NMOS transistor 606 in the operation mode included in the information D1. Specifically, when the operation mode included in the information D1 is the normal mode, the drive circuit 702 outputs a drive signal Vdr similar to the waveform illustrated in FIG. 5 and continuously drives the NMOS transistor 606.

[0124] On the other hand, when the operation mode included in the information D1 is the burst mode, the drive circuit 702 outputs a drive signal Vdr similar to the waveform illustrated in FIG. 6 and drives the NMOS transistor 606 while alternately repeating the switching period and the stop period.

[0125] <<<Operation of DC-DC Converter 22>>> FIG. 13 is a diagram for explaining the operation of the DC-DC converter 22. FIG. 14 is a flowchart showing an example of the process S10 executed by the processing circuit 120. Here, it is assumed that an AC voltage Vac is supplied to the power supply device 10 of FIG. 1 and the full-wave rectifier circuit 20 generates a rectified voltage Vrec1 before time t0. Also, here, it is assumed that the effective value of the AC voltage Vac is 100V.

[0126] First, at time t0, when the full-wave rectifier circuit 20 outputs a rectified voltage Vrec1 to the DC-DC converter 22, the rectified voltage Vrec1 is applied to terminal VH of the control IC 50 in Figure 2. As a result, the startup circuit 110 in Figure 3 charges the capacitor 61 connected to terminal VCC in Figure 2. When the power supply voltage Vcc is generated, the internal power supply 111 of the control IC 50 generates the power supply voltage Vreg, so the internal circuitry of the control IC 50 (for example, the control circuit 112) becomes operational.

[0127] In this embodiment, "startup" of the control IC 50 refers to the operation from the time the rectified voltage Vrec1 is applied to terminal VH until the control circuit 112 starts the state setting operation (described later) at time t1.

[0128] At time t1, the processing circuit 120 of the control circuit 112 performs a so-called state setting operation to set the operating conditions of the control IC 50. Specifically, the processing circuit 120 sets the signal Sclmp to a high level and the signal Sset to a high level (S20 in Figure 14) in order to obtain the resistance value of the state setting resistor 100 connected to terminal STB shown in Figures 7 and 9.

[0129] When the signal Sclmp reaches a high level, the switch control circuit 114 in Figure 7 applies a voltage Va to terminal STB, causing the NMOS transistor 102 of the variable resistor circuit 23 to turn on. Also, when the signal Sset reaches a high level, the current output circuit 300 in Figure 9 outputs a current Iset to terminal STB.

[0130] Then, since the current Iset flows to ground through terminal STB and resistor 100, a voltage Vstb corresponding to the resistance value of resistor 100 and the current Iset is generated at terminal STB. In this embodiment, for example, the memory circuit 121 is assumed to have the current values ​​of Iset and Iopt stored in advance.

[0131] Subsequently, the processing circuit 120 calculates the resistance value of resistor 100 based on the voltage Vstb and the current value of current Iset, as shown in Figure 14 (S21). Once the resistance value of resistor 100 is calculated, the processing circuit 120 stores the operating conditions (conditions C1, C2) of the control IC 50, which are determined based on the resistance value of resistor 100, in the memory circuit 121 (S22).

[0132] Specifically, the processing circuit 120 determines a threshold voltage Vth1 (i.e., condition C1) for switching between normal mode and burst mode based on the resistance value of resistor 100, and stores it in the memory circuit 121. In this embodiment, the processing circuit 120 determines the threshold voltage Vth1 based, for example, on table information showing the relationship between the threshold voltage Vth1 and the resistance value of resistor 100, which is pre-stored in the memory circuit 121. Alternatively, the processing circuit 120 may determine the threshold voltage Vth1 using, for example, a predetermined formula that defines the relationship between the resistance value of resistor 100 and the threshold voltage Vth1.

[0133] The processing circuit 120 operates the control IC 50 in normal mode when the voltage Vca is greater than the threshold voltage Vth1, and operates the control IC 50 in burst mode when the voltage Vca is less than the threshold voltage Vth1.

[0134] Thus, in this embodiment, a user utilizing the DC-DC converter 22 can determine the condition C1 for switching the operating mode of the control IC 50 retrospectively by selecting the resistor 100.

[0135] In this embodiment, the threshold voltage Vth1 (condition C1) is determined based on the resistance value of resistor 100, but the threshold voltage Vth1 may be changed depending on the level of the output voltage Vout1. For example, when the output voltage Vout1 is within a predetermined range (e.g., within ±10%) from a predetermined level (400V), the threshold voltage Vth1 may be used, and outside the predetermined range, the threshold voltage Vth may be changed.

[0136] Specifically, for example, if the output voltage Vout1 becomes greater than the maximum value within a predetermined range, a smaller value (e.g., threshold voltage Vth1 × 0.9) may be used as the threshold voltage. Also, for example, if the output voltage Vout1 becomes less than the minimum value within a predetermined range, a larger value (e.g., threshold voltage Vth1 × 1.1) may be used as the threshold voltage. In this way, even if the threshold voltage Vth1 is changed, the burst mode and the normal mode can be determined based on the resistance value of resistor 100.

[0137] Furthermore, the processing circuit 120 determines a threshold voltage Vth2 (i.e., condition C2) for determining whether the state of the load 11 is an overload state, based on the resistance value of the resistor 100, and stores it in the memory circuit 121. In this embodiment, the processing circuit 120 determines the threshold voltage Vth2 based, for example, on table information showing the relationship between the threshold voltage Vth2 and the resistance value of the resistor 100, which is pre-stored in the memory circuit 121. Alternatively, the processing circuit 120 may determine the threshold voltage Vth2 using, for example, a predetermined formula that defines the relationship between the resistance value of the resistor 100 and the threshold voltage Vth2.

[0138] Then, the processing circuit 120 stops the operation of the drive circuit 113 if the voltage Vca is greater than the threshold voltage Vth2. Therefore, in this embodiment, a user utilizing the DC-DC converter 22 can retrospectively determine the condition C2 for stopping the switching operation due to overload by selecting the resistor 100.

[0139] Furthermore, at time t2, after the resistance value of resistor 100 has been stored, the processing circuit 120 changes the signal Sset to a low level while changing the signal Sdis to a high level for a predetermined period (S23). When the signal Sset becomes low, the current Iset stops. Also, when the signal Sdis becomes high, the NMOS transistor 421 of the discharge circuit 302 in Figure 9 turns on, and the capacitor 105 is discharged. Consequently, the voltage Vstb at terminal STB becomes almost zero.

[0140] Subsequently, at time t3, the processing circuit 120 sets both signals Sdis and Sclmp to L level (S24). As a result, the discharge of capacitor 105 is stopped, and resistor 100 and thermistor 101 are connected in series to terminal STB shown in Figure 9.

[0141] Furthermore, at time t4, the processing circuit 120 executes a process to output a signal Sstb that sets the operation of the AC-DC converter 21. Specifically, the processing circuit 120 acquires a voltage Vh that changes according to the effective value of the AC voltage Vac, and outputs a signal Scom to the signal output circuit 301 (S25) so that a signal Sset indicating (effective value, operating mode) = (100V, normal mode) is output.

[0142] Furthermore, at time t4 after startup, the processing circuit 120 always outputs a signal Sset, which indicates normal mode, to the signal output circuit 301. Therefore, at this timing, the processing circuit 120 outputs an H-level signal Scom from both time t4 and t5 until a predetermined period Tx1 has elapsed.

[0143] As a result, the voltage at terminal STB will be the voltage corresponding to the reference voltage Vref2 from time t4 and t5 until a predetermined period Tx1 has elapsed. In other words, the signal Sstb will be output to the AC-DC converter 21 from time t4 and t5 until a predetermined period Tx1 has elapsed.

[0144] Then, the signal detection circuit 700 of the power factor correction IC 605 in Figure 12 detects the signal Sset ((effective value, operating mode) = (100V, normal mode)) and stores the detection result in the memory circuit 701. Therefore, the power factor correction IC 605 can operate according to the signal Set. Note that the power factor correction IC 605 corresponds to an "external circuit" outside of the control IC 50, and the signal Sset corresponds to a "setting signal".

[0145] Furthermore, at time t6, the processing circuit 120 changes the signal Sotp to a high level (S26) so that the overheat protection function is activated. As a result, the current output circuit 300 outputs the current Iotp, which is used to detect the temperature. Therefore, the terminal STB will have the current Iotp and a voltage Vstb corresponding to the combined resistance of the resistor 100 and thermistor 101. In other words, from time t6 onward, the overheat protection circuit 303 can detect whether the temperature of thermistor 101 is higher than a predetermined temperature Ta.

[0146] At time t6, the resistance values ​​of the resistors connected to terminal STB (i.e., resistor 100 and thermistor 101) are greater than the resistance value of resistor 100 connected to terminal STB during the state setting period (for example, the period from time t1 to t3). In such a case, increasing the current value of current Iotp may cause the voltage Vstb to become too large. Therefore, in this embodiment, the current value of current Iotp is set to be smaller than the current value of current Istb.

[0147] Furthermore, in this embodiment, for example, at time t6, the processing circuit 120 outputs a signal Smode indicating the normal mode and a signal Sope to operate the drive circuit 113. As a result, the drive circuit 113 in Figure 4 starts driving the NMOS transistors 32 and 33. Consequently, the DC-DC converter 22 generates an output voltage Vout2 at the target level and applies it to the load 11. Note that in Figure 13, the signals Smode and Sope are omitted for convenience.

[0148] For example, at time t7, if the temperature rises and the resistance of thermistor 101 decreases, the voltage Vstb level will decrease. Note that in Figure 13, the voltage Vstb is reduced to zero for convenience in order to make the change in voltage Vstb due to temperature rise easier to understand.

[0149] At time t7, when the voltage Vstb decreases, the voltage Votp of the overheat protection circuit 303 in Figure 9 becomes high. Then, at time t8, after a predetermined delay period Td1 has elapsed since the voltage Votp became high, the processing circuit 120 in this embodiment detects overheating and stops the operation of the drive circuit 113. The overheating state detected by the processing circuit 120 is shown in the bottom row of Figure 13.

[0150] Furthermore, for example, if the temperature of the thermistor 101 decreases at time t9, the voltage Vstb level increases. As a result, the voltage Votp of the overheat protection circuit 303 in Figure 9 becomes L level. Then, at time t10, after a predetermined delay period Td2 has elapsed since the voltage Votp became L level, the processing circuit 120 detects that it is no longer in an overheating state and starts the operation of the drive circuit 113.

[0151] Although not shown in Figure 13, for example, if the load current Iout of load 11 increases and the voltage Vca becomes higher than the threshold voltage Vth1 after time t10, the processing circuit 120 changes the operating mode of the drive circuit 113 from normal mode to burst mode.

[0152] Thus, the control IC 50 of this embodiment can perform state setting, communication, and overheat detection (or overheat protection) using a single terminal STB. Therefore, the control IC 50 can implement many functions while suppressing an increase in the number of terminals.

[0153] ===Other=== In Figure 9, a resistor 100 and a thermistor 101 are connected in series between terminal STB and ground, and an NMOS transistor 102 is connected in parallel to the thermistor 101. In this case, when the NMOS transistor 102 is turned on, a voltage corresponding to the resistor 100 is generated at terminal STB, and when the NMOS transistor 102 is turned off, a voltage corresponding to the thermistor 101 is generated at terminal STB.

[0154] However, the connection relationships of the resistor 100, thermistor 101, and NMOS transistor 102 connected to terminal STB are not limited to those shown in Figure 9. For example, the other end of a switch, one end of which is connected to terminal STB, may be connected to either the resistor 100 or thermistor 101, which are connected in parallel. Even with such a configuration, the same effects as in this embodiment can be obtained.

[0155] ===Summary=== The power supply unit 10 of this embodiment has been described above. The control IC 50 of this embodiment performs three processes using terminal STB: state setting, communication, and overheat detection (or overheat protection). However, for example, it may perform only two processes: state setting and overheat detection. Even in such a case, the increase in the number of terminals of the control IC 50 can be suppressed.

[0156] Furthermore, in this embodiment, the switch control circuit 114 connected to terminal CA controls the on / off state of the NMOS transistor 102 by outputting a voltage Va. Therefore, compared to the case where a dedicated terminal is provided for the switch control circuit 114, the number of terminals on the control IC 50 can be reduced.

[0157] Furthermore, the current output circuit 300 outputs current Iset and current Iotp to terminal STB. Therefore, in this embodiment, the voltage Vstb can be set to an appropriate level in both the state setting and overheat detection processes.

[0158] Furthermore, the discharge circuit 302 discharges the capacitor 105 when the state setting process is completed (for example, at time t2 in Figure 13). Therefore, in this embodiment, overheat detection can be performed with high accuracy while stabilizing the voltage Vstb level during the state setting process.

[0159] Furthermore, the processing circuit 120 determines whether to operate the drive circuit 113 in normal mode or burst mode based on condition C1, which corresponds to the resistance value of resistor 100. In this way, in this embodiment, the user of the power supply unit 10 can set the operating conditions of the DC-DC converter 22.

[0160] Furthermore, the processing circuit 120 can detect that the load 11 is in an overload state based on condition C2, which corresponds to the resistance value of resistor 100. In this way, in this embodiment, the user of the power supply unit 10 can set the operating conditions of the DC-DC converter 22.

[0161] Furthermore, the processing circuit 120 determines whether to operate the drive circuit 113 in normal mode or burst mode based on condition C1, which corresponds to the resistance value of resistor 100. Therefore, in this embodiment, the user of the power supply unit 10 can set the operating conditions of the DC-DC converter 22.

[0162] Furthermore, in the overheat protection circuit 303, the comparator 431 can detect whether the temperature of the thermistor 101 is higher than a predetermined temperature Ta.

[0163] Furthermore, the signal output circuit 301 outputs a signal Sstb via terminal STB to set the operation of the AC-DC converter 21, for example, during the period from time t4 to t6 in Figure 13. Therefore, in this embodiment, it is possible to implement communication functionality while suppressing an increase in the number of terminals.

[0164] Furthermore, the current output circuit 300 stops outputting current to terminal STB while the signal Sstb is being output. Therefore, the control IC 50 of this embodiment can transmit the signal Sstb to the AC-DC converter 21 with high accuracy.

[0165] Furthermore, the DC-DC converter 22 can implement various functions (for example, state setting and overheat protection) by using the control IC 50.

[0166] Furthermore, the control IC 50 in this embodiment performs three processes using terminal STB: state setting, communication, and overheat detection (or overheat protection). However, it may also perform only two processes, for example, overheat detection and communication. Even in such a case, the increase in the number of terminals of the control IC 50 can be suppressed.

[0167] Furthermore, the DC-DC converter 22 can implement various functions (for example, overheat detection and communication) by using the control IC 50.

[0168] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. Furthermore, the present invention may be modified or improved without departing from its spirit, and it goes without saying that equivalents thereof are included. [Explanation of Symbols]

[0169] 10 Power supply 11 Load 20,600 full wave rectifier circuit 21 AC-DC Converters 22 DC-DC Converters 23 Variable Resistor Circuit 65, 66, 90~92, 100, 103, 104, 411, 412, 420, 430, 610, 611 resistance 32, 33, 102, 402, 403, 421, 606 NMOS transistors 34,602 transformers 35 Control Block 40, 41, 60, 603 diodes 43 Constant Voltage Circuit 44 Light-emitting diodes 50 control ICs 30, 31, 42, 61, 63, 64, 67, 68, 105, 601 Capacitors 62 Phototransistors 101 Thermistor 110 Startup Circuit 111 Internal power supply 112 Control circuits 113,702 drive circuits 114 Switch control circuit 115 Load detection circuit 116 circuits 120 Processing Circuits 121,701 Memory circuit 200,413 operational amplifiers 210 Variable Gain Amplifier 211 buffers 300 Current Output Circuit 301 Signal Output Circuit 302 Discharge circuit 303 Overheat protection circuit 400,401 current source 410 NPN transistors 431 Comparator 432 AND gate 605 Power Factor Correction IC 700 Signal detection circuit VCC,GND,STB,BO,FB,IS,CA,HO,LO,VH,ZCD,OUT,R,S terminal

Claims

1. It is an integrated circuit, The first terminal is connected to the first resistor, the second resistor for temperature detection, and the switch. A current output circuit that outputs current to the first terminal, A switch control circuit that sets the switch to a first state so that a voltage corresponding to the first resistor is applied to the first terminal, and then sets the switch to a second state so that a voltage corresponding to the second resistor is applied to the first terminal, Memory circuits and, A processing circuit that stores the operating conditions of the integrated circuit in the memory circuit based on the first voltage of the first terminal when the switch is in the first state, A temperature detection circuit that detects temperature based on the second voltage at the first terminal when the switch is in the second state, An integrated circuit equipped with the following features.

2. The integrated circuit according to claim 1, The aforementioned integrated circuit is The power supply circuit comprises an inductor and a transistor that controls the inductor current flowing through the inductor, and controls the switching of the transistor that generates an output voltage of a target level from an input voltage. A second terminal to which a control electrode that controls the state of the switch is connected, A load detection circuit that applies a third voltage corresponding to the power consumption of the power supply circuit to the second terminal, Equipped with, The aforementioned switch control circuit is When the integrated circuit is activated, a fourth voltage is applied to the second terminal to set the switch to the first state. The level of the fourth voltage is, This is a level outside the range of the third voltage when the load of the power supply circuit changes from an unloaded state to an overloaded state. Integrated circuit.

3. An integrated circuit according to claim 1 or claim 2, The current output circuit described above is When the switch enters the first state, it outputs a first current, and after the switch enters the second state, it outputs a second current different from the first current. Integrated circuit.

4. The integrated circuit according to claim 3, After the operating conditions are stored in the memory circuit, and before the second current is output, a discharge circuit is provided to discharge the capacitor connected to the first terminal. Integrated circuit.

5. The integrated circuit according to claim 2, The system includes a drive circuit that drives the transistor based on a feedback voltage corresponding to the output voltage, The aforementioned operating conditions are: This includes conditions for determining whether the operating mode of the drive circuit is burst mode or normal mode, The aforementioned processing circuit is Based on the third voltage and the operating conditions, the operating mode of the drive circuit is changed. Integrated circuit.

6. The integrated circuit according to claim 5, The aforementioned operating conditions are: Includes conditions for detecting that the load on the power supply circuit is in an overload state, The aforementioned processing circuit is Based on the third voltage and the operating conditions, the drive circuit is controlled so that the drive of the transistor stops when the load becomes overloaded. Integrated circuit.

7. An integrated circuit according to claim 1 or claim 2, The temperature detection circuit is The circuit includes a comparison circuit that detects whether the temperature is higher than a predetermined temperature based on the second voltage when the switch is in the second state and a reference voltage. Integrated circuit.

8. An integrated circuit according to claim 1 or claim 2, After the switch enters the second state, the integrated circuit is provided with a signal output circuit that outputs a setting signal to an external circuit located outside the integrated circuit via the first terminal to set the operation of the external circuit. Integrated circuit.

9. The integrated circuit according to claim 8, The current output circuit described above is During the period in which the setting signal is output, the output of the current is stopped. Integrated circuit.

10. A power supply circuit comprising an inductor and a transistor that controls the inductor current flowing through the inductor, wherein the power supply circuit generates an output voltage of a desired level from an input voltage, The first resistor and A second resistor for temperature detection, Switch and An integrated circuit that controls the switching of the aforementioned transistor, Equipped with, The aforementioned integrated circuit is The first resistor, the second resistor, and the switch are connected to a first terminal, A current output circuit that outputs current to the first terminal, A switch control circuit that sets the switch to a first state so that a voltage corresponding to the first resistor is applied to the first terminal, and then sets the switch to a second state so that a voltage corresponding to the second resistor is applied to the first terminal, Memory circuits and, A processing circuit that stores the operating conditions of the integrated circuit in the memory circuit based on the first voltage of the first terminal when the switch is in the first state, A temperature detection circuit that detects temperature based on the second voltage at the first terminal when the switch is in the second state, A power supply circuit including this.

11. It is an integrated circuit, The first terminal to which the first resistor is connected, The first terminal is connected to a current output circuit that outputs the current to flow through the first resistor, A temperature detection circuit that detects temperature based on the first voltage at the first terminal generated by the current from the current output circuit, A signal output circuit that outputs a setting signal for setting the operation of an external circuit provided outside the integrated circuit via the first terminal, An integrated circuit equipped with the following features.

12. A power supply circuit comprising an inductor and a transistor that controls the inductor current flowing through the inductor, wherein the power supply circuit generates an output voltage of a desired level from an input voltage, The first resistor and An integrated circuit that controls the switching of the aforementioned transistor, Equipped with, The aforementioned integrated circuit is The first terminal to which the first resistor is connected, The first terminal is connected to a current output circuit that outputs the current to flow through the first resistor, A temperature detection circuit that detects temperature based on the first voltage at the first terminal generated by the current from the current output circuit, A signal output circuit that outputs a setting signal for setting the operation of an external circuit provided outside the integrated circuit via the first terminal, A power supply circuit including this.

Images