Semiconductor structure (formation of self-aligned embedded power rails for semiconductor devices)

Abstract

To solve the problem in which typical buried power rail formation is limited, in terms of its conductivity, by contact overlay issues with other conductive elements / components of a cell.SOLUTION: A self-aligned buried power rail having an adjustable height is formed between a first semiconductor device region and a second semiconductor device region. The self-aligned buried power rail having the adjustable height has improved conductivity. Notably, the self-aligned buried power rail has a first portion having a first height that is present in a gate cut trench, and a second portion having a second height, which is greater than the first height, that is present in a source / drain cut trench.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application relates to semiconductor technology, and more specifically, to a semiconductor structure having a self-aligned embedded power rail located between a first semiconductor device region and a second semiconductor device region.

Background Art

[0002] When forming a structure including a plurality of complementary metal oxide semiconductor (CMOS) devices such as an integrated circuit, a standard cell can be used as a base unit for designing and manufacturing the integrated circuit. The standard cell can be used to form one or more functional circuits, and each standard cell can have the same dedicated area (e.g., can have a standard dedicated area). By using standard cells when designing complex circuits and components, the design and manufacturing costs are reduced.

[0003] In use, each standard cell of a semiconductor device requires a power input (Vdd) and a ground (Vss) connection. To power its various components, each standard cell is typically connected to an embedded power rail that is electrically connected to the active layer of the standard cell to provide power (Vdd). In some cases, a plurality of embedded power rails can be provided for each standard cell to provide power (Vdd) and ground (Vss) respectively.

[0004] The embedded power rail is typically embedded in a shallow trench isolation structure located between adjacent semiconductor device-containing regions. However, the formation of a typical embedded power rail is limited in terms of its conductivity due to contact overlay problems with other conductive elements / components of the cell.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The formation of typical embedded power rails is limited in terms of conductivity due to contact overlay issues with other conductive elements / components of the cell. [Means for solving the problem]

[0006] A self-aligned embedded power rail having an adjustable height is formed between a first semiconductor device region and a second semiconductor device region. The self-aligned embedded power rail having an adjustable height has improved conductivity. In particular, the self-aligned embedded power rail has a first portion having a first height that exists in a gate cut trench and a second portion having a second height greater than the first portion that exists in a source / drain cut trench. The term "gate cut trench" is used throughout this application to refer to the region between the first device region and the second device region where the gate is cut, while the term "source / drain cut trench" is used throughout this application to refer to the region between the first device region and the second device region where the source / drain region is cut.

[0007] In one aspect of the present application, a semiconductor structure is provided that includes a self-aligned embedded power rail. In one embodiment of the present application, the semiconductor structure includes a first semiconductor device region including at least one semiconductor device and a second semiconductor device region including at least one other semiconductor device. The embedded power rail is located between the first semiconductor device region and the second semiconductor device region, with a first portion of the embedded power rail having a first height located in a gate cut trench, and a second portion of the embedded power rail having a second height greater than the first height located in a source / drain cut trench. There are also conductive contact structures that are in direct contact with at least the source / drain region of the at least one first semiconductor device located in the first semiconductor device region, and the second portion of the embedded power rail located in the source / drain cut trench. In some embodiments, the conductive contact structures also are in direct contact with the source / drain region of the at least one other semiconductor device located in the second semiconductor device region.

[0008] In one example, the first semiconductor device region includes a first composite film device comprising a first nanosheet device and a second nanosheet device, wherein the first nanosheet device is located on a first face of a first dielectric pillar, the second nanosheet device is located on a second face of the first dielectric pillar, and the first face of the first dielectric pillar is opposite to the second face of the first dielectric pillar. In this example, the second semiconductor device region includes a second composite film device comprising a third nanosheet device and a fourth nanosheet device, wherein the third nanosheet device is located on a first face of a second dielectric pillar, the fourth nanosheet device is located on a second face of the second dielectric pillar, the first face of the second dielectric pillar is opposite to the second face of the second dielectric pillar, and the second nanosheet device of the first composite film device faces the third nanosheet device of the second composite film device. In this example, the embedded power rail is located between the first composite film device and the second composite film device. In this example, the conductive contact structure directly contacts at least the source / drain region of the second nanosheet device of the first composite film device, and the second portion of the embedded power rail located in the source / drain cut trench. In some embodiments and in this example, the conductive contact structure also directly contacts the source / drain region of the third nanosheet device of the second composite film device.

[0009] In yet another embodiment of the present application, the semiconductor structure includes a first semiconductor device region containing at least one semiconductor device and a second semiconductor device region containing at least one other semiconductor device. An embedded power rail is located between the first semiconductor device region and the second semiconductor device region, with a first portion of the embedded power rail having a first height located in a gate cut trench, and a second portion of the embedded power rail having a second height greater than the first height located in a source / drain cut trench. There is a first conductive contact structure that directly contacts the source / drain region of the at least one semiconductor device located in the first semiconductor device region but does not directly contact the second portion of the embedded power rail, and there is a second conductive contact structure that directly contacts the source / drain region of the at least one other semiconductor device located in the second semiconductor device region but does not directly contact the second portion of the embedded power rail.

[0010] In one example, the first semiconductor device region includes a first composite film device comprising a first nanosheet device and a second nanosheet device, wherein the first nanosheet device is located on a first face of a first dielectric pillar, the second nanosheet device is located on a second face of the first dielectric pillar, and the first face of the first dielectric pillar is opposite to the second face of the first dielectric pillar. In this example, the second semiconductor device region includes a second composite film device comprising a third nanosheet device and a fourth nanosheet device, wherein the third nanosheet device is located on a first face of a second dielectric pillar, the fourth nanosheet device is located on a second face of the second dielectric pillar, the first face of the second dielectric pillar is opposite to the second face of the second dielectric pillar, and the second nanosheet device of the first composite film device faces the third nanosheet device of the second composite film device. In this example, the embedded power rail is located between the first composite film device and the second composite film device. In this example, the first conductive contact structure directly contacts the source / drain region of the second nanosheet device of the first composite film device but does not directly contact the second portion of the embedded power rail, and the second conductive contact structure directly contacts the source / drain region of the third nanosheet device of the second composite film device but does not directly contact the second portion of the embedded power rail.

[0011] In further embodiments of the present application, the semiconductor structure includes a first semiconductor device region comprising at least one semiconductor device and a second semiconductor device region comprising at least one other semiconductor device. An embedded power rail is located between the first and second semiconductor device regions, with a first portion of the embedded power rail having a first height located in a gate cut trench, and a second portion of the embedded power rail having a second height greater than the first height located in a source / drain cut trench. There are also conductive contact structures that directly contact the second portion of the embedded power rail located in the source / drain cut trench, but do not directly contact the source / drain region located in the first semiconductor device region or the source / drain region located in the second semiconductor device region.

[0012] In one example, the first semiconductor device region includes a first composite film device comprising a first nanosheet device and a second nanosheet device, wherein the first nanosheet device is located on a first face of a first dielectric pillar, the second nanosheet device is located on a second face of the first dielectric pillar, and the first face of the first dielectric pillar is opposite to the second face of the first dielectric pillar. In this example, the second semiconductor device region includes a second composite film device comprising a third nanosheet device and a fourth nanosheet device, wherein the third nanosheet device is located on a first face of a second dielectric pillar, the fourth nanosheet device is located on a second face of the second dielectric pillar, the first face of the second dielectric pillar is opposite to the second face of the second dielectric pillar, and the second nanosheet device of the first composite film device faces the third nanosheet device of the second composite film device. In this example, the embedded power rail is located between the first composite film device and the second composite film device. In this example, the conductive contact structure directly contacts the second portion of the embedded power rail located in the source / drain cut trench, but does not directly contact the source / drain region located in the first semiconductor device region or the source / drain region located in the second semiconductor device region.

[0013] In other embodiments of the present application, various methods for providing the above-described semiconductor structure are provided. In one embodiment, the method includes the use of a sacrificial material as an embedded power rail placeholder material. In yet another embodiment, the method does not include the use of such a sacrificial material layer. In any embodiment, the method makes it possible to provide a self-aligned embedded power rail having an adjustable height. Various methods of the present application will become apparent from the following drawings and the following detailed description, which illustrates a composite film device as one non-limiting example. [Brief explanation of the drawing]

[0014] [Figure 1]A cell layout including two composite membrane device regions separated by a trench isolation structure that can be used in the present application.

[0015] [Figure 2] An exemplary structure taken along the cut line X1-X1 shown in FIG. 1 of the present application. This exemplary structure includes a shallow trench isolation structure that separates a first composite membrane device region from a second composite membrane device region. The first composite membrane device region includes a first nanosheet stack and a second nanosheet stack separated by a first dielectric pillar. The second composite membrane device region includes a third nanosheet stack and a fourth nanosheet stack separated by a second dielectric pillar. The structure further includes a first dielectric material layer located on and laterally adjacent to each of the first, second, third, and fourth nanosheet stacks.

[0016] [Figure 3] A cross-sectional view of the exemplary structure shown in FIG. 2 after forming a spacer material layer.

[0017] [Figure 4] A cross-sectional view of the exemplary structure shown in FIG. 3 after forming spacers from the spacer material layer, removing the physically exposed portions of the first dielectric material layer and the portions of the shallow trench isolation structure not protected by the spacers, and forming a placeholder material layer beneath the surface of the shallow trench isolation structure.

[0018] [Figure 5] A cross-sectional view of the exemplary structure shown in FIG. 4 after forming additional trench dielectric material on the placeholder material layer.

[0019] [Figure 6] A cell layout similar to that shown in FIG. 1, including cut lines X2-X2, X3-X3, and X4-X4.

[0020] [Figure 7A] A cross-sectional view taken along the cut line X2-X2 shown in FIG. 6 of an exemplary structure shown in FIG. 5 after forming a polysilicon layer, removing spacers, forming source / drain regions, and forming an interlayer dielectric material layer. [Figure 7B] A cross-sectional view taken along the cut line X3-X3 shown in FIG. 6 of an exemplary structure shown in FIG. 5 after forming a polysilicon layer, removing spacers, forming source / drain regions, and forming an interlayer dielectric material layer. [Figure 7C] A cross-sectional view taken along the cut line X4-X4 shown in FIG. 6 of an exemplary structure shown in FIG. 5 after forming a polysilicon layer, removing spacers, forming source / drain regions, and forming an interlayer dielectric material layer.

[0021] [Figure 8A] A cross-sectional view of an exemplary structure shown in FIG. 7A after forming a gate cut trench mask. [Figure 8B] A cross-sectional view of an exemplary structure shown in FIG. 7B after forming a gate cut trench mask. [Figure 8C] A cross-sectional view of an exemplary structure shown in FIG. 7C after forming a gate cut trench mask.

[0022] [Figure 9A] A cross-sectional view of an exemplary structure shown in FIG. 8A after performing a gate cutting process in which a gate cut trench for physically exposing a placeholder material layer is formed. [Figure 9B] A cross-sectional view of an exemplary structure shown in FIG. 8B after performing a gate cutting process in which a gate cut trench for physically exposing a placeholder material layer is formed. [Figure 9C] A cross-sectional view of an exemplary structure shown in FIG. 8C after performing a gate cutting process in which a gate cut trench for physically exposing a placeholder material layer is formed.

[0023] [Figure 10A] This is a cross-sectional view of an exemplary structure shown in Figure 9A, in a gate-cut trench and after forming a dielectric material on a placeholder material layer. [Figure 10B] This is a cross-sectional view of an exemplary structure shown in Figure 9B, after forming a dielectric material on a placeholder material layer in a gate-cut trench. [Figure 10C] This is a cross-sectional view of an exemplary structure shown in Figure 9C, in a gate-cut trench and after forming a dielectric material on a placeholder material layer.

[0024] [Figure 11A] Figure 10A shows a cross-sectional view of an exemplary structure after performing a source / drain cut, which forms a source / drain cut trench that physically exposes the placeholder material layer. [Figure 11B] Figure 10B shows a cross-sectional view of an exemplary structure after performing a source / drain cut, which forms a source / drain cut trench that physically exposes the placeholder material layer. [Figure 11C] Figure 10C shows a cross-sectional view of an exemplary structure after performing a source / drain cut, which forms a source / drain cut trench that physically exposes the placeholder material layer.

[0025] [Figure 12A] Figure 11A is a cross-sectional view of an exemplary structure shown in Figure 11A, in a source / drain cut trench, after forming additional placeholder material on a physically exposed placeholder material layer. [Figure 12B] Figure 11B is a cross-sectional view of an exemplary structure shown in Figure 11B, after additional placeholder material has been formed on a physically exposed placeholder material layer in a source / drain cut trench. [Figure 12C] Figure 11C is a cross-sectional view of an exemplary structure shown in the source / drain cut trench, after additional placeholder material has been formed on a physically exposed placeholder material layer.

[0026] [Figure 13A] This is a cross-sectional view of the exemplary structure shown in Figure 12A after the gate cut trench mask has been removed. [Figure 13B] Figure 12B is a cross-sectional view of the exemplary structure shown after the gate cut trench mask has been removed. [Figure 13C] This is a cross-sectional view of the exemplary structure shown in Figure 12C after the gate cut trench mask has been removed.

[0027] [Figure 14A] Figure 13A shows a cross-sectional view of the exemplary structure after the polysilicon layer and the first dielectric material layer have been removed to expose the second and third nanosheet stacks, and each sacrificial semiconductor material nanosheet in the second and third nanosheet stacks has been replaced with a functional gate structure. [Figure 14B] Figure 13B shows a cross-sectional view of the exemplary structure after the polysilicon layer and the first dielectric material layer have been removed to expose the second and third nanosheet stacks, and each sacrificial semiconductor material nanosheet in the second and third nanosheet stacks has been replaced with a functional gate structure. [Figure 14C] Figure 13C shows a cross-sectional view of the exemplary structure after the polysilicon layer and the first dielectric material layer have been removed to expose the second and third nanosheet stacks, and each sacrificial semiconductor material nanosheet in the second and third nanosheet stacks has been replaced with a functional gate structure.

[0028] [Figure 15A] Figure 14A is a cross-sectional view of the exemplary structure shown after the removal of additional placeholder material and placeholder material layers. [Figure 15B] Figure 14B is a cross-sectional view of the exemplary structure shown after the removal of additional placeholder material and placeholder material layers. [Figure 15C] Figure 14C is a cross-sectional view of the exemplary structure shown after the removal of additional placeholder material and placeholder material layers.

[0029] [Figure 16A] Figure 15A shows a cross-sectional view of the exemplary structure after the embedded power rail has been formed in the region that previously contained additional placeholder material and placeholder material layers. [Figure 16B] Figure 15B is a cross-sectional view of the exemplary structure shown, after the embedded power rail has been formed in the region that previously contained additional placeholder material and placeholder material layers. [Figure 16C] Figure 15C is a cross-sectional view of the exemplary structure shown, after the embedded power rail has been formed in the region that previously contained additional placeholder material and placeholder material layers.

[0030] [Figure 17A] Figure 16A shows a cross-sectional view of an exemplary structure after additional interlayer dielectric material has been formed on the embedded power rail. [Figure 17B] Figure 16B is a cross-sectional view of an exemplary structure after additional interlayer dielectric material has been formed on the embedded power rail. [Figure 17C] Figure 16C shows a cross-sectional view of an exemplary structure after additional interlayer dielectric material has been formed on the embedded power rail.

[0031] [Figure 18A] This is a cross-sectional view of the exemplary structure shown in Figure 17A after the conductive contact structure has been formed. [Figure 18B] Figure 17B is a cross-sectional view of an exemplary structure after the conductive contact structure has been formed. [Figure 18C] Figure 17C is a cross-sectional view of an exemplary structure after the conductive contact structure has been formed.

[0032] [Figure 19]Figure 3 shows a cross-sectional view of an exemplary structure after forming a spacer from the spacer material layer, removing the physically exposed portion of the first dielectric material layer and the portion of the shallow trench isolation structure not protected by the spacer, and forming an embedded power rail conductive material layer beneath the surface of the shallow trench isolation structure.

[0033] [Figure 20A] This is a cross-sectional view taken along the cut line X2-X2 shown in Figure 6 of the exemplary structure shown in Figure 19, after forming the polysilicon layer, removing the spacers, forming the source / drain region, and forming the interlayer dielectric material layer. [Figure 20B] This is a cross-sectional view taken along the cut line X3-X3 shown in Figure 6 of the exemplary structure shown in Figure 19, after forming the polysilicon layer, removing the spacers, forming the source / drain region, and forming the interlayer dielectric material layer. [Figure 20C] This is a cross-sectional view taken along the cut line X4-X4 shown in Figure 6 of the exemplary structure shown in Figure 19, after forming the polysilicon layer, removing the spacers, forming the source / drain region, and forming the interlayer dielectric material layer.

[0034] [Figure 21A] This is a cross-sectional view of the exemplary structure shown in Figure 20A after the gate-cut trench mask has been formed. [Figure 21B] This is a cross-sectional view of the exemplary structure shown in Figure 20B after the gate-cut trench mask has been formed. [Figure 21C] This is a cross-sectional view of the exemplary structure shown in Figure 20C after the gate-cut trench mask has been formed.

[0035] [Figure 22A] This is a cross-sectional view of the exemplary structure shown in Figure 21A after performing a gate cutting process in which a gate cut trench is formed. [Figure 22B] Figure 21B is a cross-sectional view of the exemplary structure shown after performing a gate cutting process that forms a gate cut trench. [Figure 22C] Figure 21C is a cross-sectional view of an exemplary structure after performing a gate cutting process that forms a gate cut trench.

[0036] [Figure 23A] This is a cross-sectional view of the exemplary structure shown in Figure 22A after the dielectric material has been formed in the gate cut trench. [Figure 23B] This is a cross-sectional view of the exemplary structure shown in Figure 22B after the dielectric material has been formed in the gate cut trench. [Figure 23C] Figure 22C is a cross-sectional view of an exemplary structure after dielectric material has been formed in the gate cut trench.

[0037] [Figure 24A] Figure 23A shows a cross-sectional view of an exemplary structure after source / drain cutting has been performed, which forms a source / drain cut trench that physically exposes the embedded power rail conductive material layer. [Figure 24B] Figure 23B shows a cross-sectional view of an exemplary structure after performing a source / drain cut, which forms a source / drain cut trench that physically exposes the embedded power rail conductive material layer. [Figure 24C] Figure 23C shows a cross-sectional view of an exemplary structure after performing a source / drain cut, which forms a source / drain cut trench that physically exposes the embedded power rail conductive material layer.

[0038] [Figure 25A] Figure 24A shows a cross-sectional view of an exemplary structure in a source / drain cut trench, after the placeholder material has been formed on a physically exposed embedded power rail conductive material layer. [Figure 25B] Figure 24B shows a cross-sectional view of an exemplary structure in a source / drain cut trench, after the placeholder material has been formed on a physically exposed embedded power rail conductive material layer. [Figure 25C]Figure 24C shows a cross-sectional view of an exemplary structure in a source / drain cut trench, after the placeholder material has been formed on a physically exposed embedded power rail conductive material layer.

[0039] [Figure 26A] This is a cross-sectional view of the exemplary structure shown in Figure 25A after the gate cut trench mask has been removed. [Figure 26B] Figure 25B is a cross-sectional view of the exemplary structure after the gate cut trench mask has been removed. [Figure 26C] Figure 25C is a cross-sectional view of the exemplary structure shown after the gate cut trench mask has been removed.

[0040] [Figure 27A] Figure 26A shows a cross-sectional view of the exemplary structure after the polysilicon layer and the first dielectric material layer have been removed to expose the second and third nanosheet stacks, and each sacrificial semiconductor material nanosheet in the second and third nanosheet stacks has been replaced with a functional gate structure. [Figure 27B] Figure 26B shows a cross-sectional view of the exemplary structure after the polysilicon layer and the first dielectric material layer have been removed to expose the second and third nanosheet stacks, and each sacrificial semiconductor material nanosheet in the second and third nanosheet stacks has been replaced with a functional gate structure. [Figure 27C] Figure 26C shows a cross-sectional view of the exemplary structure after the polysilicon layer and the first dielectric material layer have been removed to expose the second and third nanosheet stacks, and each sacrificial semiconductor material nanosheet in the second and third nanosheet stacks has been replaced with a functional gate structure.

[0041] [Figure 28A] This is a cross-sectional view of the exemplary structure shown in Figure 27A after the placeholder material has been removed. [Figure 28B] Figure 27B is a cross-sectional view of the exemplary structure after the placeholder material has been removed. [Figure 28C]Figure 27C is a cross-sectional view of the exemplary structure shown after the placeholder material has been removed.

[0042] [Figure 29A] Figure 28A shows a cross-sectional view of an exemplary structure after additional embedded power rail conductive material has been formed on the physically exposed surface of the embedded power rail conductive material layer. [Figure 29B] Figure 28B shows a cross-sectional view of an exemplary structure after additional embedded power rail conductive material has been formed on the physically exposed surface of the embedded power rail conductive material layer. [Figure 29C] Figure 28C shows a cross-sectional view of an exemplary structure after additional embedded power rail conductive material has been formed on the physically exposed surface of the embedded power rail conductive material layer.

[0043] [Figure 30A] This is a cross-sectional view of the exemplary structure shown in Figure 29A after forming additional interlayer dielectric material on additional embedded power rail conductive material. [Figure 30B] Figure 29B shows a cross-sectional view of the exemplary structure after forming additional interlayer dielectric material on additional embedded power rail conductive material. [Figure 30C] Figure 29C shows a cross-sectional view of an exemplary structure after forming additional interlayer dielectric material on additional embedded power rail conductive material.

[0044] [Figure 31A] This is a cross-sectional view of the exemplary structure shown in Figure 30A after the conductive contact structure has been formed. [Figure 31B] Figure 30B is a cross-sectional view of an exemplary structure after the conductive contact structure has been formed. [Figure 31C] Figure 30C is a cross-sectional view of an exemplary structure after the conductive contact structure has been formed.

[0045] [Figure 32A]This is a cross-sectional view of an exemplary structure of the present application in the source / drain region, showing a combination of different embedded power rail and conductive contact structure designs. [Figure 32B] This is a cross-sectional view of an exemplary structure of the present application in the source / drain region, showing a combination of different embedded power rail and conductive contact structure designs.

[0046] [Figure 33A] This is a cross-sectional view of an exemplary structure of the present application in the source / drain region, showing a combination of different embedded power rail and conductive contact structure designs. [Figure 33B] This is a cross-sectional view of an exemplary structure of the present application in the source / drain region, showing a combination of different embedded power rail and conductive contact structure designs. [Modes for carrying out the invention]

[0047] Next, the present application will be described in more detail by reference to the following discussion and the accompanying drawings. Note that the drawings are provided for illustrative purposes only and are not drawn to scale. Also note that similar and corresponding elements are referred to by the same reference numerals.

[0048] The following description includes a great deal of specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, those skilled in the art will understand that various embodiments of the present application can be carried out without these specific details. In other instances, well-known structures or processing steps are not described in detail in order to avoid obscuring the present application.

[0049] When an element, such as a layer, region, or base, is described as being "on" or "over" another element, it will be understood that it may be directly on that other element, or that there may be an intervening element. In contrast, when an element is described as being "directly on" or "directly over" another element, there is no intervening element. Similarly, when an element is described as being "beneath" or "under" another element, it will be understood that it may be directly below or beneath that other element, or that there may be an intervening element. In contrast, when an element is described as being "directly beneath" or "directly under" another element, there is no intervening element.

[0050] In the following description, as an example, the present application illustrates that the embedded power rail is formed between a first semiconductor device region including a first composite film device and a second semiconductor device region including a second composite film device. Although the present application describes and illustrates such a structure, it is not limited thereto. Instead, the embedded power rail of the present application may be formed between a first semiconductor device region and a second semiconductor device region, including any type of semiconductor device, including but not limited to nanosheet-containing devices (e.g., composite nanosheet devices (e.g., composite film devices) or non-composite nanosheet devices), finFET-containing semiconductor devices, semiconductor nanowire-containing devices, or at least planar semiconductor devices. In nanosheet-containing devices, semiconductor channel material nanosheets are used as semiconductor channel material-containing structures. In finFET-containing devices, semiconductor fins are used as semiconductor channel material-containing structures. In semiconductor nanowire-containing devices, semiconductor nanowires are used as semiconductor channel material-containing structures. In planar semiconductor devices, planar semiconductor materials may be used as semiconductor channel material-containing structures. The semiconductor devices in the first semiconductor device region may be the same as or different from the semiconductor devices in the second semiconductor device region. Typically, the first and second semiconductor device regions contain semiconductor devices of the same type.

[0051] Referring first to Figure 1, an example of a cell layout is shown, each including two composite film device regions FS1 and FS2 separated by a trench isolation structure STI that may be used in this application. Although such a cell layout is described and illustrated, other cell layouts including any number of composite film devices may be used in this application.

[0052] Referring back to Figure 1, the first composite film device region FS1 includes a first dielectric pillar DP1 that separates the first vertical stack of the suspended semiconductor channel material nanosheet NS1 from the second vertical stack of the suspended semiconductor channel material nanosheet NS2. A first functional gate structure GS1 is shown in the first composite film device region FS1, which straddles and wraps around the first and second vertical stacks of the suspended semiconductor channel material nanosheets NS1 and NS2, respectively. Each vertical stack of the suspended semiconductor channel material nanosheet and the functional gate structure together provide the nanosheet device of the present application. The second composite film device region FS2 includes a second dielectric pillar PD2 that separates the third vertical stack of the suspended semiconductor channel material nanosheet NS3 from the fourth vertical stack of the suspended semiconductor channel material nanosheet NS4. A second functional gate structure GS2 is shown in the second composite film device region FS2, which straddles and wraps around the third and fourth vertical nanosheet stacks of suspended semiconductor channel material nanosheets NS3 and NS4, respectively. Figure 1 also shows a cut line X1-X1 that passes through each of the first and second composite film device regions FS1 and FS2 and exists along the longitudinal regions of the laterally adjacent first and second functional gate structures GS1 and GS2.

[0053] Referring here to Figure 2, an exemplary structure taken along the cut line X1-X1 shown in Figure 1 of the present application is illustrated. The exemplary structure includes a shallow trench separation structure 16 that separates a first composite film device region FS1 from a second composite film device region FS2. The first composite film device region FS1 includes a first nanosheet stack S1 and a second nanosheet stack S2 separated by a first dielectric pillar 20L, and the second composite film device region FS2 includes a third nanosheet stack S3 and a fourth nanosheet stack S4 separated by a second dielectric pillar 20R. The exemplary structure shown in Figure 1 further includes a first dielectric material layer 18 located on and adjacent to each of the first, second, third, and fourth nanosheet stacks S1, S2, S3, and S4 in the lateral direction.

[0054] As shown in Figure 2, each of the first, second, third, and fourth nanosheet stacks S1, S2, S3, and S4 is located on a base portion 10 of a semiconductor substrate. Each base portion 10 is composed of a semiconductor material including, for example, silicon (Si), silicon germanium (SiGe) alloy, silicon germanium carbide (SiGeC) alloy, germanium (Ge), III / V compound semiconductor, II / VI compound semiconductor, or a multilayer stack containing at least two semiconductor materials (e.g., a multilayer stack of Si and SiGe).

[0055] In some embodiments, the semiconductor substrate may be a bulk semiconductor substrate. A “bulk semiconductor substrate” means a substrate entirely composed of one or more semiconductor materials. In embodiments where a bulk semiconductor substrate is used, the base portion 10 is formed from the upper semiconductor material of the bulk semiconductor substrate. In other embodiments, the semiconductor substrate may be a semiconductor-on-insulator (SOI) substrate. An SOI substrate includes a dielectric material (e.g., silicon dioxide, or boron nitride, or a combination thereof) sandwiched between a bottom semiconductor material and an upper semiconductor material. In one such embodiment, the base portion 10 is formed from the upper semiconductor material of the SOI substrate.

[0056] As further shown in Figure 2, each of the first, second, third, and fourth nanosheet stacks S1, S2, S3, and S4 comprises alternating sacrificial semiconductor material nanosheets 12 and semiconductor channel material nanosheets 14. Each of the first, second, third, and fourth nanosheet stacks S1, S2, S3, and S4 comprises an equal number of sacrificial semiconductor material nanosheets 12 and semiconductor channel material nanosheets 14. As shown in Figure 2 and as illustrated by one embodiment of the present application, each of the first, second, third, and fourth nanosheet stacks S1, S2, S3, and S4 may comprise three sacrificial semiconductor material nanosheets 12 and three semiconductor channel material nanosheets 14. Each sacrificial semiconductor material nanosheet 12 is composed of a first semiconductor material, while each semiconductor channel material nanosheet 14 is composed of a second semiconductor material that is compositionally different from the first semiconductor material. In some embodiments, the second semiconductor material providing each semiconductor channel material nanosheet 14 is a semiconductor material capable of providing high channel mobility to an nFET device. In other embodiments, the second semiconductor material providing each semiconductor channel material nanosheet 14 is a semiconductor material capable of providing high channel mobility to a pFET device.

[0057] The first semiconductor material providing each sacrificial semiconductor material nanosheet 12 and the second semiconductor material providing each semiconductor channel material nanosheet 14 may include one of the semiconductor materials mentioned above for the base portion 10 of the semiconductor substrate. In this application, the first semiconductor material providing each sacrificial semiconductor material nanosheet 12 is compositionally different from the base portion 10 of the semiconductor substrate. The second semiconductor material providing each semiconductor channel material nanosheet 14 may be compositionally the same as or different from the base portion 10 of the semiconductor substrate. Typically, the second semiconductor material providing each semiconductor channel material nanosheet 14 is compositionally the same as the base portion 10 of the semiconductor material portion of the semiconductor substrate. In one example, the base portion 10 of the semiconductor substrate is composed of Si, the first semiconductor material providing each sacrificial semiconductor material nanosheet 12 is composed of a SiGe alloy, and the second semiconductor material providing each semiconductor channel material nanosheet 14 is composed of Si. Other combinations of semiconductor materials are possible, as long as the first semiconductor material providing each sacrificial semiconductor material nanosheet 12 is compositionally different from the second semiconductor material providing each semiconductor channel material nanosheet 14.

[0058] The width of each sacrificial semiconductor material nanosheet 12 may be the same or different. A typical width of each sacrificial semiconductor material nanosheet 12 is 1 nm to 20 nm. Other widths are intended and can be used as the width of each sacrificial semiconductor material nanosheet 12. The width of each semiconductor channel material nanosheet 14 may be the same or different. A typical width of each semiconductor channel material nanosheet 14 is 1 nm to 20 nm. Other widths are intended and can be used as the width of each semiconductor channel material nanosheet 14. The thickness (i.e., vertical height) of each sacrificial semiconductor material nanosheet 12 may be the same or different. A typical thickness of each sacrificial semiconductor material nanosheet 12 is 1 nm to 20 nm. Other thicknesses are intended and can be used as the thickness width of each sacrificial semiconductor material nanosheet 12. The thickness of each semiconductor channel material nanosheet 14 may be the same or different. A typical thickness of each semiconductor channel material nanosheet 14 is 1 nm to 20 nm. Other thicknesses are intended and can be used as the thickness of each semiconductor channel material nanosheet 14.

[0059] The shallow trench isolation structure 16 may be composed of a trench dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, or any preferred combination thereof. As shown in Figure 2, the shallow trench isolation structure 16 typically has a recessed upper surface below the uppermost surface of each base portion 10 of the semiconductor substrate.

[0060] The first dielectric material layer 18 may be composed of the same or a different dielectric material as the shallow trench isolation structure 16. Exemplary dielectric materials for the first dielectric material layer 18 include, but are not limited to, silicon dioxide or silicon oxynitride. The first dielectric material layer 18 may be a conformal layer. "Conformal layer" means that the material layer has a thickness along a horizontal surface that is the same as the thickness of the same material layer along a vertical surface. The first dielectric material layer 18 may have a thickness of 2 nm to 15 nm, but other thicknesses of the first dielectric material layer 18 are intended and may be used as the thickness of the first dielectric material layer 18.

[0061] The first and second dielectric pillars 20L and 20R are composed of dielectric materials that are compositionally different from the dielectric material that provides the first dielectric material layer 18. For example, if the first dielectric material layer 18 is composed of silicon dioxide, the first and second dielectric pillars 20L and 20R are composed of silicon nitride. The first and second dielectric pillars 20L and 20R may have upper surfaces that are coplanar with the uppermost horizontal surface of the first dielectric material layer 18 that is present on each of the first, second, third, and fourth nanosheet stacks S1, S2, S3, and S4.

[0062] The exemplary structure shown in Figure 2 can be formed using techniques well known to those skilled in the art. In one example, the exemplary structure shown in Figure 2 can be formed by first providing a bulk substrate or SOI substrate. Next, a patterned material stack of alternating layers of sacrificial semiconductor material and semiconductor channel material is formed on the surface of the bulk substrate or SOI substrate. The patterned material stack can be formed by epitaxial growth of a blanket and alternating layers of sacrificial semiconductor material and semiconductor channel material, followed by patterning the blanket layer by lithography and etching to provide the first, second, third, and fourth nanosheet stacks S1, S2, S3, and S4, respectively. Next, trench openings can be formed in the bulk substrate or SOI substrate by lithography and etching, and a base portion 10 is formed during the formation of the trench openings. Next, the trench openings are filled and recessed with trench dielectric material to provide a shallow trench isolation structure 16. Next, a first dielectric material layer 18 is formed using a deposition process such as chemical vapor deposition (CVD), plasma-extended chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). As shown in Figure 2, the first dielectric material layer 18 is formed on the physically exposed surfaces of the first, second, third, and fourth nanosheet stacks S1, S2, S3, and S4, the physically exposed surfaces of the base portion 10, and the physically exposed uppermost surface of the shallow trench separation structure 16. After the formation of the first dielectric material layer 18, the first and second dielectric pillars 20L and 20R are formed by deposition and recess etching.

[0063] Referring here to Figure 3, an exemplary structure shown in Figure 2 is illustrated after the formation of the spacer material layer 22L. The spacer material layer 22L is formed on the physically exposed surfaces of the first dielectric material layer 18 and the first and second dielectric pillars 20L, 20R. The spacer material layer 22L may consist of a spacer material such as polysilicon, silicon nitride, or a dielectric material containing atoms of Si, O, C, and N, but is not limited to these. The spacer material is typically compositionally different from at least the first dielectric material layer 18. The spacer material layer 22L may be formed by deposition of the spacer material. The deposition of the spacer material may include CVD, PECVD, PVD, or ALD. The spacer material layer 22L may have a thickness of 1 nm to 40 nm, but other thicknesses of the spacer material layer 22L are intended and may be used as the thickness of the spacer material layer 22L.

[0064] Referring to Figure 4, an exemplary structure shown in Figure 3 is illustrated after forming a spacer 22 from the spacer material layer 22L, removing the physically exposed portion of the first dielectric material layer 18 and the portion of the shallow trench isolation structure 16 not protected by the spacer 22, and forming a placeholder material layer 28 beneath the surface of the shallow trench isolation structure 16. The placeholder material layer 28 is formed in the region between the second nanosheet stack S2 and the third nanosheet stack S3.

[0065] The formation of the spacer 22 involves performing spacer etching on the spacer material layer 22L. In one embodiment, the spacer etching may include reactive ion etching (RIE). The spacer 22 is formed in the shallow trench isolation region of the structure and along the sidewalls of each nanosheet stack facing the shallow trench isolation structure 16. The spacer 22 may have an upper surface that is coplanar with the uppermost horizontal surface of the first dielectric material layer 18 present on each of the first, second, third, and fourth nanosheet stacks S1, S2, S3, and S4.

[0066] After the formation of the spacer 22, as shown in Figure 4, a portion of the first dielectric material layer 18 and the shallow trench isolation structure 16 are removed in the shallow trench isolation region of the structure. The removal of a portion of the first dielectric material layer 18 and the shallow trench isolation structure 16 in the shallow trench isolation region of the structure may include one or more etching processes. In one example, one or more RIE processes may be used to remove a portion of the first dielectric material layer 18 and the shallow trench isolation structure 16 in the shallow trench isolation region of the structure.

[0067] Removal of the first dielectric material layer 18 and a portion of the shallow trench isolation structure 16 in the shallow trench isolation region of the structure provides an opening that physically exposes the subsurface of the shallow trench isolation structure 16. The term “subsurface” is used throughout this application to refer to the surface of the material located between the uppermost surface of the material and the lowermost surface of the material.

[0068] Next, a placeholder material layer 28 is formed beneath the surface of the shallow trench separation structure 16. The placeholder material layer 28 may contain any sacrificial material, including, for example, a metal oxide such as titanium dioxide. Other sacrificial materials, such as elemental metals, may be used as the placeholder material layer 28. The sacrificial material providing the placeholder material layer 28 may be formed by a deposition process such as CVD, PECVD, PVD, ALD, plating, or sputtering, without the use of any additional masks. Recess etching may follow the deposition of the sacrificial material. The formed placeholder material layer 28 may have an uppermost surface that is perpendicularly offset to and located below the uppermost surface of the shallow trench separation structure 16.

[0069] Referring here to Figure 5, an exemplary structure shown in Figure 4 is illustrated after forming additional trench dielectric material on the placeholder material layer 28. The additional trench dielectric material is typically the same compositional trench dielectric material as the trench dielectric material used to provide the shallow trench isolation structure 16 shown in Figure 2 above. The additional trench dielectric material is formed on the placeholder material layer 28 to re-establish the integrity of the shallow trench isolation structure 16.

[0070] Referring now to Figure 6, an example of a cell layout similar to that shown in Figure 1 is illustrated, and which includes cut lines X2-X2, X3-X3, and X4-X4. The cell contains the elements enumerated in Figure 1 above, and further shows the sacrificial placeholder material 28 and the cut region CR. The cut region includes the gate cut region and the source / drain cut region. In Figure 6, the cut line X2-X2 is located in the source / drain region, cut region (i.e., source / drain cut region) of the first gate structure GS1 located on the second nanosheet stack NS2, and the source / drain region of the second gate structure GS2 located on the third nanosheet stack NS3. The cut line X3-X3 passes through the first gate structure GS1 located on the second nanosheet stack NS2, the cut region (i.e., gate cut region), and the second gate structure GS2 located on the third nanosheet stack NS3. The cut lines X4-X4 are located in the source / drain regions of the first gate structure GS1 on the second nanosheet stack NS2 and the source / drain regions of the second gate structure GS2 on the third nanosheet stack NS3, and there are no cut regions along the cut lines X4-X4.

[0071] Referring here to Figures 7A, 7B, and 7C, the exemplary structures shown in Figure 5 are illustrated, taken along the cut lines X2-X2, X3-X3, and X4-X4 shown in Figure 6, respectively, after forming the polysilicon 34 layer, removing the spacer 22, forming the source / drain region 30, and forming the interlayer dielectric material (ILD) layer 32.

[0072] The polysilicon 34 layer may be formed by a deposition process such as CVD, PECVD, or PVD. A patterning process including lithography and etching may follow the deposition of the polysilicon 34 layer. The polysilicon 34 layer is formed only in the region containing the cut line X3-X3. The removal of the spacer 22 may be performed during the etching process used to provide the polysilicon 34 layer. Alternatively, the spacer 22 may be removed before or after forming the polysilicon 24 layer using a separate etching process.

[0073] As shown in Figures 7A and 7C, the source / drain regions 30 are formed on a base portion 10 that does not include the nanosheet stacking, and the source / drain regions 30 are coupled to at least the edges of each suspended semiconductor channel material nanosheet 14. As used herein, the “source / drain” region can be either a source region or a drain region depending on the subsequent wiring and voltage application during FET operation. The source / drain regions 30 include a semiconductor material and a dopant. The semiconductor material providing each source / drain region 30 may include one of the semiconductor materials mentioned above for the base portion 10 of the semiconductor substrate. The semiconductor material providing the source / drain regions 30 may be compositionally the same as or compositionally different from each semiconductor channel material nanosheet 14. However, the semiconductor material providing the source / drain regions 30 is compositionally different from each sacrificial semiconductor material nanosheet 12.

[0074] The dopants present in each source / drain region 30 may be either p-type or n-type dopants. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor that create valence electron defects. Examples of p-type dopants, i.e., impurities, in silicon-containing semiconductor materials include, but are not limited to, boron, aluminum, gallium, and indium. The term "n-type" refers to the addition of impurities that confer free electrons to an intrinsic semiconductor. Examples of n-type dopants, i.e., impurities, in silicon-containing semiconductor materials include, but are not limited to, antimony, arsenic, and phosphorus. In one example, each source / drain region 30 is 4 × 10⁻¹⁶ 20 individual atoms / cm 3 ~3×10 21 individual atoms / cm 3 It may have a dopant concentration of [value missing]. In one example, each bottom source / drain region 46 is composed of phosphorus-doped silicon.

[0075] Each source / drain region 30 may be formed by epitaxial growth, and dopants are present during the epitaxial growth process. To reduce the height of each of the source / drain regions 30, recess etching may be optionally used.

[0076] Next, as shown in Figures 7A and 7C, an ILD material layer 32 is formed on and adjacent to the source / drain region 30 in the lateral direction. The ILD material layer 32 may consist of dielectric materials including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borosilicate glass (BPSG), spin-on low-k dielectric layers, chemical vapor deposition (CVD) low-k dielectric layers, or any combination thereof. The term "low-k" as used throughout this application refers to dielectric materials having a dielectric constant lower than that of silicon dioxide. Although not shown, the ILD material layer 32 may include a multilayer structure comprising at least two different dielectric materials stacked on top of each other, such as silicon nitride and silicon dioxide. The ILD material layer 32 may be formed by deposition processes such as CVD, PECVD, and spin-on coating. In some embodiments, a planarization process may be performed after the deposition of the dielectric materials providing the ILD material layer 32. The ILD material layer 32 typically has an uppermost surface that is coplanar with the uppermost surface of the polysilicon layer 34.

[0077] Referring here to Figures 8A, 8B, and 8C, exemplary structures shown in Figures 7A, 7B, and 7C are illustrated after the formation of the gate cut trench mask 36. The gate cut trench mask 36 is composed of a dielectric hard mask material such as silicon oxynitride, silicon nitride, or silicon dioxide. The gate cut trench mask 36 can be formed by depositing a dielectric hard mask material on a layer of polysilicon 34 and an ILD material layer 32, and then patterning the deposited hard mask material to include openings as shown in Figures 8A and 8B. No openings are formed in the hard mask layer formed in Figure 8C. Openings are formed in cut regions, i.e., regions where gate cut trenches or source / drain cut trenches are later formed.

[0078] Referring here to Figures 9A, 9B, and 9C, the exemplary structures shown in Figures 8A, 8B, and 8C are illustrated after performing a gate cutting process in which gate cut trenches 38 that physically expose the placeholder material layer 28 are formed. The gate cut trenches 38 are formed between the second and third nanosheet stacks, i.e., in the region containing the cut line X3-X3 shown in Figure 9B. No gate cut trenches are formed in the region of the structures shown in Figures 9A and 9B.

[0079] The gate cut trench 38 can be formed using one or more etching processes that are selective in removing polysilicon first. One or more etching processes remove a portion of the polysilicon layer 34, a portion of the first dielectric material layer 18, and a portion of the shallow trench isolation structure 16 that is not protected by the gate cut trench mask 36. Note that because the first etching is selective in removing the polysilicon layer 34 compared to the ILD material layer 32, via openings are present in the gate cut trench mask 36 shown in Figure 9A, while no gate cut trenches are formed.

[0080] Referring here to Figures 10A, 10B, and 10C, exemplary structures shown in Figures 9A, 9B, and 9C are illustrated in the gate cut trench 38, after the dielectric material 40 has been formed on the placeholder material layer 28 (see Figure 10B). The dielectric material 40 is also formed in via openings present in the gate cut trench mask 36 located on the ILD material layer 32 (see Figure 10A). The dielectric material 40 is compositionally different from the hard mask material that provides the gate cut trench mask 36. For example, if the gate cut trench mask 36 is made of silicon oxynitride, the dielectric material 40 is made of silicon nitride.

[0081] The dielectric material 40 can be formed using a deposition process such as CVD, PECVD, PVD, or ALD. A material removal process, such as a planarization process, may follow the deposition of the dielectric material 40. The dielectric material 40 typically has an upper surface that is coplanar with the uppermost surface of the gate cut trench mask 36.

[0082] Referring here to Figures 11A, 11B, and 11C, exemplary structures shown in Figures 10A, 10B, and 10C are illustrated after performing a source / drain cut, which forms a source / drain cut trench 41 that physically exposes the placeholder material layer 28. The source / drain cut trench 41 is formed between the source / drain regions 20, including the cut line X2-X2 shown in Figure 11A. No source / drain cut trench is formed in the regions of the structures shown in Figures 11B and 11C.

[0083] The source / drain cut trench 41 may be formed using one or more etching processes that are at least selective in removing the dielectric material 40 first. One or more etching processes remove the dielectric material 40, a portion of the ILD material layer 32, and a portion of the shallow trench isolation structure 16 that is not protected by the gate cut trench mask 36. Note that in the region of the structure shown in Figure 11B, the dielectric material 40 in that region of the structure is recessed during this step of the application.

[0084] Referring here to Figures 12A, 12B, and 12C, the exemplary structures shown in Figures 11A, 11B, and 11C are illustrated, respectively, after additional placeholder material 42 has been formed on the physically exposed placeholder material layer 28 in the source / drain cut trench 41 (see Figure 12A). The additional placeholder material 42 is also formed on the remaining dielectric material 40 in the region of the structure shown in Figure 12B.

[0085] The additional placeholder material 42 may include one of the sacrificial materials mentioned above for the placeholder material layer 28. The additional placeholder material 42 may be formed by utilizing one of the deposition processes mentioned above in the formation of the placeholder material layer 28. Typically, the additional placeholder material 42 is composed of the same sacrificial material as the placeholder material layer 28. In one such embodiment, there is no material interface between the additional placeholder material 42 and the placeholder material layer 28. In other embodiments, the additional placeholder material 42 is composed of a sacrificial material that is different in composition from the placeholder material layer 28. In one such embodiment, there is a material interface between the additional placeholder material 42 and the placeholder material layer 28. In Figure 12A, possible material interfaces between the additional placeholder material 42 and the placeholder material layer 28 are represented by dotted lines.

[0086] Referring here to Figures 13A, 13B, and 13C, the exemplary structures shown in Figures 12A, 12B, and 12C, respectively, after the removal of the gate cut trench mask 36 are illustrated. The gate cut trench mask 36 can be removed using any material removal process, such as a wet chemical etching process. Removal of the gate cut trench mask 36 physically exposes the top of the ILD material layer 32 and additional placeholder material 42 in the region of the structure shown in Figure 13A, the top of the polysilicon layer 34 and dielectric material in the region of the structure shown in Figure 13B, and only the ILD material layer 32 in the region of the structure shown in Figure 13C.

[0087] Referring here to Figures 14A, 14B, and 14C, the polysilicon 34 layer and the first dielectric material layer 18 are removed to expose the second and third nanosheet stacks NS2 and NS3, and the sacrificial semiconductor material nanosheets 14 of the second and third nanosheet stacks are replaced with functional gate structures 44 and 46, as shown in the exemplary structures in Figures 13A, 13B, and 13C, respectively. Similar processing is performed on the first nanosheet stack S1 and the fourth nanosheet stack S4.

[0088] After forming the functional gate structures 44 and 46, additional dielectric material is formed on top of the dielectric material 40. The additional dielectric material and the dielectric material 40 together provide a dielectric material structure 48. The dielectric material structure 48 is located on top of each functional gate structure and adjacent to it laterally, as shown in Figure 14B. The additional dielectric material used to provide the dielectric material structure 48 may be formed by a deposition process including, but not limited to, CVD, PECVD, PVD, or ALD.

[0089] The polysilicon 34 layer can be removed using an etching process selective for the removal of polysilicon. This removal process stops at the first dielectric material layer 18. The first dielectric material layer 18 is then removed using an etching process selective for the removal of the first dielectric material layer 18. Removal of the first dielectric material layer 18 exposes the second and third nanosheet stacks NS2 and NS3. Next, while maintaining the vertical stack of suspended semiconductor channel material nanosheets 14, the sacrificial semiconductor material nanosheets 12 are removed from the second and third nanosheet stacks NS2 and NS3 using an etching process selective for the removal of sacrificial semiconductor material nanosheets 12. Each removal of sacrificial semiconductor material nanosheets 12 may include an etching process selective for the removal of sacrificial semiconductor material relative to the semiconductor channel material. Gate cavities (not shown) are formed above and below each vertical stack of suspended semiconductor channel material nanosheets 14, and gate cavities are also present between each suspended semiconductor channel material nanosheet 14.

[0090] Next, each gate cavity is filled with a functional gate structure 44, 46. Each functional gate structure 44, 46 includes at least a gate dielectric material layer 44 and a gate electrode 46. The functional gate structures 44, 46 are wrapped around each semiconductor channel material nanosheet 14 using a vertical stack of suspended semiconductor channel material nanosheets 14. As is known, the gate dielectric material layer 44 is in direct contact with the physically exposed portion of each semiconductor channel material nanosheet 14, and the gate electrode 46 is located on the gate dielectric material layer 44. In some embodiments, the functional gate structure includes a work function metal (WFM) layer located between the gate dielectric material layer 44 and the gate electrode 46. The functional gate structure includes forming continuous layers of gate dielectric material and gate electrode material on the inside and outside of the gate cavity. The continuous layers of gate dielectric material may include silicon dioxide, or a dielectric material with a higher dielectric constant than silicon dioxide (such dielectric materials may be referred to as high-k gate dielectric materials). Examples of high-k gate dielectric materials include, for example, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), and zirconium silicon oxynitride (ZrSiO4). x N y ), tantalum oxide (TaO x These include metal oxides such as titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), tantalum scandium lead oxide (Pb(Sc,Ta)O3), or lead zinc niobite (Pb(Zn,Nb)O), or combinations thereof. High k-gate dielectric materials may further contain dopants such as lanthanum (La), aluminum (Al), or magnesium (Mg), or combinations thereof.

[0091] The continuous layer of gate dielectric material can be formed using deposition processes such as ALD, CVD, PECVD, or PVD. The continuous layer of gate dielectric material is a conformal layer with a thickness that can range from 1 nm to 10 nm. The continuous layer of gate dielectric material does not fill the entire gate cavity.

[0092] Electrode gate materials include tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag) or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), and tantalum carbide (TaC). X The conductive metal-containing material may include, but is not limited to, titanium carbide (TiC), titanium aluminum carbide, tungsten silide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silide, or nickel silide. The gate electrode material may be formed using a deposition process such as ALD, CVD, PECVD, PVD, plating, or sputtering. In some embodiments, reflow annealing or silicide annealing may be used after the deposition of the conductive metal-containing material of the present application is performed.

[0093] In some embodiments, a WFM layer may be formed on a continuous layer of gate dielectric material before the gate electrode material is formed. In other embodiments, the gate electrode consists solely of WFM. The WFM layer may be used to set the threshold voltage of the FET to a desired value. In some embodiments, the WFM layer may be selected to exert an n-type threshold voltage shift effect. "n-type threshold voltage shift," as used herein, means a shift in the effective work function of a work function metal-containing material toward the conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of such materials that can exert an n-type threshold voltage shift effect include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM layer may be selected to exert a p-type threshold voltage shift effect. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, “threshold voltage” is the lowest achievable gate voltage that activates a semiconductor device, such as a transistor, by making the device's channel conductive. The term “p-type threshold voltage shift” as used herein means a shift in the work function of a metal-containing material toward the valence band of silicon in silicon-containing materials, and a shift in the effective work function of a metal-containing material. Examples of such materials that can exhibit a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof.

[0094] A WFM layer is a conformal layer that can be formed by conformal deposition processes such as ALD, CVD, or PECVD. While WFM layers can have thicknesses ranging from 1 nm to 20 nm, other thicknesses, larger or smaller than this range, may be used as desired for specific applications.

[0095] After forming a continuous layer of gate dielectric material, an optional layer of WFM, and gate electrode material, a planarization process such as CMP is used to remove the continuous layer of gate dielectric material, an optional layer of WFM, and gate electrode material from the outside of each gate cavity. The remaining continuous layer of gate dielectric material inside the gate cavity may be referred to as the gate dielectric material layer 44, the remaining optional layer of WFM inside the gate cavity may be referred to as the WFM layer, and the remaining gate electrode material inside the gate cavity provides the gate electrode 46. It should be repeatedly noted that the WFM layer may be used only as the gate electrode 46.

[0096] Referring here to Figures 15A, 15B, and 15C, the exemplary structures shown in Figures 14A, 14B, and 14C are illustrated after the removal of the additional placeholder material 42 and placeholder material layer 28, respectively. The removal of the placeholder material layer 28 in the region of the structure shown in Figures 15B and 15C creates a void V1 in the shallow trench separation structure 16. The removal of the additional placeholder material 42 and placeholder material layer 28 in the region of the structure shown in Figure 15A provides an embedded power rail via opening 50. The removal of the additional placeholder material 42 and placeholder material layer 28 involves an etching process that is selective for the removal of sacrificial material. The embedded power rail via opening 50 is formed in the previous source / drain cut trench 41.

[0097] Referring here to Figures 16A, 16B, and 16C, the exemplary structures shown in Figures 15A, 15B, and 15C are illustrated after the embedded power rail 52 has been formed in the region that previously contained additional placeholder material 42 and placeholder material layer 28. The embedded power rail 52 is formed in the void V1 and the embedded power rail via opening 50.

[0098] The embedded power rail 52 may be composed of any conductive power rail material, including but not limited to tungsten (W), cobalt (Co), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd), and typically a thin metal adhesive layer (TiN, TaN, etc.) is formed before the conductive metal deposition. For clarity, the metal adhesive layer is not separately illustrated in the drawings of this application. The embedded power rail 52 may be formed by deposition, planarization, and recess etching of the conductive power rail material. Recess etching makes it possible to adjust the height of the embedded power rail 52 present in the embedded power rail trench 50.

[0099] The embedded power rail 52 has a first portion (see Figure 16B) located in the gate cut trench 38 and having a first height h1, and a second portion (see Figure 16A) located in the source / drain cut trench 41 and having a second height h2 greater than the first height, and the first and second portions of the embedded power rail 52 provide a continuous embedded power rail structure. As shown in Figure 16B, the first portion of the embedded power rail 52 is located completely below the uppermost surface of the shallow trench separation structure 16, and as shown in Figure 17A, the second portion of the embedded power rail 52 has an upper part that extends above the uppermost surface of the shallow trench separation structure 16. Figure 16C shows a third portion of the embedded power rail 52 that is completely enclosed by the shallow trench separation structure 16.

[0100] Referring here to Figures 17A, 17B, and 17C, the exemplary structures shown in Figures 16A, 16B, and 16C, respectively, after forming additional interlayer dielectric material on the embedded power rail 52 are illustrated. The additional ILD material is typically the same ILD material as the ILD material layer 32, and thus the additional ILD material layer re-establishes the integrity of the ILD material layer 32.

[0101] Referring here to Figures 18A, 18B, and 18C, exemplary structures shown in Figures 17A, 17B, and 17C, respectively, are illustrated after the formation of the conductive contact structure 56. In some embodiments, contact liners are present along the side and bottom walls of the conductive contact structure 56. In the region of the structure shown in Figure 18A, the conductive contact structure 56 may be formed by first recessing the ILD material layer 32 beneath the uppermost surfaces of both the embedded power rail 52 and the source / drain region 30, and then forming the conductive contact structure 56. In the region of the structure shown in Figure 18C, a contact opening is formed in the ILD material layer 32, and then the conductive contact 56 is formed in the contact opening.

[0102] In one or more embodiments where a contact liner is present, the contact liner (not shown) may include a silicide liner, such as Ti, Ni, NiPt, and a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ru, TiN, TaN, WN, WC, their alloys, or stacks thereof, such as Ti / TiN and Ti / WC. The contact liner may be formed using conformal deposition processes including PVD, RFPVD, CVD, or ALD. The formed contact liner may have a thickness in the range of 1 nm to 8 nm, although smaller and larger thicknesses may also be used.

[0103] The conductive contact structure 56 comprises a contact conductor material such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. The contact conductor material may be formed by any preferred deposition method such as ALD, CVD, PVD, or plating. A planarization process may be used to remove the contact conductor material and contact liner (if provided) located outside the contact opening. The remaining contact conductor material, and contact liner if present, provides the conductive contact structure shown in Figures 18A and 18C. In Figure 18A, the conductive contact structure 56 is in direct physical contact with the surface of the embedded power rail 52, as well as the physically exposed surface of the source / drain region 30 of the adjacent nanosheet device. In Figure 18C, the conductive contact structure 56 is in direct contact with the individual source / drain region 30.

[0104] Referring here to Figure 19, an exemplary structure shown in Figure 3 is illustrated after forming the spacer 22 from the spacer material layer 22L, removing the physically exposed portion of the first dielectric material layer 18 and the portion of the shallow trench isolation structure 16 not protected by the spacer 22, and forming the embedded power rail conductive material layer 60 beneath the surface of the shallow trench isolation structure 16. In this embodiment of the present application, the formation of the spacer 22 and the removal of the physically exposed portion of the first dielectric material layer 18 and the portion of the shallow trench isolation structure 16 are the same as those described above in the embodiment of the present application that provides the structure shown in Figure 4.

[0105] Instead of forming a placeholder material layer 28 as in Figure 4, this embodiment of the present application forms an embedded power rail conductive material layer 60 beneath the surface of the shallow trench separation structure 16. The embedded power rail conductive material layer 60 comprises one of the conductive power rail materials mentioned above for the embedded power rail 52. The embedded power rail conductive material layer 60 can be formed by first depositing the conductive power rail material and then performing recess etching. The deposition of the conductive power rail material comprises one of the deposition techniques mentioned above for the formation of the embedded power rail 52. The embedded power rail conductive material layer 60 has an upper surface that is coplanar with or slightly below the uppermost surface of the shallow trench separation structure 16.

[0106] Referring here to Figures 20A, 20B, and 20C, the exemplary structures shown in Figure 19 are illustrated, taken along the cut lines X2-X2, X3-X3, and X4-X4 shown in Figure 6, respectively, after forming the polysilicon 34 layer, removing the spacer 22, forming the source / drain region 30, and forming the interlayer dielectric material layer 32. The materials and processing steps used to provide the exemplary structures shown in Figures 20A, 20B, and 20C are the same as the materials and processing steps mentioned above in forming the structures shown in Figures 7A, 7B, and 7C.

[0107] Referring here to Figures 21A, 21B, and 21C, the exemplary structures shown in Figures 20A, 20B, and 20C, respectively, after the formation of the gate-cut trench mask 36 are illustrated. The description of the gate-cut trench mask 36 mentioned above with respect to the provision of the exemplary structures shown in Figures 8A, 8B, and 8C applies equally here to this embodiment of the present application. It should be reiterated that the gate-cut trench mask 36 has openings in the regions of the structures shown in Figures 21A and 21B, but not in Figure 21C.

[0108] Referring here to Figures 22A, 22B, and 22C, the exemplary structures shown in Figures 21A, 21B, and 21C, respectively, are illustrated after performing a gate cutting process that forms the gate cut trench 62. The gate cutting process used in this embodiment is similar to the gate cutting process mentioned above for providing the exemplary structure shown in Figure 9B. In this embodiment, one or more etching processes used to form the gate cut trench 62 are terminated on the surface of the first dielectric material layer 18.

[0109] Referring here to Figures 23A, 23B, and 24C, exemplary structures shown in Figures 22A, 22B, and 22C, respectively, are illustrated after the dielectric material 40 has been formed in the gate cut trench 62. The dielectric material 40 includes one of the materials mentioned above for the dielectric material 40 shown in Figures 10A and 10B of this application. The dielectric material 40 may be formed using one of the deposition techniques mentioned above for providing the dielectric material 40 in the structures shown in Figures 10A and 10B of this application.

[0110] Referring here to Figures 24A, 24B, and 24C, the exemplary structures shown in Figures 23A, 23B, and 23C are illustrated, respectively, after performing a source / drain cut that forms a source / drain cut trench 64 that physically exposes the embedded power rail conductive material layer 60 (see Figure 24A). The source / drain cut used to form the source / drain cut trench 64 is the same as the source / drain cut mentioned above for the formation of the source / drain cut trench 42 shown in Figure 11A. Note that the etching used to form the source / drain cut trench 64 is stopped on the surface of the embedded power rail conductive material layer 60.

[0111] Referring here to Figures 25A, 25B, and 25C, exemplary structures shown in Figures 24A, 24B, and 24C are illustrated after the placeholder material 43 has been formed in the source / drain cut trench 64 and on the physically exposed embedded power rail conductive material layer 60. The placeholder material 43 used in this embodiment of the present application includes one of the sacrificial materials mentioned above for the formation of the sacrificial placeholder material layer 28. As shown in Figure 25B, the placeholder material 43 is also formed on the dielectric material 40 present in the gate cut trench 62.

[0112] Referring here to Figures 26A, 26B, and 26C, the exemplary structures shown in Figures 25A, 25B, and 25C, respectively, after the removal of the gate cut trench mask 36 are illustrated. The removal of the gate cut trench mask 36 in this embodiment of the present application is the same as the removal of the gate cut trench mask 36 in previous embodiments of the present application (see, for example, the above description for Figures 13A, 13B, and 13C).

[0113] Referring here to Figures 27A, 27B, and 27C, the exemplary structures shown in Figures 26A, 26B, and 26C are illustrated after removing the polysilicon 34 layer and the first dielectric material layer 18 to expose the second and third nanosheet stacks, and replacing each sacrificial semiconductor material nanosheet 12 of the second and third nanosheet stacks with functional gate structures 44 and 46.

[0114] After the functional gate structures 44 and 46 are formed, an additional dielectric material is formed on top of the dielectric material 40. The additional dielectric material and the dielectric material 40 together provide a dielectric material structure 48. The dielectric structure 48 is located on top of each functional gate structure and is laterally adjacent to it, as shown in Figure 27B. The additional dielectric material used to provide the dielectric material structure 48 may be formed by a deposition process including, but not limited to, CVD, PECVD, PVD, or ALD.

[0115] The polysilicon 34 layer can be removed using the etching process described above in the removal of the same layer from the structure shown in Figure 14B above. This removal process stops at the first dielectric material layer 18. The first dielectric material layer 18 is then removed using an etching process selective for the removal of the first dielectric material layer 18. The removal of the first dielectric material layer 18 exposes the second and third nanosheet stacks NS2 and NS3. Next, while maintaining the vertical stack of suspended semiconductor channel material nanosheets 14, the sacrificial semiconductor material nanosheets 12 are removed from the second and third nanosheet stacks NS2 and NS3 using an etching process selective for the removal of sacrificial semiconductor material nanosheets 12. Each removal of the sacrificial semiconductor material nanosheets 12 may include an etching process selective for removing the sacrificial semiconductor material relative to the semiconductor channel material. Gate cavities (not shown) are formed above and below the vertical stack of suspended semiconductor channel material nanosheets, and gate cavities are also present between each suspended semiconductor channel material nanosheet 14. Next, in the formation of the functional gate structures shown in Figure 14B, each gate cavity is filled with functional gate structures 44, 46 as described above. As described above, each functional gate structure 44, 46 includes at least a gate dielectric material layer 44 and a gate electrode 46. The functional gate structures 44, 46 are wrapped around each semiconductor channel material nanosheet 14 using a vertical stack of suspended semiconductor channel material nanosheets 14.

[0116] Referring here to Figures 28A, 28B, and 28C, the exemplary structures shown in Figures 27A, 27B, and 27C, respectively, after the removal of the placeholder material 43 are illustrated. The removal of the placeholder material 43 involves an etching process that is selective for the removal of sacrificial material. The embedded power rail conductive material layer 60 in the source / drain cut trench 64 is now physically exposed.

[0117] Referring here to Figures 29A, 29B, and 29C, the exemplary structures shown in Figures 28A, 28B, and 28C are illustrated after an additional embedded power rail conductive material 66 has been formed on the physically exposed surface of the embedded power rail conductive material layer 60 (see Figure 29A). In this embodiment, the embedded power rail conductive material layer 60 and the additional embedded power rail conductive material 66 together provide an embedded power rail that may have an adjustable height. The additional embedded power rail conductive material 66 may include one of the conductive power rail materials mentioned above for the embedded power rail 52. In some embodiments, the additional embedded power rail conductive material 66 is compositionally identical to the embedded power rail conductive material layer 60. In one such embodiment, there is no material interface between the embedded power rail conductive material layer 60 and the additional embedded power rail conductive material 66. In other embodiments, the additional embedded power rail conductive material 66 is compositionally different from the embedded power rail conductive material layer 60. In one such embodiment, a material interface exists between the embedded power rail conductive material layer 60 and an additional embedded power rail conductive material 66. The additional embedded power rail conductive material 66 can be formed by depositing conductive power rail material, followed by recess etching.

[0118] In this embodiment, the embedded power rail (i.e., the embedded power rail conductive material layer 60) has a first portion located in the gate cut trench 62 having a first height h1 (see Figure 29B), and a second portion in the source / drain cut trench 64 having a second height h2 greater than the first height (i.e., the embedded power rail conductive material layer 60 and additional power rail conductive material 66, see Figure 29A). As shown in Figure 29B, the first portion of the embedded power rail is located entirely below the uppermost surface of the shallow trench isolation structure 16, and as shown in Figure 29A, the second portion of the embedded power rail (in particular, the additional embedded power rail conductive material 66) has an upper portion that extends above the uppermost surface of the shallow trench isolation structure 16. Figure 29C shows a third portion of the embedded power rail (i.e., the embedded power rail conductive material layer 60) completely enclosed by the shallow trench isolation structure 16.

[0119] Referring here to Figures 30A, 30B, and 30C, an exemplary structure shown in Figures 29A, 29B, and 29C is illustrated after forming an additional interlayer dielectric material on the additional embedded power rail conductive material 66. The additional interlayer dielectric material is typically the same dielectric material that provides the ILD material layer 32.

[0120] Referring here to Figures 31A, 31B, and 31C, exemplary structures shown in Figures 30A, 30B, and 30C, respectively, are illustrated after the formation of the conductive contact structure 56. The conductive contact structure 56 of this embodiment comprises a material and can be formed using the same techniques described above for forming the conductive contact structure 56 shown in Figures 18A and 18C.

[0121] Referring here to Figures 32A, 32B, 33A, and 33B, exemplary structures in the source / drain region are illustrated, showing different combinations of designs for the embedded power rail 52 and the conductive contact structure 56, and the structures illustrated in Figures 32A, 32B, 33A, and 33B are related to the present invention. In Figures 32A, 32B, 33A, and 33B, element 10 is the base portion of the semiconductor substrate, element 16 is the shallow trench isolation, element 30 is the source / drain region, element 32 is the ILD material layer, element 52 is the embedded power rail, and element 56 is the conductive contact structure, as defined above. In particular, Figure 32A illustrates a first flexible design in which only a single conductive contact structure 56 directly contacts the embedded power rail 52, and this direct contact occurs along the upper sidewall portion of the embedded power rail 52 and along a portion of the uppermost surface of the embedded power rail 52. Figure 32B illustrates a second flexible design in which there is no direct physical contact between the conductive contact structure 56 and the embedded power rail 52; instead, each conductive contact structure 56 directly contacts one surface of the source / drain region 30. Figure 33A illustrates a third flexible design in which the conductive contact structure 56 directly contacts the uppermost surface of the embedded power rail 52 but does not contact any part of the source / drain region 30, while Figure 33B illustrates a fourth flexible design in which the conductive contact structure 56 directly contacts the uppermost surface of the embedded power rail 52, and it should be noted that the source / drain region 30 is not connected to the illustrated embedded power rail 52 and could be wiring from another location. In Figures 33A and 33B, the embedded power rail 52 has a first width w1, while the conductive contact structure 56 has a second width w2 which is greater than the first width w1. The structures shown in Figures 32A, 32B, 33A, and 33B can be formed using a placeholder material layer, as illustrated in the embodiments shown in Figures 4, 5, and 7A to 18C, or they can be formed without using a placeholder material layer, as illustrated in the embodiments shown in Figures 19 to 31B.Therefore, the embedded power rail 52 may be a combination of the embedded power rail conductive material layer 60 and an additional power rail conductive material 66, as mentioned above.

[0122] While this application has been specifically shown and described in relation to its preferred embodiments, those skilled in the art will understand that the aforementioned and other modifications in form and detail can be made without departing from the spirit and scope of this application. Therefore, this application is not intended to be limited to the exact forms and details described and illustrated, but rather to fall within the scope of the appended claims.

Claims

1. A first semiconductor device region including at least one semiconductor device, A second semiconductor device region including at least one other semiconductor device, An embedded power rail located between the first semiconductor device region and the second semiconductor device region, wherein a first portion of the embedded power rail having a first height exists in a gate cut trench, and a second portion of the embedded power rail having a second height greater than the first height exists in a source / drain cut trench, At least, a conductive contact structure that directly contacts the source / drain region of at least one semiconductor device located in the first semiconductor device region and the second portion of the embedded power rail located in the source / drain cut trench, and A semiconductor structure comprising the features described above.

2. The semiconductor structure according to claim 1, wherein the conductive contact structure further directly contacts the source / drain region of at least one other semiconductor device located in the second semiconductor device region.

3. The semiconductor structure according to claim 1, further comprising another conductive contact structure that directly contacts the source / drain region of at least one other semiconductor device located in the second semiconductor device region.

4. The semiconductor structure according to claim 1, wherein the first portion and the second portion of the embedded power rail are made of a single conductive power rail material.

5. The semiconductor structure according to claim 1, wherein the second portion of the embedded power rail is composed of an embedded power rail conductive material layer and an additional embedded power rail conductive material, and the first portion of the embedded power rail is composed of only the embedded power rail conductive material layer.

6. The semiconductor structure according to claim 5, wherein the embedded power rail conductive material layer and the additional embedded power rail conductive material are composed of conductive power rail materials of different compositions.

7. The semiconductor structure according to claim 1, wherein the first portion of the embedded power rail is located entirely below the uppermost surface of the shallow trench separation structure, and the second portion of the embedded power rail has an upper portion that extends above the uppermost surface of the shallow trench separation structure.

8. The semiconductor structure according to any one of claims 1 to 7, wherein the at least one semiconductor device present in the first semiconductor device region includes a nanosheet-containing device, a finFET-containing semiconductor device, a semiconductor nanowire-containing device, or at least one planar semiconductor device, and the at least one other semiconductor device present in the second semiconductor device region includes a nanosheet-containing device, a finFET-containing semiconductor device, a semiconductor nanowire-containing device, or a planar semiconductor device.

9. The at least one semiconductor device in the first semiconductor device region includes a first composite film device, the at least one other semiconductor device in the second semiconductor device region includes a second composite film device, the first composite film device includes a first nanosheet device and a second nanosheet device, the first nanosheet device is located on the first surface of the first dielectric pillar, the second nanosheet device is located on the second surface of the first dielectric pillar, and the first surface of the first dielectric pillar is the first dielectric pillar The semiconductor structure according to claim 8, wherein the second composite film device comprises a third nanosheet device and a fourth nanosheet device, the third nanosheet device is located on the first face of the second dielectric pillar, the fourth nanosheet device is located on the second face of the second dielectric pillar, the first face of the second dielectric pillar is located on the opposite side of the second face of the second dielectric pillar, and the second nanosheet device of the first composite film device faces the third nanosheet device of the second composite film device.

10. A first semiconductor device region including at least one semiconductor device, A second semiconductor device region including at least one other semiconductor device, An embedded power rail located between the first semiconductor device region and the second semiconductor device region, wherein a first portion of the embedded power rail having a first height exists in a gate cut trench, and a second portion of the embedded power rail having a second height greater than the first height exists in a source / drain cut trench, A first conductive contact structure that directly contacts the source / drain region of at least one semiconductor device located in the first semiconductor device region, but does not directly contact the second portion of the embedded power rail, and A second conductive contact structure that directly contacts the source / drain region of at least one other semiconductor device in the second semiconductor device region, but does not directly contact the second portion of the embedded power rail, and A semiconductor structure comprising the features described above.

11. The semiconductor structure according to claim 10, wherein the first portion of the embedded power rail and the second portion of the embedded power rail are made of a single conductive power rail material.

12. The semiconductor structure according to claim 10, wherein the second portion of the embedded power rail is composed of an embedded power rail conductive material layer and an additional embedded power rail conductive material, and the first portion of the embedded power rail is composed of only the embedded power rail conductive material layer.

13. The semiconductor structure according to claim 12, wherein the embedded power rail conductive material layer and the additional embedded power rail conductive material are composed of conductive power rail materials of different compositions.

14. The semiconductor structure according to claim 10, wherein the first portion of the embedded power rail is located entirely below the uppermost surface of the shallow trench separation structure, and the second portion of the embedded power rail has an upper portion that extends above the uppermost surface of the shallow trench separation structure.

15. The semiconductor structure according to any one of claims 10 to 14, wherein the at least one semiconductor device present in the first semiconductor device region includes a nanosheet-containing device, a finFET-containing semiconductor device, a semiconductor nanowire-containing device, or at least one planar semiconductor device, and the at least one other semiconductor device present in the second semiconductor device region includes a nanosheet-containing device, a finFET-containing semiconductor device, a semiconductor nanowire semiconductor device, or a planar semiconductor device.

16. A first semiconductor device region including at least one semiconductor device, A second semiconductor device region including at least one other semiconductor device, An embedded power rail located between the first semiconductor device region and the second semiconductor device region, wherein a first portion of the embedded power rail having a first height exists in a gate cut trench, and a second portion of the embedded power rail having a second height greater than the first height exists in a source / drain cut trench, A conductive contact structure that directly contacts the second portion of the embedded power rail located in the source / drain cut trench, but does not directly contact the source / drain region located in the first semiconductor device region, or the source / drain region located in the second semiconductor device region. A semiconductor structure comprising the features described above.

17. The semiconductor structure according to claim 16, wherein the first portion of the embedded power rail and the second portion of the embedded power rail are made of a single conductive power rail material.

18. The semiconductor structure according to claim 16, wherein the second portion of the embedded power rail is composed of an embedded power rail conductive material layer and an additional embedded power rail conductive material, and the first portion of the embedded power rail is composed of only the embedded power rail conductive material layer.

19. The semiconductor structure according to claim 16, wherein the first portion of the embedded power rail is located entirely below the uppermost surface of the shallow trench separation structure, and the second portion of the embedded power rail has an upper portion that extends above the uppermost surface of the shallow trench separation structure.

20. The semiconductor structure according to any one of claims 16 to 19, wherein the at least one semiconductor device present in the first semiconductor device region includes a nanosheet-containing device, a finFET-containing semiconductor device, a semiconductor nanowire-containing device, or at least one planar semiconductor device, and the at least one other semiconductor device present in the second semiconductor device region includes a nanosheet-containing device, a finFET-containing semiconductor device, a semiconductor nanowire semiconductor device, or a planar semiconductor device.

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