Semiconductor structure (embedded power rail with robust connection to wrap-around contact)

Abstract

To provide a buried power rail contact structure that mitigates parasitic capacitance between a functional gate structure and contact structures (i.e., a buried power rail contact structure and a source / drain contact structure).SOLUTION: A buried power rail contact structure is provided that wraps around a source / drain region of a first field effect transistor (FET), contacts a surface of a buried power rail, and has a reduced height compared to the height of a neighboring source / drain contact structure that contacts a surface of a source / drain region of a second FET. Both the buried power rail contact structure and the source / drain contact structure have a negative taper shape, i.e., each of the buried power rail contact structure and the source / drain contact structure has outermost sidewalls that slope outward from a topmost surface of the contact structure to a bottommost surface of the contact structure.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application relates to semiconductor technology, and more particularly, to a semiconductor structure including an embedded power rail contact structure that surrounds the source / drain regions of a first field effect transistor, contacts the surface of the embedded power rail, and has a reduced height compared to the height of adjacent source / drain contact structures.

Background Art

[0002] When forming a structure including a plurality of complementary metal oxide semiconductor (CMOS) devices, such as an integrated circuit, standard cells can be used as the basic units for designing and manufacturing the integrated circuit. Standard cells can be used to form one or more functional circuits, and each standard cell can have the same footprint (e.g., can have a standard footprint). Using standard cells when designing complex circuits and components reduces design and manufacturing costs.

[0003] In use, each standard cell of a semiconductor device requires power input (Vdd) and ground (Vss) connections. To supply power to its various components, each standard cell is generally connected to a power rail that is electrically connected to the active layer of the standard cell to provide power (Vdd). In some cases, multiple power rails can be provided to each standard cell to provide power (Vdd) and ground (Vss), respectively.

[0004] Conventional power rails are formed at the wiring process (BEOL) level. To improve scale and reduce the complexity of signal line routing, one approach is to move the power rails away from the BEOL and form them beneath the active device. One typical structure is an embedded power rail, typically incorporated into the shallow trench isolation structure of a semiconductor device. The embedded power rail connects to the source / drain region of a field-effect transistor (FET) using a via-embedded power rail (VBPR) contact structure. Conventional VBPR contact structures are in close proximity to source / drain contact structures that contact the source / drain region of an adjacent FET. The proximity between the VBPR contact structure and the source / drain contact structure provides an increase in parasitic capacitance between the functional gate structure and the contact structure. Therefore, there is a need to provide an embedded power rail contact structure (i.e., an embedded power rail contact structure and source / drain contact structure) that reduces the parasitic capacitance between the functional gate structure and the contact structure. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] There is a need to provide an embedded power rail contact structure (i.e., an embedded power rail contact structure and a source / drain contact structure) that reduces parasitic capacitance between the functional gate structure and the contact structure. [Means for solving the problem]

[0006] An embedded power rail contact structure is provided that encloses the source / drain region of a first field-effect transistor (FET), contacts the surface of the embedded power rail, and has a reduced height compared to the height of an adjacent source / drain contact structure that contacts the surface of the source / drain region of a second FET. Both the embedded power rail contact structure and the source / drain contact structure have a negative tapered shape, i.e., each of the embedded power rail contact structure and the source / drain contact structure has an outermost wall that slopes outward from the top surface of the contact structure to the bottom surface of the contact structure. Such a contact structure reduces parasitic capacitance between the functional gate structure (i.e., the components of the FET) and the contact structure.

[0007] In one embodiment of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure comprises a first functional gate structure having a first source / drain region and located in a first active area of ​​a semiconductor substrate, and a second functional gate structure having a second source / drain region and located in a second active area of ​​the semiconductor substrate. The shallow trench isolation structure separates the first active area of ​​the semiconductor substrate from the second active area of ​​the semiconductor substrate. An embedded power rail is located between the first active region and the second active region, below the uppermost surface of the shallow trench isolation structure. There is an embedded power rail contact structure having a negative tapered shape that contacts the embedded power rail and the first source / drain region. There is also a source / drain contact structure having a negative tapered shape that contacts the second source / drain region, wherein the embedded power rail contact structure has an uppermost surface located below and perpendicularly offset from the uppermost surface of the source / drain contact structure.

[0008] In another embodiment of the present application, a method for forming a semiconductor structure is provided. In one embodiment, the method comprises the step of forming at least a contact conductor material layer that contacts the physically exposed surfaces of the source / drain regions of the first and second functional gate structures, and the physically exposed surfaces of the embedded power rail located in the region between the first and second functional gate structures. The contact conductor material layer is then patterned using subtractive metal etching to provide a predecessor embedded power rail contact structure and a source / drain contact structure. The predecessor embedded power rail contact structure is subsequently etched to provide an embedded power rail contact structure having a reduced height compared to the height of the source / drain contact structure. [Brief explanation of the drawing]

[0009] [Figure 1] This diagram illustrates a layout in which multiple gate structures extend over a portion of a pair of nanosheet stacks, including cutting lines XX and YY, used in this application to illustrate various cross-sectional views of the exemplary semiconductor structure of this application.

[0010] [Figure 2A] Figure 1 is a cross-sectional view through XX of an exemplary structure that may be employed in one embodiment of the present invention, the exemplary structure comprising adjacent pairs of material stacks located on the surface of a semiconductor substrate, shallow trench isolation structures that separate the active areas of the semiconductor substrate containing each material stack from each other, and embedded power rails located within the shallow trench isolation structures, each material stack comprising alternating sacrificial semiconductor material layers and semiconductor channel material layers. [Figure 2B]Figure 1 is a cross-sectional view through YY of an exemplary structure that may be employed in one embodiment of the present invention, the exemplary structure comprising adjacent pairs of material stacks located on the surface of a semiconductor substrate, shallow trench isolation structures that separate the active areas of the semiconductor substrate containing each material stack from each other, and embedded power rails located within the shallow trench isolation structures, each material stack comprising alternating sacrificial semiconductor material layers and semiconductor channel material layers.

[0011] [Figure 3A] Figure 2A shows a cross-sectional view of an exemplary structure after forming multiple sacrificial gate structures on the physically exposed surfaces of each material stack. [Figure 3B] Figure 2B shows a cross-sectional view of an exemplary structure after multiple sacrificial gate structures have been formed on the physically exposed surfaces of each material stack.

[0012] [Figure 4A] Figure 3A shows a cross-sectional view of an exemplary structure after each material stack has been converted into a nanosheet material stack containing alternating sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets, each sacrificial semiconductor material nanosheet has been recessed to form gaps, internal spacers have been formed within each gap, source / drain regions have been formed on each side of the sacrificial gate structure, and interlayer dielectric material has been formed on each source / drain region. [Figure 4B] Figure 4B shows a cross-sectional view of an exemplary structure after each material stack has been converted into a nanosheet material stack containing alternating sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets, each sacrificial semiconductor material nanosheet has been reset to form gaps, internal spacers have been formed within each gap, source / drain regions have been formed on each side of the sacrificial gate structure, and interlayer dielectric material has been formed on each source / drain region.

[0013] [Figure 5A]A cross-sectional view of an exemplary structure shown in FIG. 4A after removing each sacrificial gate structure to expose each nanosheet material stack, removing each recessed sacrificial semiconductor material nanosheet to form a gate cavity and suspend each semiconductor channel material nanosheet, and forming a functional gate structure in the volume of the gate cavity. [Figure 5B] A cross-sectional view of an exemplary structure shown in FIG. 4B after removing each sacrificial gate structure to expose each nanosheet material stack, removing each recessed sacrificial semiconductor material nanosheet to form a gate cavity and suspend each semiconductor channel material nanosheet, and forming a functional gate structure in the volume of the gate cavity.

[0014] [Figure 6A] A cross-sectional view of an exemplary structure shown in FIG. 5A after removing the upper portion of the interlayer dielectric material layer and the shallow trench isolation structure to expose the embedded power rail. [Figure 6B] A cross-sectional view of an exemplary structure shown in FIG. 5B after removing the upper portion of the interlayer dielectric material layer and the shallow trench isolation structure to expose the embedded power rail.

[0015] [Figure 7A] A cross-sectional view of an exemplary structure shown in FIG. 6A after at least forming a contact conductor material layer that contacts the physically exposed surfaces of each source / drain region and the physically exposed surface of the embedded power rail. [Figure 7B] A cross-sectional view of an exemplary structure shown in FIG. 6B after at least forming a contact conductor material layer that contacts the physically exposed surfaces of each source / drain region and the physically exposed surface of the embedded power rail.

[0016] [Figure 8A] A cross-sectional view of an exemplary structure shown in FIG. 7A after patterning the contact conductor material layer to provide a precursor embedded power contact structure and a source / drain contact structure. [Figure 8B] A cross-sectional view of an exemplary structure shown in FIG. 7B after patterning a contact conductor material layer to provide a front-end embedded power contact structure and a source / drain contact structure.

[0017] [Figure 9A] A cross-sectional view of an exemplary structure shown in FIG. 8A after forming another interlayer dielectric material layer. [Figure 9B] A cross-sectional view of an exemplary structure shown in FIG. 8B after forming another interlayer dielectric material layer.

[0018] [Figure 10A] A cross-sectional view of an exemplary structure shown in FIG. 9A after recessing a front-end embedded power rail contact structure (without recessing the source / drain contact structure) to provide an embedded power rail contact structure, and the embedded power rail contact structure has a reduced height compared to the height of the source / drain contact structure. [Figure 10B] A cross-sectional view of an exemplary structure shown in FIG. 9B after recessing a front-end embedded power rail contact structure (without recessing the source / drain contact structure) to provide an embedded power rail contact structure, and the embedded power rail contact structure has a reduced height compared to the height of the source / drain contact structure.

[0019] [Figure 11A] A cross-sectional view of an exemplary structure shown in FIG. 10A after forming an interconnect structure, and the interconnect structure includes a conductive structure incorporated in an interconnect dielectric material layer, and one of the conductive structures contacts the surface of the source / drain contact structure. [Figure 11B] A cross-sectional view of an exemplary structure shown in FIG. 10B after forming an interconnect structure, and the interconnect structure includes a conductive structure incorporated in an interconnect dielectric material layer, and one of the conductive structures contacts the surface of the source / drain contact structure. [Modes for carrying out the invention]

[0020] Next, the present application will be described in more detail by reference to the following discussion and the drawings accompanying it. Note that the drawings of the present application are provided for illustrative purposes only and are therefore not drawn to scale. Also note that similar corresponding elements are referred to by the same reference number.

[0021] The following description includes a great deal of specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, those skilled in the art will understand that the various embodiments of the present application can be carried out without these specific details. In other cases, known structures or processing steps are not described in detail in order to avoid obscuring the present application.

[0022] When an element, such as a layer, region, or substrate, is described as being "on" or "over" another element, it will be understood that it may be directly on the other element, or there may be an intervening element. In contrast, when an element is described as being "directly on" or "directly over" another element, there is no intervening element. When an element is described as being "below" or "below" another element, it will also be understood that it may be immediately below the other element, or there may be an intervening element. In contrast, when an element is described as being "immediately below" or "immediately below" another element, there is no intervening element.

[0023] Referring first to Figure 1, a diagram is provided showing a layout including multiple gate structures GS extending over a portion of a pair of semiconductor nanosheets NS. The semiconductor nanosheets NS are employed as semiconductor channel material structures. Figure 1 includes cutting lines XX and YY used in the present application to illustrate various cross-sectional views of the exemplary semiconductor structure of the present application. Cutting line XX passes through one of the nanosheet stacks, and cutting line YY is located in a region situated between two adjacent gate structures GS.

[0024] While semiconductor nanosheets NS are described and shown in this application, the application operates equally well when other types of semiconductor channel material structures are employed. Exemplary semiconductor channel material structures that may be employed in this application may include semiconductor nanosheets (e.g., including vertically stacked semiconductor channel material nanosheets), semiconductor nanowires (e.g., including vertically stacked semiconductor nanowires), semiconductor fins, or any other similar semiconductor channel material structures. Semiconductor channel material structures include, for example, silicon (Si), silicon germanium (SiGe) alloys, silicon germanium carbide (SiGeC) alloys, germanium (Ge), III / V compound semiconductors, II / VI compound semiconductors, or multilayer stacks containing at least two types of semiconductor materials (e.g., multilayer stacks of Si and SiGe). The application allows operation when the semiconductor channel material structure is on top of a semiconductor substrate.

[0025] When semiconductor nanosheets are used, a nanosheet device is provided comprising at least one semiconductor nanosheet and a functional gate structure formed on the physically exposed surface of at least one semiconductor nanosheet. When semiconductor fins are used, a finFET device is provided comprising at least one semiconductor fin and a functional gate structure formed on the physically exposed surface of at least one semiconductor fin. When semiconductor nanowires are used, a semiconductor nanowire device is provided comprising at least one semiconductor nanowire and a functional gate structure formed on the physically exposed surface of at least one semiconductor wire. When a semiconductor substrate is used as a semiconductor channel structure, a planar semiconductor device is provided comprising a functional gate structure located on the semiconductor material surface of the semiconductor substrate.

[0026] Referring here to Figures 2A and 2B, cross-sectional views are shown through XX and YY shown in Figure 1, respectively, of an exemplary structure that may be employed in one embodiment of the present application. The exemplary structure includes adjacent pairs of material stacks MS1 and MS2 located on the surface of a semiconductor substrate 10. MS1 represents a first material stack, and MS2 represents a second material stack. Although two material stacks are described and shown in the present application, the present application is not limited to using only two material stacks. Two material stacks represent the minimum number of material stacks that may be employed in the present application.

[0027] Each of the first material stack MS1 and the second material stack MS2 is located in the active area of ​​the semiconductor substrate 10, and each active area of ​​the semiconductor substrate 10 represents a different device region. Each of the first material stack MS1 and the second material stack MS2 contains alternating sacrificial semiconductor material layers 14 and semiconductor channel material layers 16. The number of sacrificial semiconductor material layers 14 and semiconductor channel material layers 16 in each of the first material stack MS1 and the second material stack MS2 is the same. That is, each of the first material stack MS1 and the second material stack MS2 contains n sacrificial semiconductor layers 14 and n semiconductor channel material layers 16, where n is an integer starting from 1. As an example, each of the first material stack MS1 and the second material stack MS2 contains three sacrificial semiconductor material layers 14 and three semiconductor channel material layers 16.

[0028] In some embodiments of the present application, as shown in Figures 2A and 2B, optional placeholder material layers 12 may be located between the first material stack MS1 and the first active area of ​​the semiconductor substrate 10, and between the second material stack MS2 and the second active area of ​​the semiconductor substrate 10, respectively. In other embodiments, the optional placeholder material layers 12 may be omitted.

[0029] The exemplary structures shown in Figures 2A and 2B further include a shallow trench isolation (SIT) structure 18 that separates a first active area of ​​the semiconductor substrate 10 containing a first material stack MS1 from a second active area of ​​the semiconductor substrate 10 containing a second material MS2. The embedded power rail 22 is located within the shallow trench isolation structure 18 that separates the first active area of ​​the semiconductor substrate 10 containing the first material stack MS1 from a second active area of ​​the semiconductor substrate 10 containing the second material MS2.

[0030] In some embodiments, protective spacers 20 protecting the first and second areas from damage during further processing may be located along the side walls of a trench that includes an embedded power rail 22 and a shallow trench isolation structure 18 that separates the first active area of ​​the semiconductor substrate 10, including the first material stack MS1 (or second material stack MS2), from the embedded power rail 22. As shown in Figure 2B, the protective spacers 20 have a height that extends above the top surfaces of both the semiconductor substrate 10 and the shallow trench isolation structure 18 that separates the first active area of ​​the semiconductor substrate 10, including the first material stack MS1 (or second material stack MS2), from the embedded power rail 22. As further shown in Figure 2B, the protective spacers 20 may be located above the bottom of the side walls of the first material stack MS1 and above the bottom of the side walls of the second material stack MS2.

[0031] The semiconductor substrate 10 may consist of one of the semiconductor materials mentioned above for semiconductor channel material structures. In one embodiment (as illustrated in the drawings of this application), the semiconductor substrate as a whole consists of at least one type of semiconductor material. In such an embodiment, the semiconductor substrate 10 may be referred to as a bulk semiconductor substrate. In other embodiments (not shown in the drawings of this application), the semiconductor substrate 10 may consist of a first semiconductor material layer, an embedded insulating layer such as silicon dioxide or boron nitride or a combination thereof, and an upper semiconductor material layer. In such an embodiment, the semiconductor substrate 10 may be referred to as an insulator-on-semiconductor substrate.

[0032] The optional placeholder material layer 12 may consist of a semiconductor material compositionally different from the upper semiconductor material portion of the semiconductor substrate 10, as well as alternating sacrificial semiconductor material layers 14 and semiconductor channel material layers 16 present in the first material stack MS1 and the second material stack MS2, respectively. In one example, when the upper semiconductor material portions of the semiconductor substrate 10 and the semiconductor channel material layer 16 are composed of silicon, the sacrificial semiconductor material layer 14 may consist of a silicon-germanium alloy having a first germanium content (e.g., 30 atomic percent germanium), and the optional placeholder material layer 12 may consist of a silicon-germanium alloy having a second germanium content different from the first germanium content (e.g., 60 atomic percent germanium).

[0033] Each sacrificial semiconductor material layer 14 in the first material stack MS1 and the second material stack MS2 is composed of a first semiconductor material, while each semiconductor channel material layer 16 in the first material stack MS1 and the second material stack MS2 is composed of a second semiconductor material that is compositionally different from the first semiconductor material. In some embodiments, the second semiconductor material providing each semiconductor channel material layer 16 in the first material stack MS1 and the second material stack MS2 is a semiconductor material capable of providing high channel mobility for an n-type FET device. In other embodiments, the second semiconductor material providing each semiconductor channel material layer 16 in the first material stack MS1 and the second material stack MS2 is a semiconductor material capable of providing high channel mobility for a p-type FET device.

[0034] The first semiconductor material providing each sacrificial semiconductor material layer 14 in the first material stack MS1 and the second material stack MS2, and the second semiconductor material providing each semiconductor channel material layer 16 in the first material stack MS1 and the second material stack MS2, may include one of the semiconductor materials mentioned above for semiconductor channel material structures. In this application, the first semiconductor material providing each sacrificial semiconductor material layer 14 may be compositionally identical to or compositionally different from at least the top semiconductor material portion of the semiconductor substrate 10. When an optional placeholder material layer 12 is present, the first semiconductor material providing each sacrificial semiconductor material layer 14 is compositionally different from the optional placeholder material layer 12. Typically, the first semiconductor material providing each sacrificial semiconductor material layer 14 is compositionally different to at least the top semiconductor material portion of the semiconductor substrate 10. The second semiconductor material providing each semiconductor channel material layer 16 may be compositionally identical to or compositionally different from at least the top semiconductor material portion of the semiconductor substrate 10. When an optional placeholder material layer 12 exists, the second semiconductor material providing each semiconductor channel material layer 16 is compositionally different from the optional placeholder material layer 12. Typically, the second semiconductor material providing each semiconductor channel material layer 16 is compositionally identical to at least the top semiconductor material portion of the semiconductor substrate 10. In one example, the semiconductor substrate 10 is composed of silicon, the first semiconductor material providing each sacrificial semiconductor material layer 14 is composed of a silicon-germanium alloy, and the second semiconductor material providing each semiconductor channel material layer 16 is composed of silicon. Other combinations of semiconductor materials are possible, as long as the first semiconductor material providing each sacrificial semiconductor material layer 14 is compositionally different from the second semiconductor material providing each semiconductor channel material layer 16.

[0035] The shallow trench isolation structure 18 may be composed of a trench dielectric material such as silicon dioxide, silicon nitride, or silicon oxynitride. In some embodiments (not shown in the drawings of this application), a thin dielectric liner (e.g., a silicon nitride liner) may be formed along the side walls and bottom surface of the STI structure 18.

[0036] The protective spacer 20 may be composed of any dielectric spacer material that is compositionally different from the trench dielectric material. The dielectric spacer material that provides the protective spacer 20 may include, but is not limited to, silicon nitride-based dielectric materials such as silicon nitride, silicon nitride-boron-carbon, or dielectrics containing atoms of Si, O, C, and N, silicon carbide-based dielectric materials such as silicon carbide, or dielectrics containing atoms of Si, C, and O, or any other dielectric material such as silicon dioxide.

[0037] The embedded power rail 22 is composed of an embedded power rail conductive material. Exemplary embedded power rail conductive materials that may be used to provide the embedded power rail 22 include, but are not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd), and a thin metal adhesive layer (TiN, TaN, etc.) is typically formed before the conductive metal deposition. For clarity, the metal adhesive layer is not shown separately in the drawings of this application.

[0038] The exemplary structures shown in Figures 2A and 2B can be formed using techniques known to those skilled in the art. In one example, the exemplary structures shown in Figures 2A and 2B can be formed by first forming an optional placeholder material layer 12 and a first material stack MS1 and a second material stack MS2 on the surface of a semiconductor substrate 10. The formation of the optional placeholder material layer 12 and the first material stack MS1 and second material stack MS2 may involve first epitaxially growing a blanket layer of the optional placeholder material, and then growing alternating blanket layers of sacrificial semiconductor material and semiconductor channel material. In one example, the blanket layer of the optional placeholder material, as well as the alternating blanket layers of sacrificial semiconductor material and semiconductor channel material, can be deposited using epitaxial growth. The blanket layers of an optional placeholder material and the alternating blanket layers of sacrificial semiconductor material and semiconductor channel material are then patterned by lithography and etching to form an optional placeholder material layer 12 and a first material stack MS1 and a second material stack MS2. The etching passes through the blanket layers of the optional placeholder material, the alternating blanket layers of sacrificial semiconductor material and semiconductor channel material, reaching the upper portion of the semiconductor substrate 10, and forms an STI trench at least between the active area containing the first material stack MS1 and the active area containing the second material stack MS2.

[0039] Next, protective spacers 20 are formed within or along the sidewalls of the STI trench, which is located between the first active area containing the first material stack M1 and the second active area containing the second material stack MS2. The protective spacers 20 can be formed by depositing a spacer dielectric material and subsequently etching the spacer. The protective spacers 20 may be pillars in the shape shown in Figure 2B. The deposition of the spacer dielectric material may include, but is not limited to, chemical vapor deposition (CVD), plasma-extended chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Spacer etching may include reactive ion etching (RIE). Unwanted protective spacers 20 can be removed by lithography and etching processes.

[0040] The remaining volume of the STI trench located between the first material stack M1 and the second material stack MS2 and the area laterally adjacent to the first material stack MS1 and the second material stack MS2 is then filled with trench dielectric material. A planarization process (e.g., chemical mechanical polishing (CMP)) or a densification process, or a combination thereof, may be performed after the trench filling process. The trench dielectric material located between the first material stack M1 and the second material stack MS2 is then reduced below the top surface of the semiconductor substrate 10.

[0041] The embedded power rail 22 is then formed on recessed trench dielectric material located between a first active area containing a first material stack M1 and a second active area containing a second material stack MS2. The formation of the embedded power rail 22 includes the deposition of the embedded power rail conductive material and subsequent recess etching. Exemplary deposition processes that may be used to form the embedded power rail conductive material include, but are not limited to, CVD, PECVD, PVD, sputtering, or plating. Recess etching reduces the height of the deposited embedded power rail conductive material, thus providing an embedded power rail 22 having a top surface located below the top surface of the semiconductor substrate 10. Additional trench dielectric material is then formed on the embedded power rail 22, providing the structure shown in Figure 2B. The STI structure 18 formed between the first active area and the second active area of ​​the semiconductor substrate 10 has a bottom and an top, with the embedded power rail 22 sandwiched between them. In some embodiments, the bottom surface of the embedded power rail 22 may be deeper than the STI structure 18 and may be located on the semiconductor substrate 10 (not shown). In this case, an additional dielectric liner is required to separate the embedded power rail 22 from the semiconductor substrate 10.

[0042] Referring here to Figures 3A and 3B, exemplary structures shown in Figures 2A and 2B are shown after multiple sacrificial gate structures 24 have been formed on the physically exposed surfaces of each material stack (i.e., the first material stack MS1 and the second material stack MS2). In exemplary embodiments, each sacrificial gate structure 24 is straddled over (i.e., located on the sidewalls and top surfaces of the first material stack MS1 and the second material stack MS2). As an example, three sacrificial gate structures 24 are shown. Although three sacrificial gate structures 24 are shown, the application also works when fewer than three (i.e., one or two) or more than three (i.e., four, five, six, etc.) sacrificial gate structures 24 are formed. Each sacrificial gate structure 24 may include a sacrificial gate cap 26 placed on it. Each sacrificial gate structure 24 further includes a dielectric spacer 28 located along its sidewall, the dielectric spacer 28 also located on the sidewalls of the first material stack MS1 and the second material stack MS2.

[0043] At least one sacrificial gate structure 24 can be formed by depositing blanket layers of a sacrificial gate dielectric material (e.g., silicon dioxide) and a sacrificial gate material (e.g., polysilicon or a metal). A blanket layer of a dielectric hard mask material, such as silicon nitride, used to provide a sacrificial gate cap 26, can be deposited on the sacrificial gate material. The deposition of the blanket layers of the dielectric hard mask material, sacrificial gate material and sacrificial gate dielectric material includes, but is not limited to, CVD, PECVD, PVD, ALD, or any combination of such deposition processes. After forming the blanket layers of the sacrificial gate dielectric material, sacrificial gate material and hard mask material, a patterning process (including lithography and etching) is used to convert the blanket layer of the hard mask material into a sacrificial gate cap 26 and the blanket layers of the sacrificial gate dielectric material and sacrificial gate dielectric material into sacrificial gate structures 24.

[0044] After forming the sacrificial gate structure 24, an optional placeholder material layer 12 is selectively removed to create a space at the bottom of the first material stack MS1 and the second material stack MS2. Next, dielectric spacers 28 are formed by depositing dielectric spacer material and subsequent spacer etching. The dielectric spacer material providing the dielectric spacers 28 may include silicon dioxide or silicon nitride. The dielectric spacers 28 also fill the space at the bottom of the first material stack MS1 and the second material stack MS2, forming the lower dielectric insulating layer 30. Dielectric spacers 28 formed along the opposing side walls of the first material stack MS1 and the second material stack MS2 are located on the uppermost surface of the protective spacer 20. Dielectric spacers 28 are formed on the STI structure 18 along the non-opposing side walls of the first material stack MS1 and the second material stack MS2.

[0045] Referring to Figures 4A and 4B, the exemplary structures shown in Figures 3A and 3B are obtained after each material stack (i.e., the first material stack MS1 and the second material stack MS2) is converted into nanosheet material stacks (i.e., the first nanosheet stack and the second nanosheet material stack) containing alternating sacrificial semiconductor material nanosheets 14NS and semiconductor channel material nanosheets 16NS, each sacrificial semiconductor material nanosheet 14NS is reset to form gaps (not shown), internal spacers 32 are formed in each gap, source / drain regions 34 are formed on each side of the sacrificial gate structure 24, and interlayer dielectric material 36 is formed on each source / drain region 36.

[0046] Converting each material stack (i.e., the first material stack MS1 and the second material stack MS2) into nanosheet material stacks (i.e., the first nanosheet stack and the second nanosheet material stack, each containing alternating sacrificial semiconductor material nanosheets 14NS and semiconductor channel material nanosheets 16NS) involves a patterning process that utilizes the sacrificial gate structure 24 and dielectric spacer 28 as a combined etching mask. The patterning involves an etching process that removes physically exposed portions of the first material stack MS1 and the second material stack MS2 that are not protected by the etching mask, while preserving the portions of the first material stack MS1 and the second material stack MS2 located beneath each etching mask. The preserved portions of the first material stack MS1 located beneath the etching mask are the first nanosheet stack of alternating sacrificial semiconductor material nanosheets 14NS (i.e., the remainder of each sacrificial semiconductor material layer 14) and the semiconductor channel material nanosheet 16NS (the remainder of the semiconductor channel material layer 16). The maintained portion of the second material stack MS2 located beneath the etching mask is a second nanosheet stack of alternating sacrificial semiconductor material nanosheets 14NS (i.e., the maintained portion of each sacrificial semiconductor material layer 14) and semiconductor channel material nanosheets 16NS (the remaining portion of the semiconductor channel material layer 16). Etching stops at the lower dielectric insulating layer 30 if an optional placeholder material layer 12 is used, or at the surface of the semiconductor substrate 10 if an optional placeholder material layer 12 is not used.

[0047] After defining the first and second nanosheet stacks of alternating sacrificial semiconductor material nanosheets 14NS and semiconductor channel material nanosheets 16NS, the edges of each sacrificial semiconductor material nanosheet 14NS are reset to form gaps (not shown). The resetting includes a lateral etching process. Next, an internal spacer 32 is formed in the gap created by resetting each sacrificial semiconductor material nanosheet 14NS. The formation of the internal spacer 32 includes conformal deposition of another dielectric spacer material, followed by isotropic etching. The other dielectric spacer material may be compositionally identical to or compositionally different from the dielectric spacer material providing the dielectric spacer 28.

[0048] After the formation of the internal spacer 32, the source / drain region 34 is formed. As used herein, the “source / drain” region may be either a source region or a drain region depending on the voltage applied during subsequent wiring and FET operation. The source / drain region 34 has sidewalls that are in direct physical contact with the outermost wall of each semiconductor channel material nanosheet. The source / drain region 34 is formed on the surface of the lower dielectric insulating layer 30. The source / drain region 34 contains semiconductor material and dopant. The semiconductor material providing each source / drain region 34 may include one of the semiconductor materials mentioned above for semiconductor channel material structures. The semiconductor material providing the source / drain region 34 may be compositionally identical to or compositionally different from each semiconductor channel material nanosheet 16NS. However, the semiconductor material providing the source / drain region 34 is compositionally different from each sacrificial semiconductor material nanosheet 14NS that has been removed.

[0049] The dopants present in each source / drain region 34 may be either p-type or n-type dopants. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor that causes valence electron depletion. Examples of p-type dopants, or impurities, in silicon-containing semiconductor materials include, but are not limited to, boron, aluminum, gallium, and indium. The term "n-type" refers to the addition of impurities that donate free electrons to an intrinsic semiconductor. Examples of n-type dopants, or impurities, in silicon-containing semiconductor materials include, but are not limited to, antimony, arsenic, and phosphorus. In one example, each source / drain region 34 is 4 × 10⁻⁶ 20 atoms / cm 3 ~3×10 21 atoms / cm 3 It may have the following dopant concentrations. In one example, each source / drain region 34 is composed of phosphorus-doped silicon.

[0050] Each source / drain region 34 may be formed by epitaxial growth in the presence of a dopant during the epitaxial growth process. The source / drain regions 34 grow laterally outward from each semiconductor channel material nanosheet 165NS. Recess etching may optionally be employed to reduce the height of each source / drain region 34.

[0051] After the formation of the source / drain region 34, an interlayer dielectric (ILD) material layer 36 is formed, and the ILD material layer 36 is a sacrificial ILD material layer. The ILD material layer 36 may consist of dielectric materials including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borosilicate glass (BPSG), spin-on low dielectric constant dielectric layers, chemical vapor deposition (CVD) low dielectric constant dielectric layers, or any combination thereof. The term “low dielectric constant (low-k)” as used throughout this application refers to dielectric materials having a dielectric constant less than 4.0 (unless otherwise specified, all dielectric constants referred to herein are relative to vacuum). Not shown, the ILD material layer 36 may include a multilayer structure comprising at least two different dielectric materials stacked in sequence, such as silicon nitride and silicon dioxide. The ILD material layer 36 may be formed by a deposition process such as CVD, PECVD, or spin-on coating. The planarization process may be performed after the deposition of the dielectric material that provides the ILD material layer 36. This planarization process physically exposes the top surface of each sacrificial gate structure 24, removes the top of each dielectric spacer 28, and removes any optional sacrificial gate cap 26, if present. In the source / drain region shown in Figure 4B, the top of the dielectric spacer 28 is removed to expose the upper sidewall portion of each source / drain region 34.

[0052] Referring now to Figures 5A and 5B, the exemplary structures shown in Figures 4A and 4B are obtained after removing each sacrificial gate structure 24 to expose each nanosheet material stack, removing each resetted sacrificial semiconductor material nanosheet 14NS to form a gate cavity (not shown) to suspend each semiconductor channel material nanosheet 16NS, and forming a functional gate structure 38 within the volume of the gate cavity.

[0053] The removal of the sacrificial gate structure 24 may involve one or more etching processes that are selective in removing the sacrificial gate structure 24. Removing the resetted sacrificial semiconductor material nanosheets 14NS from the nanosheet stack may be performed using etching that is selective in removing the sacrificial semiconductor material nanosheets 14NS in contrast to the semiconductor channel material nanosheets 16NS. For example, etching may be used to selectively remove SiGe sacrificial semiconductor material nanosheets in contrast to Si semiconductor channel material nanosheets.

[0054] Next, a functional gate structure 38 is formed in each gate cavity. The functional gate structure 38 includes at least a gate dielectric material layer and a gate electrode, neither of which are shown individually in the drawings of this application. In some embodiments, the functional gate structure 38 may enclose each semiconductor channel material nanosheet 16NS in a given vertical stack of suspended semiconductor channel material nanosheets 16NS. As is known, the gate dielectric material layer of the functional gate structure 38 is in direct contact with the physically exposed portion of each semiconductor channel material structure, and the gate electrode is located on the gate dielectric material layer. In some embodiments, the functional gate structure 38 includes a work function metal (WFM) layer positioned between the gate dielectric material layer and the gate electrode. In some embodiments, a gate cap 40 is located on the reduced functional gate structure 38. In other embodiments, the gate cap is omitted.

[0055] The functional gate structure 38 includes forming continuous layers of gate dielectric material and gate electrode material inside and outside each gate cavity. The continuous layer of gate dielectric material may include silicon oxide, or a dielectric material having a greater dielectric constant than silicon oxide (such dielectric materials may be referred to as high dielectric constant gate dielectric materials). Examples for describing high dielectric constant gate dielectric materials include, for example, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), and zirconium silicon oxynitride (ZrSiO4). x N y ), tantalum oxide (TaO x High dielectric constant gate dielectric materials may include metal oxides such as titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalate (Pb(Sc,Ta)O3), or lead zinc niobate (Pb(Zn,Nb)O), or combinations thereof. High dielectric constant gate dielectric materials may further include dopants such as lanthanum (La), aluminum (Al), or magnesium (Mg), or combinations thereof.

[0056] The continuous layer of gate dielectric material can be formed using a deposition process such as ALD, CVD, PECVD, or PVD. The continuous layer of gate dielectric material is a conformal layer with a thickness that can range from 1 nm to 10 nm. The continuous layer of gate dielectric material does not fill the entire gate cavity.

[0057] Electrode gate materials are not limited to these, but include tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag), or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), and tantalum carbide (TaC). X The conductive metal-containing material may include titanium carbide (TiC), aluminum titanium carbide, tungsten silide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silide, or nickel silide. The gate electrode material may be formed using a deposition process such as ALD, CVD, PECVD, PVD, plating, or sputtering. In some embodiments of the present application, reflow annealing or silicide annealing may be used after the deposition of the conductive metal-containing material has been performed.

[0058] In some embodiments, a layer of WFM may be formed on a continuous layer of gate dielectric material before forming the gate electrode material. In other embodiments, the gate electrode consists solely of WFM. A layer of WFM may be used to set the threshold voltage of the FET to a desired value. In some embodiments, a layer of WFM may be selected to achieve an n-type threshold voltage shift. As used herein, “n-type threshold voltage shift” means that the effective work function of a work function metal-containing material is shifted to the conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is in the range of 4.1 eV to 4.3 eV. Examples of such materials capable of achieving an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, a layer of WFM may be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, “threshold voltage” refers to the lowest feasible gate voltage that turns on a semiconductor device, such as a transistor, by making the device's channel conductive. As used herein, the term “p-type threshold voltage shift” refers to the shift of the effective work function of a metal-containing material to the silicon valence band in a silicon-containing material. Examples of such materials capable of achieving a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The WFM layer is a conformal layer that can be formed by conformal deposition processes such as ALD, CVD, or PECVD. The WFM layer may have a thickness in the range of 1 nm to 20 nm, but other thicknesses above or below this range may be used as desired for a particular application.

[0059] After forming a continuous layer of gate dielectric material, an optional layer of WFM, and gate electrode material, a planarization process, such as CMP, is used to remove the continuous layer of gate dielectric material, the optional layer of WFM, and gate electrode material from the outside of each gate cavity. The remaining continuous layer of gate dielectric material located inside the gate cavity may be referred to as the gate dielectric material layer, the remaining optional layer of WFM located inside the gate cavity may be referred to as the WFM layer, and the remaining gate electrode material located inside the gate cavity provides the gate electrode. When present, the gate cap 40 may be composed of a hard mask material, such as silicon dioxide or silicon nitride. The gate cap 40 may be formed by a deposition process and a subsequent planarization process.

[0060] In the exemplary embodiment shown in Figure 5A, the optional gate cap 40 has an upper surface that is coplanar with the upper surfaces of both the dielectric spacer 28 and the ILD material layer 36. In other embodiments, the functional gate structure 38 has an upper surface that is coplanar with the upper surfaces of both the dielectric spacer 28 and the ILD material layer 36.

[0061] Referring here to Figures 6A and 6B, exemplary structures shown in Figures 5A and 5B are shown after the removal of the ILD material layer 36 and the top of the STI structure 18 to expose the embedded power rail 22. The ILD material layer 36 may be removed using a first etching, and then a second etching (typically different from the first etching) may be used to remove the STI structure 18 located above the embedded power rail 22. In one example, the first etching is an isotropic etching selective in the removal of the ILD material layer 36, while the second etching is an isotropic etching selective in the resetting of the top of the STI structure 18 located on the embedded power rail 22. Note that during the second etching, the STI structure without the embedded power rail 22 is resetting as shown in Figure 6B.

[0062] Referring here to Figures 7A and 7B, exemplary structures shown in Figures 6A and 6B are illustrated after at least a contact conductor material layer 42 (including the sidewalls and top surface) has been formed that contacts the physically exposed surfaces of each source / drain region 34 and the physically exposed surfaces of the embedded power rail 22. The contact conductor material layer 42 comprises a silicide liner (not shown) such as Ti, Ni, or NiPt on the source / drain region 34, followed by an adhesive metal liner (also not shown) such as TiN, and then a low resistivity contact conductor material such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof is deposited thereafter. The contact conductor material layer 42 may be formed by any preferred deposition method, such as ALD, CVD, PVD, or plating. The contact conductor material layer 42 is formed on each gate cap (or uncapped) functional gate structure 38, dielectric spacer 28, and each source / drain region 34.

[0063] Referring here to Figures 8A and 8B, exemplary structures shown in Figures 7A and 7B are illustrated after the contact conductor material layer 42 has been patterned to provide the predecessor-embedded power rail contact structure 42B and the source / drain contact structure 42A, respectively. Patterning of the contact conductor material layer 42 includes a subtractive metal etching process in which a patterned masking layer (not shown), such as an organic planarization layer (OPL), is formed on a portion of the contact conductor material layer 42 on which the predecessor-embedded power rail contact structure 42B and the source / drain contact structure 42A are formed. The patterned masking layer may be formed by depositing a masking material layer and then patterning the deposited masking material layer by lithography and etching. With the patterned masking layer in place, selective subtractive metal etching is employed in removing the contact conductor material. This etching provides the predecessor-embedded power rail contact structure 42B and the source / drain contact structure 42A. The patterned masking layer is removed using a conventional material removal process followed by subtractive metal etching.

[0064] Each of the predecessor-embedded power rail contact structure 42B and the source / drain contact structure 42A has a negative taper shape. That is, each of the predecessor-embedded power rail contact structure 42B and the source / drain contact structure 42A has an outermost wall S1 (i.e., a first side wall and a second side wall opposite to the first side wall) that slopes outward from the top surface of the contact structure to the bottom surface of the contact structure. Furthermore, each of the predecessor-embedded power rail contact structure 42B and the source / drain contact structure 42A has an upper and a lower part, with the upper part having a width smaller than the lower part. Thus, each of the predecessor-embedded power rail contact structure 42B and the source / drain contact structure 42A has a pyramidal shape with a base (lower part) that is wider than the upper part.

[0065] As shown in Figure 8B, the predecessor embedded power rail contact structure 42B contacts the uppermost surface of the embedded power rail 22 and one outermost wall S1 of the source / drain region 34 (i.e., the first side wall and the second side wall opposite the first side wall). Therefore, the predecessor embedded power rail contact structure 42B can be referred to as a wrap-around contact structure. Landing on the uppermost surface of the embedded power rail 22, the predecessor embedded power rail contact structure 42B has a larger contact area (i.e., a larger limit dimension, CD) than conventional VBPR contact structures. The source / drain contact structure 42A contacts the outermost wall S1 (i.e., the first side wall and the second side wall opposite the first side wall) and the uppermost surface of another source / drain region. Therefore, the source / drain contact structure 42A can also be referred to as a wrap-around contact structure.

[0066] Referring here to Figures 9A and 9B, exemplary structures shown in Figures 8A and 8B, respectively, are shown after the formation of another interlayer dielectric (ILD) material layer 44. The other ILD material layer 44 may contain one of the dielectric materials mentioned above for the ILD material layer 36. The other ILD material layer 44 may be formed using one of the deposition processes mentioned above for the formation of the ILD material layer 36. For example, a planarization process such as chemical mechanical polishing (CMP) may follow the deposition of the dielectric material that provides the other dielectric material layer 44. At this point in the present application, the other ILD material layer 44 has an upper surface that is coplanar with the upper surfaces of both the predecessor embedded power rail contact structure 42B and the source / drain contact structure 42A.

[0067] Referring to Figures 10A and 10B, the exemplary structures shown in Figures 9A and 9B, respectively, are provided after the predecessor embedded power rail contact structure 42B has been reset (the source / drain contact structure 42A has not been reset) to provide the embedded power rail contact structure 42C. The embedded power rail contact structure 42C has a reduced height compared to the height of the source / drain contact structure 42A. That is, the embedded power rail contact structure 42C has a top surface that is vertically offset from and below the top surface of the source / drain contact structure 42A.

[0068] The reduction steps used to provide the exemplary structures shown in Figures 10A and 10B include a step of first forming a patterned masking layer 46, such as an organic planarization layer (OPL), on the portion of the exemplary structure that does not include the predecessor embedded power rail contact structure 42B, wherein the patterned masking layer 46 is located on top of the source / drain contact structure 42A. The patterned masking layer 46 may be formed by deposition, lithography, and etching. With the patterned masking layer 46 in place, recess metal etching, which is selective in removing the contact conductor material, is employed. This recess etching provides the embedded power rail contact structure 42C. After recess etching, the patterned masking layer 46 is removed using a conventional material removal process.

[0069] The embedded power rail contact structure 42C has a negative tapered shape. That is, the embedded power rail contact structure 42C has an outermost wall S1 (i.e., a first side wall and a second side wall opposite the first side wall) that slopes outward from the top surface of the contact structure to the bottom surface of the contact structure. Furthermore, the embedded power rail contact structure 42C has an upper and a lower part, with the upper part having a width smaller than the lower part. Thus, the embedded power rail contact structure 42C has a pyramidal shape with a base (lower part) that is wider than the upper part. As shown in Figure 10B, the embedded power rail contact structure 42C contacts the top surface of the embedded power rail 22 and one of the outermost walls S1 (i.e., a first side wall and a second side wall opposite the first side wall) of the source / drain region 34. Thus, the embedded power rail contact structure 42C can be referred to as a wrap-around contact structure. The embedded power rail contact structure 42C lands on the first portion of the embedded power rail 22, while the ILD material layer 44 lands on the second portion of the embedded power rail 22. The embedded power rail contact structure 42C, which lands on the uppermost surface of the embedded power rail 22, has a larger contact area than the conventional VBPR contact structure. The negative taper shape in both the embedded power rail contact structure 42C and the source / drain contact structure 42A, as well as the vertical misalignment between the uppermost surface of the embedded power rail contact structure 42C and the source / drain contact structure 42A, reduces the middle-of-the-line (MOL) congestion that is a problem for conventional contact structures and conventional VBPR contact structures. Furthermore, the negative taper shape in both the embedded power rail contact structure 42C and the source / drain contact structure 42A, as well as the vertical displacement between the uppermost surface of the embedded power rail contact structure 42C and the source / drain contact structure 42A, reduces parasitic capacitance between the functional gate structure and the contact structure (i.e., between the embedded power rail contact structure 42C and the source / drain contact structure 42A) of the present invention.

[0070] Referring now to Figures 11A and 11B, exemplary structures shown in Figures 10A and 10B, respectively, after the formation of the interconnect structure, the interconnect structure includes conductive structures 60 incorporated into the interconnect dielectric material layer 58, one of which contacts the surface of the source / drain contact structure 42A. The conductive structure 60 in contact with the source / drain contact structure 42A may have a lower via portion and an upper line portion, as shown in Figure 11A.

[0071] Prior to forming the interconnect structure, an additional dielectric material, typically compositionally identical to the dielectric material providing the ILD material layer 44, is formed on top of the embedded power rail contact structure 42C. In this application, the additional dielectric material formed on top of the embedded power rail contact structure 42C forms part of the ILD material layer 44. See Figures 11A and 11B. According to this application, the embedded power rail contact structure 42C is laterally surrounded and covered by the ILD material layer 44, so that the uppermost surface of the embedded power rail contact structure 42C is vertically offset from the uppermost surface of the ILD material layer 44 and is positioned below it overall, i.e., the embedded power rail contact structure 42C is entirely incorporated into the ILD material layer 44. The source / drain contact structure 42 is also laterally surrounded by the ILD material layer 44. However, unlike the embedded power rail contact structure 42C, the source / drain contact structure 42A has an uppermost surface that is coplanar with the uppermost surface of the ILD material layer 44. The conductive structure from the interconnect structure does not come into direct contact with the embedded power rail contact structure 42C.

[0072] The interconnect structures present in the BEOL are formed using techniques known to those skilled in the art. For example, the interconnect structures may be formed using single damascene or dual damascene processes. For example, an interconnect dielectric material layer 58 may be deposited first, and then at least one iteration of lithography and etching may be used to define openings (i.e., vias, lines, or via / line combinations) in the interconnect dielectric material layer 58. Next, conductive material providing each conductive structure 60, such as Cu, Co, or Ru, is formed within each opening, and a planarization process such as CMP may be used to remove any conductive material located outside the opening. The interconnect dielectric material layer 58 may include one of the dielectric materials mentioned above for the ILD material layer 36. In some embodiments, though not shown, a diffusion barrier liner composed of a diffusion barrier material such as Ta, Ti, TaN, TiN, or a combination thereof may be formed and present along the side walls and bottom surface of each conductive structure.

[0073] While this application has been specifically shown and described with reference to its preferred embodiments, those skilled in the art will understand that the above and other modifications in shape and detail can be made without departing from the spirit and scope of this application. Therefore, this application is not intended to be limited to the exact shape and detail described and shown, but rather to fall within the scope of the accompanying claims.

Claims

1. It is a semiconductor structure, A first functional gate structure having a first source / drain region and located in the first active area of ​​a semiconductor substrate, A second functional gate structure having a second source / drain region and located in the second active area of ​​the semiconductor substrate, A shallow trench isolation structure that separates the first active area of ​​the semiconductor substrate from the second active area of ​​the semiconductor substrate, A recessed power rail located between the first active area and the second active area, and below the uppermost surface of the shallow trench isolation structure, An embedded power rail contact structure having a negative taper shape and in contact with the embedded power rail and the first source / drain region, A source / drain contact structure having a negative taper shape and in contact with the second source / drain region The embedded power rail contact structure is offset vertically from the uppermost surface of the source / drain contact structure and has an uppermost surface located below the uppermost surface. Semiconductor structure.

2. The semiconductor structure according to claim 1, wherein the embedded power rail contact structure is a wrap-around contact that contacts the upper part of the outermost wall of the first source / drain region and the uppermost surface of the first source / drain region.

3. The semiconductor structure according to claim 1, wherein the source / drain contact structure is a wrap-around contact that contacts the upper part of the outermost wall of the second source / drain region and the uppermost surface of the second source / drain region.

4. The semiconductor structure according to claim 1, further comprising an interlayer dielectric material layer located laterally adjacent to the embedded power rail contact structure and situated on the embedded power rail contact structure.

5. The semiconductor structure according to claim 4, wherein the interlayer dielectric material layer is adjacent to the source / drain contact structure in the lateral direction, and the interlayer dielectric material layer has an uppermost surface that is coplanar with the uppermost surface of the source / drain contact structure.

6. The semiconductor structure according to claim 4, wherein the embedded power rail contact structure is in contact with a first portion of the embedded power rail, and the interlayer dielectric material layer is in contact with a second portion of the embedded power rail.

7. The semiconductor structure according to claim 2, further comprising a dielectric spacer that contacts the lower part of the outermost wall of the first source / drain region.

8. The semiconductor structure according to claim 3, further comprising a dielectric spacer in contact with the lower part of the outermost wall of the second source / drain region.

9. The semiconductor structure according to claim 1, further comprising a protective spacer located between the side wall of the embedded power rail and the first active area and the second active area of ​​the semiconductor substrate.

10. The semiconductor structure according to claim 9, wherein the protective spacer extends over the uppermost surface of the semiconductor substrate and has an uppermost surface that contacts the lower part of the outermost walls of both the first source / drain region and the second source / drain region.

11. The semiconductor structure according to claim 1, further comprising a lower dielectric insulating layer located beneath each of the first functional gate structure, the first source / drain region, the second functional gate structure, and the second source / drain region.

12. The semiconductor structure according to claim 1, wherein each of the first functional gate structure and the second functional gate structure is in contact with the surface of a semiconductor channel material structure.

13. The semiconductor structure according to claim 12, wherein the semiconductor channel material structure comprises at least one semiconductor channel material nanosheet, the first functional gate structure encloses the at least one semiconductor channel material nanosheet present in the first active area, and the second functional gate structure encloses the at least one semiconductor channel material nanosheet present in the second active area.

14. The semiconductor structure according to claim 1, further comprising an interconnect structure located on the first functional gate structure and the second functional gate structure.

15. The semiconductor structure according to claim 14, wherein the interconnect structure includes a conductive structure incorporated in an interconnect dielectric material layer, and the conductive structure is in contact with the surface of the source / drain contact structure.

16. The semiconductor structure according to any one of claims 1 to 15, wherein both the embedded power rail contact structure and the source / drain contact structure have an upper part having a first width and a lower part having a second width, the first width being smaller than the second width.

17. It is a semiconductor structure, A first functional gate structure having a first source / drain region and located in the first active area of ​​a semiconductor substrate, A second functional gate structure having a second source / drain region and located in the second active area of ​​the semiconductor substrate, A shallow trench isolation structure that separates the first active area of ​​the semiconductor substrate from the second active area of ​​the semiconductor substrate, A recessed power rail located between the first active area and the second active area, and below the uppermost surface of the shallow trench isolation structure, The embedded power rail and the embedded power rail contact structure that contacts the first source / drain region, The source / drain contact structure that contacts the second source / drain region and A semiconductor structure comprising, wherein both the embedded power rail contact structure and the source / drain contact structure are pyramidal in shape, and the embedded power rail contact structure has an uppermost surface that is vertically offset from the uppermost surface of the source / drain contact structure and is located below the uppermost surface.

18. The semiconductor structure according to claim 17, wherein the embedded power rail contact structure is a wrap-around contact that contacts the upper part of the outermost wall of the first source / drain region and the uppermost surface of the first source / drain region.

19. The semiconductor structure according to claim 17, wherein the source / drain contact structure is a wrap-around contact that contacts the upper part of the outermost wall of the second source / drain region and the uppermost surface of the second source / drain region.

20. The semiconductor structure according to any one of claims 17 to 19, further comprising an interlayer dielectric material layer located laterally adjacent to the embedded power rail contact structure, located on the embedded power rail contact structure, and located laterally adjacent to the source / drain contact structure, wherein the embedded power rail contact structure is entirely incorporated into the interlayer dielectric material layer, and the interlayer dielectric material layer has an uppermost surface that is coplanar with the uppermost surface of the source / drain contact structure.

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