Routing Instructions in Microprocessors

Abstract

A computer system, processor, programming instructions or method, or combination thereof, for balancing workload of processing pipelines including an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, at least a first processing pipeline and a second processing pipeline capable of executing a first instruction type, and an instruction decode unit for decoding instructions to determine whether the first processing pipeline or the second processing pipeline executes the first instruction type. The processor is configured to: calculate at least one of a workload group consisting of a first processing pipeline workload, a second processing pipeline workload, and combinations thereof; and select the first processing pipeline or the second processing pipeline to execute the first instruction type based on the at least one workload group.

Description

Technical Field

[0001] The present invention generally relates to data processing systems, processors, and processor architectures, and methods for processing large data width instructions for execution on high density math execution units such as, for example, one or more matrix multiply-add (MMA) units.

Background Art

[0002] Currently, processors used in data processing systems process multiple instructions at once, and often those instructions are not processed in order. In modern computer architectures, there are several known ways to design computers to execute multiple instructions at once or at least within the same time frame. For example, as one design to improve throughput, some provide multiple execution slices within a processor core to process multiple instruction threads simultaneously, where the threads share certain resources of the processor core. An execution slice may refer to multiple data processing hardware pipelines connected in parallel within a processor to process multiple instructions simultaneously. Pipelining involves processing instructions step by step, and a multi-stage pipeline maintains the same throughput as a single-stage pipeline for multi-cycle instructions. Multiple execution slices may be used as part of simultaneous multi-threading within a processor core.

[0003] Various pipeline stages may include an "instruction fetch" stage where instructions are fetched from memory. In the "decode" stage, instructions are decoded into different control bits. These control bits generally specify (i) the type of functional unit (e.g., execution unit) to perform the operation specified by the instruction, (ii) the source operands for the operation, and (iii) the destination of the result of the operation. In the "dispatch" stage, the decoded instruction is dispatched to an issue queue (ISQ) where the instruction awaits data and an available execution unit. Instructions in the issue queue are typically issued to execution units in the "execution" stage. The "execution" stage processes the operation specified by the instruction. Performing the operation specified by the instruction typically involves accepting data, e.g., one or more operands, and producing one or more results. To hold data or information for the execution unit, or both, there is usually a register file associated with the execution unit or the issue queue or both. The register file typically contains information read from or written to entries or locations within the register file, or both.

[0004] In processors with multiple execution slices or pipelines, during computation, the workload of one or more execution units may be higher, or even much higher, than the workload handled by other execution units. In other words, some execution units may be overloaded with instructions while others are lightly loaded. It is advantageous if the workloads performed by different execution units are better balanced, for example, more evenly distributed among them, which may result in improved processor performance, reduced latency, or both. [Overview of the project]

[0005] This summary of the disclosure is provided to aid in understanding computer systems, computer architecture structures, processors, processor architecture structures, register files including wide data-width (accumulator) register files, and methods for balancing the workload of execution units within a processor, and is not intended to limit the disclosure or the invention. This disclosure is directed to those skilled in the art. It should be understood that various aspects and features of this disclosure may be used advantageously individually in some embodiments and in combination with other aspects and features of this disclosure in other embodiments. Accordingly, modifications and alterations can be made to computer systems, architecture structures, processors, processor architecture structures, register files, or methods of operation thereof, or combinations thereof, to achieve different effects.

[0006] Computer systems, processors, or methods, or combinations thereof for processing information are disclosed for balancing the workload of one or more execution units within a system, a processor, or both, and in one embodiment, the focus is on balancing the workload between processor pipelines, for example, between a fixed-point (FX) pipeline and a simple (SX) pipeline within a processor. In one embodiment, the system, processor, or method, or combination thereof, focuses on reducing the workload of a first execution pipeline by routing instructions to other execution units within a system, a processor, or both. In one or more embodiments, a processor for processing information includes an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first and a second processing pipeline of the at least two processing pipelines are capable of executing a first instruction type, and an instruction decoding unit for decoding an instruction to determine whether the first or second processing pipeline executes the first instruction type. In one or more embodiments, the processor is configured to calculate at least one of a workload group consisting of a first processing pipeline workload, a second processing pipeline workload, and a combination thereof, and to select a first or second processing pipeline that executes a first instruction type based on at least one of the workload groups.

[0007] Preferably, the system or the processor or both are further configured to calculate a first processing pipeline workload and a second processing pipeline workload. Calculating the first or second processing pipeline workload includes, in one embodiment, counting the number of at least first subgroups of instructions executed in the first processing pipeline, or counting the number of at least second subgroups of instructions executed in the second processing pipeline, or both, and, in one embodiment, further including counting all instructions executed by the execution slice, and determining the proportion of the first subgroup of instructions executed in the first processing pipeline, or the proportion of the second subgroup of instructions executed in the second processing pipeline, or both, based on at least one of groups consisting of the number of first subgroups of instructions, the number of second subgroups of instructions, all instructions executed by the execution slice, and combinations thereof. Calculating the first and second processing pipeline workloads in one or more approaches is performed over a fixed or rolling interval of "N" instructions. In one embodiment, calculating the workload of the first processing pipeline further includes counting the number of third subgroups of instructions executed in the first processing pipeline and determining the proportion of the third subgroup of instructions.

[0008] In one or more embodiments, selecting a first or second processing pipeline based on at least one of a workload group includes comparing the first processing pipeline workload with the second processing pipeline workload, calculating the first processing pipeline workload, and comparing the first processing pipeline workload with a first threshold, wherein the first threshold is at least one of a first threshold group consisting of numbers, percentages, ratios, and combinations thereof; selecting a first processing pipeline to execute a first instruction type in response that the first processing pipeline workload is less than the first threshold; calculating the first processing pipeline workload; calculating the second processing pipeline workload; comparing the first processing pipeline workload with a first threshold; comparing the second processing pipeline workload with a second threshold; selecting a second processing pipeline to execute a first instruction type in response to both the first processing pipeline workload exceeding the first threshold and the second processing pipeline workload being less than the second threshold; and the first processing pipeline workload being less than or equal to the first threshold. or , the workload of the first processing pipeline exceeds the first threshold and the workload of the second processing pipeline exceeds the second threshold That's all. In a further embodiment, the selection of a first processing pipeline to execute an instruction type in response to both of the following: In a further embodiment, the selection of a first or second processing pipeline based on at least one of the workload groups in one or more embodiments includes determining whether the number or proportion of a third subgroup of instructions, or both, exceeds a third threshold, and selecting a second processing pipeline in response to the number or proportion of a third subgroup of instructions executed in the first processing pipeline, or both, exceeding the third threshold.

[0009] In one embodiment, the system or the processor or both include at least one superslice containing two execution slices, the first processing pipeline being a Compute pipe having an arithmetic logic unit (ALU) execution unit configured to execute simple arithmetic instructions, and the second processing pipeline being a Store / Branch / Simple pipe having a Simple (SX) execution unit configured to execute at least simple arithmetic instructions, the first instruction type being simple arithmetic instructions, and the instruction decode unit including a first counter for counting the number of first subgroups of instructions, the first subgroups of instructions including at least multi-cycle arithmetic instructions executed within the Compute pipe. In one embodiment, the processor is configured to use the first counter to count the number of first subgroups of instructions, compare the number of first subgroups of instructions to a first threshold, select a Compute pipe to execute simple arithmetic instructions in response that the number of first subgroups of instructions is less than the first threshold, and select a Store / Branch / Simple pipe to execute simple arithmetic instructions in response that the number of first subgroups of instructions is greater than or equal to the first threshold. In a further embodiment, the instruction decoding unit further includes a second counter for counting the number of second subgroups of instructions executed in a Store / Branch / compute pipe, wherein the second subgroup of instructions includes at least one of store instructions, dual-port load instructions, branch instructions, SX instructions, and simple groups consisting of combinations thereof, and a third counter for counting the number of instructions processed in a superslice.The processor calculates a first ratio of the first subgroup of instructions executed in the Compute pipe based on the number of instructions in the first subgroup of instructions executed in the Compute pipe pipeline and the number of instructions counted by a third counter, and uses a second counter to count the number of instructions in the second subgroup of instructions executed in the Store / Branch / Simple pipe based on the number of instructions in the second subgroup of instructions executed in the Store / Branch / Simple pipe and the number of instructions counted by the third counter. It is configured to perform the following actions: calculate the second ratio of the second subgroup of; compare the first ratio to the first ratio threshold; compare the second ratio to the second ratio threshold; select a Compute pipe to execute a simple arithmetic command in response to the first ratio being less than the first ratio threshold or the second ratio being greater than or equal to the second ratio threshold; and select a Store / Branch / Simple pipe to execute a simple arithmetic command in response to the first ratio being greater than or equal to the first ratio threshold and the second ratio being less than the second ratio threshold.

[0010] The aforementioned and other objects, features, and advantages of the present invention will become apparent from the following more specific description of exemplary embodiments of the invention shown in the accompanying drawings.

[0011] Various aspects, features, and embodiments of computer systems, computer architectures, processors, processor architectures, processor pipelines, execution units, or methods of operation thereof will be better understood when read in conjunction with the provided figures. Embodiments are provided in the figures for illustrative purposes to illustrate aspects, features, or various embodiments or combinations thereof of computer systems, computer architectures, processors, processor architectures, processor pipelines, execution units, or methods of operation thereof, or combinations thereof. However, the claims should not be limited to the exact systems, embodiments, methods, processes, or apparatus or combinations thereof shown, and the shown features or processes, or both, may be used alone or in combination with other features or processes, or both. [Brief explanation of the drawing]

[0012] [Figure 1] This figure shows an example of a data processing system in which the embodiments of this disclosure may be implemented. [Figure 2] This is a block diagram of a processor in which a particular aspect of this disclosure may be implemented. [Figure 3] This is a partial block diagram of a multislice processor having two execution slices, according to a particular aspect of the present disclosure. [Figure 4] This is a partial block diagram of a multislice processor having four execution slices arranged as two superslices, according to one embodiment of the present disclosure. [Figure 5] This is a block diagram showing a portion of the processor pipeline according to the embodiments of the present disclosure. [Figure 6] This is a simplified block diagram showing a portion of the processor pipeline according to an embodiment of the present disclosure. [Figure 7] This figure shows an example of instructions processed by a processor execution unit according to an embodiment of the present disclosure. [Figure 8]This figure shows an example of instructions processed by a processor execution unit according to an embodiment of the present disclosure. [Figure 9] This figure shows a flowchart illustrating a method according to an embodiment for adjusting the workload of one or more execution units within a processor. [Modes for carrying out the invention]

[0013] The following description is provided to illustrate the general principles of the present invention and does not limit the inventive concepts claimed herein. While the following detailed description includes numerous details to provide an understanding of computer systems, computer architectures, processors, processor architectures, processor instruction execution pipelines, execution units, and how they operate, those skilled in the art will understand that numerous different embodiments of computer systems, computer architectures, processors, processor architectures, processor instruction execution pipelines, execution units, and how they operate may be carried out without those specific details, and that the claims and the present invention should not be limited to the systems, assemblies, subassemblies, embodiments, functional units, features, circuits, processes, methods, aspects, or details, or any combination thereof, specifically described and shown herein. Furthermore, specific features described herein may be used in combination with other described features in each of the various possible combinations and permutations.

[0014] Unless otherwise defined herein, all terms shall be interpreted as broadly as possible, including the meaning implied herein, the meaning understood by those skilled in the art, the meaning defined in dictionaries, specialized books, or both. Furthermore, as used herein and in the appended claims, the singular forms "a," "an," and "the" include multiple references unless otherwise specified, and the terms "comprises" or "comprising" or both specify the presence of a described feature, integer, step, operation, element, or component or combination thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups or combinations thereof.

[0015] In the following discussion, conventional features of information processing systems, including processors and microprocessor systems, and processor architectures, which are obvious to those skilled in the art, will be omitted or only briefly described. Those skilled in the art are assumed to be familiar with general processor architectures, particularly processors having execution pipelines and one or more execution units. Note that numbered elements are often, but not always, numbered according to the diagram in which they are introduced and referred to by that number in subsequent diagrams.

[0016] Figure 1 shows an example of a data processing system 100 in which embodiments of the present disclosure may be implemented. This system has a central processing unit (CPU) 110, also called a processor 110. The CPU 110 is coupled to various other components by a system bus 112. Read-only memory ("ROM") 116 is coupled to the system bus 112 and includes a basic input / output system ("BIOS") that controls certain basic functions of the data processing system 100. Random access memory ("RAM") 114, an I / O adapter 118, and a communication adapter 134 are also coupled to the system bus 112. The I / O adapter 118 may be a small computer system interface ("SCSI") adapter that communicates with a disk storage device 120. The communication adapter 134 interconnects the bus 112 to an external network, allowing the data processing system to communicate with other such systems. Input / output devices are also connected to the system bus 112 via a user interface adapter 122 and a display adapter 136. The keyboard 124, trackball 132, mouse 126, and speaker 128 are all interconnected to bus 112 via user interface adapter 122. The display monitor 138 is connected to system bus 112 by display adapter 136. In this way, the user can input into the system via keyboard 124, trackball 132, or mouse 126, and receive output from the system via speaker 128 and display 138. Furthermore, an operating system such as AIX ("AIX" is a trademark of IBM Corporation) is used to coordinate the functions of the various components shown in Figure 1.

[0017] The CPU (or "processor") 110 includes various registers, buffers, execution units, caches, memory, and other units formed by an integrated circuit, and can operate according to reduced instruction set computing ("RISC") technology. In some embodiments, the CPU 110 processes data according to processor cycles synchronized with an internal clock (not shown).

[0018] Figure 2 shows a simplified block diagram of a processor 110 according to an embodiment. The processor 110 includes memory 202, an instruction cache 204, an instruction fetch unit 206, a decode unit 210, an execution slice 215 including an LSU processing pipeline 230 and a VSU processing pipeline 255, and a destination resource 290. The processor 110 may be contained within a computer system or distributed within a computer system. Instructions and data can be stored in memory 202, and the instruction cache 204 can access and store instructions in memory 202. Memory 202 may include any type of volatile or non-volatile memory. Memory 202 and the instruction cache 204 may include multiple cache levels.

[0019] Figure 2 shows a simplified example of an instruction fetch unit 206, a decode unit 210, and an execution slice 215. In various embodiments, the processor 110 may include multiple processing execution slices 215, for example, four execution slices 215. In one embodiment, each execution slice 215 includes an LSU processing pipeline 230 and a VSU processing pipeline 255. In one embodiment, the LSU processing pipeline 230 includes an LSU issue unit 235, an execution unit 240, and a physical register file 250. The execution unit 240 in the embodiment includes an Sx / Agen execution pipeline 245. The LSU processing pipeline 230 may also include other functions such as error checking and processing logic, one or more parallel paths through the LSU processing pipeline 230, and other functions currently or hereafter known in the art. In one embodiment, the VSU processing pipeline 255 includes a VSU issue unit 270, an execution unit 275, and a physical register file 285. In this embodiment, the execution unit 275 includes an FX / ALU execution pipeline 280. The VSU processing pipeline 255 may also include other functions such as error checking and processing logic, one or more parallel paths through the VSU processing pipeline 255, and other functions currently or hereafter known in the Art.

[0020] In the processor 110 of FIG. 2, the instruction fetch unit 206 fetches instructions from the instruction cache 204 according to the instruction address for further processing by the decode unit 210. The decode unit 210 decodes the instructions and passes the decoded instructions, parts of the instructions, or other decoded data to the appropriate pipeline 230 or 255 according to the type of the instructions. The decode unit 210 can also detect branch instructions. More specifically, in the example of FIG. 2, the decode unit 210 sends the decoded instructions to either the LSU issue unit 235 or the VSU issue unit 270. Each issue unit 235, 270 analyzes the instructions or other data and, based on the analysis, sends the decoded instructions, parts of the instructions, or other data to one or more execution units 240, 275 within the respective pipelines 230, 255. Each physical register file 250, 285 holds the data of the respective execution units 245, 280. The physical register files 250, 285 can be separate register files where the data in one register file can be used by any of the execution units 240, 275, and in one embodiment, the register files 250, 285 can be a single register file. Although the forward path through the processor 110 is depicted in FIG. 2, other feedback paths and signal paths may be included among the elements of the processor 110.

[0021] Execution units 240, 275 perform and execute the operations specified by the instructions issued to their respective execution units 240, 275. The LSU pipeline 230 has been shown together with the execution unit SX / Agen 245, but the execution unit 240 can include multiple execution units such as, for example, a load / store execution unit (LSU), a simple unit (SX) including store address generator (Agen) logic, or other execution units, or combinations thereof. The VSU pipeline 255 has been shown together with the execution unit FX / ALU 280, but the execution unit 275 can include multiple execution units such as, for example, a fixed-point execution unit (FX), a floating-point execution unit (FPU), an arithmetic logic execution unit (ALU), a vector scalar execution unit (VSU), or other execution units, or combinations thereof.

[0022] The processor 110 also includes result / write-back logic 290 for writing the results of the executed instructions, for example, the results from the LSU processing pipeline 230 and the VSU processing pipeline 255, to destination resources. The destination resources can be any type of resource including registers, cache memory, other memories, I / O circuitry for communicating with other devices, other processing circuitry, or any other type of destination for the executed instructions or data. The processor 110 may include other circuits, functional units, and components.

[0023] Instructions may be processed in a sequence of logically pipelined stages in the processor 110 of FIG. 2. However, it should be understood that the functions of these stages may be merged together so that this particular division of stages is not to be taken as a limitation, unless such a limitation is explicitly set forth in the claims of this specification. In fact, some of the stages or functional units are shown as a single logical unit in FIG. 2 for ease of understanding, and further details related thereto are provided below.

[0024] Figure 3 is a partial block diagram of the processor 110, and in this example, it shows a multi-slice processor 110 according to an embodiment of the present disclosure. Note that Figure 3 is only a schematic representation of a part of the multi-slice processor 110 for the purposes of discussion. It will be understood that the multi-slice processor may have other configurations. As shown in Figure 3, the multi-slice processor includes two processing slices - slice 0 (slice S0 or 215A) and slice 1 (slice S1 or 215B). The processor 110 includes memory 202, instruction cache 204, instruction fetch unit 206 and decode unit 210. Each of slices S0 and S1 includes an instruction dispatch unit (220A and 220B), a logical register mapper (225A and 225B), a history buffer (HB) (226A and 226B), an instruction completion table (ICT) (222A and 222B), an LSU processing pipeline (230A and 230B), and a VSU processing pipeline (255A and 225B).

[0025] Each LSU processing pipeline (230A and 230B) includes an LSU issuance unit (LSU ISQ) (235A and 235B) and execution units (240A and 240B), and each execution unit 240A and 240B within each LSU processing pipeline 230A and 230B includes an SX / Agen execution unit (245A and 245B). LSU processing pipelines 230A and 230B may also include other execution units, such as load-store units (LSUs). Each VSU processing pipeline (255A and 255B) includes a VSU issuance unit (VSU ISQ) (270A and 270B) and execution units (275A and 275B), and each execution unit 275A and 275B within each VSU processing pipeline 255A and 255B includes an FX / ALU execution unit (280A and 280B). The VSU processing pipeline (255A, 255B) may include other execution units, such as a vector scalar unit (VSU) and a floating-point execution unit (FPU). The physical register file (RF) 250A can be used by both the LSU processing pipeline 230A and the VSU processing pipeline 255A, and the physical register file 250B can be used by both the LSU processing pipeline 230B and the VSU processing pipeline 255B. While the processor 110 in Figure 3 shows a single register file 250A, 250B shared between the LSU and VSU processing pipelines, it can be understood that one or more register files 250 may be used in the LSU and VSU processing pipelines and across execution slices 215A, 215B. Execution units 240A, 240B, 275A, 275B may include one or more queues holding instructions for execution by the execution units.

[0026] The two slices 215A and 215B are shown for illustrative purposes and for discussion purposes only, and it should be noted that the multi-slice processor 110 may include two or more execution slices, each having all the components described above for each of slices S0, S1 (slices 215A and 215B). Furthermore, processing slices may be grouped into super-slices (SS395), each super-slice containing a set of processing or execution slices. For example, a multi-slice processor may include two super-slices SS0 and SS1, where SS0 (e.g., 395) contains slices S0 and S1, and SS1 (not shown) contains slices S2 and S3.

[0027] The instruction fetch unit 206 fetches instructions to be executed by the processor 110 or the processor superslice 395. Instructions fetched by the instruction fetch unit 206 are sent to the decode unit 210, where they are decoded by instruction type. The decode unit 210 sends the decoded instructions to the respective instruction dispatch units 220A and 220B. The instruction dispatch units 220A and 220B dispatch the instructions to the LSU issue unit 235 or VSU issue unit 255, depending on the type of instruction and the execution unit 240 or 275 that should process that particular instruction. The instruction dispatch units 220A and 220B dispatch the instructions to the respective LSU issue unit 235 or VSU issue unit 255, usually in program order. In one or more embodiments, each instruction dispatched to the LSU issue unit 235 or VSU issue unit 270 is marked with an identifier, such as an identification tag (iTag), to identify the instruction. Instructions can also be stamped with other information or metadata. Instructions (iTag) are typically assigned and stamped in ascending order of program for each thread.

[0028] Each LSU issue unit 235 or VSU issue unit 270 issues instructions to the respective execution units 240 or 275 based on the instruction type. For example, multicycle arithmetic instructions and matrix multiplication accumulator (MMA) instructions are typically processed by the VSU processing pipeline 255 (e.g., the FX / ALU execution unit 280), while store instructions, load instructions (including dual-port loads), branch instructions, and store instructions are typically processed by the LSU processing pipeline 230. The LSU and VSU issue units 235 and 270 typically hold the instructions until the data associated with the instructions is retrieved and the instructions are available. In certain embodiments, the LSU issue unit 235 and VSU issue unit 270 hold a set of instructions, and a physical register file 250 stores the data for the instruction inputs. The register file may be used to stage data between memory and other functional (execution) units within the processor. There may be a large number of register files and types. Once all source data has been accumulated for the instructions, the data in one or more embodiments is passed to one or more execution units designated for the execution of the instructions. The physical register (or main register) file 250 can serve to store data used in operations specified by instructions dispatched to execution units 240 and 275, and the results of operations performed by execution units 240 and 275 may be written to specified target register entries in the physical register file 250. Each execution unit, for example, SX / Agen245 and FX / ALU280, can make the result data available on the write-back bus for writing to register file (STF) entries.

[0029] The logical register mapper 225 includes metadata (e.g., iTag, STFtag, etc.) that provides a mapping between entries in a logical register (e.g., GPR1) and entries in the physical (main) register file 250 (e.g., physical register array entries). The STFtag is a pointer that associates a logical register entry with a physical register file entry. For example, when an instruction wants to read a logical register, e.g., GPR1, the logical register mapper 225 tells the respective issuing units 235 and 270, and the issuing units 235 and 270 tell the respective execution units 240 and 275, e.g., SX / Agen245 and FX / ALU280, where in the physical register file 250 they can find the data, e.g., a physical register array entry. Each execution unit 240, 275, for example SX / Agen245 or FX / ALU280, executes instructions out of order, and when each execution unit 240, 275 finishes an instruction, it sends the completed instruction, for example iTag, to ICT222. ICT222 contains a queue of instructions dispatched by dispatch unit 220 and tracks the progress of the instructions as they are processed.

[0030] If a mispredicted branch instruction or other exception is detected, the instructions and data following the mispredicted branch or exception are discarded and flushed, for example, from various units of the processor 110. A history buffer (HB) 226, for example a save and restore buffer (SRB) 226, contains both speculative register states and architect register states and backs up the logical register mapper 225 when a new instruction is dispatched. In this regard, the history buffer 226 stores information from the logical register mapper 225 when the new instruction evacuates data from the logical register mapper 226 in case the new instruction is flushed and old data needs to be recovered. The history buffer (HB) 226 retains the stored information until the new instruction is completed. The history buffer (HB) 226 interfaces with the logic register mapper 225 to return its contents from the history buffer (HB) 226 to the logic register mapper 225, updating the pointers in the logic register mapper 225 so that the instruction knows where to get the correct data, for example, the processor being returned to the state it was in before an interruptible instruction, for example, if a branch instruction was mispredicted.

[0031] A CPU 110 with multiple processing slices can execute multiple instructions simultaneously; for example, it can execute one instruction in each processing slice simultaneously in a single processing cycle. Such a CPU with multiple processing slices is sometimes called a multi-slice processor or parallel-slice processor. By processing simultaneously with multiple execution slices, the processing speed of a multi-slice processor can be significantly improved. In single-threaded (ST) mode, one thread is processed, while in SMT mode, two threads (SMT2) or four threads (SMT4) are processed simultaneously.

[0032] As described above, instructions are decoded by the decode unit 210 and directed to one of several execution units for execution by the processor. Many processors can execute a large number of instructions in one or more execution units. For example, simple arithmetic operations and other trivial instructions can be executed by multiple execution units. To reduce latency, the processor can direct instructions that can be executed by multiple pipelines and / or execution units to one of one or more pipelines and / or execution units in the processor that can execute the instructions, based on the workload of various pipelines and / or execution units. In one or more embodiments, the processor can determine the workload of one or more pipelines and / or execution units in response to executing instructions that can be executed in one or more pipelines and / or execution units, and direct those instructions for execution to one of one or more pipelines and / or execution units in the processor that can execute those instructions, based on the workload of those pipelines and / or execution units in the processor.

[0033] For example, in computationally intensive workloads, an arithmetic unit, such as a fixed-point (FX) execution unit that typically executes simple arithmetic instructions, may be overloaded with arithmetic instructions (in addition to other instructions), such as multicycle arithmetic instructions or multiplication matrix addition (MMA) instructions, or both, while other execution units, such as an SX execution unit that can also execute simple arithmetic instructions, may be lightly loaded. To reduce the FX execution workload, in one or more embodiments, a processor, such as an instruction decoding unit (IDU) within the processor, may implement logic that detects or determines, or both, the workload of the FX execution unit / pipeline and the workload of the SX execution unit / pipeline, and routes simple arithmetic instructions that can be executed by either the FX execution unit or the SX execution unit to the FX unit or the SX unit, based on the respective workloads of these two pipelines or execution units or both.

[0034] For example, trivial, simple, or both instructions that are typically processed in the VSU processing pipeline but can also be executed in the LSU processing pipeline can be directed to run in the LSU processing pipeline based on the workload of the two pipelines, and vice versa. For instance, if the workload of the VSU pipeline is heavy and the workload of the LSU pipeline is relatively light, the processor can direct simple, trivial, or both arithmetic instructions that can be executed in the LSU pipeline to the LSU pipeline. One frequently used instruction that is relatively simple and can be processed in or both of the Power ISA's processing pipelines is the addi instruction. The addi instruction is a relatively simple arithmetic operation and is usually executed in the VSU processing pipeline by an arithmetic execution unit, such as the FX execution unit. The addi instruction can also be executed in the LSU processing pipeline by an SX unit, such as the Store Address Generation (Agen) execution unit. During processor operation, the FX unit may be overloaded with arithmetic instructions other than addi instructions, such as multicycle operations, while the workload of the SX unit, which can also execute addi instructions, is light. To reduce the workload of FX execution units and shorten latency to improve processor throughput and performance, addi instructions can be redirected to SX units for execution. In one or more embodiments, an instruction decode unit (IDU) may implement logic to detect or determine the workload of one or more execution units or pipelines or both, and in response to the workload of one or more execution units / pipelines, it may redirect or reroute instructions for execution to alternative execution units or pipelines or both. One mechanism for detecting or determining the workload of different execution units or processing pipelines or both is to implement one or more counters that count the various instructions processed by a particular execution unit or processing pipeline or both.

[0035] Turning to Figure 4, another embodiment of a part of the processor 410 is illustrated. The processor 410 is a multislice processor having four execution slices configured as two superslices (SS0 and SS1). Superslice A (SS0) is the same as superslice B (SS1), and in 4-thread mode (SMT4), threads 0 and 2 are processed in SS0 and threads 1 and 3 are processed in SS1. The instruction decode unit (IDU) 210 in the disclosed embodiment has eight transmit lanes to issue queues 235A-235D, with transmit lanes 0:3 supplied to superslice A (SS0) and transmit lanes 4:7 supplied to superslice B (SS1). Transmit lanes 0:3 of the instruction decoding unit (IDU) 210 send instructions to slice 0 issue queue 235A and slice 1 issue queue 235B, while transmit lanes 4:7 of the instruction decoding unit (IDU) 210 send instructions to slice 2 issue queue 235C and slice 3 issue queue 235D. The super slice SS0 issue queues 235A, 235B and super slice SS1 issue queues 235C, 235D issue instructions to one of several pipes based on the type of instruction. In the example in Figure 4, issue queues 235A and 235B can issue instructions to one of the following: load A pipe 442A, Store / Branch / Simple A pipe 444A, slice Compute 0 pipe 476A, slice Compute 1 pipe 476B, super slice Compute A pipe 478A, or SMT4-core resource Compute pipe 484, or a combination thereof. In the example in Figure 4, issue queues 235C and 235D can issue instructions to one of the following: Load B pipe 442B, Store / Branch / Simple B pipe 444B, Slice Compute2 pipe 476C, Slice Compute3 pipe 476D, Super Slice Compute B pipe 478B, or SMT4-Core Resource Compute pipe 484, or a combination thereof.The operation of processor 410 in Figure 4 will be described primarily by referring to the operation of superslice A (SS0), so that it can be understood that superslice A (SS0) is a copy of superslice B (SS1). It can be understood that each of the pipes 442, 444, 476, 478, and 484 may contain one or more execution units for executing instructions issued down their respective pipes.

[0036] In the example in Figure 4, referring to superslice A (SS0) and recognizing that superslice B (SS1) is configured similarly, the Store / Branch / SimpleA pipe 444A contains a simple (SX) pipeline with store address generation (Agen) logic that can handle store operations and simple arithmetic operations, as well as other operations. The slice Compute0 pipe 476A contains a fixed-point (FX) pipeline with an arithmetic logic (ALU) execution unit used for arithmetic operations. Simple arithmetic operations are typically processed, for example, executed, in the slice Compute0 pipe 476A, but can also be processed, for example, executed, in the Store / Branch / Simple pipe 444A. For example, an addi instruction is typically processed by the ALU execution unit in the slice Compute0 pipe 476A, and can also be executed in the Store / Branch / SimpleA pipe 444A by the SX pipeline. In one or more embodiments, if the slice Compute0 pipe 476A has a heavy workload and the Store / Branch / SimpleA pipe 444A has a relatively light workload, simple arithmetic instructions, such as the addi instruction, can be directed to the Store / Branch / SimpleA pipe 444A for execution.

[0037] In one or more embodiments, the IDU 202 tracks one or more groups or subgroups of instructions sent to one or more processing pipelines in order to determine the workload of various processing pipelines or execution units or both. In one embodiment, one or more counters are used to track one or more groups or subgroups of instructions sent to one or more processing pipelines or execution units or both. In the exemplary embodiment shown in Figure 4, the instruction decoding unit (IDU) 210 tracks multiple instruction groups, for example, an instruction group directed to superslice A (SS0) and an instruction group directed to superslice B (SS1). In one aspect, the instruction decoding unit (IDU) 202 may have one or more counters that count specific instructions, groups of instructions, or subgroups of instructions transmitted across lanes 0:3 to superslice A (SS0), and one or more other counters that count specific instructions, groups of instructions, or subgroups of instructions transmitted across lanes 4:7 to superslice B (SS1). One or more counters that count specific instructions transmitted across lanes 0:3 to superslice A (SS0) facilitate determining the workload in superslice A (SS0) and, in one or more embodiments, determining the workload of different pipes 442A, 444A, 476A, 476B, 478A, or 484 or a combination thereof. One or more counters that count specific instructions transmitted to superslice B (SS1) via lanes 4:7 facilitate determining the workload in superslice B (SS1) and, in one or more embodiments, determining the workload of different pipes 442B, 444B, 476C, 476D, 478B, or 484 or a combination thereof.

[0038] Figure 5 shows a simplified block diagram of the instruction decoding unit (IDU) 202, in single-threaded mode (SMT1) or dual-threaded mode (SMT2), all eight (8) lanes 0:7 (527) sent to both supper slices SS0 and SS1, for example, issue queues 235A-235D, are counted by counters 411-414 and 416-419, and routing to various pipes or execution units or both affects all eight decode lanes 527. Figure 6 shows a simplified block diagram of the instruction decoding unit (IDU) 202 in 4-thread mode (SMT4), where instructions counted by counters 411-414 on transmit lanes 0:3 affect decode lanes 0:3 (628) to super-slice SS0 issue queues 235A-235B, and instructions counted by counters 416-419 on transmit lanes 4:7 affect decode lanes 4:7 (629) to super-slice SS1 issue queues 235C-235D.

[0039] In one or more embodiments, as shown in Figure 4, the IDU210 includes several counters 411-414 and counters 416-419, where counters 411-414 facilitate determining the workload of various pipelines within superslice A SS0, and counters 416-419 facilitate determining the workload of various pipelines within superslice B SS1. More specifically, counters 411-414 count various instructions (or groups / subgroups of instructions) transmitted across lanes 0:3 to issue queues 235A and 235B of superslice A (SS0), and counters 416-419 count various instructions (or groups of instructions) transmitted across lanes 4:7 to issue queues 235C and 235D of superslice B (SS1).

[0040] In one embodiment, for example, in the processor of Figure 4, counter 411 is positioned and configured to count the total number of instructions (e.g., all instructions) sent to superslice A (SS0), while counter 416 counts the total number of instructions (e.g., all instructions) sent to superslice B (SS1). Preferably, each of counters 411 and 416 may be contained within the IDU 202. In one approach, for example, in the processor 410 of Figure 4, if a simple arithmetic instruction, such as an addi instruction, is executable in multiple pipes or execution units or both within the processor, for example, a first pipe / execution unit and a second pipe / execution unit, then in order to determine the workload of different pipes or execution units or both, or the relative workload or both, the first counter may count the instructions (or groups of instructions) sent to one of the pipes or execution units or both, for example, the first pipe or execution unit or both, while the second counter may count the instructions (or groups of instructions) sent to another of the pipes or execution units or both, for example, the second pipe or execution unit or both. In one or more embodiments, based on the workload of different pipes or execution units or both, the processor may instruct different pipes or execution units or both based on the workload of one pipe or execution unit or both, for example, a first pipe or execution unit or both, or another pipe or execution unit or both, for example, a second pipe or execution unit or both.

[0041] Looking at the specific processor in Figure 4, simple arithmetic instructions, such as addi instructions, can be executed on multiple pipes or execution units of superslice A (SS0), or both. Simple arithmetic instructions, such as addi instructions, within processor 410 can be executed on slice Compute0 pipe 476A and Store / Branch / SimpleA pipe 444A within superslice SS0. In one embodiment, counter 412 is configured to count the number of a first subgroup of arithmetic resource-intensive instructions processed by slice Compute0 pipe 476A, such as multicycle arithmetic (MC Arth) instructions; counter 413 is configured to count the number of a third subgroup of instructions, such as matrix multiplication accumulator (MMA) instructions (computation instructions that consume a lot of resources); and counter 414 is configured to count the number of a second subgroup of instructions processed by Store / Branch / SimpleA pipe 444A, such as store instructions, dual port load instructions, branch instructions, and SX instructions. In the case of super slice B (SS1), it can be understood that counter 417 is configured and positioned similarly to counter 412, counter 418 is configured and positioned similarly to counter 413, and counter 419 is configured and positioned similarly to counter 414. In the embodiment, the first subgroup of instructions may include, but is not limited to, multicycle arithmetic instructions such as xxbrd, vsubcuq, ddiv, vsbox, vdivsw, and fcfid, and the third subgroup of instructions may include, but is not limited to, MMA instructions such as xvbf16ger2, xvf16ger2, xvf32ger, xvf64ger, and xvi4ger2.In the examples, the second subgroup of instructions includes, but is not limited to, store instructions, dual-port load instructions, branch instructions, and simple (SX) instructions (e.g., store instructions stsdx, std, stdu, sth, stmd, stwd; dual-port load instructions lxvp, lxvpx, lq, lqArx; branch instructions b, ba, bl, bla, bc, bca, bclr, bclrl, bcctr, bcctrl; simple (SX) instructions mfspr, mtspr, etc.).

[0042] The processor 410 includes logic that uses counter values ​​to determine the workload of the Store / Branch / SimpleA pipe 444A and the slice Compute0 pipe 476A, and can instruct simple arithmetic instructions based on the determined workload values, percentages, or both. To accommodate different workload tunings, multiple different settings can be implemented to determine, for example, when to send a simple arithmetic instruction, such as an addi instruction, to two or more pipes, such as the Store / Branch / SimpleA pipe 444A or the slice Compute0 pipe 476A. Multiple different settings can be pre-configured, preset, adjustable, programmable, or a combination thereof. The processor 410 can use a count value or ratio (percentage) or both of a specific instruction or a different instruction as a basis for determining which pipe or execution unit, or both, to direct a particular instruction, such as a simple arithmetic instruction, to and when.

[0043] In one or more embodiments, the processor determines a ratio or proportion of multicycle arithmetic instructions, a ratio or proportion of matrix multiplication and addition (MMA) instructions, or a ratio of store instructions, dual-port load instructions, branch instructions, and simple (SX) instructions processed on one superslice of the processor (SS0 or SS1), or both, and based on those ratios, determines whether to send simple arithmetic instructions, e.g., addi instructions, to slice Compute0 pipe 476A or Store / Branch / SimpleA pipe 444A. For example, the ratio of a first subgroup of instructions counted by counter 412, a third subgroup of instructions counted by counter 413, and a second subgroup of instructions counted by counter 414 is used to determine whether to send simple arithmetic instructions to slice Compute0 pipe 476A (e.g., the FX unit of slice Compute0 pipe 476A) or Store / Branch / SimpleA pipe 444A (e.g., the SX unit of Store / Branch / SimpleA pipe 444A).

[0044] The instruction ratio can be counted every fixed number of instructions "N", for example, every 64 instructions. In this case, the ratio can be calculated from the counter value after every 64 instructions, for example, after 64 instructions, after 128 instructions, after 192 instructions, etc. That is, every time 64 instructions are sent, the count for each instruction group is sampled. The processor, preferably the IDU, compares the sampling result with a threshold control setting to maintain the same routing of simple arithmetic instructions or to reroute the simple arithmetic instructions over the next 64 instructions. Here, after 64 multicycle arithmetic (MC Arth) instructions, if the workload of the FX unit processing the multicycle arithmetic (MC Arth) instructions is high (e.g., above a threshold for 64 instructions), an example is shown in Figure 7 in which a decision is made on which pipe or execution unit or both to use based on a fixed number of 64 instructions, and the simple arithmetic instructions for the next fixed 64 instructions, for example, the addi instruction, are routed to be processed by the SX unit (in the Store / Branch / Simple pipe 444). In Figure 7, after 128 instructions, the counter sampling result has changed, so the processor returns to sending simple arithmetic instructions to the FX unit in slice Compute pipe 476.

[0045] The determination or sampling of ratios and counter values, or both, can also be performed on a rolling basis, for example, over the last number "N" cycles. For example, sampling and ratios can be determined based on the last 64 instructions, such that the sampling result or the ratio, or both, is determined after each instruction based on the last 64 instructions. The processor, preferably the IDU, compares the sampling result based on the last 64 instructions to a threshold control setting to determine how to instruct the simple arithmetic instruction. An example is shown in Figure 8 of determining which pipe or execution unit, or both, to use based on a rolling number of instructions "N", for example, a rolling number of 64 instructions, after which the workload of the FX unit is determined. In Figure 8, after the first 64 instructions, the workload of the FX unit is calculated and determined to be high, so the processor instructs the simple arithmetic instruction to the SX unit in Store / Branch / Simple444. After the 64th instruction, the processor slice (SS0) begins processing instructions other than multi-cycle arithmetic (MC Arth) instructions, such as simple arithmetic (Arth), load instructions, and store instructions. After each instruction after the 64th cycle, the processor samples the results from the last 64 instructions and determines the ratio. After the 9th cycle (e.g., 72 instructions), the ratio has not changed sufficiently, and simple arithmetic instructions, such as addi instructions, continue to be routed to the SX unit in the Store / Branch / Simple pipe 444. After the 9th cycle (e.g., 72 instructions), the processor continues to process less computationally intensive workloads, and after the 10th cycle (e.g., 80 instructions), the ratio of the last 64 instructions has changed sufficiently so that simple arithmetic instructions (e.g., Addi instructions) are redirected to the FX unit (e.g., slice Compute pipe 476).

[0046] A processor, such as IDU202, can be programmed to handle a number of different conditions in order to redirect instructions to alternative pipes or execution units or both. In the example of processor 410 in Figure 4, two conditions can be programmed for IDU202 to send simple arithmetic instructions, such as the Addi instruction, from a Compute pipe such as Compute pipe 476, or an execution unit such as the FX unit, or both, to an alternative pipe, or an alternative execution unit, such as Store / Branch / Simple pipe 444 or an SX unit, or both. One condition for directing simple arithmetic instructions to Store / Branch / Simple pipe 444 (e.g., SX unit) is when multicycle instructions exceed a first threshold and store, dual load port, branch, simple (SX) instructions are below a second threshold. Another condition for directing simple arithmetic instructions, such as the Addi instruction, to Store / Branch / Simple pipe 444 (e.g., SX unit) is when MMA instructions exceed a third threshold.

[0047] For example, a first threshold related to multicycle instructions is when the number of multicycle arithmetic (MC Arth) instructions is greater than, for example, 20%, 30%, or 40% over a fixed or rolling number of instructions N (e.g., over 64 instructions), and a second threshold for store, dual load port, branch, and simple (SX) instructions over the same fixed or rolling number of instructions N is when, for example, 15%, 25%, or 35%. For a superslice A (SS0), the ratio or percentage of multicycle arithmetic (MC Arth) instructions can be calculated by looking at the count values ​​of counters 412 and 411, the ratio or percentage of store, dual port load, branch, and SX (simple) instructions can be calculated by looking at the values ​​of counters 414 and 411, and the ratio or percentage of MMA instructions can be calculated by looking at the count values ​​of counters 413 and 411. The ratio, percentage, or both can be calculated for superslice B (SS1) by using the values ​​of counters 416-419 in the same way that counters 411-414 are used in superslice A (SS0). It should be understood that the threshold percentage / ratio values ​​may differ from the exemplified values ​​and will be partly a matter of processor architecture and design considerations. The values ​​from the counters can be used, as opposed to ratios or percentages, to set conditions or thresholds, or both, to determine the workload of various pipes or execution units or both.

[0048] When the primary execution unit for processing simple arithmetic instructions has a heavy arithmetic / calculation workload, such as from multicycle arithmetic instructions or MMA instructions or both, it can be understood that balancing the workload between execution units, improving processor performance and reducing processor latency can be achieved by selectively routing simple arithmetic instructions, such as addi instructions, to alternative execution units for execution. Implementing selective routing and balancing of workloads in execution pipelines or execution units or both can be achieved using counters that compute and determine various workloads, and thresholds (adjustable, fixed) that direct different instructions to different execution pipelines or execution units or both.

[0049] Figure 9 is an exemplary flowchart by an embodiment illustrating and describing a method of processing data, such as execution instructions, in a processor, which includes adjusting the workload or execution pipelines or execution units or both within the processor, in an embodiment that includes selectively routing simple arithmetic instructions, which can be executed in multiple execution pipelines or execution units or both, to specific execution pipelines or execution units or both, in order to improve processor performance. Method 900 is described for convenience and is not intended to limit the disclosure to a series of steps or a large number of steps or both, but it should be understood that the process does not have to be performed as a series of steps, or the steps do not have to be performed in the order shown and described with respect to Figure 9, or both, the process may be integrated, or one or more steps may be performed together, or simultaneously, or the steps may be performed in the disclosed order or in an alternative order.

[0050] Method 900 in Figure 9 relates to adjusting and balancing the workload within a processor to improve the performance and throughput of a processor having multiple execution pipelines or execution units or both. In 905, a processor is provided having multiple pipelines or execution units or both capable of executing instruction types, such as simple arithmetic instructions, like the addi instruction in the Power ISA architecture. Different instructions may be applicable to other processor architectures. Process 900 is described with reference to both a first processing pipeline or a first execution unit or both capable of executing instruction types, and a second processing pipeline or a second execution unit or both, but it will be understood by those skilled in the art that there may be two or more processing pipelines or two or more execution units or both within a processor capable of executing instruction types, and that process 900, which adjusts or balances the workload between two or more processing pipelines or two or more execution units or both, is also applicable to such a processor.

[0051] In 910, the workload of a first processing pipeline or execution unit, or both, capable of executing a simple arithmetic instruction is calculated. For the sake of ease of discussion, process 900 will be described with reference to a simple arithmetic instruction, but it will be understood by those skilled in the art that process 900 is applicable to other instruction types that can be executed by multiple processing pipelines or execution units, or both. In the embodiment, process 900 is described with reference to a slice Compute pipe as a first processing pipeline capable of executing simple arithmetic instructions, and an FX execution unit (e.g., within the first processing pipeline) as a first execution unit capable of executing simple arithmetic instructions. In the embodiment, process 900 is described with reference to a Store / Branch / Simple pipe as a second processing pipeline capable of executing simple arithmetic instructions, and an SX execution unit (e.g., within the second processing pipeline) as a second execution unit capable of executing simple arithmetic instructions.

[0052] In one or more implementations, in 915, the workload of the first processing pipeline or the first execution unit or both may be calculated by counting all instructions executed by the first processing pipeline or the first execution unit or both. One approach is to understand that in 915, the workload of the first processing pipeline or the first execution unit or both may be calculated by counting subgroups of instructions executed by the first processing pipeline or the first execution unit or both. For example, in 915, the workload of the first processing pipeline or the first execution unit or both may be calculated by counting multicycle arithmetic instructions, which are subgroups of instructions executed by the first processing pipeline or the first execution unit or both. A further approach is that in 915, the workload of the first processing pipeline or the first execution unit or both may be calculated by counting multiple subgroups of instructions executed by the first processing pipeline or the first execution unit or both. For example, in 915, the workload of the first processing pipeline or the first execution unit or both may be calculated by counting multicycle arithmetic instructions, which are a first subgroup of instructions executed by the first processing pipeline or the first execution unit or both, and by counting matrix multiplication accumulator (MMA) instructions, which are a second subgroup of instructions executed by the first processing pipeline or the first execution unit or both. It may be understood that one or more counters may be provided to count various instructions or instruction groups / subgroups or both within the processor, processing pipeline, or execution unit or a combination thereof.

[0053] In one or more embodiments, 920 counts all instructions executed in the processor or processing slice, and 925 calculates the ratio or percentage of instructions executed in the first processing pipeline or the first execution unit or both. One approach is that in 925, the ratio or percentage of instructions executed in the first processing pipeline or the first execution unit or both would be determined by dividing the number of instructions (or subgroups of instructions) executed in the first processing pipeline or the first execution unit or both by the total number of instructions processed in each processor / processing slice. The counts in 915 and 920, depending on the embodiment, are determined over a fixed or rolling number "N" of instructions in the processor / processing slice. For example, the count of instructions in the first processing pipeline or the first execution unit or both in 915, the count of all instructions executed in the processor or processing slice or both in 920, and the calculation / determination of the ratio or percentage or both in 925 can be done over a fixed 64 instruction interval or over a rolling 64 instruction interval.

[0054] In one embodiment, it may be understood that, instead of using the ratio or proportion of instructions (or subgroups of instructions) executed in the first processing pipeline or execution unit or both, the number of instructions (or subgroups of instructions) "N" may be counted in 915 and used in 910 as the basis for determining / calculating the workload of the first processing pipeline or the first execution unit or both.

[0055] After calculating the workload of the first processing pipeline or the first execution unit or both in 910 (for example, after calculating the number / ratio / percentage of instructions (or groups of instructions) in 915 / 925), process 900 proceeds to 930, where, according to one or more approaches, the workload of the second processing pipeline or the second execution unit or both capable of executing instruction types, e.g., simple arithmetic instructions, is calculated or determined, or both. In one or more implementations, in 935, the workload of the second processing pipeline (e.g., Store / Branch / Simple pipe) or the second execution unit (e.g., SX execution unit) or both may be calculated by counting all instructions executed in the second processing pipeline or the second execution unit or both. In one approach, it may be understood that in 935, the workload of the second processing pipeline or the second execution unit or both may be calculated by counting subgroups of instructions executed by the second processing pipeline or the second execution unit or both. For example, in 935, the workload of a second processing pipeline or a second execution unit, or both, may be calculated by counting store instructions, dual-port load instructions, branch instructions, and SX instructions, which are subgroups of instructions executed by the second processing pipeline or the second execution unit, or both. A further approach is that in 935, the workload of a second processing pipeline or a second execution unit, or both, may be calculated by counting multiple subgroups of instructions executed by the second processing pipeline or the second execution unit, or both. It can be understood that one or more counters may be provided to count various instructions or instruction groups / subgroups, or both, within a processor, processing pipeline, or execution unit, or a combination thereof.

[0056] In one or more embodiments, 940 will calculate the ratio or percentage of instructions executed in the second processing pipeline or the second execution unit or both. One approach is that in 940, the ratio or percentage of instructions executed in the second processing pipeline or the second execution unit or both will be determined by dividing the number of instructions (or subgroups of instructions) executed in the second processing pipeline or the second execution unit or both by the total number of instructions processed in each processor / processing slice. The total number of instructions processed in each processor / processing slice is determined in 920. The counts in 935 and 920, depending on the embodiment, are determined over a fixed or rolling number "N" of instructions in the processor / processing slice. For example, the count of instructions in the second processing pipeline or the second execution unit or both in 935, the count of all instructions executed in the processor or processing slice or both in 920, and the calculation / determination of the ratio or percentage or both in 940 can be done over a fixed 64 instruction interval or over a rolling 64 instruction interval.

[0057] According to the embodiment, instead of using the ratio or proportion of instructions (or subgroups of instructions) executed in the second processing pipeline or the second execution unit or both, the number of instructions (or subgroups of instructions) "N" may be counted in 935 and used in 930 as the basis for determining / calculating the workload of the second processing pipeline or the second execution unit or both.

[0058] After calculating the workload of the second processing pipeline or the second execution unit or both in 930 (for example, after calculating the number / ratio / percentage of instructions (or instruction groups) in 935 / 940), process 900 follows 945, in which, according to one or more approaches, the workload of the first processing pipeline or the first execution unit or both is compared to the workload of the second processing pipeline or the second execution unit or both. In one or more implementations, in 950, the ratio / percentage / number of instructions (or groups / subgroups of instructions) executed in the first processing pipeline or the first execution unit or both is compared to a first threshold. For example, the ratio or percentage or both of a first subgroup of instructions processed / executed in the first processing pipeline or the first execution unit or both, e.g., multicycle arithmetic instructions executed in the Compute pipe by the FX unit, is compared to a first threshold, which could be, for example, 20%, 30%, or 40%. In another example, the number "N" of a first subgroup of instructions processed / executed in a first processing pipeline or a first execution unit or both, for example, multicycle arithmetic instructions executed in the Compute pipeline by an FX unit, is compared to a first threshold, which could be, for example, the 5th, 25th, 32nd, or 45th of a fixed or rolling interval of, for example, 64 cycles, of instructions executed by the processor or a processing slice or both, or a combination thereof. It should be understood that the first threshold may differ from the example above, and may be fixed, predetermined, programmable, adjustable, or a combination thereof, and may depend in part on processor and design considerations.In one embodiment, comparing the ratio / percentage / number of instructions (or groups / subgroups of instructions) executed in a first processing pipeline or a first execution unit or both to a first threshold at 950 provides a baseline workload for the first processing pipeline or the first execution unit or both, below which instruction types, e.g., simple arithmetic instructions, are processed in the first processing pipeline or the first execution unit or both; above which the processor may execute instruction types, e.g., simple arithmetic instructions, in a second processing pipeline or a second execution unit or both.

[0059] In one or more implementations, in 955, the ratio / percentage / number of instructions (or groups / subgroups of instructions) executed in the second processing pipeline or the second execution unit or both is compared to a second threshold. For example, the ratio or percentage or both of the first subgroup of instructions processed / executed in the second processing pipeline or the second execution unit or both, e.g., store instructions, dual-port load instructions, branch instructions, SX instructions executed by the SX unit in the Store / Branch / Simple pipe, is compared to the second threshold, where the second threshold may be, for example, 15%, 25%, or 35%. In another embodiment, the number "N" of the first subgroup of instructions processed / executed in the first processing pipeline or the first execution unit or both, e.g., multicycle arithmetic instructions executed by the SX unit in the Store / Branch / Simple pipe, is compared to the second threshold, where the second threshold may be, for example, the 15th, 32nd, 45th, or 50th of 64 instructions executed by the processor or processing slice or both, at fixed or rolling intervals, or a combination thereof. The second threshold may differ from the example above, and it should be understood that the second threshold may be fixed, predetermined, programmable, adjustable, or a combination thereof, and may depend in part on processor and design considerations. In one embodiment, comparing the ratio / percentage / number of instructions (or groups / subgroups of instructions) executed in the second processing pipeline or the second execution unit or both to the second threshold at 955 provides a baseline workload for the second processing pipeline or the second execution unit or both, below which instruction types, e.g., simple arithmetic instructions, are processed in the second processing pipeline or the second execution unit or both, and above which the processor executes instruction types, e.g., simple arithmetic instructions, in the first processing pipeline or the first execution unit or both.

[0060] In step 945, after comparing the workload of the first processing pipeline or the first execution unit or both with that of the second processing pipeline or the second execution unit or both (for example, in step 950 / 955, after comparing the ratio / percentage / number of instructions (or groups of instructions) executed in the first and second processing pipelines or the first and second execution units or both with the first and second thresholds), process 900 proceeds to step 960, in accordance with one or more approaches, to select the first or second processing pipeline or the first or second execution unit or both to execute a first type of instruction, such as a simple arithmetic instruction, based on the workload of the first and second pipelines or the first and second execution units or both.

[0061] In one example, in the 960, a first processing pipeline (e.g., a Compute pipe) or a first execution unit (e.g., an FX unit), or both, is selected to process a first type of instruction, e.g., a simple arithmetic instruction, in response to the workload of the first processing pipeline or the first execution unit, or both (e.g., determined in the 925 / 950) being below a first threshold, e.g., less than 20%. The first threshold may be different from the 20% example above, and it may be understood that the first threshold may be a fixed, predetermined, programmable, or adjustable ratio / percentage / number, or a combination thereof, and may be partially dependent on the processor and design configuration. In another embodiment, in 960, a second processing pipeline (e.g., a Store / Branch / Simple pipe) or a second execution unit (e.g., an SX unit) or both are selected to process / execute a first type of instruction, e.g., a simple arithmetic instruction, in response to the workload of the first processing pipeline or the first execution unit or both (e.g., determined by 925 / 950) exceeding a first threshold, e.g., more than 20%, and the workload of the second processing pipeline or the second execution unit or both (e.g., determined by 940 / 955) being below a second threshold, e.g., less than 15%. The second threshold may be different from the 15% example above, and it may be understood that the second threshold may be a fixed, predetermined, programmable, or adjustable ratio / percentage / number, or a combination thereof, and may be partially dependent on the processor and design configuration. As stated above, it may be further understood that the first and second thresholds may be expressed as numerical values ​​instead of ratios or percentages.

[0062] Alternatively, or additionally, or both, in 960, a first or second processing pipeline, or a first or second execution unit, or both, may be selected to execute a first type of instruction, such as a simple arithmetic instruction, based on the workload of only the first or second or both pipelines, or the workload of only the first or second or both execution units, or both. For example, in 960, a first or second processing pipeline, or a first or second execution unit, or both, may be selected to execute a type of instruction based on the workload of only the first processing pipeline / execution unit, or the workload of only the second processing pipeline / execution unit. According to one embodiment, in the 960, a second processing pipeline (e.g., a Store / Branch / Simple pipe) or a second execution unit (e.g., an SX unit), or both, executes an instruction of a certain type, e.g., a simple arithmetic instruction, in response to the first processing pipeline (e.g., a Compute pipe) or a first execution unit (e.g., an FX unit), or both, processing / executing a second subgroup of instructions exceeding a third threshold, e.g., matrix multiplication accumulator (MMA) instructions. Since MMA instructions generally require a lot of computational resources, when the first processing pipeline or a first execution unit (e.g., an FX unit), or both, are executing MMA instructions exceeding the third threshold, the processor processes a first type of instruction, e.g., a simple arithmetic instruction, in the second processing pipeline or a second execution unit, or both.

[0063] The third threshold could be, for example, 5%, 10%, or 15%. In another example, the third threshold could be, for example, the 5th, 15th, or 25th of the fixed or rolling intervals of 64 instructions executed by the processor or / or a processing slice. It should be understood that the third threshold may differ from the examples above, and that it may be fixed, predetermined, programmable, adjustable, or a combination thereof, and may depend in part on the processor and design considerations. It should be understood that multiple conditions or criteria or both may be set in determining which processing pipeline or execution unit or both may be selected in the 960 to execute a first type of instruction that can be executed in one or more processing pipelines or execution units or both. Therefore, it should be understood that one or more of the criteria / conditions discussed above may be used alone, in various combinations, or both to select different processing pipelines or execution units or both.

[0064] Therefore, the blocks in a flowchart diagram support combinations of means for performing a specified function, combinations of steps for performing a specified function, and program instructions for performing a specified function. It will also be understood that each block in a flowchart diagram, and combinations of blocks in a flowchart diagram, can be implemented by a special-purpose hardware-based computer system that performs a specified function or step, or by a combination of special-purpose hardware and computer instructions.

[0065] The present invention may be a system, method, or computer program product or combination thereof, integrated at any possible level of technical detail. The computer program product may include a computer-readable storage medium storing computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0066] A computer-readable storage medium can be a tangible device capable of holding and storing instructions used by an instruction execution device. A computer-readable storage medium may, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or a suitable combination thereof. More specific examples of computer-readable storage media include portable computer diskettes, hard disks, RAM, ROM, EPROM (or flash memory), SRAM, CD-ROM, DVD, memory stick, floppy disk, punch cards, or grooved raised structures, and mechanically encoded devices on which instructions are recorded, and suitable combinations thereof. The computer-readable storage medium as used herein should not be interpreted as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.

[0067] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof). The network consists of copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. The network adapter card or network interface of each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage on the computer-readable storage medium within each computing / processing device.

[0068] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as SmAlltAlk and C++, and procedural programming languages ​​such as the C programming language or similar programming languages. The computer-readable program instructions are executable as a standalone software package, either entirely on the user's computer or partially on the user's computer. Alternatively, they may be executable partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer-readable program instructions by personalizing them using state information of computer-readable program instructions in order to perform aspects of the present invention.

[0069] Aspects of the present invention are described herein with reference to flowcharts or block diagrams, or both, of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in a flowchart or block diagram, or both, and any combination of blocks in a flowchart or block diagram, or both, can be implemented by computer-readable program instructions.

[0070] These computer-readable program instructions can be provided to a general-purpose computer, a dedicated computer processor, or other programmable data processing device to generate a machine, such that instructions executed via the processor of a computer or other programmable data processing device generate means for implementing functions / operations specified in one or more blocks of a flowchart or block diagram or both. These computer-readable program instructions can also be stored in a computer-readable storage medium that can be connected to a computer, a programmable data processing device, or other device or combination of devices that function in a particular way, such that the computer-readable storage medium on which the instructions are stored constitutes one of the outputs containing instructions that implement the modes of function / operations specified in one or more blocks of a flowchart or block diagram or both.

[0071] Computer-readable program instructions, like instructions that perform a function / action specified in one or more blocks of a flowchart or block diagram or both on a computer, other programmable device, or other device, can also be loaded into a computer, other programmable data processing device, or other device and perform a series of operational steps on the computer, other programmable device, or other device to produce a computer-implemented process.

[0072] The flowcharts and block diagrams in the figures illustrate the configuration, function, and operation of executable implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction, which constitutes one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions shown in the blocks may differ from the order shown in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or the blocks may be executed in reverse order depending on the functions they relate to. It should also be noted that each block in a block diagram or flowchart, or both, and any combination of blocks in a block diagram or flowchart, or both, can be implemented by a special-purpose hardware-based system that performs a specified function or operation, or a combination of special-purpose hardware and computer instructions.

[0073] Furthermore, systems according to various embodiments may include a processor and logic that is integrated with the processor, or executable by the processor, or both, and the logic is configured to perform one or more process steps described herein. Integrated with the processor means that the processor has logic incorporated as hardware logic, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc. Executable by the processor means that the logic is hardware logic, software logic, such as firmware, part of an operating system, part of an application program, or a combination of hardware and software logic that is accessible by the processor and configured to cause the processor to perform some function when executed by the processor. The software logic may be stored in local memory or remote memory or both of any memory type, as known in the art. Any processor known in the art may be used, such as a software processor module or a hardware processor, such as an ASIC, FPGA, central processing unit (CPU), integrated circuit (IC), graphics processing unit (GPU), or a combination thereof.

[0074] It should be clear that by combining various features of the aforementioned systems, methodologies, or both in any way, multiple combinations can be created from the explanations presented above.

[0075] It will be further understood that embodiments of the present invention may be provided in the form of a service deployed on behalf of the customer to provide services on demand.

[0076] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive, nor are they intended to limit the disclosed embodiments. It will be apparent to those skilled in the art that many modifications and changes are possible without departing from the scope of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, their practical application to market-based technologies, or technical improvements, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. A processor for processing information, wherein the processor is At least two processing pipelines, each having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline among the at least two processing pipelines are capable of executing a first instruction type, The system includes an instruction decoding unit that decodes an instruction for determining whether to execute the first instruction type in the first processing pipeline or the second processing pipeline, The aforementioned processor, Calculate at least one of the first processing pipeline workload, the second processing pipeline workload, and a workload group consisting of a combination thereof, Selecting a first or second processing pipeline that executes the first instruction type based on at least one of the aforementioned workload groups, It is configured to perform, Selecting the first processing pipeline or the second processing pipeline based on at least one of the aforementioned workload groups is: Calculating the workload of the first processing pipeline, Calculating the workload of the second processing pipeline, Comparing the workload of the first processing pipeline with a first threshold, The second processing pipeline workload is compared with a second threshold, In response to the first processing pipeline workload being less than or equal to the first threshold, or both the first processing pipeline workload exceeding the first threshold and the second processing pipeline workload being greater than or equal to the second threshold, the first processing pipeline is selected to execute the first instruction type. In response to both the first processing pipeline workload exceeding the first threshold and the second processing pipeline workload being less than the second threshold, the second processing pipeline is selected to execute the first instruction type. Executing the first instruction type in the selected first processing pipeline or the second processing pipeline, A processor that includes this.

2. The processor according to claim 1, wherein calculating the first processing pipeline workload includes counting the number of at least first subgroups of instructions executed in the first processing pipeline.

3. A processor for processing information, wherein the processor is At least two processing pipelines, each having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline among the at least two processing pipelines are capable of executing a first instruction type, The system includes an instruction decoding unit that decodes an instruction for determining whether to execute the first instruction type in the first processing pipeline or the second processing pipeline, The aforementioned processor, Calculate at least one of the first processing pipeline workload, the second processing pipeline workload, and a workload group consisting of a combination thereof, Selecting a first or second processing pipeline that executes the first instruction type based on at least one of the aforementioned workload groups, Calculating the workload of the first processing pipeline, Calculating the workload of the second processing pipeline, It is configured to perform, Calculating the workload of the first processing pipeline is Counting the number of at least a first subgroup of instructions executed in the first processing pipeline, Counting all the instructions executed by the at least two processing pipelines, The proportion of the first subgroup of instructions executed in the first processing pipeline is determined based on the number of the first subgroup of instructions, all the instructions executed by the at least two processing pipelines, and at least one group consisting of combinations thereof. A processor that includes this.

4. The processor according to claim 1, wherein calculating the workload of the second processing pipeline includes counting the number of at least a second subgroup of instructions executed in the second processing pipeline.

5. A processor for processing information, wherein the processor is At least two processing pipelines, each having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline among the at least two processing pipelines are capable of executing a first instruction type, The system includes an instruction decoding unit that decodes an instruction for determining whether to execute the first instruction type in the first processing pipeline or the second processing pipeline, The aforementioned processor, Calculate at least one of the first processing pipeline workload, the second processing pipeline workload, and a workload group consisting of a combination thereof, Selecting a first or second processing pipeline that executes the first instruction type based on at least one of the aforementioned workload groups, Calculating the workload of the first processing pipeline, Calculating the workload of the second processing pipeline, It is configured to perform, Calculating the workload of the second processing pipeline is Counting the number of at least a second subgroup of instructions executed in the second processing pipeline, Counting all the instructions executed by the at least two processing pipelines, The proportion of the second subgroup of instructions executed in the second processing pipeline is determined based on the number of the second subgroup of instructions, all the instructions executed by the at least two processing pipelines, and at least one group consisting of combinations thereof. A processor that includes this.

6. A processor for processing information, wherein the processor is At least two processing pipelines, each having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline among the at least two processing pipelines are capable of executing a first instruction type, The system includes an instruction decoding unit that decodes an instruction for determining whether to execute the first instruction type in the first processing pipeline or the second processing pipeline, The aforementioned processor, Calculate at least one of the first processing pipeline workload, the second processing pipeline workload, and a workload group consisting of a combination thereof, Selecting a first or second processing pipeline that executes the first instruction type based on at least one of the aforementioned workload groups, It is configured to perform, Selecting the first processing pipeline or the second processing pipeline based on at least one of the workload groups includes comparing the workload of the first processing pipeline with the workload of the second processing pipeline. Selecting the first processing pipeline or the second processing pipeline based on at least one of the workload groups comprises calculating the workload of the first processing pipeline and comparing the workload of the first processing pipeline to a first threshold, wherein the first threshold is at least one of a first threshold group consisting of numbers, percentages, ratios, and combinations thereof, in a processor.

7. Selecting the first processing pipeline or the second processing pipeline based on at least one of the aforementioned workload groups is: The processor according to claim 6, comprising selecting the first processing pipeline to execute the first instruction type in response to the first processing pipeline workload being less than the first threshold.

8. The processor according to claim 1, wherein the calculation of the first processing pipeline workload and the calculation of the second processing pipeline workload are performed over fixed or rolling "N" instruction intervals.

9. A processor for processing information, wherein the processor is At least two processing pipelines, each having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline among the at least two processing pipelines are capable of executing a first instruction type, The system includes an instruction decoding unit that decodes an instruction for determining whether to execute the first instruction type in the first processing pipeline or the second processing pipeline, The aforementioned processor, Calculate at least one of the first processing pipeline workload, the second processing pipeline workload, and a workload group consisting of a combination thereof, Selecting a first or second processing pipeline that executes the first instruction type based on at least one of the aforementioned workload groups, Calculating the workload of the first processing pipeline, Calculating the workload of the second processing pipeline, It is configured to perform, A processor that calculates the first processing pipeline workload, further comprising: counting the number of at least first subgroups of instructions executed in the first processing pipeline; counting the number of third subgroups of instructions executed in the first processing pipeline; determining whether the number of third subgroups of instructions exceeds a third threshold; and, in response to whether the number of third subgroups of instructions executed in the first processing pipeline exceeds the third threshold, selecting the second processing pipeline that executes the first instruction type.

10. The processor according to claim 1, wherein the first instruction type is a simple arithmetic instruction.

11. A processor for processing information, The processor includes at least one superslice comprising two execution slices, each execution slice comprising a processing pipeline capable of executing at least two first instruction types, wherein the first processing pipeline is a Compute pipe having arithmetic logic unit (ALU) execution units configured to execute simple arithmetic instructions, and the second processing pipeline is a Store / Branch / Simple pipe having simple (SX) execution units configured to execute at least simple arithmetic instructions, wherein the first instruction type is a simple arithmetic instruction. The system includes an instruction decoding unit for decoding instructions to determine whether to execute the first instruction type in the first processing pipeline or the second processing pipeline, the instruction decoding unit including a first counter for counting the number of first subgroups of instructions, the first subgroups of instructions including at least multi-cycle arithmetic instructions executed in the Compute pipeline, The aforementioned processor, Using the first counter, the number of the first subgroups of instructions is counted, Comparing the number of the first subgroup of instructions with a first threshold, Selecting the Compute pipe to execute the simple arithmetic instruction in response to the number of the first subgroup of instructions being less than the first threshold, In response to the first subgroup of instructions being greater than or equal to the first threshold, the Store / Branch / Simple pipe is selected to execute the simple arithmetic instructions, Executing the simple arithmetic instruction in the selected Compute pipe or Store / Branch / Simple pipe, A processor configured to perform the following actions.

12. The instruction decoding unit further, A second counter for counting the number of second subgroups of instructions executed within the Store / Branch / Simple pipe, wherein the second subgroup of instructions includes at least one of store instructions, dual-port load instructions, branch instructions, SX instructions, and simple groups consisting of combinations thereof. The system comprises a third counter for counting the number of instructions processed by at least one superslice, The aforementioned processor, Based on the number of the first subgroup of instructions executed in the Compute pipe pipeline and the number of instructions counted by the third counter, a first ratio of the first subgroup of instructions executed in the Compute pipe is calculated. Using the second counter, the number of the second subgroup of instructions is counted, Based on the number of instructions in the second subgroup executed by the Store / Branch / Simple pipe and the number of instructions counted by the third counter, a second ratio of the second subgroup of instructions executed by the Store / Branch / Simple pipe is calculated. Comparing the first ratio with a first ratio threshold, Comparing the aforementioned second ratio with a second ratio threshold, In response to the first ratio being less than the first ratio threshold, or the second ratio being greater than or equal to the second ratio threshold, select the Compute pipe that executes the simple arithmetic instruction, In response to the first ratio being greater than or equal to the first ratio threshold, and further in response to the second ratio being less than the second ratio threshold, select the Store / Branch / Simple pipe that executes the simple arithmetic instruction, Configured to perform, The processor according to claim 11.

13. The instruction decoding unit further, A fourth counter for counting the number of third subgroups of instructions executed within the Compute pipe, wherein the third subgroup of instructions includes at least one of matrix multiplication accumulator instructions, and the fourth counter includes: The aforementioned processor, Using the fourth counter, the number of the third subgroup of instructions is counted, Calculating a third ratio of the third subgroup of instructions executed in the Compute pipe based on the number of instructions in the third subgroup of instructions executed in the Compute pipe of the superslice, the number of instructions counted by the third counter, and at least one of the groups consisting of combinations thereof, Comparing the aforementioned third ratio with the third ratio threshold, Regardless of the comparison between the first ratio and the first ratio threshold, or the comparison between the second ratio and the second ratio threshold, in response to the third ratio exceeding the third ratio threshold, select the Store / Branch / Simple pipe that executes the simple arithmetic instruction, The processor according to claim 12, configured to perform the following:

14. A method for processing information with a processor, wherein the method is To provide at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline of the at least two processing pipelines are capable of executing a first instruction type. Calculate at least one of the first processing pipeline workload, the second processing pipeline workload, and a workload group consisting of a combination thereof, Selecting a first or second processing pipeline that executes the first instruction type based on at least one of the aforementioned workload groups, Includes, Calculating the first processing pipeline workload includes counting the number of at least a first subgroup of instructions executed in the first processing pipeline, Calculating the workload of the second processing pipeline includes counting the number of at least a second subgroup of instructions executed in the second processing pipeline, The above method further, Counting the number of at least third subgroups of instructions executed in the first processing pipeline, which are different from the first subgroup of instructions, Selecting the first processing pipeline to execute the first instruction type in response to the third subgroup of instructions being less than or equal to a third threshold and the first processing pipeline workload being less than or equal to a first threshold, or both of the first processing pipeline workload exceeding the first threshold and the second processing pipeline workload being greater than or equal to a second threshold, In response to the fact that the number of at least the third subgroup of instructions exceeds the third threshold, and the workload of the first processing pipeline exceeds the first threshold and the workload of the second processing pipeline is less than the second threshold, the second processing pipeline is selected to execute the second instruction type, Executing the first instruction type in the selected first processing pipeline or the second processing pipeline, Methods that include...

15. A method for processing information with a processor, wherein the method is: To provide at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline of the at least two processing pipelines are capable of executing a first instruction type. Calculate at least one of the first processing pipeline workload, the second processing pipeline workload, and a workload group consisting of a combination thereof, Selecting a first or second processing pipeline that executes the first instruction type based on at least one of the aforementioned workload groups, Includes, Calculating the first processing pipeline workload includes counting the number of at least a first subgroup of instructions executed in the first processing pipeline, The above method further, A method comprising selecting the first processing pipeline to execute the first instruction type in response to the first processing pipeline workload being less than a first threshold.

16. Calculating the workload of the second processing pipeline includes counting the number of at least a second subgroup of instructions executed in the second processing pipeline, The above method further, This includes selecting the second processing pipeline that executes the first instruction type in response to the first processing pipeline workload being greater than or equal to a first threshold and the second processing pipeline workload being less than a second threshold, The method according to claim 15.

17. A computer program comprising program code adapted to perform the method described in any one of claims 14 to 16 when the computer program is executed on a computer.

Images