Area-efficient high-speed sequence generator and error tester

Abstract

To provide a compact combined error checker and combined PRBS sequence generator which shares an LFSR and reduces complexity, cost and area required for implementation.SOLUTION: In a communication system, control logic selects different modes of operation. An error detector compares two sequence signals and records errors in response to differences between the two sequence signals. A sequence signal generator generates a sequence signal for use by the error detector as a reference sequence signal or for transmission to a remote transceiver. The system includes one or more switching elements configured to selectively route the generated sequence as feedback into the sequence generator or the received sequence signal into the sequence generator in accordance with whether the combined error checker and sequence generator is in an error checker mode or in a sequence generator mode.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] 1. Technical Field The present invention relates to a sequence generator and an error checker, and particularly to a compact composite PRBS sequence generator and an error checker.

Background Art

[0002] 2. Background Art [[ID=z16]]Functionalities and complexities are constantly added to communication systems. To improve test efficiency, end users require built-in diagnostic functions for quickly debugging the system without the need to deploy and connect complex and expensive test equipment. In data centers, this means breaking low-performance links, injecting known data patterns such as a pseudo-random bit sequence (PRBS) generator, and checking for bit errors at various locations to properly debug the links.

[0003] Industrial standards such as IEEE802.3bs / cd define the PRBS13Q generation polynomial as 1+x+x +x 12 +x 13 However, other polynomials may be used for other applications. The most common circuits for PRBS generators and checkers are based on multiplexers (MUX) / demultiplexers (DEMUX) or linear feedback shift registers (LFSR), respectively. Pseudo-random bit sequence (PRBS) generators and error checkers are essential parts of many wired and wireless communication circuits for checking the accuracy of signal chain functions. The generator generates patterns (sequence signals) and transmits these patterns over the channel. At the receiving end, the checker checks whether there are errors in the received signal.

[0004] In conventional technology, sequence generators and error checkers are separate modules within each channel path of an integrated circuit. Some PRBS generation polynomials need to be implemented in circuits with exclusive OR (XOR) gates that have multiple inputs. In designs where area is a critical factor, implementing PRBS generators and checkers requires a considerable amount of area, and the numerous devices reduce the timing margin.

[0005] Figure 1 shows a conventional transceiver having separate sequence generators and error checkers. This embodiment is an optical environment having a lower transmit path and an upper receive path, both on a space-limited die 104. Referring to the lower path, differential inputs 108A, 108B receive the outgoing signal for transmission. Input 108 is connected to an equalizer 112 that performs signal equalization before transmission. The output of the equalizer 112 is provided to one or more buffers 116, which are connected to a clock and data recovery circuit (CDR) 120 and a multiplexer 128. A sequence generator 124 is also connected to the multiplexer 128 to provide the multiplexer with a pseudo-random sequence. The output of the multiplexer is connected to a driver 132 configured to present the outgoing signal on output 140. The error checker 136 receives the outgoing signal and is configured to perform error checking based on a comparison of the expected bit pattern with a known bit pattern (sequence) that may be generated by the sequence generator of the transmitting station.

[0006] Turning to the upper receiving path, input 150 receives an electrical signal converted from an optical signal. Input 150 is connected to a transimpedance amplifier (TIA) 154, which includes a feedback resistor 156. The output of the TIA 154 is connected to an analog front-end (AFE) circuit 160. The AFE circuit 160 is connected to a CDR 164 and a multiplexer 168. A sequence generator 172 also provides an input to the multiplexer 168. The multiplexer selectively outputs one of its inputs to a driver 172 based on a control signal, and the driver provides the received signal to differential outputs 180A, 180B and an error checker 176. The error checker 176 is configured to receive the outgoing signal and perform an error check based on a comparison of the expected bit pattern with a known bit pattern (sequence) that may be generated by the sequence generator of the transmitting station.

[0007] A drawback of this configuration, as mentioned above, is that the sequence generator and error checker are separate modules, with each path acting as both a sequence generator and an error checker. Therefore, there is circuit overlap. The composite PRBS generating polynomial is implemented using a circuit with an exclusive OR (XOR) gate having multiple inputs. In high-speed circuits operating above multi-gigahertz, XOR gates are area-inefficient and undesirably require a large number of transistors for implementation.

[0008] Figure 2 shows an exemplary circuit for implementing a two-input difference XOR gate in BICMOS. This figure is provided for illustrative purposes to help understand the number and complexity of transistors required to implement even a two-input XOR gate. The two inputs are A+ and A-, representing signal A and its inverted form. Similarly, the second signals are B+ and B-. Although this configuration is only a two-input difference XOR gate, its implementation is complex and requires 12 bipolar transistors as shown. A similar circuit structure for implementing an n-input XOR gate is 2 nIt requires (n+1) bipolar transistors. The number of transistors required increases almost exponentially as the number of inputs increases. A single 6-input XOR gate requires the use of 448 bipolar transistors, and conventional implementations of sequence generators require multiple 6-input XOR gates as well as numerous XOR gates with fewer inputs and additional circuit elements. The size, cost, and complexity of conventional sequence generators are enormous.

[0009] Furthermore, such a large number of elements can introduce excessive and undesirable parasitic capacitance, reducing the timing margin to an unacceptable level and, if left unaddressed, interfering with circuit operation. [Overview of the Initiative] [Means for solving the problem]

[0010] overview To overcome the shortcomings of the prior art and provide further advantages, a shared error tester and sequence generator are disclosed. In one embodiment, this shared error tester and sequence generator includes a sequence generator having a sequence generator input, a sequence generator output, and one or more feedback paths. The sequence generator is configured to generate a generated sequence signal. An error detector is configured to compare the received sequence signal with the generated sequence signal for the difference and record the difference as an error. Also part of this embodiment is an analog front end configured to receive and restore the received sequence signal from a remote transceiver. Control logic is configured to selectively establish the shared error tester and sequence generator in error tester mode or sequence generator mode.

[0011] In one configuration, the error detector comprises one or more XOR gates. The sequence generator may also comprise a core of a linear feedback shift register configured to generate a pseudo-random binary sequence. The shared error checker and sequence generator may include one or more switching elements configured to selectively send the generated sequence signal as feedback to the sequence generator, or the received sequence signal to the sequence generator. In one embodiment, the sequence generator comprises fewer than 70 transistors. The sequence generator may also comprise fewer than three 3-input XOR gates. In one configuration, the shared error checker and sequence generator are configured to output a sequence signal to be transmitted to a remote transceiver.

[0012] Also disclosed is an operating method for a shared error checker and sequence generator to evaluate the operation of a data communication system in a local transceiver. This method includes the steps of receiving a received sequence signal from a remote transceiver and generating a generated sequence signal in the local transceiver using the shared error checker and sequence generator. This method also includes the steps of providing the received sequence signal to the shared error checker and sequence generator and comparing the received sequence signal with the generated sequence signal using the shared error checker and sequence generator. Next, the shared error checker and sequence generator are used to generate an error count in response to the difference between the received sequence signal and the generated sequence signal.

[0013] In one embodiment, the shared error checker and sequence generator can be put into error checker mode or sequence signal generation mode using control logic. It is also disclosed that the error detector may comprise one or more XOR gates. The sequence generator may be the core of a linear feedback shift register configured to generate a pseudo-random binary sequence. The shared error checker and sequence generator may include one or more switching elements configured to selectively send a generated sequence signal as feedback to the sequence generator, or a received sequence signal to the sequence generator. In one embodiment, the sequence generator comprises fewer than 70 transistors. The sequence generator may comprise fewer than three 3-input XOR gates.

[0014] A composite error checker and sequence generator sharing a core of a linear feedback shift register is also disclosed. In one configuration, the system includes a clock and data recovery system configured to recover clock and data signals received via a channel from a remote transceiver. Part of the system also includes control logic configured to activate one of two or more operating modes of the composite error checker and sequence generator, as well as an error detector configured to compare two sequence signals and record an error in response to the difference between the two sequence signals. A sequence signal generator is provided and configured to generate sequence signals for use by the error detector as a reference sequence signal or for transmission to a remote transceiver.

[0015] The error detector may be formed from one or more XOR gates. In one embodiment, the core of the linear feedback shift register is configured to generate a pseudo-random binary sequence used by the error checker. The combined error checker and sequence generator may include one or more switching elements configured to selectively send the generated sequence signal as feedback to the sequence generator, or the received sequence signal to the sequence generator, depending on whether the combined error checker and sequence generator are in error checker mode or sequence generator mode. In one configuration, the core of the linear feedback shift register consists of fewer than 70 transistors. Furthermore, the sequence generator may consist of fewer than three 3-input XOR gates.

[0016] Other systems, methods, features, and advantages of the present invention will become apparent to those skilled in the art by examining the following drawings and detailed description. All such additional systems, methods, features, and advantages are contained within this description, fall within the scope of the present invention, and are intended to be protected by the appended claims.

[0017] Brief explanation of the drawing The elements in the drawings are not necessarily to scale; instead, the focus is on illustrating the principles of the invention. In the drawings, the same reference numbers indicate corresponding parts in different figures. [Brief explanation of the drawing]

[0018] [Figure 1] A conventional transceiver having separate sequence generators and error checkers is shown. [Figure 2] This shows an example circuit for implementing a two-input difference XOR gate in BICMOS. [Figure 3] This document illustrates an exemplary communication system having an area-efficient shared error checker and sequence generator. [Figure 4]FIG. 3 shows a block diagram of an exemplary embodiment of a composite sequence generator and error checker as shown. [Figure 5] FIG. 3 shows a block diagram of an exemplary embodiment of a control and feedback system for the core of a linear feedback shift register focused on error tracking. [Figure 6] FIG. 6 shows an exemplary block diagram showing an exemplary layout of control logic elements for an improved sequence generator, such as an improved linear feedback shift register (LFSR) core. [Figure 7] FIG. 9 shows a local transceiver and a remote transceiver connected via a channel. **DETAILED DESCRIPTION**

[0019] Detailed Description FIG. 3 shows an exemplary communication system having an area - efficient shared error checker and sequence generator. This is only one possible embodiment, and thus other configurations are possible without departing from the scope of the claims. Similar elements are identified by the same reference numbers as compared to FIG. 1. As shown in FIG. 3, a composite error checker and sequence generator 304 is associated with the receive path. The error checker and sequence generator 304 provides an input to the multiplexer 168 and receives a signal as an input from the driver 172. One or more control inputs 312 are provided to the receive path error checker and sequence generator 304 to control the input / output function and the internal mode of operation. A clock signal is also provided to the receive path error checker and sequence generator 304.

[0020] A combined error tester and sequence generator 308 is associated with the transmit path. The error tester and sequence generator 308 provides an output to the multiplexer 128 and receives an input from the driver 132. One or more control inputs 316 are provided to the transmit path error tester and sequence generator 308 to control the input / output function and the internal mode of operation. A clock signal may also be provided to the transmit path error tester and sequence generator 308. The receive path error tester, sequence generator 304, transmit path error tester, and sequence generator 308 may also be further integrated into a single element to further reduce area requirements, cost, and complexity. Thus, the combined device is shared between the transmit path and the receive path.

[0021] The configuration shown in Figure 3 overcomes the shortcomings of the prior art by requiring less space, reducing complexity, and providing improved timing margins compared to the prior art embodiment. The reduction in required space is achieved by sharing the linear feedback shift register and several related elements between the sequence generation function and the error checking function, and also by improving the design layout, as will be discussed in later figures.

[0022] Figure 4 is a block diagram of an exemplary embodiment of a composite sequence generator and error checker as shown in Figure 3. This is only one possible layout and arrangement of elements, and other configurations are possible without departing from the claims. Control logic 404 is shown as generally present and is distributed throughout the system to guide the operation of the various elements shown and described herein. A clock data recovery circuit (CDR) 408 receives a data signal at input 412. After recovering the clock and data, the CDR 408 provides the data to a demultiplexer 416 via a transmission line or equivalent trace 420. The clock signal is provided to a phase interpolator 426, which then distributes the clock signal to an error counter 430 and at least an LFSR (linear feedback shift register) core 434.

[0023] The data provided to the demultiplexer 416 is output as four low-rate data streams on output 438 based on the clock control signal. The low-rate data streams are provided to banks of LFSR core 434 and XOR gate 442. The LFSR core 434 processes the data as described in detail below to generate low-rate data output signals on data path 446. The low-rate output signals are provided to banks of one or more buffers 450 and XOR gate 442. Only one connection is shown to reduce graphic clutter with other connections shown as Q12, Q11, and Q10, and the connection is indicated by this notation. The outputs of one or more buffers 450 are provided as most significant bit and least significant bit outputs in PAM4 mode and as two independent streams in NRZ mode. The XOR gate 442 compares its two inputs to determine if there is a difference between the inputs to the XOR gate. Different inputs to the XOR gate 442 result in a logic 1 output indicating an error. The error counter 430 processes the output from the XOR gate 442 to track errors. The error count is output to the error output 454.

[0024] During operation, the received signal is supplied to the CDR408, which restores the clock and data signals. The data signal is sent to the banks of the LFSR core 434 and the two-input XOR gate 442. The LFSR core 434 processes the data to generate sequence signals (pattern signals), such as the PRBS signal, which is returned to the bank of the XOR gate 442 and functions as a second input. The difference between the data input to the LFSR core 434 (received sequence signal) and the sequence signal generated by the LFSR core is recorded as an error by the error counter 430. Errors can be processed by an on-chip processor or an external processor to optimize system performance or diagnose problems. The output of the buffer 450 is supplied to the MUX168 or 128, or any signal path requiring performance optimization or error detection.

[0025] Figure 5 shows a block diagram of an exemplary embodiment of a control and feedback system for an LFSR core focused on error tracking. For simplicity, only half of the circuit is drawn, and many details are omitted. The restored clock signal from the clock restore module 508 is distributed throughout the circuit, as is the control logic 404, both of which are generally shown. The restored data from the data restore module 504 is deserialized, as shown, and distributed to four multiplexers 512. The multiplexers 512 also receive feedback signals from the LFSR core 434 as a second input. In response to the control signal, the multiplexers 512 select either the tester open-loop mode CDR output 514 or the tester closed-loop mode and generator mode feedback signal 513 as their output.

[0026] A feedback signal from the LFSR core 434 is also provided to the error detector 516. The error detector 516 compares the received data with the sequence signal generated by the LFSR core 434 and detects the difference. The difference between the received signal and the sequence generated by the LFSR core 434 is recorded as an error by the counter 520. The recovered data (which may be a sequence signal received from a remote transceiver) is assumed to be the same as, or should be the same as, the sequence signal generated by the LFSR core. By comparing a known sequence signal transmitted from a remote transmitter with the same sequence generated at the local receiver, errors can be detected to reveal problems with the operation of the remote transmitter, the local receiver, or the channel. Parallel branching can be used to reduce the effective data rate for processing to 1 / 2 or 1 / 4, enabling the use of less expensive integrated circuit technology. Parallel-series and series-parallel converters may be used for this function.

[0027] The LFSR core 434, described in more detail below, is configured to generate sequence signals. The LFSR core is split into two or more paths to enable lower-rate systems. The output of the LFSR core 434 is also provided to a multiplexer 530, which combines the low-rate data streams into a full-rate data stream and provides it to one or more output buffers 534. The resulting full-rate data stream is provided to the signal path for system optimization or error detection. The data rate can be further reduced by additional processing paths. A consideration of the operation of the system in Figure 5 is described below.

[0028] Figure 6 is an exemplary block diagram showing an exemplary control logic element layout for an improved sequence generator, such as an improved linear feedback shift register (LFSR) core. This is only one possible configuration, and other configurations that also benefit from the advances shown in Figure 6 are possible. The layout concept illustrated by the example in Figure 6 offers a significant reduction in area and improvement in timing margins compared to prior art embodiments, such as those referenced in the background section. Where necessary, only a single path is described to avoid repetition of explanation.

[0029] Starting at a high level, the LFSR600 is shared between the error checker and the sequence generator, as shown in Figure 3. The MUX622 has inputs 604, 608, 612 and outputs 616, 620. The inputs include a feedback or remapped NRZ (non-return-to-zero) (PAM2) input 604, a feedback PAM4 input 608, and retiming and deserialized data streams 612 from an external source such as inputs 1a, 1b, 2a, 2b shown in Figure 4 from the demultiplexer 416 (Figure 4). The NRZ input 604 is used when the system is in NRZ mode. The PAM4 input 608 is used when the system is in PAM4 mode. The differential data stream 612 is used when the system is in error check mode. When the LFSR core is in generator mode, the multiplexer 622 selects the feedback signal 608. When the LFSR core is in PAM4 tester open-loop mode, multiplexer 622 selects external input 612. When the LFSR core is in NRZ tester open-loop mode, the lower two multiplexers 622 select external input 612. The upper two multiplexers select the NRZ signal from the remapped LFSR register. In tester closed-loop mode, multiplexer 622 first selects input 612 to initialize the LFSR core register. After all registers are loaded, multiplexer 622 switches to generator mode. As shown in the figure, the NRZ path through NRZ XOR gate 670 is shown as connecting to 3-to-1 multiplexer 674. Several 3-to-1 multiplexers are shown, each with an output connecting to a D flip-flop element or register such as register X1 624. The upper path will be discussed later.

[0030] The PAM4 feedback 608 and the retiming and deserialized input data 612 are supplied to a two-input XOR gate 634, which functions as an error checker. The XOR gate 634 compares the two inputs and outputs a logic value of 1 indicating an error if the inputs are different, and a logic value of 0 indicating no error (no difference between the two inputs) if the inputs are the same. The output of the XOR gate 634 may be supplied to an error counter, such as the error counter 430 shown in Figure 4. Other paths generally operate similarly and are therefore not described.

[0031] The output of multiplexer 622 is provided to register X1 624, which functions as memory and delay. Register X1 624, as shown in the figure, provides to register X5 626 and generates an output that is fed back to the two-input XOR gate 626 and the three-input XOR gate 638, as well as XOR gates 640 and 642. For simplicity in Figure 6, many feedback paths have been omitted, and numerical notation is used to identify the feedback paths. For example, register X1 624 feeds back to all XOR gates that have a 1 before its input. The output of register X5 is provided as an input to register X9 628 and is fed back to function as an input to all XOR gates labeled 5, as indicated by feedback path 644. The output of register X9 628 is provided as an input to register X13 630 and is fed back as an input to all XOR gates that have an input labeled 9. The output of register X13 is provided as an input to multiplexer 632. The same notation is followed for the other paths shown in Figure 6. To avoid redundancy, individual paths and feedback loops will not be described in detail.

[0032] Returning to XOR gate 636, its output is supplied to flip-flop 646, and the output of the flip-flop is supplied to another XOR gate 648. The output of XOR gate 648 is supplied to flip-flop 650. As is understood in the art, flip-flops 646 and 650 delay the signals by one or more clock cycles to maintain clock alignment and timing margins. Numerous other flip-flops are shown in Figure 6 but are not described in detail. The output of flip-flop 650 is supplied as an input to a 3-input XOR gate 638. The other two inputs to XOR gate 638 are feedback signals from registers X1 624 and X2 654.

[0033] The two lower paths generate output 620 from multiplexer 658. Multiplexers 616 and 620 provide conversion from half rate to full rate. Outputs 616 and 620 provide signals such that there are two streams for PAM4 (defining a 4-level signal) and one output for NRZ (defining a 2-level signal). To aid understanding, as shown in Figure 4, outputs 616 and 620 correspond to outputs from buffer 450. The parallel sequence generator and tester can have many parallel branches configured to operate at 1 / 2, 1 / 4, and 1 / 8 data rates. It can also have multiple outputs for NRZ and PAM4 signals.

[0034] Timing margins are degraded by delays in wiring and XOR gates. However, the LFSR core is clock-based. The D flip-flop retimings the feedback signal to restore the timing margin to approximately the same amount as the delay of a single 3-input XOR gate. This is a significant improvement over prior art. A signal "xn" delayed by one register is "xn+4". A signal "xn" delayed by two registers is "xn+8". Therefore, the feedback loop in the first row of Figure 6 achieves x1+x2+x9+x11+x12+x13 with only one XOR gate delay plus one multiplexer delay. The XOR gate in the feedback loop requires only 68 bipolar transistors. If the feedback loop were implemented with a 6-input XOR gate, 448 bipolar transistors would be required. Therefore, the disclosed configuration and method not only reduces the area to 15% of the original, but also limits the delay in the feedback loop to one XOR gate delay plus one multiplexer delay plus interconnection delay. This represents a significant improvement over prior art. As a result, the embodiment shown in Figure 6 improves timing margins and reduces the area required for implementation.

[0035] Furthermore, in this embodiment, the maximum number of inputs to any XOR gate is limited to three, which significantly reduces the required implementation area. The flip-flop samples and retiming the output of the XOR gate in the feedback loop to restore the timing margin. The search algorithm performed in this design demonstrates that if the initial state of the flip-flop in the feedback loop is properly reset, it does not affect the LFSR as a generator or tester. The retiming stage in the LFSR feedback loop reduces area and improves the timing margin.

[0036] In Figure 6, the total number of bipolar transistors in the circuit required to implement the 6-input XOR gate function is 68, which is far fewer than the 448 transistors required for the one-stage solution. Simulations of other embodiments, such as the direct cascade method, show only a timing margin of 3 picoseconds at 58 Gbps in typical corners. The embodiment shown in Figure 6 has a timing margin of 10.5 picoseconds under the same simulation conditions.

[0037] In area-prioritized designs, supporting both non-return-two-zero (NRZ) PRBS13 generators and inspectors and PAM4 PRBS13 generators and inspectors makes area constraints more challenging. Therefore, we discuss two other methods for reducing the required area.

[0038] The first method is to remap the registers in Figure 6 to avoid the extra area cost of the NRZ LFSR core. While the NRZ generator does not require extra circuitry, the LFSR core for the NRZ tester is different from that for pulse amplitude modulation 4 levels (PAM4). In NRZ tester mode, there is only one input stream, different from the two input streams of PAM4. The NRZ input stream can be deserialized into 2 or 4 streams. This results in a 1 / 4 rate when deserialized into 4 streams, which requires another phase interpolator (PI) to synchronize the data and clock. The remapping allows for the reuse of all DFFs within the PAM4 LFSR core without an extra PI, as the core still operates at half rate. This is a more area-efficient method. The remapping is shown in Figure 6.

[0039] The generated sequence signal may be of any type. From a circuit implementation perspective, 1+x+x 2 +x 12 +x 13The generating polynomial defined as is more difficult than some higher-order generating polynomials and is used here to discuss design methods. High-speed applications prefer parallel structures that allow the LFSR core to operate at lower speeds. In a 4-branch parallel PRBS13 LFSR core, the feedback loop to register x1 is,

[0040]

number

[0041] Here, q'1 is the next state of register x1, and q1 is the current state of register x1. This feedback loop requires a 6-input XOR gate. Furthermore, since register x1 itself also appears as an input to the feedback loop, the procedure for retiming it with a D flip-flop becomes complicated.

[0042] In a bipolar difference embodiment, an n-input XOR gate is typically (n+1)2 n It requires 100 bipolar transistors. Therefore, the area of ​​a 6-input XOR gate is not only 37 times larger than that of a 2-input XOR gate, but its parasitic input and output capacitances also become bottlenecks for high-speed operation. Cascading 3-input and 2-input XOR gates reduces the area, but worsens the timing margin by introducing extra delay into the feedback loop.

[0043] Moving on from the layout and hardware of exemplary embodiments of the present invention, a description of the advantages over the prior art and operation is provided. In this disclosure, two methods are used to reduce the area required to implement the PRBS two-value and four-value generators and testers. The first technique is to use a shared sequence signal generation core. As shown in Figure 3, a shared linear feedback shift register (LFSR) core is used for the generator and tester. Since the core occupies most of the area in the generator and the tester shares the sequence signal generation core, the area of ​​the majority area-consuming portion is halved. The second method is to implement multi-input XOR gate functionality with two-input and three-input XOR gates and retiming the intermediate output with a D flip-flop. The second method also improves the timing margin to allow the sequence signal generator and error tester to operate at higher frequencies.

[0044] During operation, a shared system with a shared LFSR core can be used in either sequence generator mode or error checker mode. The operation is described in more detail below.

[0045] Operation in sequence generator mode The system may be used in sequence generator mode to generate sequence signals used to verify the operation of specific local transmit functions, channel characteristics, and remote receiver functions. This is best understood in relation to Figure 7, which shows a local transceiver 704 and a remote transceiver 708 connected via channel 712. In sequence generator mode, the combined error checker and sequence generator 308A generate sequence signals and transmit them from the local transceiver 704 to the remote transceiver 708 via channel 712. At the remote transceiver 708, the sequence signals are received and processed as would be done for data.

[0046] Similarly, the combined error checker and sequence generator 308B generates a sequence signal and transmits it from the remote transceiver 708 to the local transceiver 704 via channel 712. The local transceiver 704 receives the sequence signal and processes it as would be done for data.

[0047] In both scenarios, to verify the operation of the transmitter and receiver processing and to evaluate the channel, an identical sequence signal is generated and compared to the received sequence transmitted from the opposing transceiver. The comparison is performed by a composite error checker and an error checker for the sequence generator, and errors are tracked and recorded.

[0048] In particular, the combined error tester and sequence generator 308A is placed in sequence generation mode to generate a sequence signal that is transmitted from the local transceiver 704 to the remote transceiver 708 via channel 712. At the remote transceiver 708, the received sequence signal is processed. At the remote transceiver 708, the combined error tester and sequence generator 308B is placed in sequence generation mode and generates the same sequence signal that is transmitted from the transceiver 704. The input sequence signal (from the local transceiver 704) is compared with the sequence signal generated by the combined error tester and sequence generator 308B at the remote transceiver 708. At the other station, the combined error tester and sequence generator transmits the generated sequence to the channel. After passing through the channel, the remote transmitter receives it as input. The CDR restores the clock and data and transmits them to the tester. In this case, the same LFSR core is used. The CDR handles the channel delay. To perform comparisons and track errors, the combined error tester and sequence generator 308B is placed into error testing mode. This process provides the transceiver with an internal, space-efficient sequence generator and error tester that can be used to evaluate and test the transmitter, channel, and receiver.

[0049] Operation in error checking mode As mentioned above, a combined error tester and sequence generator can also be placed in error tester mode to compare the input sequence signal with the received sequence signal to check for errors and record the errors in an error counter.

[0050] Operation Overview Referring to Figure 5, the multiplexer 530 combines the parallel LFSR outputs from the LSFR core 434 to generate a binary or quaternary PRBS output. The output buffer 534 buffers the output to drive the next stage circuit. In one embodiment, to conserve power, the multiplexer 530 and buffer 534 are powered on only when the generator mode is activated. To conserve power, the data restorer 504, multiplexer 512, error detector 516, and error counter 520 may be powered on only when the error tester mode is activated. The combined generator and tester share a clock restorer module 508.

[0051] The generator and tester circuits are controlled by the control logic block 404. The control logic block 404 can be configured in several different operating modes to enable the error tester mode and the sequence signal generator mode.

[0052] Generator-only mode One possible mode is the sequence signal generator-only mode. In the sequence signal generator-only mode, the LFSR core 434, multiplexer 530, buffer 534, clock restorer 508, and control logic 404 are powered on. Other components are powered off to reduce power consumption. In this operating mode, the clock restorer 508 may also be a local clock source.

[0053] Open-loop mode for the tester only The composite sequence generator and error checker may also operate in a checker-only open-loop mode. In checker-only open-loop mode, the feedback loop of the LFSR core 434 is opened by the multiplexer 512, and therefore the output of the LFSR core is directed only to the error detector 516. As a result, the only input to the multiplexer 512 is the output of the data recovery module 504, which enters the LFSR core, is processed by the LFSR core, and causes the feedback loop to generate new bits. The new bits are compared with the received data by the error detector 516 to detect errors. The error counter 520 counts and records the number of errors if errors are detected.

[0054] Closed-loop mode for the tester only The composite sequence generator and error tester may also operate in a tester-only closed-loop mode. In this mode, the feedback loop of the LFSR core 434 is closed by the multiplexer 512. As a result, the recovered data from module 504 enters the LFSR core 434 only during the synchronization phase. The synchronization phase is defined as the time when all registers in the LFSR core are loaded with error-free bits from the data recovery output. This step synchronizes the local LFSR core with the LFSR core of the remote transmitter. Data and clock recovery take into account the delay between the two LFSR cores. After synchronization, the multiplexer 512 switches to local feedback only from the LFSR core 434. New bits generated by the feedback loop are compared with the received (recovered) data to detect errors. Errors are detected by the error detector 516 and counted by the error counter 520. In the tester-only closed-loop mode, the multiplexer 530 and buffer 534 can be powered off.

[0055] Generator plus tester mode The combined sequence generator and error checker may also operate in generator-plus-checker mode. In generator-plus-checker mode, the feedback loop of the LFSR core 434 is closed. Received data from the data recovery module 504 enters the LFSR core 434 only during the synchronization phase. For example, in one embodiment, the LFSR core is a state machine whose output is determined solely by its current state. The system provides a receive sequence for initializing the LFSR core in checker mode. In one embodiment, the core has 13 registers, and the number of internal states is 2^13-1=8191. Thus, the sequence is 8191 bits long.

[0056] After synchronization, the multiplexer 512 switches to local feedback, resulting in an input to the LSFR core 434, which is a feedback signal. The resulting LFSR output is compared by the error detector 516 with the received data from the data recovery module 504 to detect errors. Data errors are recorded by the counter 512. During operation in generator-plus-tester mode, the multiplexer 530 and buffer 534 are powered on.

[0057] Low power mode The composite sequence generator and error tester may also operate in low-power mode. In low-power mode, only control logic 404 is powered on. After system optimization or diagnosis is complete, the PRBS generator and tester are not used by the system, and low-power mode helps conserve power and reduce temperature.

[0058] While various embodiments of the present invention have been described, it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the invention. Furthermore, the various features, elements, and embodiments described herein may be claimed or combined in any combination or arrangement.

Claims

1. A shared error checker and sequence generator, A sequence generator having a sequence generator input, a sequence generator output, and one or more feedback paths, configured to generate a sequence signal, An error detector configured to compare the received sequence signal with the generated sequence signal for the difference and record the difference as an error, An analog front end configured to receive and restore the received sequence signal from a remote transceiver, The system comprises control logic configured to selectively establish the shared error checker and sequence generator in either error checker mode or sequence generator mode, The shared error tester and sequence generator includes one or more switching elements configured to selectively send the generated sequence signal as feedback to the sequence generator, or the received sequence signal to the sequence generator, wherein the error tester and sequence generator are integrated into a single element and shared between the transmit path and the receive path.

2. The shared error checker and sequence generator according to claim 1, wherein the error detector comprises one or more XOR gates.

3. The shared error checker and sequence generator according to claim 1, wherein the sequence generator comprises a core of a linear feedback shift register configured to generate a pseudo-random binary sequence.

4. The shared error tester and sequence generator according to claim 1, wherein the sequence generator comprises fewer than 70 transistors.

5. The shared error checker and sequence generator according to claim 1, wherein the sequence generator is composed of fewer than three three-input XOR gates.

6. The shared error tester and sequence generator according to claim 1, wherein the shared error tester and sequence generator are configured to output a sequence signal to be transmitted to a remote transceiver.

7. A method for the operation of a shared error checker and sequence generator for evaluating the operation of a data communication system in a local transceiver, The steps include receiving a sequence signal from a remote transceiver, A step of generating a generated sequence signal in the local transceiver using a shared error checker and a sequence generator, The steps include providing the received sequence signal to the shared error checker and the sequence generator, The steps include comparing the received sequence signal with the generated sequence signal using the shared error checker and sequence generator, The step of generating an error count in response to the difference between the received sequence signal and the generated sequence signal using the shared error checker and sequence generator, The shared error tester and sequence generator are configured to switch between error tester mode and sequence signal generation mode using control logic. The shared error checker and sequence generator include one or more switching elements configured to selectively send the generated sequence signal as feedback to the sequence generator, or the received sequence signal to the sequence generator, wherein the error checker and sequence generator are integrated into a single element and shared between a transmission path and a reception path.

8. The method according to claim 7, wherein the error detector comprises one or more XOR gates.

9. The method according to claim 7, wherein the sequence generator comprises a core of a linear feedback shift register configured to generate a pseudo-random binary sequence.

10. The method according to claim 7, wherein the sequence generator is composed of fewer than 70 transistors.

11. The method according to claim 7, wherein the sequence generator is composed of fewer than three three-input XOR gates.

12. A composite error checker and sequence generator that share a core of a linear feedback shift register, A clock and data recovery system configured to recover clock and data signals received via a channel from a remote transceiver, Control logic configured to activate one of two or more operating modes of the aforementioned combined error checker and sequence generator, An error detector configured to compare two sequence signals and record an error in response to the difference between the two sequence signals, The system includes a sequence signal generator configured to generate a sequence signal for use as a reference sequence signal by the error detector or for transmission to a remote transceiver, The aforementioned combined error tester and sequence generator are configured to switch between error tester mode and sequence signal generation mode using control logic. The aforementioned error tester and sequence generator are integrated into a single element and shared between the transmission path and the reception path, forming a combined error tester and sequence generator.

13. The composite error tester and sequence generator according to claim 12, wherein the error detector comprises one or more XOR gates.

14. The composite error checker and sequence generator according to claim 12, wherein the core of the linear feedback shift register is configured to generate a pseudo-random binary sequence used by the error checker.

15. The combined error tester and sequence generator according to claim 12, wherein the combined error tester and sequence generator includes one or more switching elements configured to selectively send a generated sequence signal as feedback to the sequence generator or a received sequence signal to the sequence generator, depending on whether the combined error tester and sequence generator are in error tester mode or sequence generator mode.

16. The composite error tester and sequence generator according to claim 12, wherein the core of the linear feedback shift register is composed of fewer than 70 transistors.

17. The composite error checker and sequence generator according to claim 12, wherein the sequence generator comprises fewer than three three-input XOR gates.

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