AD converter

Abstract

To provide high precision.SOLUTION: An AD converter 100 includes analog signal input circuits 11 and 12 which receive input of an analog input signal and output a first analog output signal and a second analog output signal based on the analog input signal at different timings, an integrating unit 30 that integrates the first analog output signal and the second analog output signal to output a first integrated signal and a second integrated signal, a prediction unit that predicts an integrated signal to be output by an integration circuit after the output on the basis of the first integrated signal and the second integrated signal output by the integration unit, and outputs the predicted integrated signal, and a quantization unit that generates a digital signal obtained by quantizing the predicted integrated signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an AD converter.

Background Art

[0002] Conventionally, an AD converter having a quantizer and an integrator and a primary delta-sigma modulator for converting an input analog signal into a digital signal is known. Patent Document 1 discloses that in an AD converter, one integration is divided into two integrations, a first integration and a second integration. Patent Document 1 Japanese Unexamined Patent Application Publication No. 2017-216523

Summary of the Invention

[0003] In a first aspect of the present invention, an AD converter is provided. The AD converter may include an analog signal input circuit to which an analog input signal is input and that outputs a first analog output signal and a second analog output signal based on the analog input signal at different timings. The AD converter may include an integration circuit that integrates the first analog output signal and the second analog output signal and outputs a first integration signal and a second integration signal. The AD converter may include a prediction circuit that predicts an integration signal to be output after the integration circuit outputs based on the first integration signal and the second integration signal output by the integration circuit and outputs a predicted integration signal. The AD converter may include a quantization circuit that generates a digital signal obtained by quantizing the predicted integration signal.

[0004] The prediction circuit may predict an integration signal to be output after the integration circuit outputs based on a difference between the first integration signal and the second integration signal output by the integration circuit at different timings.

[0005] The prediction circuit may have three capacitors connected in parallel. The prediction circuit may have a plurality of switches that switch the connection of one end side of the three capacitors between the output of the integration circuit and a reference potential. The prediction circuit may have a plurality of switches that switch the connection of the other end side of the three capacitors between the output of the prediction circuit and a reference potential.

[0006] The analog signal input circuit may have a first analog signal input circuit that receives an analog input signal and outputs a first analog output signal. It may also have a second analog signal input circuit that receives an analog input signal at a different timing than the first analog signal input circuit and outputs a second analog output signal. The first analog signal input circuit and the second analog signal input circuit may be connected to a common integrating circuit.

[0007] The AD converter may repeat, in a time-division manner, a first operating period in which an integrating circuit integrates a first analog output signal, and a second operating period in which an integrating circuit integrates a second analog output signal.

[0008] In the first operating period, the AD converter may have a first analog signal input circuit output a first analog output signal to an integrating circuit, and a second analog signal input circuit sample an analog input signal. In the second operating period, the AD converter may have a first analog signal input circuit sample an analog input signal, and a second analog signal input circuit output a second analog output signal to an integrating circuit.

[0009] The prediction circuit may predict which of the first and second integral signals will be output after the output of the integrating circuit, based on the first and second integral signals output by the integrating circuit at different timings.

[0010] The AD converter may include a third analog signal input circuit that outputs a third analog output signal based on an integral signal output by an integrating circuit after the output. The AD converter may include a second integrating circuit that integrates the third analog output signal and outputs a third integral signal. The AD converter may include an adder circuit that adds the analog input signal and the third integral signal to a predicted integral signal and outputs the added predicted integral signal to a quantization circuit.

[0011] The AD converter may include a fourth analog signal input circuit that outputs a fourth analog output signal to an adder circuit in response to an input analog input signal. The AD converter may also include a fifth analog signal input circuit that outputs a fifth analog output signal to an adder circuit in response to a third integral signal. The adder circuit adds the fourth analog output signal and the fifth analog output signal to the predicted integral signal and outputs the added predicted integral signal to the quantization circuit.

[0012] In a second embodiment of the present invention, an AD converter is provided. The AD converter may repeatedly perform integration and sampling operations by dividing the M-th conversion period (M is an integer of 2 or more) into X periods (X is an integer of 2 or more). The AD converter may include an analog signal input circuit that outputs an analog output signal based on an input analog signal in each of the X divisions of the conversion period. The AD converter may include an integration circuit that integrates the output of the analog signal input circuit. The AD converter may include a prediction circuit that predicts the integral signal output from the integration circuit in the last (X) division of the M-th conversion period based on the integral signal output from the integration circuit in the last (X) division of the M-th conversion period and the integral signals output from the integration circuit in any of the periods other than the last (X) division of the M-th conversion period (1 to X-1), or the integral signals of two different periods in any of the periods other than the last (X) division of the M-th conversion period (1 to X-1), and outputs a predicted integral signal. The AD converter may include a quantization circuit that generates a digital signal obtained by quantizing the predicted integral signal.

[0013] The prediction circuit may predict the integral signal output from the integrating circuit in the last (Xth) period based on the difference between the integral signal output from the integrating circuit in the last (Xth) period of the X divisions in the immediately preceding (M-1) conversion period and the integral signal output from the integrating circuit in any period other than the last (Xth) period of the X divisions in the M conversion period (from 1 to X-1), or the difference between the integral signals of two different periods in any period other than the last (Xth) period of the X divisions in the M conversion period (from 1 to X-1).

[0014] The prediction circuit may have three capacitors connected in parallel and multiple switches that switch the connection to one end of the three capacitors between the output of the integrating circuit and a reference potential. The prediction circuit may also have multiple switches that switch the connection to the other end of the three capacitors between the output of the prediction circuit and a reference potential.

[0015] The analog signal input circuit may include a first analog signal input circuit that receives an analog input signal and outputs a first analog output signal. It may also include a second analog signal input circuit that receives an analog input signal at a different timing than the first analog signal input circuit and outputs a second analog output signal. The first analog signal input circuit and the second analog signal input circuit may be connected to a common integrating circuit.

[0016] During the L1st period (where L1 is an integer between 1 and X-1), the first analog signal input circuit may output a first analog output signal to the integrating circuit, and the second analog signal input circuit may sample the analog input signal. During the L2nd period (where L2 is an integer greater than L1 and less than or equal to X-1), the first analog signal input circuit may sample the analog input signal, and the second analog signal input circuit may output a second analog output signal to the integrating circuit.

[0017] The AD converter may include a third analog signal input circuit that outputs a third analog output signal based on the integral signal output from the integrating circuit during the last (Xth) period of the X division. The AD converter may include a second integrating circuit that integrates the third analog output signal and outputs a third integral signal. The AD converter may include an adder circuit that adds the analog input signal and the third integral signal to a predicted integral signal and outputs the added predicted integral signal to the quantization circuit.

[0018] The AD converter may include a fourth analog signal input circuit that outputs a fourth analog output signal to an adder circuit in response to an input analog input signal. The AD converter may also include a fifth analog signal input circuit that outputs a fifth analog output signal to an adder circuit in response to a third integral signal. The adder circuit may add the fourth analog output signal and the fifth analog output signal to the predicted integral signal and output the added predicted integral signal to a quantization circuit.

[0019] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0020] [Figure 1] The configuration of the AD converter 100 in the first embodiment is shown. [Figure 2] A more detailed configuration of the integrator 10 and quantization unit 40 of the AD converter 100 of the first embodiment is shown. [Figure 3] An example of clock signals P1, P2, and PCOMP is shown. [Figure 4] An example of the specific configuration of the prediction unit 60 in the AD converter 100 is shown. [Figure 5] The timing chart for the integral signal AOUTB of the integral unit 30 is shown. [Figure 6] An example of a timing chart for the AD converter 100 according to Example 1 is shown. [Figure 7] (a) The block of the first-order moving average filter and (b) its frequency characteristics are shown. [Figure 8] Shows an overview of the configuration of the ADC 200 of the second embodiment. [Figure 9] Shows an example of the timing chart of the ADC 200 of the second embodiment. [Figure 10] Shows an overview of the configuration of the ADC 300 of the third embodiment. [Figure 11] Shows a more detailed configuration of the ADC 300 of the third embodiment. [Figure 12] Shows the configuration of the prediction addition unit. [Figure 13] Shows an example of the timing chart of the ADC 300 of Embodiment 3. [Figure 14] Shows a modified example of the prediction addition unit. [Figure 15] Shows the clock signal P1, the clock signal P2, the clock signal P3, the clock signal P4, and the clock signal PCOMP. [Figure 16] Shows the timing chart of the integration result AOUTB of the integration unit 30 in the ADC 300. [Figure 17] Shows an example of the timing chart of the ADC 300. [Figure 18] Shows an outline of the configuration of the AD conversion device 400.

Mode for Carrying Out the Invention

[0021] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0022] Figure 1 shows an overview of the configuration of the AD converter 100 of the first embodiment. The AD converter 100 divides the M-th conversion period (M is an integer of 2 or more) into X periods (X is an integer of 2 or more), repeatedly performing integration and sampling operations to quantize the input analog input signal Ain into bit data and output it. For example, the AD converter 100 is an AD converter having a first-order delta-sigma modulator, but it may also be an AD converter having a higher-order delta-sigma modulator. The AD converter 100 comprises an integrator 10 (integration circuit of the present application), a prediction unit 60 (prediction circuit of the present application), a quantization unit 40 (quantization circuit of the present application), and a control unit 50. The integrator 10 comprises a first analog signal input circuit 11, a second analog signal input circuit 12, a first reference signal input circuit 21, a second reference signal input circuit 22, and an integration unit 30. The integrator 10, the prediction unit 60, and the quantization unit 40 are each input to at least one of the clock signals P1 and P2 and operate in accordance with the clock signal.

[0023] The first analog signal input circuit 11 is connected to the input terminal of the AD converter 100 and the integration unit 30. In each period, when the conversion period is divided equally into X, an analog input signal Ain is input from the input terminal, and a first analog output signal Aout1 is output to the integration unit 30. The second analog signal input circuit 12 is connected to the input terminal and the integration unit 30. An analog input signal Ain is input at a different timing than that of the first analog signal input circuit 11, and a second analog output signal Aout2 is output to the integration unit 30. The first analog signal input circuit 11 and the second analog signal input circuit 12 are connected to a common integration unit 30 and sample the analog input signal Ain at different timings. The first analog signal input circuit 11 and the second analog signal input circuit 12 may sample alternately and output analog output signals Aout1 and Aout2 alternately to the integration unit 30. For example, during the L1st period of the Mth conversion period (where L1 is an integer between 1 and X-1), the first analog signal input circuit outputs a first analog output signal Aout1 to the integration unit 30, and the second analog signal input circuit 12 samples the analog input signal Ain. During the L2nd period of the Mth conversion period (where L2 is an integer greater than L1 and less than or equal to X-1), the first analog signal input circuit 11 samples the analog input signal Ain, and the second analog signal input circuit 12 outputs a second analog output signal Aout2 to the integration unit 30.

[0024] The first reference signal input circuit 21 is connected to the integration unit 30 and the quantization unit 40, and receives the digital signal D and the inverted signal DB of the digital signal D from the quantization unit 40, as well as the reference input signal Sref. The first reference signal input circuit 21 generates a positive or negative feedback signal ±Sfb1 from the input signals and outputs it to the integration unit 30. The first reference signal input circuit 21 may have a DA converter that converts the digital signal to an analog signal.

[0025] The second reference signal input circuit 22 is connected to the integration unit 30 and the quantization unit 40, and receives the digital signal D and the inverted signal DB of the digital signal D from the quantization unit 40, as well as the reference input signal Sref. The second reference signal input circuit 22 outputs a positive or negative feedback signal ±Sfb2 from the input signals to the integration unit 30. The second reference signal input circuit 22 may have a DA converter that converts digital signals to analog signals. The second reference signal input circuit 22 may output the feedback signal Sfb2 at a different timing than the output of the feedback signal Sfb1 of the first reference signal input circuit 21. The first reference signal input circuit 21 and the second reference signal input circuit 22 may alternately output the feedback signals Sfb1 and Sfb2.

[0026] The integration unit 30 is connected to the prediction unit 60 and integrates the first analog output signal Aout1 and the second analog output signal Aout2, outputting the integration results, the first integrated signal and the second integrated signal AOUTB, to the prediction unit 60. Since the first reference signal input circuit 21 and the second reference signal input circuit 22, and the first analog signal input circuit 11 and the second analog signal input circuit 12 are all commonly connected to the input of the integration unit 30, the integration unit 30 may receive analog output signals Aout1 and Aout2 with the feedback signals Sfb1 and Sfb2 added to them.

[0027] The integration unit 30 may integrate the first analog output signal Aout1 and the second analog output signal Aout2, which are input at different timings, at different timings and output the corresponding first integrated signal AOUTB and second integrated signal AOUTB, respectively. The integration unit 30 may output the first integrated signal AOUTB and the second integrated signal AOUTB alternately.

[0028] The prediction unit 60 is connected to the quantization unit 40 and predicts the integral signal that the integration unit 30 will output after the output of the first and second integral signals, based on the first and second integral signals AOUTB output by the integration unit 30. The prediction unit 60 may predict at least one of the future first and second integral signals based on the first and second integral signals. The prediction unit 60 may predict the integral signal output from the integration unit 30 in the last (Xth) period of the X division in the immediately preceding conversion period (M-1th), based on the integral signal output from the integration unit 30 in the last (Xth) period of the X division in the Mth conversion period (e.g., the difference between the integral signals), or the integral signals of two different periods in any of the periods other than the last (Xth) period of the X division in the Mth conversion period (e.g., the difference between the integral signals), and output the predicted integral signal AOUTB'. The prediction unit 60 may predict one of the first and second integral signals to be output after the output of the integration unit 30, based on the first and second integral signals output by the integration unit 30 at different timings, and output the predicted integral signal AOUTB', which is the prediction result, to the quantization unit 40. As an example, the prediction unit 60 may, after receiving the first integral signal AOUTB, output a second predicted integral signal AOUTB', which is the result of predicting the next second integral signal AOUTB, before or during the reception of the next second integral signal AOUTB.

[0029] The quantization unit 40 generates a digital signal D and an inverted signal DB of the digital signal D by quantizing the predicted integral signal AOUTB' of the prediction unit 60, and outputs the digital signal D and the inverted signal DB to the first reference signal input circuit 21 and the second reference signal input circuit 22. The quantization unit 40 may also output the generated digital signal D to the outside of the AD converter 100.

[0030] The control unit 50 controls the quantization timing of the quantization unit 40. The control unit 50 may output a clock signal PCOMP to the quantization unit 40 in order to control the quantization timing in the quantization unit 40.

[0031] Figure 2 shows a more detailed configuration of the integrator 10 and quantization unit 40 of the AD converter 100 of the first embodiment. The first analog signal input circuit 11 includes a capacitor CA1, a plurality of switches SA1 and SA2 that switch the connection to one end of the capacitor CA1 between the input terminal and a reference potential, and a plurality of switches SB1 and SB2 that switch the connection to the other end of the capacitor CA1 between the output of the first analog signal input circuit 11 and a reference potential.

[0032] The second analog signal input circuit 12 includes a capacitor CA2 connected in parallel with capacitor CA1, a plurality of switches SC1 and SC2 that switch the connection to one end of capacitor CA2 between an input terminal and a reference potential, and a plurality of switches SD1 and SD2 that switch the connection to the other end of capacitor CA2 between the output of the second analog signal input circuit 12 and a reference potential. Here, the reference potential may be a predetermined potential, for example, the ground potential, and the same applies hereinafter in this specification.

[0033] The first analog signal input circuit 11 and the second analog signal input circuit 12 may output analog output signals Aout1 and Aout2 at different operating periods phi(1) and phi(2) depending on the clock signals P1 and P2. During operating period phi(1), switches SA1 and SB1 are turned on and switches SA2 and SB2 are turned off in the first analog signal input circuit 11, and switches SC1 and SD1 are turned on and switches SC2 and SD2 are turned off in the second analog signal input circuit 12. On the other hand, during operating period phi(2), switches SA1 and SB1 are turned off and switches SA2 and SB2 are turned on in the first analog signal input circuit 11, and switches SC1 and SD1 are turned off and switches SC2 and SD2 are turned on in the second analog signal input circuit 12.

[0034] The first reference signal input circuit 21 includes two capacitors connected in parallel, a plurality of switches SE1, SE2, SG1, SG2 that switch the connection of one end of the two capacitors CR1, CR1B between the input terminal to which the reference input signal Sref is input and the reference potential, a plurality of switches SF1, SF2, SH1, SH2 that switch the connection of the other end of the two capacitors CR1, CR1B between the output of the first reference signal input circuit 21 and the reference potential, and a plurality of switches SS1, SS1B that switch the output of the first reference signal input circuit 21.

[0035] The second reference signal input circuit 22 includes two capacitors CR2 and CR2B connected in parallel, a plurality of switches SI1, SI2, SK1, and SK2 that switch the connection of one end of the two capacitors CR2 and CR2B between the input terminal of the reference input signal Sref and a reference potential, a plurality of switches SJ1, SJ2, SL1, and SL2 that switch the connection of the other end of the two capacitors CR2 and CR2B between the output of the second reference signal input circuit 22 and a reference potential, and a plurality of switches SS2 and SS2B that switch the output of the second reference signal input circuit 22.

[0036] The first reference signal input circuit 21 and the second reference signal input circuit 22 may sample charge at different operating periods phi(1) and phi(2) depending on the clock signals P1 and P2. During operating period phi(1), switches SE1, SF1, SG1, and SH1 are turned on and switches SE2, SF2, SG2, and SH2 are turned off in the first reference signal input circuit 21, and switches SI1, SJ1, SL1, and SK1 are turned on and switches SI2, SJ2, SL2, and SK2 are turned off in the second reference signal input circuit 22. Meanwhile, during the operating period phi(2), in the first reference signal input circuit 21, switches SE1, SF1, SG1, and SH1 are turned off, and switches SE2, SF2, SG2, and SH2 are turned on. In the second reference signal input circuit 22, switches SI1, SJ1, SL1, and SK1 are turned off, and switches SI2, SJ2, SL2, and SK2 are turned on.

[0037] The switches SS1 and SS1B of the first reference signal input circuit 21 and the switches SS2 and SS2B of the second reference signal input circuit 22 are connected between the other ends of capacitors CR1 and CR1B and their outputs, and control the output of the reference input signal Sref. Switch SS1 of the first reference signal input circuit 21 and switch SS2 of the second reference signal input circuit 22 are input to the inverted signal DB from the quantization unit 40, and are turned on when the inverted signal DB is high (hereinafter also referred to as H) and turned off when it is low (hereinafter also referred to as L). Switch SS1B of the first reference signal input circuit 21 and switch SS2B of the second reference signal input circuit 22 are input to the digital signal D from the quantization unit 40, and are turned on when the digital signal D is high (H) and turned off when it is low (L).

[0038] In the first reference signal input circuit 21, when switches SF2 and SH2 are ON during the operating period phi(2), either capacitor CR1 or capacitor CR1B is connected to the integrating unit 30. On the other hand, in the first reference signal input circuit 21, when switches SF2 and SH2 are OFF during the operating period phi(1), capacitors CR1 and CR1B are not connected to the integrating unit 30, regardless of the state of switches SS1 and SS1B.

[0039] The first reference signal input circuit 21 subtracts the feedback signal Sfb from the analog output signal Aout1 by connecting the capacitor CR1B to the integration unit 30 when the digital signal D from the quantization unit 40 is high (H). In other words, charge is drawn from the input of the integration unit 30 to the capacitor CR1B. On the other hand, the first reference signal input circuit 21 adds the feedback signal Sfb to the analog output signal Aout1 by connecting the capacitor CR1 to the integration unit 30 when the digital signal D from the quantization unit 40 is low (L). In other words, charge is transferred from the capacitor CR1B to the integration unit 30.

[0040] The second reference signal input circuit 22 connects either capacitor CR1 or capacitor CR1B to the integrator 30 when switches SF2 and SH2 are ON during the operating period phi(2). On the other hand, in the first reference signal input circuit 21, switches SF2 and SH2 are OFF during the operating period phi(1), so capacitors CR1 and CR1B are not connected to the integrator 30 regardless of the state of switches SS1 and SS1B. The second reference signal input circuit 22 connects either capacitor CR1 or capacitor CR1B to the integrator 30 during the operating period phi(1).

[0041] The second reference signal input circuit 22 subtracts the feedback signal Sfb from the analog output signal Aout2 by connecting capacitor CR2B to the integrator 30 when the digital signal D from the quantization unit 40 is high (H). In other words, charge is drawn from the input of the integrator 30 to capacitor CR2B. On the other hand, the second reference signal input circuit 22 adds the feedback signal Sfb to the analog output signal Aout2 by connecting capacitor CR2 to the integrator 30 when the digital signal D from the quantization unit 40 is low (L). In other words, charge is transferred from capacitor CR2B to the integrator 30.

[0042] The integration unit 30 comprises an operational amplifier 31 and a capacitor CF1. The operational amplifier 31 has an inverting input terminal connected to the outputs of the first analog signal input circuit 11, the second analog signal input circuit 12, the first reference signal input circuit 21, and the second reference signal input circuit 22, a forward input terminal connected to a reference potential, and an output terminal connected to the prediction unit 60. The capacitor CF1 is provided between the inverting input terminal and the output terminal of the operational amplifier 31.

[0043] The integration unit 30 performs integration of the analog output signal Aout1 and the feedback signal Sfb1 during the operating period phi(2). The integration unit 30 also performs integration of the analog output signal Aout2 and the feedback signal Sfb2 during the operating period phi(1). Thus, the integration unit 30 may divide one period of the operating period phi(1) and operating period phi(2) into two parts and perform one integration over one period.

[0044] The integrator 10 includes a first analog signal input circuit 11 and a second analog signal input circuit 12 as analog signal input circuits, and a first reference signal input circuit 21 and a second reference signal input circuit 22 as a feedback section. Therefore, both the analog output signal Aout and the feedback signal Sfb can be divided into two parts and integrated in the integrator 30. The AD converter 100 can operate with negative feedback by inputting feedback signals Sfb1 and Sfb2 corresponding to the integration result of the integrator 30 to the integrator 30.

[0045] The quantization unit 40 includes a comparator 41 and a logic circuit 42. The comparator 41 has an input terminal connected to the prediction unit 60 and an output terminal connected to the logic circuit 42. The comparator 41 receives the prediction integral signal AOUTB' from the prediction unit 60 as input and quantizes the prediction integral signal AOUTB' to generate a quantized signal C. The comparator 41 may generate the quantized signal C by quantizing the prediction integral signal AOUTB' that is input at the rising edge time of the clock signal PCOMP. The comparator 41 outputs the generated quantized signal C to the logic circuit 42. In this embodiment, the comparator 41 is a 1-bit quantizer, but it may be a multi-bit quantizer.

[0046] The logic circuit 42 has output terminals (Q terminal, QB terminal) connected to the first reference signal input circuit 21, the second reference signal input circuit 22, and an external device. The logic circuit 42 may have a clock signal P1 input to its clock terminal. The logic circuit 42 outputs a digital signal D according to the quantization signal C output by the comparator 41. The logic circuit 42 may be composed of D flip-flops (DFFs). The logic circuit 42 outputs its input as a digital signal D on the rising edge of the clock signal P1. The logic circuit 42 holds the same output signal until the next rising edge of the clock signal P1.

[0047] Figure 3 shows an example of clock signals P1, P2, and PCOMP. Clock signal P1 is high during the operating period phi(1) and low during the rest of the period. Clock signal P2 is high during the operating period phi(2) and low during the rest of the period. Clock signal PCOMP is high for part of the operating period phi(2) and low during the rest of the period.

[0048] During the first operating period phi(2), the first analog signal input circuit 11 may output a first analog output signal Aout1 to the integrating unit 30, and the second analog signal input circuit 12 may sample an analog input signal Ain. During the second operating period, the first analog signal input circuit 11 may sample an analog input signal Ain, and the second analog signal input circuit 12 may output a second analog output signal Aout2 to the integrating unit 30.

[0049] For example, the first analog signal input circuit 11 samples the analog input signal Ain by storing a charge corresponding to the analog input signal Ain in capacitor CA1 during the operating period phi(1), and outputs the stored charge as a first analog output signal Aout1 to the integration unit 30 during the operating period phi(2). The second analog signal input circuit 12 samples the analog input signal Ain by storing a charge corresponding to the analog input signal Ain in capacitor CA2 during the operating period phi(2), and outputs the stored charge as a second analog output signal Aout2 to the integration unit 30 during the operating period phi(1).

[0050] The first reference signal input circuit 21 samples the reference input signal Sref by storing a charge corresponding to the reference input signal Sref in capacitor CR1 during the operating period phi(1). Capacitor CR1B resets the stored charge. In other words, capacitor CR1B samples the zero signal, which is intended to be zero V, as a charge. Switch SS1 receives a signal corresponding to the charge sampled by capacitor CR1 during the operating period phi(1), and switch SS1B receives a signal corresponding to the charge sampled by capacitor CR1B.

[0051] The second reference signal input circuit 22 samples the reference input signal Sref by storing a charge corresponding to the reference input signal Sref in capacitor CR2 during the operating period phi(2). Capacitor CR2B resets the stored charge. In other words, capacitor CR2B samples the zero signal, which is intended to be zero V, as a charge. Switch SS2 receives a signal corresponding to the charge sampled by capacitor CR2 during the operating period phi(2), and switch SS2B receives a signal corresponding to the charge sampled by capacitor CR2B.

[0052] Thus, the AD converter 100 may alternately repeat, in a time-division manner, a first operating period phi(2) in which the integrating unit 30 integrates the first analog output signal Aout1, and a second operating period phi(1) in which the integrating unit 30 integrates the second analog output signal Aout2.

[0053] Figure 4 shows an example of a specific configuration of the prediction unit 60 in the AD converter 100. The prediction unit 60 has three capacitors CP1, CP2, and CP3, multiple switches SPA1, SPA2, SPC1, SPC2, SPE1, SPE2, SPB1, SPB2, SPD1, SPD2, SPF1, SPF2, and a polarity inversion circuit 65, which constitute three prediction circuits 61, 62, and 63. The polarity inversion circuit 65 may output a signal with the polarity of the input charge inverted, and may be configured as an inverting amplifier. The three capacitors CP1, CP2, and CP3 are connected in parallel between the input and output of the prediction unit 60. The capacitance values ​​of capacitors CP1 and CP2 are 2C (C>0), and the capacitance value of capacitor CP3 may be C. Multiple switches SPA1, SPA2, SPC1, SPC2, SPE1, SPE2 switch the connection to one end of the three capacitors CP1, CP2, CP3 using the output of the integration unit 30 and a reference potential, according to the clock signals P1, P2. Multiple switches SPB1, SPB2, SPD1, SPD2, SPF1, SPF2 switch the connection to the other end of the three capacitors CP1, CP2, CP3 using the output of the prediction unit 60 and a reference potential, according to the clock signals P1, P2.

[0054] The prediction unit 60 may predict which of the first and second integral signals will be output next to the output of the integration unit 30, based on the difference between the first integral signal AOUTB and the second integral signal AOUTB output by the integration unit 30 at different timings.

[0055] In the prediction unit 60, during the operating period phi(2), switches SPA1, SPB1, SPC1, SPD1, SPE1, SPF1 are turned off, and switches SPA2, SPB2, SPC2, SPD2, SPE2, SPF2 are turned on. In the prediction unit 60, during the operating period phi(1), switches SPA1, SPB1, SPC1, SPD1, SPE1, SPF1 are turned on, and switches SPA2, SPB2, SPC2, SPD2, SPE2, SPF2 are turned off.

[0056] During the operating period phi(2), the prediction circuit 61 samples a charge corresponding to the output signal AOUTB of the integrator 10 into the capacitor CP1, and during the operating period phi(1), it transfers the sampled charge Q1 from capacitor CP1 to the quantization unit 40. During the operating period phi(2), the prediction circuit 62 resets the charge of capacitor CP2, and during the operating period phi(1), it samples a charge corresponding to the output signal AOUTB of the integrator 10 into capacitor CP2 and transfers the sampled charge Q2 to the quantization unit 40. During the operating period phi(2), the prediction circuit 63 samples a charge corresponding to the output signal AOUTB of the integrator 10 into capacitor CP3, and during the operating period phi(1), it inputs the sampled charge from capacitor CP3 to the polarity inversion circuit 65, and the polarity inversion circuit 65 transfers the charge Q3, with the polarity of the input charge inverted, to the quantization unit 40.

[0057] The prediction unit 60 may output a combined charge Q, obtained by combining the charge Q1 sampled by the prediction circuit 61, the charge Q2 sampled by the prediction circuit 62, and the charge Q3 sampled by the prediction circuit 63, as an output signal AOUTB' to the quantization unit 40 during the operating period phi(1). Next, the relationship between charges Q1, Q2, Q3, and Q will be explained.

[0058] Figure 5 shows the timing chart of the integral signal AOUTB from the integrating unit 30. In Figure 5, the vertical axis represents the voltage level of the integral signal AOUTB, and the horizontal axis represents the passage of time.

[0059] V11 is the voltage level of the integral signal AOUTB of the integrator 30 at the completion of integration in the current (Nth) operating period phi(1), V02 is the voltage level of the integral signal AOUTB of the integrator 30 at the completion of integration in the previous (N-1) operating period phi(2), and V12 is the voltage level of the integral signal AOUTB of the integrator 30 at the completion of integration in the next (N+1) operating period phi(2). Vstep1, which is the difference between the previous and current voltage levels, is half the change in the voltage level of the integral signal AOUTB of the integrator 30 when one integration is performed between the current operating period phi(1) and the next operating period phi(2). Vtep1 can be expressed as in equation (1), and V12 as in equation (2).

[0060] Vstep1=V11-V02=V12-V11 (1) V12=V02+(V11-V02)+(V12-V11)=V02+2×Vstep1···(2)

[0061] Here, according to the timing chart in Figure 5, the charge Q1 output to the quantization unit 40 during the current operating period phi(1) is given by equation (3), charge Q2 by equation (4), charge Q3 by equation (5), and the combined charge Q of charges Q1, Q2, and Q3 is given by equation (6).

[0062] Q1 = -2C × V02·····(3) Q2 = 2C × V11·····(4) Q3 = C × V02·····(5) Q=Q1+Q2+Q3=C×V12 (6)

[0063] Thus, the prediction unit 60 generates a charge Q during the operating period phi(1) that corresponds to the voltage level of the integral signal AOUTB of the integral unit 30 at the completion of integration in the next operating period phi(2), and outputs it to the quantization unit 40 as the predicted integral signal AOUTB'. Although the prediction unit 60 generates the predicted integral signal AOUTB' using a switched capacitor as shown in Figure 4, the predicted integral signal AOUTB' may also be generated using a resistor divider, amplifier, etc.

[0064] Figure 6 shows an example of a timing chart for the AD converter 100 according to Embodiment 1. In Figure 6, the integrator operation (11, 21) shows the operation of the first analog signal input circuit 11 and the first reference signal input circuit 21 in the integrator 10, and the integrator operation (12, 22) shows the operation of the second analog signal input circuit 12 and the second reference signal input circuit 22 in the integrator 10. Here, the integration in the integrator operation in Figure 6 shows the operation of integrating the outputs from the corresponding analog signal input circuit and reference signal input circuit in the integrator unit 30, and the same applies hereafter in this specification. In Figure 6, P1, P2, and PCOMP show clock signals, C shows the output of the comparator 41, and D shows the digital signal output from the logic circuit 42. AOUTB and AOUTB' show the integrated signal of the integrator 10 and the predicted integrated signal of the prediction unit 60.

[0065] The AD converter 100 operates with operating periods phi(1) and phi(2) as one period. In this embodiment, operating periods phi(1) and phi(2) are the same length, but they may be different lengths.

[0066] The AD converter 100 divides the sampling operation into sampling operation (1) and sampling operation (2). The AD converter 100 also divides the integration operation into integration operation (1) and integration operation (2). During the operation period phi(1), the first analog signal input circuit 11 and the first reference signal input circuit 21 perform sampling operation (1), which is the first sampling, in response to the input of the clock signal P1. During the subsequent operation period phi(2), the integration unit 30 performs integration operation (1), which is the second integration, in response to the inputs from the first analog signal input circuit 11 and the first reference signal input circuit 21. During the operation period phi(2), the second analog signal input circuit 12 and the second reference signal input circuit 22 perform sampling operation (2), which is the second sampling, in response to the input of the clock signal P2. During the subsequent operating period phi(1), the integrating unit 30 performs an integration operation (2), which is the first integration, in response to the inputs of the second analog signal input circuit 12 and the second reference signal input circuit 22. In this way, the AD converter 100 performs sampling and integration operations during both the operating period phi(1) and the operating period phi(2).

[0067] The AD converter 100 can alleviate the slewing requirement (i.e., the output change speed requirement) of the integration unit 30 by dividing a single integration into multiple steps. As a result, the AD converter 100 can reduce the power consumption in the integration unit 30.

[0068] The integral signal AOUTB of the integral unit 30 rises when the digital signal D is low (L) due to the integral operation of the integral unit 30, and falls when the digital signal D is high (H) due to the integral operation of the integral unit 30. The integral signal AOUTB of the integral unit 30 becomes the integration completion value AO1 when the integral unit 30 completes its integration. Furthermore, the integral signal AOUTB of the integral unit 30 is integrated to half the level of the integration completion value AO1 in the first integration operation (2) during the operation period phi(1), and becomes the integration completion value AO1 in the second integration operation (1) during the operation period phi(2).

[0069] The digital signal D output from the logic circuit 42 is determined according to the quantization signal C at the rising edge of the clock signal P1. Digital signal D0 is determined according to the quantization signal C0 at the rising edge of the clock signal P1. Digital signal D1 is determined according to the quantization signal C1 at the rising edge of the next clock signal P1. As a result, the AD converter 100 operates with the set polarity from the rising edge of one clock signal P1 to the rising edge of the next clock signal P1.

[0070] The prediction unit 60 generates a predicted integral signal AOUTB' in which the integral end value AO1 in the operation period phi(2) is predicted during the operation period phi(1). The control unit 50 causes the quantization unit 40 to perform quantization of the predicted integral signal AOUTB' output by the prediction unit 60. The quantization unit 40 outputs a quantized signal C which is obtained by quantizing the predicted integral signal AOUTB' that is input at the rising edge of the clock signal PCOMP. The logic circuit 42 outputs its input as a digital signal D at the rising edge of the clock signal P1 and holds the output of the same digital signal until the rising edge of the next clock signal P1.

[0071] The period tCOMP is the period from the rising edge of the clock signal PCOMP to the rising edge of the clock signal P1, and represents the period from the start of the quantization operation to the time when the output digital signal D is determined. The power consumption of the quantization unit 40 changes according to the length of the period tCOMP. For example, as the period tCOMP becomes longer, the speed requirement to the quantization unit 40 is relaxed, and the power consumption of the quantization unit 40 is reduced.

[0072] In this embodiment, the AD converter 100 has virtually no error with the actual integral end value AO1 because the quantization unit 40 quantizes the predicted integral signal AOUTB' output by the prediction unit 60, which predicts the integral end value AO1. This enables a high signal-to-noise ratio. Furthermore, since the AD converter 100 starts quantization of the predicted integral signal AOUTB' output by the prediction unit 60 at the rising edge time of the clock signal PCOMP, the period tCOMP can be made longer, and the power consumption of the quantization unit 40 can be reduced.

[0073] Figure 7 shows (a) a block of the first-order moving average filter and (b) its frequency characteristics. In this embodiment, the AD converter 100 performs one integral in two parts: the period immediately preceding the current period in which the first integral is performed (operating period phi(1)) and the current period in which the second integral is performed (operating period phi(2)). The sum of the first and second integral results is output as the integral result AOUTB. Thus, the transfer function H(z) with an analog input signal Ain or a reference input signal Sref as input and the integral result AOUTB as output can be expressed by equation (7), which has the transfer characteristics of a moving average filter when using the z function.

[0074] H(z) = 1 / 2 × (1 + z) -1 )·····(7)

[0075] In this embodiment, the AD converter 100 takes a reference input signal Sref as input and the integral result AOUTB as output. The transfer function H(z) has the transfer characteristics of a moving average filter, as shown in equation (7). Therefore, it is less susceptible to noise in the low-frequency signal domain of the signal being converted by high-frequency noise such as external digital signals.

[0076] Figure 8 shows an overview of the configuration of the AD converter 200 of the second embodiment. The AD converter 200 of the second embodiment has the same configuration and functions as the AD converter 100 of the first embodiment, except that the integrator 10 has four analog signal input circuits 111-141 and four reference signal input circuits 211-241. The AD converter 200 of the second embodiment divides one integral into four integrals, and at the timing when the integrator 10 outputs the second integral result after performing the second integral, it predicts the fourth integral result after performing the fourth integral and quantizes the predicted integral signal AOUTB'.Hereafter, the same configuration and functions as the AD converter 100 of the first embodiment may be omitted from the explanation, and the configuration and functions that differ from the AD converter 100 of the first embodiment will be mainly described.

[0077] The four analog signal input circuits 111-141 may each have the same configuration and function as the first analog signal input circuit 11 or the second analog signal input circuit 12 of the AD converter 100 in the first embodiment. The four analog signal input circuits 111-141 may perform sampling and output of analog output signals at different time intervals. The four reference signal input circuits 211-241 may each have the same configuration and function as the first reference signal input circuit 21 or the second reference signal input circuit 22 of the AD converter 100 in the first embodiment.

[0078] Figure 9 shows an example of a timing chart for the AD converter 200 of the second embodiment. Here, in Figure 9, the integrator operation (111, 211) indicates the operation of the first analog signal input circuit 111 and the first reference signal input circuit 211 in the integrator 10, the integrator operation (121, 221) indicates the operation of the second analog signal input circuit 121 and the second reference signal input circuit 221 in the integrator 10, the integrator operation (131, 231) indicates the operation of the third analog signal input circuit 131 and the third reference signal input circuit 231 in the integrator 10, and the integrator operation (141, 241) indicates the operation of the fourth analog signal input circuit 141 and the fourth reference signal input circuit 241 in the integrator 10. In Figure 9, P1, P2, and PCOMP indicate clock signals, C indicates the output of the comparator 41, and D indicates the digital signal output from the logic circuit 42. AOUTB and AOUTB' represent the integrated signal from the integrator 10 and the predicted integrated signal from the prediction unit 60.

[0079] The AD converter 200 operates by alternately repeating the operating periods phi(1), phi(2), phi(3), and phi(4), defined by the clock signals P1 and P2, in a time-division manner. The AD converter 200 operates with the operating periods phi(1), phi(2), phi(3), and phi(4) as one period. The operating periods phi(1), phi(2), phi(3), and phi(4) may be of the same length or different lengths. The AD converter 200 divides the sampling operation into sampling operation (1), sampling operation (2), sampling operation (3), and sampling operation (4) and performs it. The AD converter 200 divides the integration operation into integration operation (1), integration operation (2), integration operation (3), and integration operation (4) and performs it.

[0080] The prediction unit 60 may have the same configuration and functions as the prediction unit 60 of the AD converter 100 in the first embodiment. The prediction unit 60 may predict the integral result at the end of one period based on the integral result during one period of integral operation. For example, the prediction unit 60 may generate a predicted integral signal AOUTB' in the operating period phi(2) that predicts the integral end value AO1 in the future operating period phi(4).

[0081] Figure 10 shows an overview of the configuration of the AD converter 300 of the third embodiment. The AD converter of the third embodiment has the same configuration and functions as the AD converter 100 of the first embodiment, except that it includes a second integrator 20 and a predictive summer 80 (the summer circuit of this application). The AD converter 300 is, for example, an AD converter having a second-order delta-sigma modulator, and can achieve a higher signal-to-noise ratio by shifting the quantization noise to the higher frequency side than the AD converter 100 of the first embodiment. Clock signals P1 and P2 are input to the second integrator 20 and the predictive summer 80. Hereinafter, the same configuration and functions as the AD converter 100 of the first embodiment may be omitted from the description, and the configuration and functions that differ from the AD converter 100 of the first embodiment will be mainly described.

[0082] The second integrator 20 includes a third analog signal input circuit 13 and a second integration unit 70 (the second integration circuit of this application). The third analog signal input circuit 13 is connected between the output of the integrator 10 and the second integration unit 70. The third analog signal input circuit 13 receives the first integration signal AOUTB and the second integration signal AOUTB from the second integration unit 70 at different timings and outputs a third analog output signal AOUT3 based on either the first integration signal AOUTB or the second integration signal AOUTB. The third analog signal input circuit 13 outputs a third analog output signal AOUT3 based on the integration signal AOUTB output from the first integration unit 30 in the last (Xth) period of the X division. The third analog signal input circuit 13 may sample the integration signal AOUTB during the operating period phi(1) and output the analog output signal AOUT3 during the operating period phi(2).

[0083] The second integration unit 70 is connected to the predictive summing unit 80 and integrates the analog output signal AOUT3 from the third analog signal input circuit 13 to output the integrated signal AOUTC. The second integration unit 70 receives clock signals P1 and P2 as input and integrates the analog output signal AOUT3 during the operating period phi(2) to output the integrated signal AOUTC to the predictive summing unit 80.

[0084] The prediction summer 80 is connected to an input terminal to which the analog input signal Ain is input, the output of the first integrator 30, and the output of the second integrator 70. The prediction summer 80 adds the analog input signal Ain and the second integrator signal AOUTC to the prediction integrator signal AOUTB' and outputs the summing result AOUTD to the quantization unit 40. Next, the AD converter 300 of the third embodiment will be described in more detail.

[0085] Figure 11 shows a more detailed configuration of the AD converter 300 of the third embodiment. The third analog signal input circuit 13 includes a capacitor CB1, a plurality of switches SM1 and SM2 that switch the connection to one end of the capacitor CB1 between the output of the integrator 30 and a reference potential, and a plurality of switches SN1 and SN2 that switch the connection to the other end of the capacitor CB1 between the output of the third analog signal input circuit 13 and a reference potential.

[0086] Switches SM1 and SN1 are turned on when clock signal P1 is high and turned off when clock signal P2 is high. Similarly, switches SM2 and SN2 are turned on when clock signal P2 is high and turned off when clock signal P1 is high. The third analog signal input circuit 13 stores a charge in capacitor CB1 corresponding to the integral signal AOUTB of the integral unit 30 during the operating period phi(1), and then transfers the stored charge to the second integral unit 70 during the next operating period phi(2). Thus, the analog signal input circuit 13 may perform a sampling operation during the operating period phi(1) and an integration operation during the operating period phi(2).

[0087] The second integration unit 70 includes an operational amplifier 71 and a capacitor CF2. The operational amplifier 71 has its inverting input terminal connected to the output of the third analog signal input circuit 13, its forward input terminal connected to a reference potential, and its output terminal connected to the predictive summing unit 80. The capacitor CF2 is provided between the inverting input terminal and the output terminal of the operational amplifier 71. The second integration unit 70 may perform integration of the analog output signal Aout3 during the operating period phi(2). In this embodiment, the operational amplifier 71 has a single-ended input and single-ended output with its forward input terminal connected to ground, but it may also have a differential input and differential output.

[0088] Figure 12 shows the configuration of the prediction summing unit 80. The prediction summing unit 80 includes an analog signal input circuit 14, an analog signal input circuit 15, and a prediction unit 60. The prediction unit 60 may have the same configuration and function as the prediction unit 60 of the AD converter 100 in the first embodiment.

[0089] The analog signal input circuit 14 is connected to the input terminal of the AD converter 300 and receives an analog input signal Ain. The analog signal input circuit 14 outputs an analog output signal Ain' according to the input analog input signal Ain. The analog signal input circuit 14 includes a capacitor CC1, a plurality of switches SO1 and SO2 that switch the connection to one end of the capacitor CC1 between the input terminal and a reference potential, and a plurality of switches SP1 and SP2 that switch the connection to the other end of the capacitor CC1 between the output of the analog signal input circuit 14 and a reference potential. Switches SO1 and SP1 are turned on when the clock signal P1 is high and off when the clock signal P2 is high. Switches SO2 and SP2 are turned on when the clock signal P2 is high and off when the clock signal P1 is high. As a result, during the operating period phi(1), the capacitor CC1 outputs a charge corresponding to the analog input signal Ain as the analog output signal Ain'. During the next operating period phi(2), the capacitor CC1 resets the accumulated charge. In other words, capacitor CC1 samples the zero signal, which is intended to be zero V, as a charge.

[0090] The analog signal input circuit 15 is connected to the output of the second integrator 20 and receives the integral signal AOUTC as input. The analog signal input circuit 15 outputs an analog output signal AOUTC' according to the integral signal AOUTC. The analog signal input circuit 15 includes a capacitor CD1, a plurality of switches SQ1 and SQ2 that switch the connection to one end of the capacitor CD1 between the output of the second integrator 20 and a reference potential, and a plurality of switches SR1 and SR2 that switch the connection to the other end of the capacitor CD1 between the output of the analog signal input circuit 15 and a reference potential. Switches SQ1 and SR1 are turned on when the clock signal P1 is high and turned off when the clock signal P2 is high. Switches SQ2 and SR2 are turned on when the clock signal P2 is high and turned off when the clock signal P1 is high. As a result, during the operating period phi(1), the capacitor CD1 outputs a charge corresponding to the integral signal AOUTC from the second integrator 70 as the output signal AOUTC'. Furthermore, during the next operating period phi(2), capacitor CD1 resets its accumulated charge. In other words, capacitor CD1 samples the zero signal, which is intended to be zero V, as a charge.

[0091] The prediction unit 60 generates a charge Q during the operating period phi(1) that corresponds to the voltage level of the integrated signal AOUTB of the operational amplifier 31 at the completion of integration in the next operating period phi(2), and outputs it as the predicted integrated signal AOUTB'. The summation result AOUTD can be realized by connecting the analog output signal Ain' from the analog signal input circuit 14, the analog output signal AOUTC' from the analog signal input circuit 15, and the predicted integrated signal AOUTB' from the prediction unit 60.

[0092] The prediction summer 80 may, during the operating period phi(1), add the analog output signal Ain' from the analog signal input circuit 14, the analog output signal AOUTC' from the analog signal input circuit 15, and the prediction integral signal AOUTB' from the prediction unit 60, and output the summing result AOUTD to the quantization unit 40. The comparator 41 quantizes the summing result AOUTD, which is input at the rising edge of the clock signal PCOMP, to generate a quantized signal C.

[0093] Figure 13 shows an example of a timing chart for the AD converter 300 according to Embodiment 3. In Figure 13, Integrator 1 operation (11, 21) shows the operation of the first analog signal input circuit 11 and the first reference signal input circuit 21 in the integrator 10, and Integrator 1 operation (12, 22) shows the operation of the second analog signal input circuit 12 and the second reference signal input circuit 22 in the integrator 10. In Figure 13, Integrator 2 operation shows the operation of the second integrator 20. P1, P2, and PCOMP represent clock signals, C represents the output of the comparator 41, and D represents the digital signal output from the logic circuit 42. AOUTB and AOUTB' represent the integral signal of the integrator 10 and the predicted integral signal of the prediction unit 60, and AOUTC' represents the analog output signal of the analog signal input circuit 15.

[0094] The AD converter 300 operates by alternately repeating operating periods phi(1) and phi(2) in a time-division manner, with operating periods phi(1) and phi(2) forming one period. In this embodiment, operating periods phi(1) and phi(2) are of the same length, but they may be of different lengths.

[0095] The AD converter 300 divides the sampling operation into sampling operation (1) and sampling operation (2), and the integration operation into integration operation (1) and integration operation (2). The prediction adder 80 adds the analog output signal Ain' from the analog signal input circuit 14, the analog output signal AOUTC' from the analog signal input circuit 15, and the prediction integral signal AOUTB' from the prediction unit 60, which predicts the integration end value AO1 in the operation period phi(2), during the operation period phi(1), to generate the summation result AOUTD. The control unit 50 causes the quantization unit 40 to perform quantization on the summation result AOUTD from the prediction adder 80. The quantization unit 40 outputs a quantized signal C, which is the summation result AOUTD input at the rising edge of the clock signal PCOMP. The logic circuit 42 outputs its input as a digital signal D at the rising edge of the clock signal P1 and holds the same output signal until the rising edge of the next clock signal P1.

[0096] Figure 14 shows the configuration of a modified prediction summer 800. The modified prediction summer 800 is connected to an input terminal into which an analog input signal Ain is input, the output of the first integral unit 30, and the output of the second integral unit 70. The prediction summer 800 receives the analog input signal Ain, the integral signal AOUTB, and the integral signal AOUTC as inputs, and outputs an integral signal AOUTD' obtained by adding the analog input signal Ain and the integral signal AOUTC to the predicted integral signal AOUTB'' to the quantization unit 40. The prediction summer 800 has an analog signal input circuit 140, an analog signal input circuit 150, and a prediction unit 600.

[0097] The analog signal input circuit 140 is connected to the input terminal of the AD converter 300, receives an analog input signal Ain, and outputs an analog input signal Ain''. The analog signal input circuit 140 includes a capacitor CC1, a plurality of switches SS1, SS34 that switch the connection to one end of the capacitor CC1 between the input terminal and a reference potential, a plurality of switches ST1, ST3 that switch the connection to the other end of the capacitor CC1 between the output of the analog signal input circuit 140 and a reference potential, and a polarity inversion circuit 142 connected to the output of the analog signal input circuit 140. The polarity inversion circuit 142 may output a signal with the polarity of the input charge reversed, and may be configured as an inverting amplifier.

[0098] The analog signal input circuit 150 is connected to the output of the second integrator 20, receives the integral signal AOUTC as input, and outputs the analog output signal AOUTC''. The analog signal input circuit 150 includes a capacitor CC2, a plurality of switches SU1, SU34 that switch the connection to one end of the capacitor CC2 between the output of the second integrator 20 and a reference potential, a plurality of switches SV1, SV3 that switch the connection to the other end of the capacitor CC2 between the output of the analog signal input circuit 150 and a reference potential, and a polarity inversion circuit 151. The polarity inversion circuit 151 may output a signal with the polarity of the input charge reversed, and may be configured as an inverting amplifier.

[0099] The prediction unit 600 is connected to the output of the integrator 10, receives the integral signal AOUTB as input, and outputs the predicted integral signal AOUTB''. The prediction unit 600 has three capacitors CP1, CP2, and CP3 connected in parallel between the input and output of the prediction unit 600, multiple switches SPG4, SPG13, SPH3, SPH4, SPI1, SPI34, SPJ1, SPJ3, SPK4, SPK13, SPL3, and SPL4, and polarity inversion circuits 621 and 631, forming three prediction circuits 610, 620, and 630.

[0100] The prediction circuit 610 includes a capacitor CP1 and switches SPG4, SPG13, SPH3, and SPH4. The capacitance value of capacitor CP1 is, for example, 2C. Switches SPG13 and SPG4 switch the connection to one end of capacitor CP1 between the output of integrator 10 and a reference potential. Switches SPH3 and SPH4 switch the connection to the other end of capacitor CP1 between the output of prediction circuit 610 and a reference potential.

[0101] The prediction circuit 620 includes a capacitor CP2, switches SPI1, SPI34, SPJ1, and SPJ3, and a polarity inversion circuit 621 connected to the output of the prediction circuit 620. The capacitance value of capacitor CP2 is, for example, 2C. Switches SPI1 and SPI34 switch the connection to one end of capacitor CP2 between the output of integrator 10 and a reference potential. Switches SPJ1 and SPJ3 switch the connection to the other end of capacitor CP2 between the input of polarity inversion circuit 621 and a reference potential. Polarity inversion circuit 621 may output a signal with the polarity of the input charge reversed, and may be configured as an inverting amplifier.

[0102] The prediction circuit 630 includes a capacitor CP3, switches SPK4, SPK13, SPL3, and SPL4, and a polarity inversion circuit 631 connected to the output of the prediction circuit 630. The capacitance value of capacitor CP3 is, for example, C. Switches SPK4 and SPK13 switch the connection to one end of capacitor CP3 between the output of integrator 10 and a reference potential. Switches SPL3 and SPL4 switch the connection to the other end of capacitor CP3 between the input of polarity inversion circuit 631 and a reference potential. Polarity inversion circuit 631 may output a signal with the polarity of the input charge reversed, and may be configured as an inverting amplifier.

[0103] Figure 15 shows the clock signals P1, P2, P3, P4, and PCOMP that operate the AD converter 300 according to Embodiment 3, which includes a predictive summing unit 800. Clock signal P1 is high during the operating period phi(1) and low during the rest of the period. Clock signal P2 is high during the operating period phi(2) and low during the rest of the period. Clock signals P3 and PCOMP are high during the operating period phi(3) and low during the rest of the period. Clock signal P4 is high during the operating period phi(4) and low during the rest of the period. Clock signal P3 is high during the first half of the operating period phi(2), and clock signal P4 is high during the second half of the operating period phi(2). Clock signals P3 and PCOMP are clock signals whose rising and falling edges are at the same timing.

[0104] In the analog signal input circuit 140, switch SS1 turns on when clock signal P1 is high and turns off when clock signal P3 is high and clock signal P4 is high. Switch SS34 turns on when clock signal P3 is high and clock signal P4 is high and turns off when clock signal P1 is high. Switch ST1 turns on when clock signal P1 is high and turns off when clock signal P3 is high and clock signal P4 is high. Switch ST3 turns on when clock signal P3 is high and turns off when clock signal P1 is high and clock signal P4 is high.

[0105] The analog signal input circuit 140 samples a charge corresponding to the analog input signal Ain into capacitor CC1 during the operating period phi(1), transfers the sampled charge to capacitor CC1 during the operating period phi(3), and transfers the charge with its polarity reversed by the polarity inversion circuit 142 as the output signal Ain'' to the quantization unit 40. In this embodiment, the analog signal input circuit 140 is in a single-ended configuration, but in the case of a differential configuration, it may sample a charge corresponding to a signal with the opposite polarity of the analog input signal Ain.

[0106] In the analog signal input circuit 150, switch SU1 turns on when clock signal P1 is high, and turns off when clock signal P3 is high and clock signal P4 is high. Switch SU34 turns on when clock signal P3 is high and clock signal P4 is high, and turns off when clock signal P1 is high. Switch SV1 turns on when clock signal P1 is high, and turns off when clock signal P3 is high and clock signal P4 is high. Switch SV3 turns on when clock signal P3 is high, and turns off when clock signal P1 is high and clock signal P4 is high.

[0107] The analog signal input circuit 150 samples a charge corresponding to the output signal AOUTC of the operational amplifier 71 into the capacitor CC2 during the operating period phi(1). During the operating period phi(3), it transfers the sampled charge into the capacitor CC2 to the polarity inversion circuit 151, and transfers the charge with its polarity reversed by the polarity inversion circuit 151 to the quantization unit 40 as the output signal AOUTC''. In this embodiment, the analog signal input circuit 150 is in a single-ended configuration, but in the case of a differential configuration, it may sample a charge corresponding to a signal with the opposite polarity of the output signal AOUTC of the operational amplifier 71.

[0108] In the prediction circuit 610, switch SPG13 turns on when clock signal P1 is high and clock signal P3 is high, and turns off when clock signal P4 is high. Switch SPG4 turns on when clock signal P4 is high, and turns off when clock signal P1 is high and clock signal P3 is high. Switch SPH3 turns on when clock signal P3 is high, and turns off when clock signal P1 is high and clock signal P4 is high. Switch SPH4 turns on when clock signal P4 is high, and turns off when clock signal P1 is high and clock signal P3 is high.

[0109] The prediction circuit 610 samples a charge corresponding to the output signal AOUTB of the operational amplifier 31 into the capacitor CP1 during the operating period phi(4), and transfers the sampled charge Q1 to the capacitor CP1 during the operating period phi(3).

[0110] In the prediction circuit 620, switch SPI1 turns on when clock signal P1 is high, and turns off when clock signal P3 is high and clock signal P4 is high. Switch SPI34 turns on when clock signal P3 is high and clock signal P4 is high, and turns off when clock signal P1 is high. Switch SPJ1 turns on when clock signal P1 is high, and turns off when clock signal P3 is high and clock signal P4 is high. Switch SPJ3 turns on when clock signal P3 is high, and turns off when clock signal P1 is high and clock signal P4 is high.

[0111] The prediction circuit 620 samples a charge corresponding to the output signal AOUTB of the operational amplifier 31 into the capacitor CP2 during the operating period phi(1), and during the operating period phi(3), it transfers the sampled charge to the capacitor CP2 as charge Q2, whose polarity has been reversed by the polarity inversion circuit 621. In this embodiment, the prediction circuit 620 is in a single-ended configuration, but in the case of a differential configuration, it may sample a charge corresponding to the signal with the opposite polarity of the output signal AOUTB of the operational amplifier 31.

[0112] In the prediction circuit 630, switch SPK13 turns on when clock signal P1 is high and clock signal P3 is high, and turns off when clock signal P4 is high. Switch SPK4 turns on when clock signal P4 is high, and turns off when clock signal P1 is high and clock signal P3 is high. Switch SPL3 turns on when clock signal P3 is high, and turns off when clock signal P1 is high and clock signal P4 is high. Switch SPL4 turns on when clock signal P4 is high, and turns off when clock signal P1 is high and clock signal P3 is high.

[0113] The prediction circuit 630 samples a charge corresponding to the output signal AOUTB of the operational amplifier 31 into the capacitor CP3 during the operating period phi(4), and during the operating period phi(3), it transfers the sampled charge to the capacitor CP3 as charge Q3, whose polarity has been reversed by the polarity inversion circuit 631. In this embodiment, the prediction circuit 630 is in a single-ended configuration, but in the case of a differential configuration, it may sample a charge corresponding to the signal with the opposite polarity of the output signal AOUTB of the operational amplifier 31.

[0114] The prediction unit 600 outputs a charge Q, which is a composite of the charge Q1 sampled by the prediction circuit 610, the charge Q2 sampled by the prediction circuit 620, and the charge Q3 sampled by the prediction circuit 630, to the quantization unit 40 as an output signal AOUTB'' during the operating period phi(3). During the operating period phi(3), the prediction unit 600 generates a charge Q corresponding to the voltage level of the output signal AOUTB of the operational amplifier 31 at the completion of integration in the next operating period phi(2), and outputs it as a predicted integral signal AOUTB''. The summation result AOUTD' can be realized by connecting the output signal Ain'' of the analog signal input circuit 140, the output signal AOUTC'' of the analog signal input circuit 150, and the predicted integral signal AOUTB'' of the prediction unit 600. The prediction summer 800 adds the output signal Ain'' of the analog signal input circuit 140, the output signal AOUTC'' of the analog signal input circuit 150, and the prediction integral signal AOUTB'' of the prediction unit 600, and outputs the summing result AOUTD' to the quantization unit 40. The comparator 41 receives the summing result AOUTD' from the prediction summer 800 as input and generates a quantized signal C by quantizing the summing result AOUTD'. The comparator 41 generates the quantized signal C by quantizing the summing result AOUTD' which is input at the rising edge of the clock signal PCOMP.

[0115] Figure 16 shows a timing chart of the integration result AOUTB of the integration unit 30 in the AD converter 300 according to Embodiment 3, which includes a prediction summing unit 800. In Figure 16, the vertical axis represents the voltage level of the integration signal AOUTB, and the horizontal axis represents the passage of time.

[0116] V11 is the voltage level of the output signal AOUTB of the operational amplifier 31 at the completion of integration in the current (N) operating period phi(1), V02 is the voltage level of the output signal AOUTB of the operational amplifier 31 at the completion of integration in the previous (N-1) operating period phi(2), and V12 is the voltage level of the output signal AOUTB of the operational amplifier 31 at the completion of integration in the next (N+1) operating period phi(2). The operating period phi(2) is divided into the first operating period phi(3) and the second operating period phi(4). Vstep1 is half the change in the voltage level of the output signal AOUTB of the operational amplifier 31 when one integration is performed between the current operating period phi(1) and the next operating period phi(2). In other words, Vtep1 can be expressed as in equation (1) in the description of the AD converter 100 of the first embodiment, and V12 can be expressed as in equation (2).

[0117] Here, following the timing chart in Figure 16, the charge Q1 output to the quantization unit 40 during the operation period phi(3) within the next operation period phi(2) is given by equation (3) in the AD converter 100 of the first embodiment, charge Q2 by equation (4), charge Q3 by equation (5), and the combined charge Q of charges Q1, Q2, and Q3 is given by equation (6).

[0118] In this example, the prediction unit 600 generates a charge Q in the first half of the next operating period phi(3), which is the first half of the next operating period phi(2), that corresponds to the voltage level of the output signal AOUTB of the operational amplifier 31 at the completion of integration in the next operating period phi(2), and outputs it to the quantization unit 40 as a predicted integral signal AOUTB''. In this example, the prediction unit 600 generates the predicted integral signal AOUTB'' using a switched capacitor, but the predicted integral signal AOUTB'' may also be generated using a resistor divider, amplifier, etc.

[0119] In the AD converter 300 according to Embodiment 3, which includes a predictive summer 800, the output signal AOUTB of the integrator 30 and the output signal AOUTC of the integrator 70 do not short-circuit via the switch and capacitance during any of the operating periods phi(1), phi(2), and phi(3). Therefore, the integral signal AOUTB of the integrator 30 and the integral signal AOUTC of the integrator 70 do not interfere with each other. As a result, the AD converter 300 according to Embodiment 3, which includes a predictive summer 800, can achieve a higher signal-to-noise ratio than the AD converter 300 according to Embodiment 3, which includes a predictive summer 80.

[0120] Figure 17 shows an example of a timing chart for the AD converter 300 according to Embodiment 3, which includes a prediction summer 800. The AD converter 300 with the prediction summer 800 in this embodiment operates by alternately repeating the operation period phi(1) and the operation period phi(2) in a time-division manner. The AD converter 300 with the prediction summer 800 operates with the operation period phi(1) and the operation period phi(2) as one period. In this embodiment, the operation period phi(1) and the operation period phi(2) are of the same length, but they may be of different lengths. In this embodiment, the AD converter 300 with the prediction summer 800 operates by dividing the operation period phi(2) into the first half operation period phi(3) and the second half operation period phi(4). The AD converter 300 with the prediction summer 800 in this embodiment performs the sampling operation by dividing it into sampling operation (1) and sampling operation (2). The AD converter 300 performs the integration operation by dividing it into integration operation (1) and integration operation (2).

[0121] In this example, the predictive summer 800 adds the output signal Ain'' of the analog signal input circuit 140, the output signal AOUTC'' of the analog signal input circuit 150, and the predicted integral signal AOUTB'' of the prediction unit 600, which predicts the integral end value AO1 during the operating period phi(2), to generate the summation result AOUTD''. The control unit 50 causes the quantization unit 40 to perform quantization on the summation result AOUTD'' of the predictive summer 800. The quantization unit 40 outputs a quantized signal C obtained by quantizing the summation result AOUTD, which is input at the falling edge of the clock signal PCOMP. The logic circuit 42 outputs its input as a digital signal D at the rising edge of the clock signal P1 and holds the same output signal until the rising edge of the next clock signal P1.

[0122] The power consumption of the quantization unit 40 changes depending on the length of the period tCOMP. In this specification, the period tCOMP is the period from the start time of the quantization operation in the quantization unit 40 to the time when the output signal is determined. For example, as the period tCOMP becomes longer, the speed requirement for the quantization unit 40 is reduced, and the power consumption of the quantization unit 40 is reduced. The period tCOMP is the period from the falling edge time of the clock signal PCOMP to the rising edge time of the clock signal P1.

[0123] In the AD converter 300 according to Embodiment 3, which includes a predictive summer 800, quantization of the summing result AOUTD' of the predictive summer 800 begins at the falling edge of the clock signal PCOMP, resulting in a shorter period tCOMP compared to the AD converter 300 according to Embodiment 3, which includes a predictive summer 80. Consequently, the power consumption of the quantization unit 40 increases in the AD converter 300 according to Embodiment 3, which includes a predictive summer 800, compared to the AD converter 300 according to Embodiment 3, which includes a predictive summer 80. Furthermore, the clock signal PCOMP may exhibit duty cycle fluctuations due to manufacturing process variations, power supply voltage fluctuations, and temperature fluctuations (PVT fluctuations), making it difficult to secure the necessary period tCOMP for quantization and posing a challenge to achieving high speed. In such cases, using a clock signal PCOM generated from a PLL circuit can mitigate duty cycle fluctuations. On the other hand, the AD converter 300 according to Embodiment 3, which includes a predictive summer 800, can achieve a higher signal-to-noise ratio than the AD converter 300 according to Embodiment 3, which includes a predictive summer 80.

[0124] The AD converters 100, 200, and 300 of the first to third embodiments described above can reduce the power consumption of the integrating unit 30 by dividing a single integration into multiple steps, thereby easing the slewing requirement (i.e., the output change speed requirement) of the integrating unit 30. Furthermore, by performing quantization using the predicted integrated signal, the period from the start time of the quantization operation to the start time of the next integration can be extended, thereby reducing the power consumption of the quantizing unit 40. By performing quantization using the predicted integrated signal, the error with respect to the integrated completion value can be reduced, and the error noise contained in the quantized signal can be reduced.

[0125] Furthermore, the logic circuit 42 may receive a clock signal that rises slightly earlier than the rising edge of clock signal P1, instead of the clock signal P1, to avoid overlap with the integral operation. Also, the switches SS1 and SS2 of the first reference signal input circuit 21 and the second reference signal input circuit 22 may be turned on at the same time, or they may be turned on with a half-phase difference. Similarly, the switches SS1B and SS2B may be turned on at the same time, or they may be turned on with a half-phase difference. The selection between switches SS1 and SS1B may be performed using a signal obtained by resynchronizing the digital signal D and the inverted signal DB at the rising edge of the clock signal P2, or at a time slightly earlier.

[0126] The AD converters 100, 200, and 300 may have only one analog signal input circuit or one reference signal input circuit, and may be configured to split only one of the analog output signal Aout and the feedback signal Sfb. Alternatively, the AD converters 100, 200, and 300 may split the analog output signal Aout and the feedback signal Sfb into three or six parts, and may have three or six analog signal input circuits and six reference signal input circuits, respectively.

[0127] Furthermore, the clock terminal of logic circuit 42 may be input to the clock signal P2. To avoid overlap with the integral operation, the clock terminal of logic circuit 42 may be input to a clock signal with a rising edge earlier than the rising edge of clock signal P1.

[0128] Figure 18 shows a schematic configuration of the AD converter. The AD converter 400 quantizes the input analog input signal Ain into bit data and outputs it. The AD converter 400 comprises an AD converter 410, an AD converter 420, a digital filter 430, a digital filter 440, and a noise cancellation circuit 90. The AD converter 410 may be one of the AD converters 100, 200, and 300 of the first to third embodiments. The AD converter 420 may be one of the AD converters 100, 200, and 300 of the first to third embodiments, with the prediction unit 60 and prediction summing units 80 and 800 removed.

[0129] For example, the AD converter 400 is a MASH (Multi-Stage Noise Shaping) modulator with the AD converter 410 as the pre-stage and the AD converter 420 as the post-stage, connected in a dependent manner. Alternatively, the AD converter 400 may be an AD converter having a third-order delta-sigma modulator.

[0130] The AD converter 410 is connected to the digital filter 430 and the AD converter 420. Depending on the input analog input signal Ain, the AD converter 410 outputs an integral signal AOUTC to the AD converter 420, and outputs a digital signal D1 corresponding to the signal obtained by quantizing the summation result AOUTD to the digital filter 430. The AD converter 420 is connected to the digital filter 440. Depending on the input of the predicted integral signal AOUTD, the AD converter 420 quantizes the signal output by the integrator of the AD converter 420 and outputs a digital signal D2.

[0131] Digital filter 430 is connected to noise cancellation circuit 90, multiplies the input digital signal D1 by coefficient H1, and outputs digital signal D1'. Digital filter 440 is connected to noise cancellation circuit 90, multiplies the input digital signal D2 by coefficient H2, and outputs digital signal D2'. Digital signals D1' and D2' are input to noise cancellation circuit 90. Noise cancellation circuit 90 subtracts digital signal D2' from digital signal D1' and outputs digital signal D3. The coefficients H1 of digital filter 430 and H2 of digital filter 440 may be selected so that the quantization noise of the preceding AD converter 410 is canceled out in the digital signal D3, which is the output signal of noise cancellation circuit 90.

[0132] The AD converter 400 uses the AD converters 100, 200, and 300 from Embodiments 1 to 3 as the pre-stage of the MASH modulator. For example, the AD converter 100 predicts and generates the second integral result at the timing of outputting the first integral result, and then quantizes it, so the output digital signals D1 and D1' do not contain error signals. Therefore, in the noise cancellation circuit 90, the quantization noise of the preceding AD converter 410 does not remain in the result of subtracting the digital signal D2' from the digital signal D1'. If the AD converter 420, which does not have a prediction unit 60, is used as the pre-stage of the MASH modulator, quantization is performed using the signal during the second integral, so the output digital signal contains error signals. As a result, in the noise cancellation circuit 90, the quantization noise of the preceding AD converter 410 remains in the result of subtracting the digital signal D2' from the digital signal D1'. Therefore, by applying the AD converters 100, 200, and 300 of the first to third embodiments as the preamplifier to the MASH modulator, a high signal-to-noise ratio can be achieved.

[0133] Furthermore, the AD converter 300 according to Embodiment 3 may be applied before the MASH modulator in the AD converter 400. By applying a high-order delta-sigma modulator such as the AD converter 300 according to Embodiment 3, the quantization noise can be shifted to the high-frequency side, thereby achieving a higher signal-to-noise ratio. In addition, any of the AD converters 100, 200, or 300 from Embodiments 1 to 3 may be applied after the MASH modulator in the AD converter 400.

[0134] The prediction units of the AD converters 100, 200, and 300 described above output a predicted integral signal based on the integral signals of two consecutive periods among the X-divided periods during the conversion period. However, the unit is not limited to this, and may similarly output a predicted integral signal based on the integral signals of two non-contiguous periods (for example, the difference between two integral signals).

[0135] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0136] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0137] 10 Integrator 11 Analog signal input circuit 12 Analog signal input circuit 13 Analog signal input circuit 14 Analog signal input circuit 20 Integrator 21 Reference signal input circuit 22 Reference signal input circuit 23. Reference signal input circuit 24. Reference signal input circuit 30 Integral part 31 Op-amps 40 Quantization section 41 Comparator 42 Logic Circuits 50 Control Unit 60 Prediction Section 61 Prediction Circuit 62 Prediction Circuit 63 Prediction Circuit 70 Integral section 71 Op-amps 80 Prediction Addition Section 90 Noise Cancellation Circuit 100 AD Converters 111 Analog signal input circuit 121 Analog signal input circuit 131 Analog signal input circuit 141 Analog signal input circuit 142 Polarity Inversion Circuit 151 Polarity Inversion Circuit 200 AD Converters 211 Reference signal input circuit 221 Reference signal input circuit 231 Reference signal input circuit 241 Reference signal input circuit 300 AD Converters 400 AD Converter 410 AD Converter 420 AD Converter 430 Digital Filters 440 Digital Filters 610 Prediction Circuit 620 Prediction Circuit 630 Prediction Circuit 621 Polarity Inversion Circuit 631 Polarity Inversion Circuit 140 Analog signal input circuit 150 Analog signal input circuit 600 Prediction Section 800 Prediction Addition Unit

Claims

1. An AD converter that converts an analog input signal to a digital signal for each conversion period including a first operating period and a second operating period, A first analog signal input circuit receives the aforementioned analog input signal and outputs a first analog output signal obtained by sampling the analog input signal during the second operating period within the conversion period during the first operating period, A second analog signal input circuit receives the aforementioned analog input signal and outputs a second analog output signal during the second operating period, which is obtained by sampling the analog input signal during a first operating period prior to the second operating period within the conversion period. An integrating circuit that outputs a first integrated signal obtained by integrating the first analog output signal over the first operating period, and outputs a second integrated signal obtained by integrating the second analog output signal over the second operating period, A prediction circuit predicts the second integral signal that the integration circuit will output at the completion of the second operating period within the current conversion period, based on the second integral signal integrated by the integration circuit in the previous conversion period and the first integral signal integrated by the integration circuit in the current conversion period, after the first operating period within the current conversion period and before the completion of the second operating period within the current conversion period, and outputs it as a predicted integral signal for the current conversion period. A quantization circuit that generates a digital signal obtained by quantizing the aforementioned predicted integral signal, A reference signal input circuit receives the digital signal from the quantization circuit and inputs a feedback signal corresponding to the input digital signal to the integration circuit. An AD converter equipped with [a specific feature].

2. The prediction circuit predicts the second integral signal in the current conversion period based on the difference between the second integral signal integrated by the integration circuit in the previous conversion period and the first integral signal integrated by the integration circuit in the current conversion period. The AD converter according to claim 1.

3. The prediction circuit comprises three capacitors connected in parallel, a plurality of switches that switch the connection to one end of the three capacitors between the output of the integration circuit and a reference potential, and a plurality of switches that switch the connection to the other end of the three capacitors between the output of the prediction circuit and a reference potential. The AD converter according to claim 1.

4. An AD converter that, in the Mth conversion period (where M is an integer of 2 or more), divides the conversion period into X periods (where X is an integer of 2 or more) including a first operating period and a second operating period, repeatedly performs integration and sampling operations, and converts an analog input signal into a digital signal for each conversion period, An analog signal input circuit that outputs an analog output signal based on an input analog input signal in each period obtained by dividing the conversion period into X equal parts, wherein the analog signal input circuit comprises: a first analog signal input circuit that receives the analog input signal and outputs a first analog output signal obtained by sampling the analog input signal in the second operating period within the conversion period during the first operating period; and a second analog signal input circuit that receives the analog input signal and outputs a second analog output signal obtained by sampling the analog input signal in the first operating period prior to the second operating period within the conversion period during the second operating period, An integrating circuit that outputs a first integrated signal obtained by integrating the first analog output signal over the first operating period, and outputs a second integrated signal obtained by integrating the second analog output signal over the second operating period, A prediction circuit predicts the second integral signal that the integration circuit will output at the completion of the second operating period within the Mth conversion period, based on the second integral signal integrated by the integration circuit in the immediately preceding conversion period (M-1th) and the first integral signal integrated by the integration circuit in the Mth conversion period, after the first operating period within the Mth conversion period and before the completion of the second operating period within the Mth conversion period, and outputs it as a predicted integral signal for the Mth conversion period. A quantization circuit that generates a digital signal obtained by quantizing the aforementioned predicted integral signal, A reference signal input circuit receives the digital signal from the quantization circuit and inputs a feedback signal corresponding to the input digital signal to the integration circuit. An AD converter equipped with [a specific feature].

5. The prediction circuit predicts the second integral signal that the integration circuit will output at the completion of the second operating period within the Mth conversion period, based on the difference between the second integral signal integrated by the integration circuit during the immediately preceding conversion period (M-1th) and the first integral signal integrated by the integration circuit during the Mth conversion period. The AD converter according to claim 4.

6. The prediction circuit comprises three capacitors connected in parallel, a plurality of switches that switch the connection to one end of the three capacitors between the output of the integration circuit and a reference potential, and a plurality of switches that switch the connection to the other end of the three capacitors between the output of the prediction circuit and a reference potential. The AD converter according to claim 4.

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